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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/dmi.h>
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_atomic_helper.h>
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_crtc_helper.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38.  
  39. /* Here's the desired hotplug mode */
  40. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45.                            ADPA_CRT_HOTPLUG_ENABLE)
  46.  
  47. struct intel_crt {
  48.         struct intel_encoder base;
  49.         /* DPMS state is stored in the connector, which we need in the
  50.          * encoder's enable/disable callbacks */
  51.         struct intel_connector *connector;
  52.         bool force_hotplug_required;
  53.         u32 adpa_reg;
  54. };
  55.  
  56. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57. {
  58.         return container_of(encoder, struct intel_crt, base);
  59. }
  60.  
  61. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62. {
  63.         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64. }
  65.  
  66. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67.                                    enum pipe *pipe)
  68. {
  69.         struct drm_device *dev = encoder->base.dev;
  70.         struct drm_i915_private *dev_priv = dev->dev_private;
  71.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72.         enum intel_display_power_domain power_domain;
  73.         u32 tmp;
  74.  
  75.         power_domain = intel_display_port_power_domain(encoder);
  76.         if (!intel_display_power_is_enabled(dev_priv, power_domain))
  77.                 return false;
  78.  
  79.         tmp = I915_READ(crt->adpa_reg);
  80.  
  81.         if (!(tmp & ADPA_DAC_ENABLE))
  82.                 return false;
  83.  
  84.         if (HAS_PCH_CPT(dev))
  85.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  86.         else
  87.                 *pipe = PORT_TO_PIPE(tmp);
  88.  
  89.         return true;
  90. }
  91.  
  92. static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  93. {
  94.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  95.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  96.         u32 tmp, flags = 0;
  97.  
  98.         tmp = I915_READ(crt->adpa_reg);
  99.  
  100.         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  101.                 flags |= DRM_MODE_FLAG_PHSYNC;
  102.         else
  103.                 flags |= DRM_MODE_FLAG_NHSYNC;
  104.  
  105.         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
  106.                 flags |= DRM_MODE_FLAG_PVSYNC;
  107.         else
  108.                 flags |= DRM_MODE_FLAG_NVSYNC;
  109.  
  110.         return flags;
  111. }
  112.  
  113. static void intel_crt_get_config(struct intel_encoder *encoder,
  114.                                  struct intel_crtc_state *pipe_config)
  115. {
  116.         struct drm_device *dev = encoder->base.dev;
  117.         int dotclock;
  118.  
  119.         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
  120.  
  121.         dotclock = pipe_config->port_clock;
  122.  
  123.         if (HAS_PCH_SPLIT(dev))
  124.                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
  125.  
  126.         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
  127. }
  128.  
  129. static void hsw_crt_get_config(struct intel_encoder *encoder,
  130.                                struct intel_crtc_state *pipe_config)
  131. {
  132.         intel_ddi_get_config(encoder, pipe_config);
  133.  
  134.         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
  135.                                               DRM_MODE_FLAG_NHSYNC |
  136.                                               DRM_MODE_FLAG_PVSYNC |
  137.                                               DRM_MODE_FLAG_NVSYNC);
  138.         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
  139. }
  140.  
  141. /* Note: The caller is required to filter out dpms modes not supported by the
  142.  * platform. */
  143. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  144. {
  145.         struct drm_device *dev = encoder->base.dev;
  146.         struct drm_i915_private *dev_priv = dev->dev_private;
  147.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  148.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  149.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  150.         u32 adpa;
  151.  
  152.         if (INTEL_INFO(dev)->gen >= 5)
  153.                 adpa = ADPA_HOTPLUG_BITS;
  154.         else
  155.                 adpa = 0;
  156.  
  157.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  158.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  159.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  160.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  161.  
  162.         /* For CPT allow 3 pipe config, for others just use A or B */
  163.         if (HAS_PCH_LPT(dev))
  164.                 ; /* Those bits don't exist here */
  165.         else if (HAS_PCH_CPT(dev))
  166.                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
  167.         else if (crtc->pipe == 0)
  168.                 adpa |= ADPA_PIPE_A_SELECT;
  169.         else
  170.                 adpa |= ADPA_PIPE_B_SELECT;
  171.  
  172.         if (!HAS_PCH_SPLIT(dev))
  173.                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
  174.  
  175.         switch (mode) {
  176.         case DRM_MODE_DPMS_ON:
  177.                 adpa |= ADPA_DAC_ENABLE;
  178.                 break;
  179.         case DRM_MODE_DPMS_STANDBY:
  180.                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  181.                 break;
  182.         case DRM_MODE_DPMS_SUSPEND:
  183.                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  184.                 break;
  185.         case DRM_MODE_DPMS_OFF:
  186.                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  187.                 break;
  188.         }
  189.  
  190.         I915_WRITE(crt->adpa_reg, adpa);
  191. }
  192.  
  193. static void intel_disable_crt(struct intel_encoder *encoder)
  194. {
  195.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  196. }
  197.  
  198. static void pch_disable_crt(struct intel_encoder *encoder)
  199. {
  200. }
  201.  
  202. static void pch_post_disable_crt(struct intel_encoder *encoder)
  203. {
  204.         intel_disable_crt(encoder);
  205. }
  206.  
  207. static void intel_enable_crt(struct intel_encoder *encoder)
  208. {
  209.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  210.  
  211.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  212. }
  213.  
  214. static enum drm_mode_status
  215. intel_crt_mode_valid(struct drm_connector *connector,
  216.                      struct drm_display_mode *mode)
  217. {
  218.         struct drm_device *dev = connector->dev;
  219.  
  220.         int max_clock = 0;
  221.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  222.                 return MODE_NO_DBLESCAN;
  223.  
  224.         if (mode->clock < 25000)
  225.                 return MODE_CLOCK_LOW;
  226.  
  227.         if (IS_GEN2(dev))
  228.                 max_clock = 350000;
  229.         else
  230.                 max_clock = 400000;
  231.         if (mode->clock > max_clock)
  232.                 return MODE_CLOCK_HIGH;
  233.  
  234.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  235.         if (HAS_PCH_LPT(dev) &&
  236.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  237.                 return MODE_CLOCK_HIGH;
  238.  
  239.         return MODE_OK;
  240. }
  241.  
  242. static bool intel_crt_compute_config(struct intel_encoder *encoder,
  243.                                      struct intel_crtc_state *pipe_config)
  244. {
  245.         struct drm_device *dev = encoder->base.dev;
  246.  
  247.         if (HAS_PCH_SPLIT(dev))
  248.                 pipe_config->has_pch_encoder = true;
  249.  
  250.         /* LPT FDI RX only supports 8bpc. */
  251.         if (HAS_PCH_LPT(dev))
  252.                 pipe_config->pipe_bpp = 24;
  253.  
  254.         /* FDI must always be 2.7 GHz */
  255.         if (HAS_DDI(dev)) {
  256.                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
  257.                 pipe_config->port_clock = 135000 * 2;
  258.  
  259.                 pipe_config->dpll_hw_state.wrpll = 0;
  260.                 pipe_config->dpll_hw_state.spll =
  261.                         SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
  262.         }
  263.  
  264.         return true;
  265. }
  266.  
  267. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  268. {
  269.         struct drm_device *dev = connector->dev;
  270.         struct intel_crt *crt = intel_attached_crt(connector);
  271.         struct drm_i915_private *dev_priv = dev->dev_private;
  272.         u32 adpa;
  273.         bool ret;
  274.  
  275.         /* The first time through, trigger an explicit detection cycle */
  276.         if (crt->force_hotplug_required) {
  277.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  278.                 u32 save_adpa;
  279.  
  280.                 crt->force_hotplug_required = 0;
  281.  
  282.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  283.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  284.  
  285.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  286.                 if (turn_off_dac)
  287.                         adpa &= ~ADPA_DAC_ENABLE;
  288.  
  289.                 I915_WRITE(crt->adpa_reg, adpa);
  290.  
  291.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  292.                              1000))
  293.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  294.  
  295.                 if (turn_off_dac) {
  296.                         I915_WRITE(crt->adpa_reg, save_adpa);
  297.                         POSTING_READ(crt->adpa_reg);
  298.                 }
  299.         }
  300.  
  301.         /* Check the status to see if both blue and green are on now */
  302.         adpa = I915_READ(crt->adpa_reg);
  303.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  304.                 ret = true;
  305.         else
  306.                 ret = false;
  307.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  308.  
  309.         return ret;
  310. }
  311.  
  312. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  313. {
  314.         struct drm_device *dev = connector->dev;
  315.         struct intel_crt *crt = intel_attached_crt(connector);
  316.         struct drm_i915_private *dev_priv = dev->dev_private;
  317.         u32 adpa;
  318.         bool ret;
  319.         u32 save_adpa;
  320.  
  321.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  322.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  323.  
  324.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  325.  
  326.         I915_WRITE(crt->adpa_reg, adpa);
  327.  
  328.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  329.                      1000)) {
  330.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  331.                 I915_WRITE(crt->adpa_reg, save_adpa);
  332.         }
  333.  
  334.         /* Check the status to see if both blue and green are on now */
  335.         adpa = I915_READ(crt->adpa_reg);
  336.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  337.                 ret = true;
  338.         else
  339.                 ret = false;
  340.  
  341.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  342.  
  343.         return ret;
  344. }
  345.  
  346. /**
  347.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  348.  *
  349.  * Not for i915G/i915GM
  350.  *
  351.  * \return true if CRT is connected.
  352.  * \return false if CRT is disconnected.
  353.  */
  354. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  355. {
  356.         struct drm_device *dev = connector->dev;
  357.         struct drm_i915_private *dev_priv = dev->dev_private;
  358.         u32 stat;
  359.         bool ret = false;
  360.         int i, tries = 0;
  361.  
  362.         if (HAS_PCH_SPLIT(dev))
  363.                 return intel_ironlake_crt_detect_hotplug(connector);
  364.  
  365.         if (IS_VALLEYVIEW(dev))
  366.                 return valleyview_crt_detect_hotplug(connector);
  367.  
  368.         /*
  369.          * On 4 series desktop, CRT detect sequence need to be done twice
  370.          * to get a reliable result.
  371.          */
  372.  
  373.         if (IS_G4X(dev) && !IS_GM45(dev))
  374.                 tries = 2;
  375.         else
  376.                 tries = 1;
  377.  
  378.         for (i = 0; i < tries ; i++) {
  379.                 /* turn on the FORCE_DETECT */
  380.                 i915_hotplug_interrupt_update(dev_priv,
  381.                                               CRT_HOTPLUG_FORCE_DETECT,
  382.                                               CRT_HOTPLUG_FORCE_DETECT);
  383.                 /* wait for FORCE_DETECT to go off */
  384.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  385.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  386.                              1000))
  387.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  388.         }
  389.  
  390.         stat = I915_READ(PORT_HOTPLUG_STAT);
  391.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  392.                 ret = true;
  393.  
  394.         /* clear the interrupt we just generated, if any */
  395.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  396.  
  397.         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
  398.  
  399.         return ret;
  400. }
  401.  
  402. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  403.                                 struct i2c_adapter *i2c)
  404. {
  405.         struct edid *edid;
  406.  
  407.         edid = drm_get_edid(connector, i2c);
  408.  
  409.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  410.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  411.                 intel_gmbus_force_bit(i2c, true);
  412.                 edid = drm_get_edid(connector, i2c);
  413.                 intel_gmbus_force_bit(i2c, false);
  414.         }
  415.  
  416.         return edid;
  417. }
  418.  
  419. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  420. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  421.                                 struct i2c_adapter *adapter)
  422. {
  423.         struct edid *edid;
  424.         int ret;
  425.  
  426.         edid = intel_crt_get_edid(connector, adapter);
  427.         if (!edid)
  428.                 return 0;
  429.  
  430.         ret = intel_connector_update_modes(connector, edid);
  431.         kfree(edid);
  432.  
  433.         return ret;
  434. }
  435.  
  436. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  437. {
  438.         struct intel_crt *crt = intel_attached_crt(connector);
  439.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  440.         struct edid *edid;
  441.         struct i2c_adapter *i2c;
  442.  
  443.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  444.  
  445.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  446.         edid = intel_crt_get_edid(connector, i2c);
  447.  
  448.         if (edid) {
  449.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  450.  
  451.                 /*
  452.                  * This may be a DVI-I connector with a shared DDC
  453.                  * link between analog and digital outputs, so we
  454.                  * have to check the EDID input spec of the attached device.
  455.                  */
  456.                 if (!is_digital) {
  457.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  458.                         return true;
  459.                 }
  460.  
  461.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  462.         } else {
  463.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  464.         }
  465.  
  466.         kfree(edid);
  467.  
  468.         return false;
  469. }
  470.  
  471. static enum drm_connector_status
  472. intel_crt_load_detect(struct intel_crt *crt)
  473. {
  474.         struct drm_device *dev = crt->base.base.dev;
  475.         struct drm_i915_private *dev_priv = dev->dev_private;
  476.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  477.         uint32_t save_bclrpat;
  478.         uint32_t save_vtotal;
  479.         uint32_t vtotal, vactive;
  480.         uint32_t vsample;
  481.         uint32_t vblank, vblank_start, vblank_end;
  482.         uint32_t dsl;
  483.         uint32_t bclrpat_reg;
  484.         uint32_t vtotal_reg;
  485.         uint32_t vblank_reg;
  486.         uint32_t vsync_reg;
  487.         uint32_t pipeconf_reg;
  488.         uint32_t pipe_dsl_reg;
  489.         uint8_t st00;
  490.         enum drm_connector_status status;
  491.  
  492.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  493.  
  494.         bclrpat_reg = BCLRPAT(pipe);
  495.         vtotal_reg = VTOTAL(pipe);
  496.         vblank_reg = VBLANK(pipe);
  497.         vsync_reg = VSYNC(pipe);
  498.         pipeconf_reg = PIPECONF(pipe);
  499.         pipe_dsl_reg = PIPEDSL(pipe);
  500.  
  501.         save_bclrpat = I915_READ(bclrpat_reg);
  502.         save_vtotal = I915_READ(vtotal_reg);
  503.         vblank = I915_READ(vblank_reg);
  504.  
  505.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  506.         vactive = (save_vtotal & 0x7ff) + 1;
  507.  
  508.         vblank_start = (vblank & 0xfff) + 1;
  509.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  510.  
  511.         /* Set the border color to purple. */
  512.         I915_WRITE(bclrpat_reg, 0x500050);
  513.  
  514.         if (!IS_GEN2(dev)) {
  515.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  516.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  517.                 POSTING_READ(pipeconf_reg);
  518.                 /* Wait for next Vblank to substitue
  519.                  * border color for Color info */
  520.                 intel_wait_for_vblank(dev, pipe);
  521.                 st00 = I915_READ8(VGA_MSR_WRITE);
  522.                 status = ((st00 & (1 << 4)) != 0) ?
  523.                         connector_status_connected :
  524.                         connector_status_disconnected;
  525.  
  526.                 I915_WRITE(pipeconf_reg, pipeconf);
  527.         } else {
  528.                 bool restore_vblank = false;
  529.                 int count, detect;
  530.  
  531.                 /*
  532.                 * If there isn't any border, add some.
  533.                 * Yes, this will flicker
  534.                 */
  535.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  536.                         uint32_t vsync = I915_READ(vsync_reg);
  537.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  538.  
  539.                         vblank_start = vsync_start;
  540.                         I915_WRITE(vblank_reg,
  541.                                    (vblank_start - 1) |
  542.                                    ((vblank_end - 1) << 16));
  543.                         restore_vblank = true;
  544.                 }
  545.                 /* sample in the vertical border, selecting the larger one */
  546.                 if (vblank_start - vactive >= vtotal - vblank_end)
  547.                         vsample = (vblank_start + vactive) >> 1;
  548.                 else
  549.                         vsample = (vtotal + vblank_end) >> 1;
  550.  
  551.                 /*
  552.                  * Wait for the border to be displayed
  553.                  */
  554.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  555.                         ;
  556.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  557.                         ;
  558.                 /*
  559.                  * Watch ST00 for an entire scanline
  560.                  */
  561.                 detect = 0;
  562.                 count = 0;
  563.                 do {
  564.                         count++;
  565.                         /* Read the ST00 VGA status register */
  566.                         st00 = I915_READ8(VGA_MSR_WRITE);
  567.                         if (st00 & (1 << 4))
  568.                                 detect++;
  569.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  570.  
  571.                 /* restore vblank if necessary */
  572.                 if (restore_vblank)
  573.                         I915_WRITE(vblank_reg, vblank);
  574.                 /*
  575.                  * If more than 3/4 of the scanline detected a monitor,
  576.                  * then it is assumed to be present. This works even on i830,
  577.                  * where there isn't any way to force the border color across
  578.                  * the screen
  579.                  */
  580.                 status = detect * 4 > count * 3 ?
  581.                          connector_status_connected :
  582.                          connector_status_disconnected;
  583.         }
  584.  
  585.         /* Restore previous settings */
  586.         I915_WRITE(bclrpat_reg, save_bclrpat);
  587.  
  588.         return status;
  589. }
  590.  
  591. static enum drm_connector_status
  592. intel_crt_detect(struct drm_connector *connector, bool force)
  593. {
  594.         struct drm_device *dev = connector->dev;
  595.         struct drm_i915_private *dev_priv = dev->dev_private;
  596.         struct intel_crt *crt = intel_attached_crt(connector);
  597.         struct intel_encoder *intel_encoder = &crt->base;
  598.         enum intel_display_power_domain power_domain;
  599.         enum drm_connector_status status;
  600.         struct intel_load_detect_pipe tmp;
  601.         struct drm_modeset_acquire_ctx ctx;
  602.  
  603.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
  604.                       connector->base.id, connector->name,
  605.                       force);
  606.  
  607.         power_domain = intel_display_port_power_domain(intel_encoder);
  608.         intel_display_power_get(dev_priv, power_domain);
  609.  
  610.         if (I915_HAS_HOTPLUG(dev)) {
  611.                 /* We can not rely on the HPD pin always being correctly wired
  612.                  * up, for example many KVM do not pass it through, and so
  613.                  * only trust an assertion that the monitor is connected.
  614.                  */
  615.                 if (intel_crt_detect_hotplug(connector)) {
  616.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  617.                         status = connector_status_connected;
  618.                         goto out;
  619.                 } else
  620.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  621.         }
  622.  
  623.         if (intel_crt_detect_ddc(connector)) {
  624.                 status = connector_status_connected;
  625.                 goto out;
  626.         }
  627.  
  628.         /* Load detection is broken on HPD capable machines. Whoever wants a
  629.          * broken monitor (without edid) to work behind a broken kvm (that fails
  630.          * to have the right resistors for HP detection) needs to fix this up.
  631.          * For now just bail out. */
  632.         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
  633.                 status = connector_status_disconnected;
  634.                 goto out;
  635.         }
  636.  
  637.         if (!force) {
  638.                 status = connector->status;
  639.                 goto out;
  640.         }
  641.  
  642.         drm_modeset_acquire_init(&ctx, 0);
  643.  
  644.         /* for pre-945g platforms use load detect */
  645.         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
  646.                 if (intel_crt_detect_ddc(connector))
  647.                         status = connector_status_connected;
  648.                 else if (INTEL_INFO(dev)->gen < 4)
  649.                         status = intel_crt_load_detect(crt);
  650.                 else
  651.                         status = connector_status_unknown;
  652.                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
  653.         } else
  654.                 status = connector_status_unknown;
  655.  
  656.         drm_modeset_drop_locks(&ctx);
  657.         drm_modeset_acquire_fini(&ctx);
  658.  
  659. out:
  660.         intel_display_power_put(dev_priv, power_domain);
  661.         return status;
  662. }
  663.  
  664. static void intel_crt_destroy(struct drm_connector *connector)
  665. {
  666.         drm_connector_cleanup(connector);
  667.         kfree(connector);
  668. }
  669.  
  670. static int intel_crt_get_modes(struct drm_connector *connector)
  671. {
  672.         struct drm_device *dev = connector->dev;
  673.         struct drm_i915_private *dev_priv = dev->dev_private;
  674.         struct intel_crt *crt = intel_attached_crt(connector);
  675.         struct intel_encoder *intel_encoder = &crt->base;
  676.         enum intel_display_power_domain power_domain;
  677.         int ret;
  678.         struct i2c_adapter *i2c;
  679.  
  680.         power_domain = intel_display_port_power_domain(intel_encoder);
  681.         intel_display_power_get(dev_priv, power_domain);
  682.  
  683.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  684.         ret = intel_crt_ddc_get_modes(connector, i2c);
  685.         if (ret || !IS_G4X(dev))
  686.                 goto out;
  687.  
  688.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  689.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
  690.         ret = intel_crt_ddc_get_modes(connector, i2c);
  691.  
  692. out:
  693.         intel_display_power_put(dev_priv, power_domain);
  694.  
  695.         return ret;
  696. }
  697.  
  698. static int intel_crt_set_property(struct drm_connector *connector,
  699.                                   struct drm_property *property,
  700.                                   uint64_t value)
  701. {
  702.         return 0;
  703. }
  704.  
  705. static void intel_crt_reset(struct drm_connector *connector)
  706. {
  707.         struct drm_device *dev = connector->dev;
  708.         struct drm_i915_private *dev_priv = dev->dev_private;
  709.         struct intel_crt *crt = intel_attached_crt(connector);
  710.  
  711.         if (INTEL_INFO(dev)->gen >= 5) {
  712.                 u32 adpa;
  713.  
  714.                 adpa = I915_READ(crt->adpa_reg);
  715.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  716.                 adpa |= ADPA_HOTPLUG_BITS;
  717.                 I915_WRITE(crt->adpa_reg, adpa);
  718.                 POSTING_READ(crt->adpa_reg);
  719.  
  720.                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
  721.                 crt->force_hotplug_required = 1;
  722.         }
  723.  
  724. }
  725.  
  726. /*
  727.  * Routines for controlling stuff on the analog port
  728.  */
  729.  
  730. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  731.         .reset = intel_crt_reset,
  732.         .dpms = drm_atomic_helper_connector_dpms,
  733.         .detect = intel_crt_detect,
  734.         .fill_modes = drm_helper_probe_single_connector_modes,
  735.         .destroy = intel_crt_destroy,
  736.         .set_property = intel_crt_set_property,
  737.         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  738.         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  739.         .atomic_get_property = intel_connector_atomic_get_property,
  740. };
  741.  
  742. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  743.         .mode_valid = intel_crt_mode_valid,
  744.         .get_modes = intel_crt_get_modes,
  745.         .best_encoder = intel_best_encoder,
  746. };
  747.  
  748. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  749.         .destroy = intel_encoder_destroy,
  750. };
  751.  
  752. static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  753. {
  754.         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  755.         return 1;
  756. }
  757.  
  758. static const struct dmi_system_id intel_no_crt[] = {
  759.         {
  760.                 .callback = intel_no_crt_dmi_callback,
  761.                 .ident = "ACER ZGB",
  762.                 .matches = {
  763.                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  764.                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  765.                 },
  766.         },
  767.         {
  768.                 .callback = intel_no_crt_dmi_callback,
  769.                 .ident = "DELL XPS 8700",
  770.                 .matches = {
  771.                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  772.                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
  773.                 },
  774.         },
  775.         { }
  776. };
  777.  
  778. void intel_crt_init(struct drm_device *dev)
  779. {
  780.         struct drm_connector *connector;
  781.         struct intel_crt *crt;
  782.         struct intel_connector *intel_connector;
  783.         struct drm_i915_private *dev_priv = dev->dev_private;
  784.  
  785.         /* Skip machines without VGA that falsely report hotplug events */
  786.         if (dmi_check_system(intel_no_crt))
  787.                 return;
  788.  
  789.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  790.         if (!crt)
  791.                 return;
  792.  
  793.         intel_connector = intel_connector_alloc();
  794.         if (!intel_connector) {
  795.                 kfree(crt);
  796.                 return;
  797.         }
  798.  
  799.         connector = &intel_connector->base;
  800.         crt->connector = intel_connector;
  801.         drm_connector_init(dev, &intel_connector->base,
  802.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  803.  
  804.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  805.                          DRM_MODE_ENCODER_DAC);
  806.  
  807.         intel_connector_attach_encoder(intel_connector, &crt->base);
  808.  
  809.         crt->base.type = INTEL_OUTPUT_ANALOG;
  810.         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
  811.         if (IS_I830(dev))
  812.                 crt->base.crtc_mask = (1 << 0);
  813.         else
  814.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  815.  
  816.         if (IS_GEN2(dev))
  817.                 connector->interlace_allowed = 0;
  818.         else
  819.                 connector->interlace_allowed = 1;
  820.         connector->doublescan_allowed = 0;
  821.  
  822.         if (HAS_PCH_SPLIT(dev))
  823.                 crt->adpa_reg = PCH_ADPA;
  824.         else if (IS_VALLEYVIEW(dev))
  825.                 crt->adpa_reg = VLV_ADPA;
  826.         else
  827.                 crt->adpa_reg = ADPA;
  828.  
  829.         crt->base.compute_config = intel_crt_compute_config;
  830.         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
  831.                 crt->base.disable = pch_disable_crt;
  832.                 crt->base.post_disable = pch_post_disable_crt;
  833.         } else {
  834.                 crt->base.disable = intel_disable_crt;
  835.         }
  836.         crt->base.enable = intel_enable_crt;
  837.         if (I915_HAS_HOTPLUG(dev))
  838.                 crt->base.hpd_pin = HPD_CRT;
  839.         if (HAS_DDI(dev)) {
  840.                 crt->base.get_config = hsw_crt_get_config;
  841.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  842.         } else {
  843.                 crt->base.get_config = intel_crt_get_config;
  844.                 crt->base.get_hw_state = intel_crt_get_hw_state;
  845.         }
  846.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  847.         intel_connector->unregister = intel_connector_unregister;
  848.  
  849.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  850.  
  851.         drm_connector_register(connector);
  852.  
  853.         if (!I915_HAS_HOTPLUG(dev))
  854.                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  855.  
  856.         /*
  857.          * Configure the automatic hotplug detection stuff
  858.          */
  859.         crt->force_hotplug_required = 0;
  860.  
  861.         /*
  862.          * TODO: find a proper way to discover whether we need to set the the
  863.          * polarity and link reversal bits or not, instead of relying on the
  864.          * BIOS.
  865.          */
  866.         if (HAS_PCH_LPT(dev)) {
  867.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  868.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  869.  
  870.                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
  871.         }
  872.  
  873.         intel_crt_reset(connector);
  874. }
  875.