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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43.                            ADPA_CRT_HOTPLUG_ENABLE)
  44.  
  45. struct intel_crt {
  46.         struct intel_encoder base;
  47.         /* DPMS state is stored in the connector, which we need in the
  48.          * encoder's enable/disable callbacks */
  49.         struct intel_connector *connector;
  50.         bool force_hotplug_required;
  51.         u32 adpa_reg;
  52. };
  53.  
  54. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  55. {
  56.         return container_of(encoder, struct intel_crt, base);
  57. }
  58.  
  59. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  60. {
  61.         return intel_encoder_to_crt(intel_attached_encoder(connector));
  62. }
  63.  
  64. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  65.                                    enum pipe *pipe)
  66. {
  67.         struct drm_device *dev = encoder->base.dev;
  68.         struct drm_i915_private *dev_priv = dev->dev_private;
  69.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  70.         u32 tmp;
  71.  
  72.         tmp = I915_READ(crt->adpa_reg);
  73.  
  74.         if (!(tmp & ADPA_DAC_ENABLE))
  75.                 return false;
  76.  
  77.         if (HAS_PCH_CPT(dev))
  78.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  79.         else
  80.                 *pipe = PORT_TO_PIPE(tmp);
  81.  
  82.         return true;
  83. }
  84.  
  85. static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  86. {
  87.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  88.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  89.         u32 tmp, flags = 0;
  90.  
  91.         tmp = I915_READ(crt->adpa_reg);
  92.  
  93.         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  94.                 flags |= DRM_MODE_FLAG_PHSYNC;
  95.         else
  96.                 flags |= DRM_MODE_FLAG_NHSYNC;
  97.  
  98.         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
  99.                 flags |= DRM_MODE_FLAG_PVSYNC;
  100.         else
  101.                 flags |= DRM_MODE_FLAG_NVSYNC;
  102.  
  103.         return flags;
  104. }
  105.  
  106. static void intel_crt_get_config(struct intel_encoder *encoder,
  107.                                  struct intel_crtc_config *pipe_config)
  108. {
  109.         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
  110. }
  111.  
  112. static void hsw_crt_get_config(struct intel_encoder *encoder,
  113.                                struct intel_crtc_config *pipe_config)
  114. {
  115.         intel_ddi_get_config(encoder, pipe_config);
  116.  
  117.         pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
  118.                                               DRM_MODE_FLAG_NHSYNC |
  119.                                               DRM_MODE_FLAG_PVSYNC |
  120.                                               DRM_MODE_FLAG_NVSYNC);
  121.         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
  122. }
  123.  
  124. /* Note: The caller is required to filter out dpms modes not supported by the
  125.  * platform. */
  126. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  127. {
  128.         struct drm_device *dev = encoder->base.dev;
  129.         struct drm_i915_private *dev_priv = dev->dev_private;
  130.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  131.         u32 temp;
  132.  
  133.         temp = I915_READ(crt->adpa_reg);
  134.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  135.         temp &= ~ADPA_DAC_ENABLE;
  136.  
  137.         switch (mode) {
  138.         case DRM_MODE_DPMS_ON:
  139.                 temp |= ADPA_DAC_ENABLE;
  140.                 break;
  141.         case DRM_MODE_DPMS_STANDBY:
  142.                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  143.                 break;
  144.         case DRM_MODE_DPMS_SUSPEND:
  145.                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  146.                 break;
  147.         case DRM_MODE_DPMS_OFF:
  148.                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  149.                 break;
  150.         }
  151.  
  152.         I915_WRITE(crt->adpa_reg, temp);
  153. }
  154.  
  155. static void intel_disable_crt(struct intel_encoder *encoder)
  156. {
  157.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  158. }
  159.  
  160. static void intel_enable_crt(struct intel_encoder *encoder)
  161. {
  162.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  163.  
  164.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  165. }
  166.  
  167. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  168. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  169. {
  170.         struct drm_device *dev = connector->dev;
  171.         struct intel_encoder *encoder = intel_attached_encoder(connector);
  172.         struct drm_crtc *crtc;
  173.         int old_dpms;
  174.  
  175.         /* PCH platforms and VLV only support on/off. */
  176.         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  177.                 mode = DRM_MODE_DPMS_OFF;
  178.  
  179.         if (mode == connector->dpms)
  180.                 return;
  181.  
  182.         old_dpms = connector->dpms;
  183.         connector->dpms = mode;
  184.  
  185.         /* Only need to change hw state when actually enabled */
  186.         crtc = encoder->base.crtc;
  187.         if (!crtc) {
  188.                 encoder->connectors_active = false;
  189.                 return;
  190.         }
  191.  
  192.         /* We need the pipe to run for anything but OFF. */
  193.         if (mode == DRM_MODE_DPMS_OFF)
  194.                 encoder->connectors_active = false;
  195.         else
  196.                 encoder->connectors_active = true;
  197.  
  198.         /* We call connector dpms manually below in case pipe dpms doesn't
  199.          * change due to cloning. */
  200.         if (mode < old_dpms) {
  201.                 /* From off to on, enable the pipe first. */
  202.                 intel_crtc_update_dpms(crtc);
  203.  
  204.                 intel_crt_set_dpms(encoder, mode);
  205.         } else {
  206.                 intel_crt_set_dpms(encoder, mode);
  207.  
  208.                 intel_crtc_update_dpms(crtc);
  209.         }
  210.  
  211.         intel_modeset_check_state(connector->dev);
  212. }
  213.  
  214. static int intel_crt_mode_valid(struct drm_connector *connector,
  215.                                 struct drm_display_mode *mode)
  216. {
  217.         struct drm_device *dev = connector->dev;
  218.  
  219.         int max_clock = 0;
  220.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  221.                 return MODE_NO_DBLESCAN;
  222.  
  223.         if (mode->clock < 25000)
  224.                 return MODE_CLOCK_LOW;
  225.  
  226.         if (IS_GEN2(dev))
  227.                 max_clock = 350000;
  228.         else
  229.                 max_clock = 400000;
  230.         if (mode->clock > max_clock)
  231.                 return MODE_CLOCK_HIGH;
  232.  
  233.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  234.         if (HAS_PCH_LPT(dev) &&
  235.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  236.                 return MODE_CLOCK_HIGH;
  237.  
  238.         return MODE_OK;
  239. }
  240.  
  241. static bool intel_crt_compute_config(struct intel_encoder *encoder,
  242.                                      struct intel_crtc_config *pipe_config)
  243. {
  244.         struct drm_device *dev = encoder->base.dev;
  245.  
  246.         if (HAS_PCH_SPLIT(dev))
  247.                 pipe_config->has_pch_encoder = true;
  248.  
  249.         /* LPT FDI RX only supports 8bpc. */
  250.         if (HAS_PCH_LPT(dev))
  251.                 pipe_config->pipe_bpp = 24;
  252.  
  253.         return true;
  254. }
  255.  
  256. static void intel_crt_mode_set(struct intel_encoder *encoder)
  257. {
  258.  
  259.         struct drm_device *dev = encoder->base.dev;
  260.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  261.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  262.         struct drm_i915_private *dev_priv = dev->dev_private;
  263.         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  264.         u32 adpa;
  265.  
  266.         if (HAS_PCH_SPLIT(dev))
  267.         adpa = ADPA_HOTPLUG_BITS;
  268.         else
  269.                 adpa = 0;
  270.  
  271.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  272.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  273.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  274.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  275.  
  276.         /* For CPT allow 3 pipe config, for others just use A or B */
  277.         if (HAS_PCH_LPT(dev))
  278.                 ; /* Those bits don't exist here */
  279.         else if (HAS_PCH_CPT(dev))
  280.                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
  281.         else if (crtc->pipe == 0)
  282.                         adpa |= ADPA_PIPE_A_SELECT;
  283.                 else
  284.                         adpa |= ADPA_PIPE_B_SELECT;
  285.  
  286.         if (!HAS_PCH_SPLIT(dev))
  287.                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
  288.  
  289.         I915_WRITE(crt->adpa_reg, adpa);
  290. }
  291.  
  292. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  293. {
  294.         struct drm_device *dev = connector->dev;
  295.         struct intel_crt *crt = intel_attached_crt(connector);
  296.         struct drm_i915_private *dev_priv = dev->dev_private;
  297.         u32 adpa;
  298.         bool ret;
  299.  
  300.         /* The first time through, trigger an explicit detection cycle */
  301.         if (crt->force_hotplug_required) {
  302.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  303.                 u32 save_adpa;
  304.  
  305.                 crt->force_hotplug_required = 0;
  306.  
  307.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  308.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  309.  
  310.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  311.                 if (turn_off_dac)
  312.                         adpa &= ~ADPA_DAC_ENABLE;
  313.  
  314.                 I915_WRITE(crt->adpa_reg, adpa);
  315.  
  316.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  317.                              1000))
  318.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  319.  
  320.                 if (turn_off_dac) {
  321.                         I915_WRITE(crt->adpa_reg, save_adpa);
  322.                         POSTING_READ(crt->adpa_reg);
  323.                 }
  324.         }
  325.  
  326.         /* Check the status to see if both blue and green are on now */
  327.         adpa = I915_READ(crt->adpa_reg);
  328.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  329.                 ret = true;
  330.         else
  331.                 ret = false;
  332.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  333.  
  334.         return ret;
  335. }
  336.  
  337. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  338. {
  339.         struct drm_device *dev = connector->dev;
  340.         struct intel_crt *crt = intel_attached_crt(connector);
  341.         struct drm_i915_private *dev_priv = dev->dev_private;
  342.         u32 adpa;
  343.         bool ret;
  344.         u32 save_adpa;
  345.  
  346.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  347.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  348.  
  349.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  350.  
  351.         I915_WRITE(crt->adpa_reg, adpa);
  352.  
  353.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  354.                      1000)) {
  355.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  356.                 I915_WRITE(crt->adpa_reg, save_adpa);
  357.         }
  358.  
  359.         /* Check the status to see if both blue and green are on now */
  360.         adpa = I915_READ(crt->adpa_reg);
  361.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  362.                 ret = true;
  363.         else
  364.                 ret = false;
  365.  
  366.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  367.  
  368.         /* FIXME: debug force function and remove */
  369.         ret = true;
  370.  
  371.         return ret;
  372. }
  373.  
  374. /**
  375.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  376.  *
  377.  * Not for i915G/i915GM
  378.  *
  379.  * \return true if CRT is connected.
  380.  * \return false if CRT is disconnected.
  381.  */
  382. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  383. {
  384.         struct drm_device *dev = connector->dev;
  385.         struct drm_i915_private *dev_priv = dev->dev_private;
  386.         u32 hotplug_en, orig, stat;
  387.         bool ret = false;
  388.         int i, tries = 0;
  389.  
  390.         if (HAS_PCH_SPLIT(dev))
  391.                 return intel_ironlake_crt_detect_hotplug(connector);
  392.  
  393.         if (IS_VALLEYVIEW(dev))
  394.                 return valleyview_crt_detect_hotplug(connector);
  395.  
  396.         /*
  397.          * On 4 series desktop, CRT detect sequence need to be done twice
  398.          * to get a reliable result.
  399.          */
  400.  
  401.         if (IS_G4X(dev) && !IS_GM45(dev))
  402.                 tries = 2;
  403.         else
  404.                 tries = 1;
  405.         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  406.         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  407.  
  408.         for (i = 0; i < tries ; i++) {
  409.                 /* turn on the FORCE_DETECT */
  410.                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  411.                 /* wait for FORCE_DETECT to go off */
  412.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  413.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  414.                              1000))
  415.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  416.         }
  417.  
  418.         stat = I915_READ(PORT_HOTPLUG_STAT);
  419.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  420.                 ret = true;
  421.  
  422.         /* clear the interrupt we just generated, if any */
  423.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  424.  
  425.         /* and put the bits back */
  426.         I915_WRITE(PORT_HOTPLUG_EN, orig);
  427.  
  428.         return ret;
  429. }
  430.  
  431. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  432.                                 struct i2c_adapter *i2c)
  433. {
  434.         struct edid *edid;
  435.  
  436.         edid = drm_get_edid(connector, i2c);
  437.  
  438.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  439.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  440.                 intel_gmbus_force_bit(i2c, true);
  441.                 edid = drm_get_edid(connector, i2c);
  442.                 intel_gmbus_force_bit(i2c, false);
  443.         }
  444.  
  445.         return edid;
  446. }
  447.  
  448. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  449. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  450.                                 struct i2c_adapter *adapter)
  451. {
  452.         struct edid *edid;
  453.         int ret;
  454.  
  455.         edid = intel_crt_get_edid(connector, adapter);
  456.         if (!edid)
  457.                 return 0;
  458.  
  459.         ret = intel_connector_update_modes(connector, edid);
  460.         kfree(edid);
  461.  
  462.         return ret;
  463. }
  464.  
  465. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  466. {
  467.         struct intel_crt *crt = intel_attached_crt(connector);
  468.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  469.         struct edid *edid;
  470.         struct i2c_adapter *i2c;
  471.  
  472.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  473.  
  474.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  475.         edid = intel_crt_get_edid(connector, i2c);
  476.  
  477.         if (edid) {
  478.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  479.  
  480.                 /*
  481.                  * This may be a DVI-I connector with a shared DDC
  482.                  * link between analog and digital outputs, so we
  483.                  * have to check the EDID input spec of the attached device.
  484.                  */
  485.                 if (!is_digital) {
  486.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  487.                         return true;
  488.                 }
  489.  
  490.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  491.                 } else {
  492.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  493.                 }
  494.  
  495.         kfree(edid);
  496.  
  497.         return false;
  498. }
  499.  
  500. static enum drm_connector_status
  501. intel_crt_load_detect(struct intel_crt *crt)
  502. {
  503.         struct drm_device *dev = crt->base.base.dev;
  504.         struct drm_i915_private *dev_priv = dev->dev_private;
  505.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  506.         uint32_t save_bclrpat;
  507.         uint32_t save_vtotal;
  508.         uint32_t vtotal, vactive;
  509.         uint32_t vsample;
  510.         uint32_t vblank, vblank_start, vblank_end;
  511.         uint32_t dsl;
  512.         uint32_t bclrpat_reg;
  513.         uint32_t vtotal_reg;
  514.         uint32_t vblank_reg;
  515.         uint32_t vsync_reg;
  516.         uint32_t pipeconf_reg;
  517.         uint32_t pipe_dsl_reg;
  518.         uint8_t st00;
  519.         enum drm_connector_status status;
  520.  
  521.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  522.  
  523.         bclrpat_reg = BCLRPAT(pipe);
  524.         vtotal_reg = VTOTAL(pipe);
  525.         vblank_reg = VBLANK(pipe);
  526.         vsync_reg = VSYNC(pipe);
  527.         pipeconf_reg = PIPECONF(pipe);
  528.         pipe_dsl_reg = PIPEDSL(pipe);
  529.  
  530.         save_bclrpat = I915_READ(bclrpat_reg);
  531.         save_vtotal = I915_READ(vtotal_reg);
  532.         vblank = I915_READ(vblank_reg);
  533.  
  534.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  535.         vactive = (save_vtotal & 0x7ff) + 1;
  536.  
  537.         vblank_start = (vblank & 0xfff) + 1;
  538.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  539.  
  540.         /* Set the border color to purple. */
  541.         I915_WRITE(bclrpat_reg, 0x500050);
  542.  
  543.         if (!IS_GEN2(dev)) {
  544.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  545.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  546.                 POSTING_READ(pipeconf_reg);
  547.                 /* Wait for next Vblank to substitue
  548.                  * border color for Color info */
  549.                 intel_wait_for_vblank(dev, pipe);
  550.                 st00 = I915_READ8(VGA_MSR_WRITE);
  551.                 status = ((st00 & (1 << 4)) != 0) ?
  552.                         connector_status_connected :
  553.                         connector_status_disconnected;
  554.  
  555.                 I915_WRITE(pipeconf_reg, pipeconf);
  556.         } else {
  557.                 bool restore_vblank = false;
  558.                 int count, detect;
  559.  
  560.                 /*
  561.                 * If there isn't any border, add some.
  562.                 * Yes, this will flicker
  563.                 */
  564.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  565.                         uint32_t vsync = I915_READ(vsync_reg);
  566.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  567.  
  568.                         vblank_start = vsync_start;
  569.                         I915_WRITE(vblank_reg,
  570.                                    (vblank_start - 1) |
  571.                                    ((vblank_end - 1) << 16));
  572.                         restore_vblank = true;
  573.                 }
  574.                 /* sample in the vertical border, selecting the larger one */
  575.                 if (vblank_start - vactive >= vtotal - vblank_end)
  576.                         vsample = (vblank_start + vactive) >> 1;
  577.                 else
  578.                         vsample = (vtotal + vblank_end) >> 1;
  579.  
  580.                 /*
  581.                  * Wait for the border to be displayed
  582.                  */
  583.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  584.                         ;
  585.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  586.                         ;
  587.                 /*
  588.                  * Watch ST00 for an entire scanline
  589.                  */
  590.                 detect = 0;
  591.                 count = 0;
  592.                 do {
  593.                         count++;
  594.                         /* Read the ST00 VGA status register */
  595.                         st00 = I915_READ8(VGA_MSR_WRITE);
  596.                         if (st00 & (1 << 4))
  597.                                 detect++;
  598.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  599.  
  600.                 /* restore vblank if necessary */
  601.                 if (restore_vblank)
  602.                         I915_WRITE(vblank_reg, vblank);
  603.                 /*
  604.                  * If more than 3/4 of the scanline detected a monitor,
  605.                  * then it is assumed to be present. This works even on i830,
  606.                  * where there isn't any way to force the border color across
  607.                  * the screen
  608.                  */
  609.                 status = detect * 4 > count * 3 ?
  610.                          connector_status_connected :
  611.                          connector_status_disconnected;
  612.         }
  613.  
  614.         /* Restore previous settings */
  615.         I915_WRITE(bclrpat_reg, save_bclrpat);
  616.  
  617.         return status;
  618. }
  619.  
  620. static enum drm_connector_status
  621. intel_crt_detect(struct drm_connector *connector, bool force)
  622. {
  623.         struct drm_device *dev = connector->dev;
  624.         struct intel_crt *crt = intel_attached_crt(connector);
  625.         enum drm_connector_status status;
  626.         struct intel_load_detect_pipe tmp;
  627.  
  628.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
  629.                       connector->base.id, drm_get_connector_name(connector),
  630.                       force);
  631.  
  632.         if (I915_HAS_HOTPLUG(dev)) {
  633.                 /* We can not rely on the HPD pin always being correctly wired
  634.                  * up, for example many KVM do not pass it through, and so
  635.                  * only trust an assertion that the monitor is connected.
  636.                  */
  637.                 if (intel_crt_detect_hotplug(connector)) {
  638.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  639.                         return connector_status_connected;
  640.                 } else
  641.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  642.         }
  643.  
  644.         if (intel_crt_detect_ddc(connector))
  645.                 return connector_status_connected;
  646.  
  647.         /* Load detection is broken on HPD capable machines. Whoever wants a
  648.          * broken monitor (without edid) to work behind a broken kvm (that fails
  649.          * to have the right resistors for HP detection) needs to fix this up.
  650.          * For now just bail out. */
  651.         if (I915_HAS_HOTPLUG(dev))
  652.                 return connector_status_disconnected;
  653.  
  654.         if (!force)
  655.                 return connector->status;
  656.  
  657.         /* for pre-945g platforms use load detect */
  658.         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  659.                         if (intel_crt_detect_ddc(connector))
  660.                                 status = connector_status_connected;
  661.                         else
  662.                                 status = intel_crt_load_detect(crt);
  663.                 intel_release_load_detect_pipe(connector, &tmp);
  664.                 } else
  665.                         status = connector_status_unknown;
  666.  
  667.         return status;
  668. }
  669.  
  670. static void intel_crt_destroy(struct drm_connector *connector)
  671. {
  672.         drm_sysfs_connector_remove(connector);
  673.         drm_connector_cleanup(connector);
  674.         kfree(connector);
  675. }
  676.  
  677. static int intel_crt_get_modes(struct drm_connector *connector)
  678. {
  679.         struct drm_device *dev = connector->dev;
  680.         struct drm_i915_private *dev_priv = dev->dev_private;
  681.         int ret;
  682.         struct i2c_adapter *i2c;
  683.  
  684.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  685.         ret = intel_crt_ddc_get_modes(connector, i2c);
  686.         if (ret || !IS_G4X(dev))
  687.                 return ret;
  688.  
  689.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  690.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  691.         return intel_crt_ddc_get_modes(connector, i2c);
  692. }
  693.  
  694. static int intel_crt_set_property(struct drm_connector *connector,
  695.                                   struct drm_property *property,
  696.                                   uint64_t value)
  697. {
  698.         return 0;
  699. }
  700.  
  701. static void intel_crt_reset(struct drm_connector *connector)
  702. {
  703.         struct drm_device *dev = connector->dev;
  704.         struct drm_i915_private *dev_priv = dev->dev_private;
  705.         struct intel_crt *crt = intel_attached_crt(connector);
  706.  
  707.         if (INTEL_INFO(dev)->gen >= 5) {
  708.                 u32 adpa;
  709.  
  710.                 adpa = I915_READ(crt->adpa_reg);
  711.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  712.                 adpa |= ADPA_HOTPLUG_BITS;
  713.                 I915_WRITE(crt->adpa_reg, adpa);
  714.                 POSTING_READ(crt->adpa_reg);
  715.  
  716.                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  717.                 crt->force_hotplug_required = 1;
  718.         }
  719.  
  720. }
  721.  
  722. /*
  723.  * Routines for controlling stuff on the analog port
  724.  */
  725.  
  726. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  727.         .reset = intel_crt_reset,
  728.         .dpms = intel_crt_dpms,
  729.         .detect = intel_crt_detect,
  730.         .fill_modes = drm_helper_probe_single_connector_modes,
  731.         .destroy = intel_crt_destroy,
  732.         .set_property = intel_crt_set_property,
  733. };
  734.  
  735. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  736.         .mode_valid = intel_crt_mode_valid,
  737.         .get_modes = intel_crt_get_modes,
  738.         .best_encoder = intel_best_encoder,
  739. };
  740.  
  741. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  742.         .destroy = intel_encoder_destroy,
  743. };
  744.  
  745. void intel_crt_init(struct drm_device *dev)
  746. {
  747.         struct drm_connector *connector;
  748.         struct intel_crt *crt;
  749.         struct intel_connector *intel_connector;
  750.         struct drm_i915_private *dev_priv = dev->dev_private;
  751.  
  752.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  753.         if (!crt)
  754.                 return;
  755.  
  756.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  757.         if (!intel_connector) {
  758.                 kfree(crt);
  759.                 return;
  760.         }
  761.  
  762.         connector = &intel_connector->base;
  763.         crt->connector = intel_connector;
  764.         drm_connector_init(dev, &intel_connector->base,
  765.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  766.  
  767.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  768.                          DRM_MODE_ENCODER_DAC);
  769.  
  770.         intel_connector_attach_encoder(intel_connector, &crt->base);
  771.  
  772.         crt->base.type = INTEL_OUTPUT_ANALOG;
  773.         crt->base.cloneable = true;
  774.         if (IS_I830(dev))
  775.                 crt->base.crtc_mask = (1 << 0);
  776.         else
  777.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  778.  
  779.         if (IS_GEN2(dev))
  780.                 connector->interlace_allowed = 0;
  781.         else
  782.         connector->interlace_allowed = 1;
  783.         connector->doublescan_allowed = 0;
  784.  
  785.         if (HAS_PCH_SPLIT(dev))
  786.                 crt->adpa_reg = PCH_ADPA;
  787.         else if (IS_VALLEYVIEW(dev))
  788.                 crt->adpa_reg = VLV_ADPA;
  789.         else
  790.                 crt->adpa_reg = ADPA;
  791.  
  792.         crt->base.compute_config = intel_crt_compute_config;
  793.         crt->base.mode_set = intel_crt_mode_set;
  794.         crt->base.disable = intel_disable_crt;
  795.         crt->base.enable = intel_enable_crt;
  796.         if (IS_HASWELL(dev))
  797.                 crt->base.get_config = hsw_crt_get_config;
  798.         else
  799.         crt->base.get_config = intel_crt_get_config;
  800.         if (I915_HAS_HOTPLUG(dev))
  801.                 crt->base.hpd_pin = HPD_CRT;
  802.         if (HAS_DDI(dev))
  803.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  804.         else
  805.         crt->base.get_hw_state = intel_crt_get_hw_state;
  806.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  807.  
  808.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  809.  
  810.         drm_sysfs_connector_add(connector);
  811.  
  812.         if (!I915_HAS_HOTPLUG(dev))
  813.                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  814.  
  815.         /*
  816.          * Configure the automatic hotplug detection stuff
  817.          */
  818.         crt->force_hotplug_required = 0;
  819.  
  820.         /*
  821.          * TODO: find a proper way to discover whether we need to set the the
  822.          * polarity and link reversal bits or not, instead of relying on the
  823.          * BIOS.
  824.          */
  825.         if (HAS_PCH_LPT(dev)) {
  826.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  827.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  828.  
  829.                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
  830.         }
  831. }
  832.