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  1. /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  2.  * All Rights Reserved.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  */
  24.  
  25. #ifndef _I915_REG_H_
  26. #define _I915_REG_H_
  27.  
  28. #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
  29. #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
  30.  
  31. #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
  32.  
  33. #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
  34. #define _MASKED_BIT_DISABLE(a) ((a) << 16)
  35.  
  36. /*
  37.  * The Bridge device's PCI config space has information about the
  38.  * fb aperture size and the amount of pre-reserved memory.
  39.  * This is all handled in the intel-gtt.ko module. i915.ko only
  40.  * cares about the vga bit for the vga rbiter.
  41.  */
  42. #define INTEL_GMCH_CTRL         0x52
  43. #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
  44. #define SNB_GMCH_CTRL           0x50
  45. #define    SNB_GMCH_GGMS_SHIFT  8 /* GTT Graphics Memory Size */
  46. #define    SNB_GMCH_GGMS_MASK   0x3
  47. #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
  48. #define    SNB_GMCH_GMS_MASK    0x1f
  49. #define    IVB_GMCH_GMS_SHIFT   4
  50. #define    IVB_GMCH_GMS_MASK    0xf
  51.  
  52.  
  53. /* PCI config space */
  54.  
  55. #define HPLLCC  0xc0 /* 855 only */
  56. #define   GC_CLOCK_CONTROL_MASK         (0xf << 0)
  57. #define   GC_CLOCK_133_200              (0 << 0)
  58. #define   GC_CLOCK_100_200              (1 << 0)
  59. #define   GC_CLOCK_100_133              (2 << 0)
  60. #define   GC_CLOCK_166_250              (3 << 0)
  61. #define GCFGC2  0xda
  62. #define GCFGC   0xf0 /* 915+ only */
  63. #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
  64. #define   GC_DISPLAY_CLOCK_190_200_MHZ  (0 << 4)
  65. #define   GC_DISPLAY_CLOCK_333_MHZ      (4 << 4)
  66. #define   GC_DISPLAY_CLOCK_MASK         (7 << 4)
  67. #define   GM45_GC_RENDER_CLOCK_MASK     (0xf << 0)
  68. #define   GM45_GC_RENDER_CLOCK_266_MHZ  (8 << 0)
  69. #define   GM45_GC_RENDER_CLOCK_320_MHZ  (9 << 0)
  70. #define   GM45_GC_RENDER_CLOCK_400_MHZ  (0xb << 0)
  71. #define   GM45_GC_RENDER_CLOCK_533_MHZ  (0xc << 0)
  72. #define   I965_GC_RENDER_CLOCK_MASK     (0xf << 0)
  73. #define   I965_GC_RENDER_CLOCK_267_MHZ  (2 << 0)
  74. #define   I965_GC_RENDER_CLOCK_333_MHZ  (3 << 0)
  75. #define   I965_GC_RENDER_CLOCK_444_MHZ  (4 << 0)
  76. #define   I965_GC_RENDER_CLOCK_533_MHZ  (5 << 0)
  77. #define   I945_GC_RENDER_CLOCK_MASK     (7 << 0)
  78. #define   I945_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
  79. #define   I945_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
  80. #define   I945_GC_RENDER_CLOCK_250_MHZ  (3 << 0)
  81. #define   I945_GC_RENDER_CLOCK_400_MHZ  (5 << 0)
  82. #define   I915_GC_RENDER_CLOCK_MASK     (7 << 0)
  83. #define   I915_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
  84. #define   I915_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
  85. #define   I915_GC_RENDER_CLOCK_333_MHZ  (4 << 0)
  86. #define LBB     0xf4
  87.  
  88. /* Graphics reset regs */
  89. #define I965_GDRST 0xc0 /* PCI config register */
  90. #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
  91. #define  GRDOM_FULL     (0<<2)
  92. #define  GRDOM_RENDER   (1<<2)
  93. #define  GRDOM_MEDIA    (3<<2)
  94. #define  GRDOM_RESET_ENABLE (1<<0)
  95.  
  96. #define GEN6_MBCUNIT_SNPCR      0x900c /* for LLC config */
  97. #define   GEN6_MBC_SNPCR_SHIFT  21
  98. #define   GEN6_MBC_SNPCR_MASK   (3<<21)
  99. #define   GEN6_MBC_SNPCR_MAX    (0<<21)
  100. #define   GEN6_MBC_SNPCR_MED    (1<<21)
  101. #define   GEN6_MBC_SNPCR_LOW    (2<<21)
  102. #define   GEN6_MBC_SNPCR_MIN    (3<<21) /* only 1/16th of the cache is shared */
  103.  
  104. #define GEN6_MBCTL              0x0907c
  105. #define   GEN6_MBCTL_ENABLE_BOOT_FETCH  (1 << 4)
  106. #define   GEN6_MBCTL_CTX_FETCH_NEEDED   (1 << 3)
  107. #define   GEN6_MBCTL_BME_UPDATE_ENABLE  (1 << 2)
  108. #define   GEN6_MBCTL_MAE_UPDATE_ENABLE  (1 << 1)
  109. #define   GEN6_MBCTL_BOOT_FETCH_MECH    (1 << 0)
  110.  
  111. #define GEN6_GDRST      0x941c
  112. #define  GEN6_GRDOM_FULL                (1 << 0)
  113. #define  GEN6_GRDOM_RENDER              (1 << 1)
  114. #define  GEN6_GRDOM_MEDIA               (1 << 2)
  115. #define  GEN6_GRDOM_BLT                 (1 << 3)
  116.  
  117. #define RING_PP_DIR_BASE(ring)          ((ring)->mmio_base+0x228)
  118. #define RING_PP_DIR_BASE_READ(ring)     ((ring)->mmio_base+0x518)
  119. #define RING_PP_DIR_DCLV(ring)          ((ring)->mmio_base+0x220)
  120. #define   PP_DIR_DCLV_2G                0xffffffff
  121.  
  122. #define GAM_ECOCHK                      0x4090
  123. #define   ECOCHK_SNB_BIT                (1<<10)
  124. #define   ECOCHK_PPGTT_CACHE64B         (0x3<<3)
  125. #define   ECOCHK_PPGTT_CACHE4B          (0x0<<3)
  126.  
  127. #define GAC_ECO_BITS                    0x14090
  128. #define   ECOBITS_PPGTT_CACHE64B        (3<<8)
  129. #define   ECOBITS_PPGTT_CACHE4B         (0<<8)
  130.  
  131. #define GAB_CTL                         0x24000
  132. #define   GAB_CTL_CONT_AFTER_PAGEFAULT  (1<<8)
  133.  
  134. /* VGA stuff */
  135.  
  136. #define VGA_ST01_MDA 0x3ba
  137. #define VGA_ST01_CGA 0x3da
  138.  
  139. #define VGA_MSR_WRITE 0x3c2
  140. #define VGA_MSR_READ 0x3cc
  141. #define   VGA_MSR_MEM_EN (1<<1)
  142. #define   VGA_MSR_CGA_MODE (1<<0)
  143.  
  144. /*
  145.  * SR01 is the only VGA register touched on non-UMS setups.
  146.  * VLV doesn't do UMS, so the sequencer index/data registers
  147.  * are the only VGA registers which need to include
  148.  * display_mmio_offset.
  149.  */
  150. #define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
  151. #define SR01                    1
  152. #define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
  153.  
  154. #define VGA_AR_INDEX 0x3c0
  155. #define   VGA_AR_VID_EN (1<<5)
  156. #define VGA_AR_DATA_WRITE 0x3c0
  157. #define VGA_AR_DATA_READ 0x3c1
  158.  
  159. #define VGA_GR_INDEX 0x3ce
  160. #define VGA_GR_DATA 0x3cf
  161. /* GR05 */
  162. #define   VGA_GR_MEM_READ_MODE_SHIFT 3
  163. #define     VGA_GR_MEM_READ_MODE_PLANE 1
  164. /* GR06 */
  165. #define   VGA_GR_MEM_MODE_MASK 0xc
  166. #define   VGA_GR_MEM_MODE_SHIFT 2
  167. #define   VGA_GR_MEM_A0000_AFFFF 0
  168. #define   VGA_GR_MEM_A0000_BFFFF 1
  169. #define   VGA_GR_MEM_B0000_B7FFF 2
  170. #define   VGA_GR_MEM_B0000_BFFFF 3
  171.  
  172. #define VGA_DACMASK 0x3c6
  173. #define VGA_DACRX 0x3c7
  174. #define VGA_DACWX 0x3c8
  175. #define VGA_DACDATA 0x3c9
  176.  
  177. #define VGA_CR_INDEX_MDA 0x3b4
  178. #define VGA_CR_DATA_MDA 0x3b5
  179. #define VGA_CR_INDEX_CGA 0x3d4
  180. #define VGA_CR_DATA_CGA 0x3d5
  181.  
  182. /*
  183.  * Memory interface instructions used by the kernel
  184.  */
  185. #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
  186.  
  187. #define MI_NOOP                 MI_INSTR(0, 0)
  188. #define MI_USER_INTERRUPT       MI_INSTR(0x02, 0)
  189. #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
  190. #define   MI_WAIT_FOR_OVERLAY_FLIP      (1<<16)
  191. #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
  192. #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
  193. #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  194. #define MI_FLUSH                MI_INSTR(0x04, 0)
  195. #define   MI_READ_FLUSH         (1 << 0)
  196. #define   MI_EXE_FLUSH          (1 << 1)
  197. #define   MI_NO_WRITE_FLUSH     (1 << 2)
  198. #define   MI_SCENE_COUNT        (1 << 3) /* just increment scene count */
  199. #define   MI_END_SCENE          (1 << 4) /* flush binner and incr scene count */
  200. #define   MI_INVALIDATE_ISP     (1 << 5) /* invalidate indirect state pointers */
  201. #define MI_BATCH_BUFFER_END     MI_INSTR(0x0a, 0)
  202. #define MI_SUSPEND_FLUSH        MI_INSTR(0x0b, 0)
  203. #define   MI_SUSPEND_FLUSH_EN   (1<<0)
  204. #define MI_REPORT_HEAD          MI_INSTR(0x07, 0)
  205. #define MI_OVERLAY_FLIP         MI_INSTR(0x11, 0)
  206. #define   MI_OVERLAY_CONTINUE   (0x0<<21)
  207. #define   MI_OVERLAY_ON         (0x1<<21)
  208. #define   MI_OVERLAY_OFF        (0x2<<21)
  209. #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
  210. #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
  211. #define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
  212. #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
  213. /* IVB has funny definitions for which plane to flip. */
  214. #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
  215. #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
  216. #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
  217. #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
  218. #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
  219. #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
  220. #define MI_ARB_ON_OFF           MI_INSTR(0x08, 0)
  221. #define   MI_ARB_ENABLE                 (1<<0)
  222. #define   MI_ARB_DISABLE                (0<<0)
  223.  
  224. #define MI_SET_CONTEXT          MI_INSTR(0x18, 0)
  225. #define   MI_MM_SPACE_GTT               (1<<8)
  226. #define   MI_MM_SPACE_PHYSICAL          (0<<8)
  227. #define   MI_SAVE_EXT_STATE_EN          (1<<3)
  228. #define   MI_RESTORE_EXT_STATE_EN       (1<<2)
  229. #define   MI_FORCE_RESTORE              (1<<1)
  230. #define   MI_RESTORE_INHIBIT            (1<<0)
  231. #define MI_STORE_DWORD_IMM      MI_INSTR(0x20, 1)
  232. #define   MI_MEM_VIRTUAL        (1 << 22) /* 965+ only */
  233. #define MI_STORE_DWORD_INDEX    MI_INSTR(0x21, 1)
  234. #define   MI_STORE_DWORD_INDEX_SHIFT 2
  235. /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
  236.  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
  237.  *   simply ignores the register load under certain conditions.
  238.  * - One can actually load arbitrary many arbitrary registers: Simply issue x
  239.  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
  240.  */
  241. #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
  242. #define MI_FLUSH_DW             MI_INSTR(0x26, 1) /* for GEN6 */
  243. #define   MI_FLUSH_DW_STORE_INDEX       (1<<21)
  244. #define   MI_INVALIDATE_TLB     (1<<18)
  245. #define   MI_FLUSH_DW_OP_STOREDW        (1<<14)
  246. #define   MI_INVALIDATE_BSD     (1<<7)
  247. #define   MI_FLUSH_DW_USE_GTT           (1<<2)
  248. #define   MI_FLUSH_DW_USE_PPGTT         (0<<2)
  249. #define MI_BATCH_BUFFER         MI_INSTR(0x30, 1)
  250. #define   MI_BATCH_NON_SECURE   (1)
  251. /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
  252. #define   MI_BATCH_NON_SECURE_I965 (1<<8)
  253. #define   MI_BATCH_PPGTT_HSW            (1<<8)
  254. #define   MI_BATCH_NON_SECURE_HSW       (1<<13)
  255. #define MI_BATCH_BUFFER_START   MI_INSTR(0x31, 0)
  256. #define   MI_BATCH_GTT              (2<<6) /* aliased with (1<<7) on gen4 */
  257. #define MI_SEMAPHORE_MBOX       MI_INSTR(0x16, 1) /* gen6+ */
  258. #define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
  259. #define  MI_SEMAPHORE_UPDATE        (1<<21)
  260. #define  MI_SEMAPHORE_COMPARE       (1<<20)
  261. #define  MI_SEMAPHORE_REGISTER      (1<<18)
  262. #define  MI_SEMAPHORE_SYNC_RV       (2<<16)
  263. #define  MI_SEMAPHORE_SYNC_RB       (0<<16)
  264. #define  MI_SEMAPHORE_SYNC_VR       (0<<16)
  265. #define  MI_SEMAPHORE_SYNC_VB       (2<<16)
  266. #define  MI_SEMAPHORE_SYNC_BR       (2<<16)
  267. #define  MI_SEMAPHORE_SYNC_BV       (0<<16)
  268. #define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
  269. /*
  270.  * 3D instructions used by the kernel
  271.  */
  272. #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
  273.  
  274. #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
  275. #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  276. #define   SC_UPDATE_SCISSOR       (0x1<<1)
  277. #define   SC_ENABLE_MASK          (0x1<<0)
  278. #define   SC_ENABLE               (0x1<<0)
  279. #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
  280. #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  281. #define   SCI_YMIN_MASK      (0xffff<<16)
  282. #define   SCI_XMIN_MASK      (0xffff<<0)
  283. #define   SCI_YMAX_MASK      (0xffff<<16)
  284. #define   SCI_XMAX_MASK      (0xffff<<0)
  285. #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  286. #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
  287. #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  288. #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  289. #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
  290. #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  291. #define GFX_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
  292. #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  293. #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
  294. #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
  295. #define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
  296. #define XY_MONO_SRC_COPY_IMM_BLT        ((2<<29)|(0x71<<22)|5)
  297. #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
  298. #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
  299. #define   BLT_DEPTH_8                   (0<<24)
  300. #define   BLT_DEPTH_16_565              (1<<24)
  301. #define   BLT_DEPTH_16_1555             (2<<24)
  302. #define   BLT_DEPTH_32                  (3<<24)
  303. #define   BLT_ROP_GXCOPY                (0xcc<<16)
  304. #define XY_SRC_COPY_BLT_SRC_TILED       (1<<15) /* 965+ only */
  305. #define XY_SRC_COPY_BLT_DST_TILED       (1<<11) /* 965+ only */
  306. #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
  307. #define   ASYNC_FLIP                (1<<22)
  308. #define   DISPLAY_PLANE_A           (0<<20)
  309. #define   DISPLAY_PLANE_B           (1<<20)
  310. #define GFX_OP_PIPE_CONTROL(len)        ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
  311. #define   PIPE_CONTROL_GLOBAL_GTT_IVB                   (1<<24) /* gen7+ */
  312. #define   PIPE_CONTROL_CS_STALL                         (1<<20)
  313. #define   PIPE_CONTROL_TLB_INVALIDATE                   (1<<18)
  314. #define   PIPE_CONTROL_QW_WRITE (1<<14)
  315. #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
  316. #define   PIPE_CONTROL_WRITE_FLUSH                      (1<<12)
  317. #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH        (1<<12) /* gen6+ */
  318. #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE     (1<<11) /* MBZ on Ironlake */
  319. #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE         (1<<10) /* GM45+ only */
  320. #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE           (1<<9)
  321. #define   PIPE_CONTROL_NOTIFY   (1<<8)
  322. #define   PIPE_CONTROL_VF_CACHE_INVALIDATE              (1<<4)
  323. #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE           (1<<3)
  324. #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE           (1<<2)
  325. #define   PIPE_CONTROL_STALL_AT_SCOREBOARD              (1<<1)
  326. #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH                (1<<0)
  327. #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
  328.  
  329.  
  330. /*
  331.  * Reset registers
  332.  */
  333. #define DEBUG_RESET_I830                0x6070
  334. #define  DEBUG_RESET_FULL               (1<<7)
  335. #define  DEBUG_RESET_RENDER             (1<<8)
  336. #define  DEBUG_RESET_DISPLAY            (1<<9)
  337.  
  338. /*
  339.  * DPIO - a special bus for various display related registers to hide behind:
  340.  *  0x800c: m1, m2, n, p1, p2, k dividers
  341.  *  0x8014: REF and SFR select
  342.  *  0x8014: N divider, VCO select
  343.  *  0x801c/3c: core clock bits
  344.  *  0x8048/68: low pass filter coefficients
  345.  *  0x8100: fast clock controls
  346.  *
  347.  * DPIO is VLV only.
  348.  */
  349. #define DPIO_PKT                        (VLV_DISPLAY_BASE + 0x2100)
  350. #define  DPIO_RID                       (0<<24)
  351. #define  DPIO_OP_WRITE                  (1<<16)
  352. #define  DPIO_OP_READ                   (0<<16)
  353. #define  DPIO_PORTID                    (0x12<<8)
  354. #define  DPIO_BYTE                      (0xf<<4)
  355. #define  DPIO_BUSY                      (1<<0) /* status only */
  356. #define DPIO_DATA                       (VLV_DISPLAY_BASE + 0x2104)
  357. #define DPIO_REG                        (VLV_DISPLAY_BASE + 0x2108)
  358. #define DPIO_CTL                        (VLV_DISPLAY_BASE + 0x2110)
  359. #define  DPIO_MODSEL1                   (1<<3) /* if ref clk b == 27 */
  360. #define  DPIO_MODSEL0                   (1<<2) /* if ref clk a == 27 */
  361. #define  DPIO_SFR_BYPASS                (1<<1)
  362. #define  DPIO_RESET                     (1<<0)
  363.  
  364. #define _DPIO_DIV_A                     0x800c
  365. #define   DPIO_POST_DIV_SHIFT           (28) /* 3 bits */
  366. #define   DPIO_K_SHIFT                  (24) /* 4 bits */
  367. #define   DPIO_P1_SHIFT                 (21) /* 3 bits */
  368. #define   DPIO_P2_SHIFT                 (16) /* 5 bits */
  369. #define   DPIO_N_SHIFT                  (12) /* 4 bits */
  370. #define   DPIO_ENABLE_CALIBRATION       (1<<11)
  371. #define   DPIO_M1DIV_SHIFT              (8) /* 3 bits */
  372. #define   DPIO_M2DIV_MASK               0xff
  373. #define _DPIO_DIV_B                     0x802c
  374. #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
  375.  
  376. #define _DPIO_REFSFR_A                  0x8014
  377. #define   DPIO_REFSEL_OVERRIDE          27
  378. #define   DPIO_PLL_MODESEL_SHIFT        24 /* 3 bits */
  379. #define   DPIO_BIAS_CURRENT_CTL_SHIFT   21 /* 3 bits, always 0x7 */
  380. #define   DPIO_PLL_REFCLK_SEL_SHIFT     16 /* 2 bits */
  381. #define   DPIO_PLL_REFCLK_SEL_MASK      3
  382. #define   DPIO_DRIVER_CTL_SHIFT         12 /* always set to 0x8 */
  383. #define   DPIO_CLK_BIAS_CTL_SHIFT       8 /* always set to 0x5 */
  384. #define _DPIO_REFSFR_B                  0x8034
  385. #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
  386.  
  387. #define _DPIO_CORE_CLK_A                0x801c
  388. #define _DPIO_CORE_CLK_B                0x803c
  389. #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
  390.  
  391. #define _DPIO_LFP_COEFF_A               0x8048
  392. #define _DPIO_LFP_COEFF_B               0x8068
  393. #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
  394.  
  395. #define DPIO_FASTCLK_DISABLE            0x8100
  396.  
  397. #define DPIO_DATA_CHANNEL1              0x8220
  398. #define DPIO_DATA_CHANNEL2              0x8420
  399.  
  400. /*
  401.  * Fence registers
  402.  */
  403. #define FENCE_REG_830_0                 0x2000
  404. #define FENCE_REG_945_8                 0x3000
  405. #define   I830_FENCE_START_MASK         0x07f80000
  406. #define   I830_FENCE_TILING_Y_SHIFT     12
  407. #define   I830_FENCE_SIZE_BITS(size)    ((ffs((size) >> 19) - 1) << 8)
  408. #define   I830_FENCE_PITCH_SHIFT        4
  409. #define   I830_FENCE_REG_VALID          (1<<0)
  410. #define   I915_FENCE_MAX_PITCH_VAL      4
  411. #define   I830_FENCE_MAX_PITCH_VAL      6
  412. #define   I830_FENCE_MAX_SIZE_VAL       (1<<8)
  413.  
  414. #define   I915_FENCE_START_MASK         0x0ff00000
  415. #define   I915_FENCE_SIZE_BITS(size)    ((ffs((size) >> 20) - 1) << 8)
  416.  
  417. #define FENCE_REG_965_0                 0x03000
  418. #define   I965_FENCE_PITCH_SHIFT        2
  419. #define   I965_FENCE_TILING_Y_SHIFT     1
  420. #define   I965_FENCE_REG_VALID          (1<<0)
  421. #define   I965_FENCE_MAX_PITCH_VAL      0x0400
  422.  
  423. #define FENCE_REG_SANDYBRIDGE_0         0x100000
  424. #define   SANDYBRIDGE_FENCE_PITCH_SHIFT 32
  425.  
  426. /* control register for cpu gtt access */
  427. #define TILECTL                         0x101000
  428. #define   TILECTL_SWZCTL                        (1 << 0)
  429. #define   TILECTL_TLB_PREFETCH_DIS      (1 << 2)
  430. #define   TILECTL_BACKSNOOP_DIS         (1 << 3)
  431.  
  432. /*
  433.  * Instruction and interrupt control regs
  434.  */
  435. #define PGTBL_ER        0x02024
  436. #define RENDER_RING_BASE        0x02000
  437. #define BSD_RING_BASE           0x04000
  438. #define GEN6_BSD_RING_BASE      0x12000
  439. #define BLT_RING_BASE           0x22000
  440. #define RING_TAIL(base)         ((base)+0x30)
  441. #define RING_HEAD(base)         ((base)+0x34)
  442. #define RING_START(base)        ((base)+0x38)
  443. #define RING_CTL(base)          ((base)+0x3c)
  444. #define RING_SYNC_0(base)       ((base)+0x40)
  445. #define RING_SYNC_1(base)       ((base)+0x44)
  446. #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
  447. #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
  448. #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
  449. #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
  450. #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
  451. #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
  452. #define RING_MAX_IDLE(base)     ((base)+0x54)
  453. #define RING_HWS_PGA(base)      ((base)+0x80)
  454. #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
  455. #define ARB_MODE                0x04030
  456. #define   ARB_MODE_SWIZZLE_SNB  (1<<4)
  457. #define   ARB_MODE_SWIZZLE_IVB  (1<<5)
  458. #define RENDER_HWS_PGA_GEN7     (0x04080)
  459. #define RING_FAULT_REG(ring)    (0x4094 + 0x100*(ring)->id)
  460. #define DONE_REG                0x40b0
  461. #define BSD_HWS_PGA_GEN7        (0x04180)
  462. #define BLT_HWS_PGA_GEN7        (0x04280)
  463. #define RING_ACTHD(base)        ((base)+0x74)
  464. #define RING_NOPID(base)        ((base)+0x94)
  465. #define RING_IMR(base)          ((base)+0xa8)
  466. #define RING_TIMESTAMP(base)    ((base)+0x358)
  467. #define   TAIL_ADDR             0x001FFFF8
  468. #define   HEAD_WRAP_COUNT       0xFFE00000
  469. #define   HEAD_WRAP_ONE         0x00200000
  470. #define   HEAD_ADDR             0x001FFFFC
  471. #define   RING_NR_PAGES         0x001FF000
  472. #define   RING_REPORT_MASK      0x00000006
  473. #define   RING_REPORT_64K       0x00000002
  474. #define   RING_REPORT_128K      0x00000004
  475. #define   RING_NO_REPORT        0x00000000
  476. #define   RING_VALID_MASK       0x00000001
  477. #define   RING_VALID            0x00000001
  478. #define   RING_INVALID          0x00000000
  479. #define   RING_WAIT_I8XX        (1<<0) /* gen2, PRBx_HEAD */
  480. #define   RING_WAIT             (1<<11) /* gen3+, PRBx_CTL */
  481. #define   RING_WAIT_SEMAPHORE   (1<<10) /* gen6+ */
  482. #if 0
  483. #define PRB0_TAIL       0x02030
  484. #define PRB0_HEAD       0x02034
  485. #define PRB0_START      0x02038
  486. #define PRB0_CTL        0x0203c
  487. #define PRB1_TAIL       0x02040 /* 915+ only */
  488. #define PRB1_HEAD       0x02044 /* 915+ only */
  489. #define PRB1_START      0x02048 /* 915+ only */
  490. #define PRB1_CTL        0x0204c /* 915+ only */
  491. #endif
  492. #define IPEIR_I965      0x02064
  493. #define IPEHR_I965      0x02068
  494. #define INSTDONE_I965   0x0206c
  495. #define GEN7_INSTDONE_1         0x0206c
  496. #define GEN7_SC_INSTDONE        0x07100
  497. #define GEN7_SAMPLER_INSTDONE   0x0e160
  498. #define GEN7_ROW_INSTDONE       0x0e164
  499. #define I915_NUM_INSTDONE_REG   4
  500. #define RING_IPEIR(base)        ((base)+0x64)
  501. #define RING_IPEHR(base)        ((base)+0x68)
  502. #define RING_INSTDONE(base)     ((base)+0x6c)
  503. #define RING_INSTPS(base)       ((base)+0x70)
  504. #define RING_DMA_FADD(base)     ((base)+0x78)
  505. #define RING_INSTPM(base)       ((base)+0xc0)
  506. #define INSTPS          0x02070 /* 965+ only */
  507. #define INSTDONE1       0x0207c /* 965+ only */
  508. #define ACTHD_I965      0x02074
  509. #define HWS_PGA         0x02080
  510. #define HWS_ADDRESS_MASK        0xfffff000
  511. #define HWS_START_ADDRESS_SHIFT 4
  512. #define PWRCTXA         0x2088 /* 965GM+ only */
  513. #define   PWRCTX_EN     (1<<0)
  514. #define IPEIR           0x02088
  515. #define IPEHR           0x0208c
  516. #define INSTDONE        0x02090
  517. #define NOPID           0x02094
  518. #define HWSTAM          0x02098
  519. #define DMA_FADD_I8XX   0x020d0
  520.  
  521. #define ERROR_GEN6      0x040a0
  522. #define GEN7_ERR_INT    0x44040
  523. #define   ERR_INT_MMIO_UNCLAIMED (1<<13)
  524.  
  525. #define DERRMR          0x44050
  526.  
  527. /* GM45+ chicken bits -- debug workaround bits that may be required
  528.  * for various sorts of correct behavior.  The top 16 bits of each are
  529.  * the enables for writing to the corresponding low bit.
  530.  */
  531. #define _3D_CHICKEN     0x02084
  532. #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
  533. #define _3D_CHICKEN2    0x0208c
  534. /* Disables pipelining of read flushes past the SF-WIZ interface.
  535.  * Required on all Ironlake steppings according to the B-Spec, but the
  536.  * particular danger of not doing so is not specified.
  537.  */
  538. # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
  539. #define _3D_CHICKEN3    0x02090
  540. #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL             (1 << 10)
  541. #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL          (1 << 5)
  542.  
  543. #define MI_MODE         0x0209c
  544. # define VS_TIMER_DISPATCH                              (1 << 6)
  545. # define MI_FLUSH_ENABLE                                (1 << 12)
  546. # define ASYNC_FLIP_PERF_DISABLE                        (1 << 14)
  547.  
  548. #define GEN6_GT_MODE    0x20d0
  549. #define   GEN6_GT_MODE_HI       (1 << 9)
  550. #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
  551.  
  552. #define GFX_MODE        0x02520
  553. #define GFX_MODE_GEN7   0x0229c
  554. #define RING_MODE_GEN7(ring)    ((ring)->mmio_base+0x29c)
  555. #define   GFX_RUN_LIST_ENABLE           (1<<15)
  556. #define   GFX_TLB_INVALIDATE_ALWAYS     (1<<13)
  557. #define   GFX_SURFACE_FAULT_ENABLE      (1<<12)
  558. #define   GFX_REPLAY_MODE               (1<<11)
  559. #define   GFX_PSMI_GRANULARITY          (1<<10)
  560. #define   GFX_PPGTT_ENABLE              (1<<9)
  561.  
  562. #define VLV_DISPLAY_BASE 0x180000
  563.  
  564. #define SCPD0           0x0209c /* 915+ only */
  565. #define IER             0x020a0
  566. #define IIR             0x020a4
  567. #define IMR             0x020a8
  568. #define ISR             0x020ac
  569. #define VLV_GUNIT_CLOCK_GATE    (VLV_DISPLAY_BASE + 0x2060)
  570. #define   GCFG_DIS              (1<<8)
  571. #define VLV_IIR_RW      (VLV_DISPLAY_BASE + 0x2084)
  572. #define VLV_IER         (VLV_DISPLAY_BASE + 0x20a0)
  573. #define VLV_IIR         (VLV_DISPLAY_BASE + 0x20a4)
  574. #define VLV_IMR         (VLV_DISPLAY_BASE + 0x20a8)
  575. #define VLV_ISR         (VLV_DISPLAY_BASE + 0x20ac)
  576. #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT            (1<<18)
  577. #define   I915_DISPLAY_PORT_INTERRUPT                   (1<<17)
  578. #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT    (1<<15)
  579. #define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT      (1<<14) /* p-state */
  580. #define   I915_HWB_OOM_INTERRUPT                        (1<<13)
  581. #define   I915_SYNC_STATUS_INTERRUPT                    (1<<12)
  582. #define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT   (1<<11)
  583. #define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT   (1<<10)
  584. #define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT     (1<<9)
  585. #define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT   (1<<8)
  586. #define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT          (1<<7)
  587. #define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT           (1<<6)
  588. #define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT          (1<<5)
  589. #define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT           (1<<4)
  590. #define   I915_DEBUG_INTERRUPT                          (1<<2)
  591. #define   I915_USER_INTERRUPT                           (1<<1)
  592. #define   I915_ASLE_INTERRUPT                           (1<<0)
  593. #define   I915_BSD_USER_INTERRUPT                      (1<<25)
  594. #define EIR             0x020b0
  595. #define EMR             0x020b4
  596. #define ESR             0x020b8
  597. #define   GM45_ERROR_PAGE_TABLE                         (1<<5)
  598. #define   GM45_ERROR_MEM_PRIV                           (1<<4)
  599. #define   I915_ERROR_PAGE_TABLE                         (1<<4)
  600. #define   GM45_ERROR_CP_PRIV                            (1<<3)
  601. #define   I915_ERROR_MEMORY_REFRESH                     (1<<1)
  602. #define   I915_ERROR_INSTRUCTION                        (1<<0)
  603. #define INSTPM          0x020c0
  604. #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
  605. #define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
  606.                                         will not assert AGPBUSY# and will only
  607.                                         be delivered when out of C3. */
  608. #define   INSTPM_FORCE_ORDERING                         (1<<7) /* GEN6+ */
  609. #define ACTHD           0x020c8
  610. #define FW_BLC          0x020d8
  611. #define FW_BLC2         0x020dc
  612. #define FW_BLC_SELF     0x020e0 /* 915+ only */
  613. #define   FW_BLC_SELF_EN_MASK      (1<<31)
  614. #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
  615. #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
  616. #define MM_BURST_LENGTH     0x00700000
  617. #define MM_FIFO_WATERMARK   0x0001F000
  618. #define LM_BURST_LENGTH     0x00000700
  619. #define LM_FIFO_WATERMARK   0x0000001F
  620. #define MI_ARB_STATE    0x020e4 /* 915+ only */
  621.  
  622. /* Make render/texture TLB fetches lower priorty than associated data
  623.  *   fetches. This is not turned on by default
  624.  */
  625. #define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
  626.  
  627. /* Isoch request wait on GTT enable (Display A/B/C streams).
  628.  * Make isoch requests stall on the TLB update. May cause
  629.  * display underruns (test mode only)
  630.  */
  631. #define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
  632.  
  633. /* Block grant count for isoch requests when block count is
  634.  * set to a finite value.
  635.  */
  636. #define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
  637. #define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
  638. #define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
  639. #define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
  640. #define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
  641.  
  642. /* Enable render writes to complete in C2/C3/C4 power states.
  643.  * If this isn't enabled, render writes are prevented in low
  644.  * power states. That seems bad to me.
  645.  */
  646. #define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
  647.  
  648. /* This acknowledges an async flip immediately instead
  649.  * of waiting for 2TLB fetches.
  650.  */
  651. #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
  652.  
  653. /* Enables non-sequential data reads through arbiter
  654.  */
  655. #define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
  656.  
  657. /* Disable FSB snooping of cacheable write cycles from binner/render
  658.  * command stream
  659.  */
  660. #define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
  661.  
  662. /* Arbiter time slice for non-isoch streams */
  663. #define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
  664. #define   MI_ARB_TIME_SLICE_1                   (0 << 5)
  665. #define   MI_ARB_TIME_SLICE_2                   (1 << 5)
  666. #define   MI_ARB_TIME_SLICE_4                   (2 << 5)
  667. #define   MI_ARB_TIME_SLICE_6                   (3 << 5)
  668. #define   MI_ARB_TIME_SLICE_8                   (4 << 5)
  669. #define   MI_ARB_TIME_SLICE_10                  (5 << 5)
  670. #define   MI_ARB_TIME_SLICE_14                  (6 << 5)
  671. #define   MI_ARB_TIME_SLICE_16                  (7 << 5)
  672.  
  673. /* Low priority grace period page size */
  674. #define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
  675. #define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
  676.  
  677. /* Disable display A/B trickle feed */
  678. #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
  679.  
  680. /* Set display plane priority */
  681. #define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
  682. #define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
  683.  
  684. #define CACHE_MODE_0    0x02120 /* 915+ only */
  685. #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
  686. #define   CM0_IZ_OPT_DISABLE      (1<<6)
  687. #define   CM0_ZR_OPT_DISABLE      (1<<5)
  688. #define   CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
  689. #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
  690. #define   CM0_COLOR_EVICT_DISABLE (1<<3)
  691. #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
  692. #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
  693. #define BB_ADDR         0x02140 /* 8 bytes */
  694. #define GFX_FLSH_CNTL   0x02170 /* 915+ only */
  695. #define GFX_FLSH_CNTL_GEN6      0x101008
  696. #define   GFX_FLSH_CNTL_EN      (1<<0)
  697. #define ECOSKPD         0x021d0
  698. #define   ECO_GATING_CX_ONLY    (1<<3)
  699. #define   ECO_FLIP_DONE         (1<<0)
  700.  
  701. #define CACHE_MODE_1            0x7004 /* IVB+ */
  702. #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
  703.  
  704. /* GEN6 interrupt control
  705.  * Note that the per-ring interrupt bits do alias with the global interrupt bits
  706.  * in GTIMR. */
  707. #define GEN6_RENDER_HWSTAM      0x2098
  708. #define GEN6_RENDER_IMR         0x20a8
  709. #define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT          (1 << 8)
  710. #define   GEN6_RENDER_PPGTT_PAGE_FAULT                  (1 << 7)
  711. #define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED           (1 << 6)
  712. #define   GEN6_RENDER_L3_PARITY_ERROR                   (1 << 5)
  713. #define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT     (1 << 4)
  714. #define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR       (1 << 3)
  715. #define   GEN6_RENDER_SYNC_STATUS                       (1 << 2)
  716. #define   GEN6_RENDER_DEBUG_INTERRUPT                   (1 << 1)
  717. #define   GEN6_RENDER_USER_INTERRUPT                    (1 << 0)
  718.  
  719. #define GEN6_BLITTER_HWSTAM     0x22098
  720. #define GEN6_BLITTER_IMR        0x220a8
  721. #define   GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT     (1 << 26)
  722. #define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR      (1 << 25)
  723. #define   GEN6_BLITTER_SYNC_STATUS                      (1 << 24)
  724. #define   GEN6_BLITTER_USER_INTERRUPT                   (1 << 22)
  725.  
  726. #define GEN6_BLITTER_ECOSKPD    0x221d0
  727. #define   GEN6_BLITTER_LOCK_SHIFT                       16
  728. #define   GEN6_BLITTER_FBC_NOTIFY                       (1<<3)
  729.  
  730. #define GEN6_BSD_SLEEP_PSMI_CONTROL     0x12050
  731. #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
  732. #define   GEN6_BSD_SLEEP_FLUSH_DISABLE  (1 << 2)
  733. #define   GEN6_BSD_SLEEP_INDICATOR      (1 << 3)
  734. #define   GEN6_BSD_GO_INDICATOR         (1 << 4)
  735.  
  736. #define GEN6_BSD_HWSTAM                 0x12098
  737. #define GEN6_BSD_IMR                    0x120a8
  738. #define   GEN6_BSD_USER_INTERRUPT       (1 << 12)
  739.  
  740. #define GEN6_BSD_RNCID                  0x12198
  741.  
  742. #define GEN7_FF_THREAD_MODE             0x20a0
  743. #define   GEN7_FF_SCHED_MASK            0x0077070
  744. #define   GEN7_FF_TS_SCHED_HS1          (0x5<<16)
  745. #define   GEN7_FF_TS_SCHED_HS0          (0x3<<16)
  746. #define   GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
  747. #define   GEN7_FF_TS_SCHED_HW           (0x0<<16) /* Default */
  748. #define   GEN7_FF_VS_REF_CNT_FFME       (1 << 15)
  749. #define   GEN7_FF_VS_SCHED_HS1          (0x5<<12)
  750. #define   GEN7_FF_VS_SCHED_HS0          (0x3<<12)
  751. #define   GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
  752. #define   GEN7_FF_VS_SCHED_HW           (0x0<<12)
  753. #define   GEN7_FF_DS_SCHED_HS1          (0x5<<4)
  754. #define   GEN7_FF_DS_SCHED_HS0          (0x3<<4)
  755. #define   GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4)  /* Default */
  756. #define   GEN7_FF_DS_SCHED_HW           (0x0<<4)
  757.  
  758. /*
  759.  * Framebuffer compression (915+ only)
  760.  */
  761.  
  762. #define FBC_CFB_BASE            0x03200 /* 4k page aligned */
  763. #define FBC_LL_BASE             0x03204 /* 4k page aligned */
  764. #define FBC_CONTROL             0x03208
  765. #define   FBC_CTL_EN            (1<<31)
  766. #define   FBC_CTL_PERIODIC      (1<<30)
  767. #define   FBC_CTL_INTERVAL_SHIFT (16)
  768. #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
  769. #define   FBC_CTL_C3_IDLE       (1<<13)
  770. #define   FBC_CTL_STRIDE_SHIFT  (5)
  771. #define   FBC_CTL_FENCENO       (1<<0)
  772. #define FBC_COMMAND             0x0320c
  773. #define   FBC_CMD_COMPRESS      (1<<0)
  774. #define FBC_STATUS              0x03210
  775. #define   FBC_STAT_COMPRESSING  (1<<31)
  776. #define   FBC_STAT_COMPRESSED   (1<<30)
  777. #define   FBC_STAT_MODIFIED     (1<<29)
  778. #define   FBC_STAT_CURRENT_LINE (1<<0)
  779. #define FBC_CONTROL2            0x03214
  780. #define   FBC_CTL_FENCE_DBL     (0<<4)
  781. #define   FBC_CTL_IDLE_IMM      (0<<2)
  782. #define   FBC_CTL_IDLE_FULL     (1<<2)
  783. #define   FBC_CTL_IDLE_LINE     (2<<2)
  784. #define   FBC_CTL_IDLE_DEBUG    (3<<2)
  785. #define   FBC_CTL_CPU_FENCE     (1<<1)
  786. #define   FBC_CTL_PLANEA        (0<<0)
  787. #define   FBC_CTL_PLANEB        (1<<0)
  788. #define FBC_FENCE_OFF           0x0321b
  789. #define FBC_TAG                 0x03300
  790.  
  791. #define FBC_LL_SIZE             (1536)
  792.  
  793. /* Framebuffer compression for GM45+ */
  794. #define DPFC_CB_BASE            0x3200
  795. #define DPFC_CONTROL            0x3208
  796. #define   DPFC_CTL_EN           (1<<31)
  797. #define   DPFC_CTL_PLANEA       (0<<30)
  798. #define   DPFC_CTL_PLANEB       (1<<30)
  799. #define   DPFC_CTL_FENCE_EN     (1<<29)
  800. #define   DPFC_CTL_PERSISTENT_MODE      (1<<25)
  801. #define   DPFC_SR_EN            (1<<10)
  802. #define   DPFC_CTL_LIMIT_1X     (0<<6)
  803. #define   DPFC_CTL_LIMIT_2X     (1<<6)
  804. #define   DPFC_CTL_LIMIT_4X     (2<<6)
  805. #define DPFC_RECOMP_CTL         0x320c
  806. #define   DPFC_RECOMP_STALL_EN  (1<<27)
  807. #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
  808. #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
  809. #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
  810. #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
  811. #define DPFC_STATUS             0x3210
  812. #define   DPFC_INVAL_SEG_SHIFT  (16)
  813. #define   DPFC_INVAL_SEG_MASK   (0x07ff0000)
  814. #define   DPFC_COMP_SEG_SHIFT   (0)
  815. #define   DPFC_COMP_SEG_MASK    (0x000003ff)
  816. #define DPFC_STATUS2            0x3214
  817. #define DPFC_FENCE_YOFF         0x3218
  818. #define DPFC_CHICKEN            0x3224
  819. #define   DPFC_HT_MODIFY        (1<<31)
  820.  
  821. /* Framebuffer compression for Ironlake */
  822. #define ILK_DPFC_CB_BASE        0x43200
  823. #define ILK_DPFC_CONTROL        0x43208
  824. /* The bit 28-8 is reserved */
  825. #define   DPFC_RESERVED         (0x1FFFFF00)
  826. #define ILK_DPFC_RECOMP_CTL     0x4320c
  827. #define ILK_DPFC_STATUS         0x43210
  828. #define ILK_DPFC_FENCE_YOFF     0x43218
  829. #define ILK_DPFC_CHICKEN        0x43224
  830. #define ILK_FBC_RT_BASE         0x2128
  831. #define   ILK_FBC_RT_VALID      (1<<0)
  832.  
  833. #define ILK_DISPLAY_CHICKEN1    0x42000
  834. #define   ILK_FBCQ_DIS          (1<<22)
  835. #define   ILK_PABSTRETCH_DIS    (1<<21)
  836.  
  837.  
  838. /*
  839.  * Framebuffer compression for Sandybridge
  840.  *
  841.  * The following two registers are of type GTTMMADR
  842.  */
  843. #define SNB_DPFC_CTL_SA         0x100100
  844. #define   SNB_CPU_FENCE_ENABLE  (1<<29)
  845. #define DPFC_CPU_FENCE_OFFSET   0x100104
  846.  
  847.  
  848. /*
  849.  * GPIO regs
  850.  */
  851. #define GPIOA                   0x5010
  852. #define GPIOB                   0x5014
  853. #define GPIOC                   0x5018
  854. #define GPIOD                   0x501c
  855. #define GPIOE                   0x5020
  856. #define GPIOF                   0x5024
  857. #define GPIOG                   0x5028
  858. #define GPIOH                   0x502c
  859. # define GPIO_CLOCK_DIR_MASK            (1 << 0)
  860. # define GPIO_CLOCK_DIR_IN              (0 << 1)
  861. # define GPIO_CLOCK_DIR_OUT             (1 << 1)
  862. # define GPIO_CLOCK_VAL_MASK            (1 << 2)
  863. # define GPIO_CLOCK_VAL_OUT             (1 << 3)
  864. # define GPIO_CLOCK_VAL_IN              (1 << 4)
  865. # define GPIO_CLOCK_PULLUP_DISABLE      (1 << 5)
  866. # define GPIO_DATA_DIR_MASK             (1 << 8)
  867. # define GPIO_DATA_DIR_IN               (0 << 9)
  868. # define GPIO_DATA_DIR_OUT              (1 << 9)
  869. # define GPIO_DATA_VAL_MASK             (1 << 10)
  870. # define GPIO_DATA_VAL_OUT              (1 << 11)
  871. # define GPIO_DATA_VAL_IN               (1 << 12)
  872. # define GPIO_DATA_PULLUP_DISABLE       (1 << 13)
  873.  
  874. #define GMBUS0                  0x5100 /* clock/port select */
  875. #define   GMBUS_RATE_100KHZ     (0<<8)
  876. #define   GMBUS_RATE_50KHZ      (1<<8)
  877. #define   GMBUS_RATE_400KHZ     (2<<8) /* reserved on Pineview */
  878. #define   GMBUS_RATE_1MHZ       (3<<8) /* reserved on Pineview */
  879. #define   GMBUS_HOLD_EXT        (1<<7) /* 300ns hold time, rsvd on Pineview */
  880. #define   GMBUS_PORT_DISABLED   0
  881. #define   GMBUS_PORT_SSC        1
  882. #define   GMBUS_PORT_VGADDC     2
  883. #define   GMBUS_PORT_PANEL      3
  884. #define   GMBUS_PORT_DPC        4 /* HDMIC */
  885. #define   GMBUS_PORT_DPB        5 /* SDVO, HDMIB */
  886. #define   GMBUS_PORT_DPD        6 /* HDMID */
  887. #define   GMBUS_PORT_RESERVED   7 /* 7 reserved */
  888. #define   GMBUS_NUM_PORTS       (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
  889. #define GMBUS1                  0x5104 /* command/status */
  890. #define   GMBUS_SW_CLR_INT      (1<<31)
  891. #define   GMBUS_SW_RDY          (1<<30)
  892. #define   GMBUS_ENT             (1<<29) /* enable timeout */
  893. #define   GMBUS_CYCLE_NONE      (0<<25)
  894. #define   GMBUS_CYCLE_WAIT      (1<<25)
  895. #define   GMBUS_CYCLE_INDEX     (2<<25)
  896. #define   GMBUS_CYCLE_STOP      (4<<25)
  897. #define   GMBUS_BYTE_COUNT_SHIFT 16
  898. #define   GMBUS_SLAVE_INDEX_SHIFT 8
  899. #define   GMBUS_SLAVE_ADDR_SHIFT 1
  900. #define   GMBUS_SLAVE_READ      (1<<0)
  901. #define   GMBUS_SLAVE_WRITE     (0<<0)
  902. #define GMBUS2                  0x5108 /* status */
  903. #define   GMBUS_INUSE           (1<<15)
  904. #define   GMBUS_HW_WAIT_PHASE   (1<<14)
  905. #define   GMBUS_STALL_TIMEOUT   (1<<13)
  906. #define   GMBUS_INT             (1<<12)
  907. #define   GMBUS_HW_RDY          (1<<11)
  908. #define   GMBUS_SATOER          (1<<10)
  909. #define   GMBUS_ACTIVE          (1<<9)
  910. #define GMBUS3                  0x510c /* data buffer bytes 3-0 */
  911. #define GMBUS4                  0x5110 /* interrupt mask (Pineview+) */
  912. #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
  913. #define   GMBUS_NAK_EN          (1<<3)
  914. #define   GMBUS_IDLE_EN         (1<<2)
  915. #define   GMBUS_HW_WAIT_EN      (1<<1)
  916. #define   GMBUS_HW_RDY_EN       (1<<0)
  917. #define GMBUS5                  0x5120 /* byte index */
  918. #define   GMBUS_2BYTE_INDEX_EN  (1<<31)
  919.  
  920. /*
  921.  * Clock control & power management
  922.  */
  923.  
  924. #define VGA0    0x6000
  925. #define VGA1    0x6004
  926. #define VGA_PD  0x6010
  927. #define   VGA0_PD_P2_DIV_4      (1 << 7)
  928. #define   VGA0_PD_P1_DIV_2      (1 << 5)
  929. #define   VGA0_PD_P1_SHIFT      0
  930. #define   VGA0_PD_P1_MASK       (0x1f << 0)
  931. #define   VGA1_PD_P2_DIV_4      (1 << 15)
  932. #define   VGA1_PD_P1_DIV_2      (1 << 13)
  933. #define   VGA1_PD_P1_SHIFT      8
  934. #define   VGA1_PD_P1_MASK       (0x1f << 8)
  935. #define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
  936. #define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
  937. #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
  938. #define   DPLL_VCO_ENABLE               (1 << 31)
  939. #define   DPLL_DVO_HIGH_SPEED           (1 << 30)
  940. #define   DPLL_EXT_BUFFER_ENABLE_VLV    (1 << 30)
  941. #define   DPLL_SYNCLOCK_ENABLE          (1 << 29)
  942. #define   DPLL_REFA_CLK_ENABLE_VLV      (1 << 29)
  943. #define   DPLL_VGA_MODE_DIS             (1 << 28)
  944. #define   DPLLB_MODE_DAC_SERIAL         (1 << 26) /* i915 */
  945. #define   DPLLB_MODE_LVDS               (2 << 26) /* i915 */
  946. #define   DPLL_MODE_MASK                (3 << 26)
  947. #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
  948. #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
  949. #define   DPLLB_LVDS_P2_CLOCK_DIV_14    (0 << 24) /* i915 */
  950. #define   DPLLB_LVDS_P2_CLOCK_DIV_7     (1 << 24) /* i915 */
  951. #define   DPLL_P2_CLOCK_DIV_MASK        0x03000000 /* i915 */
  952. #define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
  953. #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
  954. #define   DPLL_LOCK_VLV                 (1<<15)
  955. #define   DPLL_INTEGRATED_CLOCK_VLV     (1<<13)
  956.  
  957. #define   DPLL_FPA01_P1_POST_DIV_MASK_I830      0x001f0000
  958. /*
  959.  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  960.  * this field (only one bit may be set).
  961.  */
  962. #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
  963. #define   DPLL_FPA01_P1_POST_DIV_SHIFT  16
  964. #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
  965. /* i830, required in DVO non-gang */
  966. #define   PLL_P2_DIVIDE_BY_4            (1 << 23)
  967. #define   PLL_P1_DIVIDE_BY_TWO          (1 << 21) /* i830 */
  968. #define   PLL_REF_INPUT_DREFCLK         (0 << 13)
  969. #define   PLL_REF_INPUT_TVCLKINA        (1 << 13) /* i830 */
  970. #define   PLL_REF_INPUT_TVCLKINBC       (2 << 13) /* SDVO TVCLKIN */
  971. #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
  972. #define   PLL_REF_INPUT_MASK            (3 << 13)
  973. #define   PLL_LOAD_PULSE_PHASE_SHIFT            9
  974. /* Ironlake */
  975. # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
  976. # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
  977. # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)        (((x)-1) << 9)
  978. # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
  979. # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
  980.  
  981. /*
  982.  * Parallel to Serial Load Pulse phase selection.
  983.  * Selects the phase for the 10X DPLL clock for the PCIe
  984.  * digital display port. The range is 4 to 13; 10 or more
  985.  * is just a flip delay. The default is 6
  986.  */
  987. #define   PLL_LOAD_PULSE_PHASE_MASK             (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
  988. #define   DISPLAY_RATE_SELECT_FPA1              (1 << 8)
  989. /*
  990.  * SDVO multiplier for 945G/GM. Not used on 965.
  991.  */
  992. #define   SDVO_MULTIPLIER_MASK                  0x000000ff
  993. #define   SDVO_MULTIPLIER_SHIFT_HIRES           4
  994. #define   SDVO_MULTIPLIER_SHIFT_VGA             0
  995. #define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
  996. /*
  997.  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  998.  *
  999.  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
  1000.  */
  1001. #define   DPLL_MD_UDI_DIVIDER_MASK              0x3f000000
  1002. #define   DPLL_MD_UDI_DIVIDER_SHIFT             24
  1003. /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
  1004. #define   DPLL_MD_VGA_UDI_DIVIDER_MASK          0x003f0000
  1005. #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT         16
  1006. /*
  1007.  * SDVO/UDI pixel multiplier.
  1008.  *
  1009.  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
  1010.  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
  1011.  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
  1012.  * dummy bytes in the datastream at an increased clock rate, with both sides of
  1013.  * the link knowing how many bytes are fill.
  1014.  *
  1015.  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
  1016.  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
  1017.  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
  1018.  * through an SDVO command.
  1019.  *
  1020.  * This register field has values of multiplication factor minus 1, with
  1021.  * a maximum multiplier of 5 for SDVO.
  1022.  */
  1023. #define   DPLL_MD_UDI_MULTIPLIER_MASK           0x00003f00
  1024. #define   DPLL_MD_UDI_MULTIPLIER_SHIFT          8
  1025. /*
  1026.  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
  1027.  * This best be set to the default value (3) or the CRT won't work. No,
  1028.  * I don't entirely understand what this does...
  1029.  */
  1030. #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK       0x0000003f
  1031. #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT      0
  1032. #define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
  1033. #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
  1034.  
  1035. #define _FPA0   0x06040
  1036. #define _FPA1   0x06044
  1037. #define _FPB0   0x06048
  1038. #define _FPB1   0x0604c
  1039. #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
  1040. #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
  1041. #define   FP_N_DIV_MASK         0x003f0000
  1042. #define   FP_N_PINEVIEW_DIV_MASK        0x00ff0000
  1043. #define   FP_N_DIV_SHIFT                16
  1044. #define   FP_M1_DIV_MASK        0x00003f00
  1045. #define   FP_M1_DIV_SHIFT                8
  1046. #define   FP_M2_DIV_MASK        0x0000003f
  1047. #define   FP_M2_PINEVIEW_DIV_MASK       0x000000ff
  1048. #define   FP_M2_DIV_SHIFT                0
  1049. #define DPLL_TEST       0x606c
  1050. #define   DPLLB_TEST_SDVO_DIV_1         (0 << 22)
  1051. #define   DPLLB_TEST_SDVO_DIV_2         (1 << 22)
  1052. #define   DPLLB_TEST_SDVO_DIV_4         (2 << 22)
  1053. #define   DPLLB_TEST_SDVO_DIV_MASK      (3 << 22)
  1054. #define   DPLLB_TEST_N_BYPASS           (1 << 19)
  1055. #define   DPLLB_TEST_M_BYPASS           (1 << 18)
  1056. #define   DPLLB_INPUT_BUFFER_ENABLE     (1 << 16)
  1057. #define   DPLLA_TEST_N_BYPASS           (1 << 3)
  1058. #define   DPLLA_TEST_M_BYPASS           (1 << 2)
  1059. #define   DPLLA_INPUT_BUFFER_ENABLE     (1 << 0)
  1060. #define D_STATE         0x6104
  1061. #define  DSTATE_GFX_RESET_I830                  (1<<6)
  1062. #define  DSTATE_PLL_D3_OFF                      (1<<3)
  1063. #define  DSTATE_GFX_CLOCK_GATING                (1<<1)
  1064. #define  DSTATE_DOT_CLOCK_GATING                (1<<0)
  1065. #define DSPCLK_GATE_D           0x6200
  1066. # define DPUNIT_B_CLOCK_GATE_DISABLE            (1 << 30) /* 965 */
  1067. # define VSUNIT_CLOCK_GATE_DISABLE              (1 << 29) /* 965 */
  1068. # define VRHUNIT_CLOCK_GATE_DISABLE             (1 << 28) /* 965 */
  1069. # define VRDUNIT_CLOCK_GATE_DISABLE             (1 << 27) /* 965 */
  1070. # define AUDUNIT_CLOCK_GATE_DISABLE             (1 << 26) /* 965 */
  1071. # define DPUNIT_A_CLOCK_GATE_DISABLE            (1 << 25) /* 965 */
  1072. # define DPCUNIT_CLOCK_GATE_DISABLE             (1 << 24) /* 965 */
  1073. # define TVRUNIT_CLOCK_GATE_DISABLE             (1 << 23) /* 915-945 */
  1074. # define TVCUNIT_CLOCK_GATE_DISABLE             (1 << 22) /* 915-945 */
  1075. # define TVFUNIT_CLOCK_GATE_DISABLE             (1 << 21) /* 915-945 */
  1076. # define TVEUNIT_CLOCK_GATE_DISABLE             (1 << 20) /* 915-945 */
  1077. # define DVSUNIT_CLOCK_GATE_DISABLE             (1 << 19) /* 915-945 */
  1078. # define DSSUNIT_CLOCK_GATE_DISABLE             (1 << 18) /* 915-945 */
  1079. # define DDBUNIT_CLOCK_GATE_DISABLE             (1 << 17) /* 915-945 */
  1080. # define DPRUNIT_CLOCK_GATE_DISABLE             (1 << 16) /* 915-945 */
  1081. # define DPFUNIT_CLOCK_GATE_DISABLE             (1 << 15) /* 915-945 */
  1082. # define DPBMUNIT_CLOCK_GATE_DISABLE            (1 << 14) /* 915-945 */
  1083. # define DPLSUNIT_CLOCK_GATE_DISABLE            (1 << 13) /* 915-945 */
  1084. # define DPLUNIT_CLOCK_GATE_DISABLE             (1 << 12) /* 915-945 */
  1085. # define DPOUNIT_CLOCK_GATE_DISABLE             (1 << 11)
  1086. # define DPBUNIT_CLOCK_GATE_DISABLE             (1 << 10)
  1087. # define DCUNIT_CLOCK_GATE_DISABLE              (1 << 9)
  1088. # define DPUNIT_CLOCK_GATE_DISABLE              (1 << 8)
  1089. # define VRUNIT_CLOCK_GATE_DISABLE              (1 << 7) /* 915+: reserved */
  1090. # define OVHUNIT_CLOCK_GATE_DISABLE             (1 << 6) /* 830-865 */
  1091. # define DPIOUNIT_CLOCK_GATE_DISABLE            (1 << 6) /* 915-945 */
  1092. # define OVFUNIT_CLOCK_GATE_DISABLE             (1 << 5)
  1093. # define OVBUNIT_CLOCK_GATE_DISABLE             (1 << 4)
  1094. /**
  1095.  * This bit must be set on the 830 to prevent hangs when turning off the
  1096.  * overlay scaler.
  1097.  */
  1098. # define OVRUNIT_CLOCK_GATE_DISABLE             (1 << 3)
  1099. # define OVCUNIT_CLOCK_GATE_DISABLE             (1 << 2)
  1100. # define OVUUNIT_CLOCK_GATE_DISABLE             (1 << 1)
  1101. # define ZVUNIT_CLOCK_GATE_DISABLE              (1 << 0) /* 830 */
  1102. # define OVLUNIT_CLOCK_GATE_DISABLE             (1 << 0) /* 845,865 */
  1103.  
  1104. #define RENCLK_GATE_D1          0x6204
  1105. # define BLITTER_CLOCK_GATE_DISABLE             (1 << 13) /* 945GM only */
  1106. # define MPEG_CLOCK_GATE_DISABLE                (1 << 12) /* 945GM only */
  1107. # define PC_FE_CLOCK_GATE_DISABLE               (1 << 11)
  1108. # define PC_BE_CLOCK_GATE_DISABLE               (1 << 10)
  1109. # define WINDOWER_CLOCK_GATE_DISABLE            (1 << 9)
  1110. # define INTERPOLATOR_CLOCK_GATE_DISABLE        (1 << 8)
  1111. # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE    (1 << 7)
  1112. # define MOTION_COMP_CLOCK_GATE_DISABLE         (1 << 6)
  1113. # define MAG_CLOCK_GATE_DISABLE                 (1 << 5)
  1114. /** This bit must be unset on 855,865 */
  1115. # define MECI_CLOCK_GATE_DISABLE                (1 << 4)
  1116. # define DCMP_CLOCK_GATE_DISABLE                (1 << 3)
  1117. # define MEC_CLOCK_GATE_DISABLE                 (1 << 2)
  1118. # define MECO_CLOCK_GATE_DISABLE                (1 << 1)
  1119. /** This bit must be set on 855,865. */
  1120. # define SV_CLOCK_GATE_DISABLE                  (1 << 0)
  1121. # define I915_MPEG_CLOCK_GATE_DISABLE           (1 << 16)
  1122. # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE      (1 << 15)
  1123. # define I915_MOTION_COMP_CLOCK_GATE_DISABLE    (1 << 14)
  1124. # define I915_BD_BF_CLOCK_GATE_DISABLE          (1 << 13)
  1125. # define I915_SF_SE_CLOCK_GATE_DISABLE          (1 << 12)
  1126. # define I915_WM_CLOCK_GATE_DISABLE             (1 << 11)
  1127. # define I915_IZ_CLOCK_GATE_DISABLE             (1 << 10)
  1128. # define I915_PI_CLOCK_GATE_DISABLE             (1 << 9)
  1129. # define I915_DI_CLOCK_GATE_DISABLE             (1 << 8)
  1130. # define I915_SH_SV_CLOCK_GATE_DISABLE          (1 << 7)
  1131. # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE    (1 << 6)
  1132. # define I915_SC_CLOCK_GATE_DISABLE             (1 << 5)
  1133. # define I915_FL_CLOCK_GATE_DISABLE             (1 << 4)
  1134. # define I915_DM_CLOCK_GATE_DISABLE             (1 << 3)
  1135. # define I915_PS_CLOCK_GATE_DISABLE             (1 << 2)
  1136. # define I915_CC_CLOCK_GATE_DISABLE             (1 << 1)
  1137. # define I915_BY_CLOCK_GATE_DISABLE             (1 << 0)
  1138.  
  1139. # define I965_RCZ_CLOCK_GATE_DISABLE            (1 << 30)
  1140. /** This bit must always be set on 965G/965GM */
  1141. # define I965_RCC_CLOCK_GATE_DISABLE            (1 << 29)
  1142. # define I965_RCPB_CLOCK_GATE_DISABLE           (1 << 28)
  1143. # define I965_DAP_CLOCK_GATE_DISABLE            (1 << 27)
  1144. # define I965_ROC_CLOCK_GATE_DISABLE            (1 << 26)
  1145. # define I965_GW_CLOCK_GATE_DISABLE             (1 << 25)
  1146. # define I965_TD_CLOCK_GATE_DISABLE             (1 << 24)
  1147. /** This bit must always be set on 965G */
  1148. # define I965_ISC_CLOCK_GATE_DISABLE            (1 << 23)
  1149. # define I965_IC_CLOCK_GATE_DISABLE             (1 << 22)
  1150. # define I965_EU_CLOCK_GATE_DISABLE             (1 << 21)
  1151. # define I965_IF_CLOCK_GATE_DISABLE             (1 << 20)
  1152. # define I965_TC_CLOCK_GATE_DISABLE             (1 << 19)
  1153. # define I965_SO_CLOCK_GATE_DISABLE             (1 << 17)
  1154. # define I965_FBC_CLOCK_GATE_DISABLE            (1 << 16)
  1155. # define I965_MARI_CLOCK_GATE_DISABLE           (1 << 15)
  1156. # define I965_MASF_CLOCK_GATE_DISABLE           (1 << 14)
  1157. # define I965_MAWB_CLOCK_GATE_DISABLE           (1 << 13)
  1158. # define I965_EM_CLOCK_GATE_DISABLE             (1 << 12)
  1159. # define I965_UC_CLOCK_GATE_DISABLE             (1 << 11)
  1160. # define I965_SI_CLOCK_GATE_DISABLE             (1 << 6)
  1161. # define I965_MT_CLOCK_GATE_DISABLE             (1 << 5)
  1162. # define I965_PL_CLOCK_GATE_DISABLE             (1 << 4)
  1163. # define I965_DG_CLOCK_GATE_DISABLE             (1 << 3)
  1164. # define I965_QC_CLOCK_GATE_DISABLE             (1 << 2)
  1165. # define I965_FT_CLOCK_GATE_DISABLE             (1 << 1)
  1166. # define I965_DM_CLOCK_GATE_DISABLE             (1 << 0)
  1167.  
  1168. #define RENCLK_GATE_D2          0x6208
  1169. #define VF_UNIT_CLOCK_GATE_DISABLE              (1 << 9)
  1170. #define GS_UNIT_CLOCK_GATE_DISABLE              (1 << 7)
  1171. #define CL_UNIT_CLOCK_GATE_DISABLE              (1 << 6)
  1172. #define RAMCLK_GATE_D           0x6210          /* CRL only */
  1173. #define DEUC                    0x6214          /* CRL only */
  1174.  
  1175. #define FW_BLC_SELF_VLV         (VLV_DISPLAY_BASE + 0x6500)
  1176. #define  FW_CSPWRDWNEN          (1<<15)
  1177.  
  1178. /*
  1179.  * Palette regs
  1180.  */
  1181.  
  1182. #define _PALETTE_A              (dev_priv->info->display_mmio_offset + 0xa000)
  1183. #define _PALETTE_B              (dev_priv->info->display_mmio_offset + 0xa800)
  1184. #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
  1185.  
  1186. /* MCH MMIO space */
  1187.  
  1188. /*
  1189.  * MCHBAR mirror.
  1190.  *
  1191.  * This mirrors the MCHBAR MMIO space whose location is determined by
  1192.  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
  1193.  * every way.  It is not accessible from the CP register read instructions.
  1194.  *
  1195.  */
  1196. #define MCHBAR_MIRROR_BASE      0x10000
  1197.  
  1198. #define MCHBAR_MIRROR_BASE_SNB  0x140000
  1199.  
  1200. /** 915-945 and GM965 MCH register controlling DRAM channel access */
  1201. #define DCC                     0x10200
  1202. #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
  1203. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
  1204. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
  1205. #define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
  1206. #define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
  1207. #define DCC_CHANNEL_XOR_BIT_17                          (1 << 9)
  1208.  
  1209. /** Pineview MCH register contains DDR3 setting */
  1210. #define CSHRDDR3CTL            0x101a8
  1211. #define CSHRDDR3CTL_DDR3       (1 << 2)
  1212.  
  1213. /** 965 MCH register controlling DRAM channel configuration */
  1214. #define C0DRB3                  0x10206
  1215. #define C1DRB3                  0x10606
  1216.  
  1217. /** snb MCH registers for reading the DRAM channel configuration */
  1218. #define MAD_DIMM_C0                     (MCHBAR_MIRROR_BASE_SNB + 0x5004)
  1219. #define MAD_DIMM_C1                     (MCHBAR_MIRROR_BASE_SNB + 0x5008)
  1220. #define MAD_DIMM_C2                     (MCHBAR_MIRROR_BASE_SNB + 0x500C)
  1221. #define   MAD_DIMM_ECC_MASK             (0x3 << 24)
  1222. #define   MAD_DIMM_ECC_OFF              (0x0 << 24)
  1223. #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF  (0x1 << 24)
  1224. #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON  (0x2 << 24)
  1225. #define   MAD_DIMM_ECC_ON               (0x3 << 24)
  1226. #define   MAD_DIMM_ENH_INTERLEAVE       (0x1 << 22)
  1227. #define   MAD_DIMM_RANK_INTERLEAVE      (0x1 << 21)
  1228. #define   MAD_DIMM_B_WIDTH_X16          (0x1 << 20) /* X8 chips if unset */
  1229. #define   MAD_DIMM_A_WIDTH_X16          (0x1 << 19) /* X8 chips if unset */
  1230. #define   MAD_DIMM_B_DUAL_RANK          (0x1 << 18)
  1231. #define   MAD_DIMM_A_DUAL_RANK          (0x1 << 17)
  1232. #define   MAD_DIMM_A_SELECT             (0x1 << 16)
  1233. /* DIMM sizes are in multiples of 256mb. */
  1234. #define   MAD_DIMM_B_SIZE_SHIFT         8
  1235. #define   MAD_DIMM_B_SIZE_MASK          (0xff << MAD_DIMM_B_SIZE_SHIFT)
  1236. #define   MAD_DIMM_A_SIZE_SHIFT         0
  1237. #define   MAD_DIMM_A_SIZE_MASK          (0xff << MAD_DIMM_A_SIZE_SHIFT)
  1238.  
  1239. /** snb MCH registers for priority tuning */
  1240. #define MCH_SSKPD                       (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
  1241. #define   MCH_SSKPD_WM0_MASK            0x3f
  1242. #define   MCH_SSKPD_WM0_VAL             0xc
  1243.  
  1244. /* Clocking configuration register */
  1245. #define CLKCFG                  0x10c00
  1246. #define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
  1247. #define CLKCFG_FSB_533                                  (1 << 0)        /* hrawclk 133 */
  1248. #define CLKCFG_FSB_667                                  (3 << 0)        /* hrawclk 166 */
  1249. #define CLKCFG_FSB_800                                  (2 << 0)        /* hrawclk 200 */
  1250. #define CLKCFG_FSB_1067                                 (6 << 0)        /* hrawclk 266 */
  1251. #define CLKCFG_FSB_1333                                 (7 << 0)        /* hrawclk 333 */
  1252. /* Note, below two are guess */
  1253. #define CLKCFG_FSB_1600                                 (4 << 0)        /* hrawclk 400 */
  1254. #define CLKCFG_FSB_1600_ALT                             (0 << 0)        /* hrawclk 400 */
  1255. #define CLKCFG_FSB_MASK                                 (7 << 0)
  1256. #define CLKCFG_MEM_533                                  (1 << 4)
  1257. #define CLKCFG_MEM_667                                  (2 << 4)
  1258. #define CLKCFG_MEM_800                                  (3 << 4)
  1259. #define CLKCFG_MEM_MASK                                 (7 << 4)
  1260.  
  1261. #define TSC1                    0x11001
  1262. #define   TSE                   (1<<0)
  1263. #define TR1                     0x11006
  1264. #define TSFS                    0x11020
  1265. #define   TSFS_SLOPE_MASK       0x0000ff00
  1266. #define   TSFS_SLOPE_SHIFT      8
  1267. #define   TSFS_INTR_MASK        0x000000ff
  1268.  
  1269. #define CRSTANDVID              0x11100
  1270. #define PXVFREQ_BASE            0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
  1271. #define   PXVFREQ_PX_MASK       0x7f000000
  1272. #define   PXVFREQ_PX_SHIFT      24
  1273. #define VIDFREQ_BASE            0x11110
  1274. #define VIDFREQ1                0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
  1275. #define VIDFREQ2                0x11114
  1276. #define VIDFREQ3                0x11118
  1277. #define VIDFREQ4                0x1111c
  1278. #define   VIDFREQ_P0_MASK       0x1f000000
  1279. #define   VIDFREQ_P0_SHIFT      24
  1280. #define   VIDFREQ_P0_CSCLK_MASK 0x00f00000
  1281. #define   VIDFREQ_P0_CSCLK_SHIFT 20
  1282. #define   VIDFREQ_P0_CRCLK_MASK 0x000f0000
  1283. #define   VIDFREQ_P0_CRCLK_SHIFT 16
  1284. #define   VIDFREQ_P1_MASK       0x00001f00
  1285. #define   VIDFREQ_P1_SHIFT      8
  1286. #define   VIDFREQ_P1_CSCLK_MASK 0x000000f0
  1287. #define   VIDFREQ_P1_CSCLK_SHIFT 4
  1288. #define   VIDFREQ_P1_CRCLK_MASK 0x0000000f
  1289. #define INTTOEXT_BASE_ILK       0x11300
  1290. #define INTTOEXT_BASE           0x11120 /* INTTOEXT1-8 (0x1113c) */
  1291. #define   INTTOEXT_MAP3_SHIFT   24
  1292. #define   INTTOEXT_MAP3_MASK    (0x1f << INTTOEXT_MAP3_SHIFT)
  1293. #define   INTTOEXT_MAP2_SHIFT   16
  1294. #define   INTTOEXT_MAP2_MASK    (0x1f << INTTOEXT_MAP2_SHIFT)
  1295. #define   INTTOEXT_MAP1_SHIFT   8
  1296. #define   INTTOEXT_MAP1_MASK    (0x1f << INTTOEXT_MAP1_SHIFT)
  1297. #define   INTTOEXT_MAP0_SHIFT   0
  1298. #define   INTTOEXT_MAP0_MASK    (0x1f << INTTOEXT_MAP0_SHIFT)
  1299. #define MEMSWCTL                0x11170 /* Ironlake only */
  1300. #define   MEMCTL_CMD_MASK       0xe000
  1301. #define   MEMCTL_CMD_SHIFT      13
  1302. #define   MEMCTL_CMD_RCLK_OFF   0
  1303. #define   MEMCTL_CMD_RCLK_ON    1
  1304. #define   MEMCTL_CMD_CHFREQ     2
  1305. #define   MEMCTL_CMD_CHVID      3
  1306. #define   MEMCTL_CMD_VMMOFF     4
  1307. #define   MEMCTL_CMD_VMMON      5
  1308. #define   MEMCTL_CMD_STS        (1<<12) /* write 1 triggers command, clears
  1309.                                            when command complete */
  1310. #define   MEMCTL_FREQ_MASK      0x0f00 /* jitter, from 0-15 */
  1311. #define   MEMCTL_FREQ_SHIFT     8
  1312. #define   MEMCTL_SFCAVM         (1<<7)
  1313. #define   MEMCTL_TGT_VID_MASK   0x007f
  1314. #define MEMIHYST                0x1117c
  1315. #define MEMINTREN               0x11180 /* 16 bits */
  1316. #define   MEMINT_RSEXIT_EN      (1<<8)
  1317. #define   MEMINT_CX_SUPR_EN     (1<<7)
  1318. #define   MEMINT_CONT_BUSY_EN   (1<<6)
  1319. #define   MEMINT_AVG_BUSY_EN    (1<<5)
  1320. #define   MEMINT_EVAL_CHG_EN    (1<<4)
  1321. #define   MEMINT_MON_IDLE_EN    (1<<3)
  1322. #define   MEMINT_UP_EVAL_EN     (1<<2)
  1323. #define   MEMINT_DOWN_EVAL_EN   (1<<1)
  1324. #define   MEMINT_SW_CMD_EN      (1<<0)
  1325. #define MEMINTRSTR              0x11182 /* 16 bits */
  1326. #define   MEM_RSEXIT_MASK       0xc000
  1327. #define   MEM_RSEXIT_SHIFT      14
  1328. #define   MEM_CONT_BUSY_MASK    0x3000
  1329. #define   MEM_CONT_BUSY_SHIFT   12
  1330. #define   MEM_AVG_BUSY_MASK     0x0c00
  1331. #define   MEM_AVG_BUSY_SHIFT    10
  1332. #define   MEM_EVAL_CHG_MASK     0x0300
  1333. #define   MEM_EVAL_BUSY_SHIFT   8
  1334. #define   MEM_MON_IDLE_MASK     0x00c0
  1335. #define   MEM_MON_IDLE_SHIFT    6
  1336. #define   MEM_UP_EVAL_MASK      0x0030
  1337. #define   MEM_UP_EVAL_SHIFT     4
  1338. #define   MEM_DOWN_EVAL_MASK    0x000c
  1339. #define   MEM_DOWN_EVAL_SHIFT   2
  1340. #define   MEM_SW_CMD_MASK       0x0003
  1341. #define   MEM_INT_STEER_GFX     0
  1342. #define   MEM_INT_STEER_CMR     1
  1343. #define   MEM_INT_STEER_SMI     2
  1344. #define   MEM_INT_STEER_SCI     3
  1345. #define MEMINTRSTS              0x11184
  1346. #define   MEMINT_RSEXIT         (1<<7)
  1347. #define   MEMINT_CONT_BUSY      (1<<6)
  1348. #define   MEMINT_AVG_BUSY       (1<<5)
  1349. #define   MEMINT_EVAL_CHG       (1<<4)
  1350. #define   MEMINT_MON_IDLE       (1<<3)
  1351. #define   MEMINT_UP_EVAL        (1<<2)
  1352. #define   MEMINT_DOWN_EVAL      (1<<1)
  1353. #define   MEMINT_SW_CMD         (1<<0)
  1354. #define MEMMODECTL              0x11190
  1355. #define   MEMMODE_BOOST_EN      (1<<31)
  1356. #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
  1357. #define   MEMMODE_BOOST_FREQ_SHIFT 24
  1358. #define   MEMMODE_IDLE_MODE_MASK 0x00030000
  1359. #define   MEMMODE_IDLE_MODE_SHIFT 16
  1360. #define   MEMMODE_IDLE_MODE_EVAL 0
  1361. #define   MEMMODE_IDLE_MODE_CONT 1
  1362. #define   MEMMODE_HWIDLE_EN     (1<<15)
  1363. #define   MEMMODE_SWMODE_EN     (1<<14)
  1364. #define   MEMMODE_RCLK_GATE     (1<<13)
  1365. #define   MEMMODE_HW_UPDATE     (1<<12)
  1366. #define   MEMMODE_FSTART_MASK   0x00000f00 /* starting jitter, 0-15 */
  1367. #define   MEMMODE_FSTART_SHIFT  8
  1368. #define   MEMMODE_FMAX_MASK     0x000000f0 /* max jitter, 0-15 */
  1369. #define   MEMMODE_FMAX_SHIFT    4
  1370. #define   MEMMODE_FMIN_MASK     0x0000000f /* min jitter, 0-15 */
  1371. #define RCBMAXAVG               0x1119c
  1372. #define MEMSWCTL2               0x1119e /* Cantiga only */
  1373. #define   SWMEMCMD_RENDER_OFF   (0 << 13)
  1374. #define   SWMEMCMD_RENDER_ON    (1 << 13)
  1375. #define   SWMEMCMD_SWFREQ       (2 << 13)
  1376. #define   SWMEMCMD_TARVID       (3 << 13)
  1377. #define   SWMEMCMD_VRM_OFF      (4 << 13)
  1378. #define   SWMEMCMD_VRM_ON       (5 << 13)
  1379. #define   CMDSTS                (1<<12)
  1380. #define   SFCAVM                (1<<11)
  1381. #define   SWFREQ_MASK           0x0380 /* P0-7 */
  1382. #define   SWFREQ_SHIFT          7
  1383. #define   TARVID_MASK           0x001f
  1384. #define MEMSTAT_CTG             0x111a0
  1385. #define RCBMINAVG               0x111a0
  1386. #define RCUPEI                  0x111b0
  1387. #define RCDNEI                  0x111b4
  1388. #define RSTDBYCTL               0x111b8
  1389. #define   RS1EN                 (1<<31)
  1390. #define   RS2EN                 (1<<30)
  1391. #define   RS3EN                 (1<<29)
  1392. #define   D3RS3EN               (1<<28) /* Display D3 imlies RS3 */
  1393. #define   SWPROMORSX            (1<<27) /* RSx promotion timers ignored */
  1394. #define   RCWAKERW              (1<<26) /* Resetwarn from PCH causes wakeup */
  1395. #define   DPRSLPVREN            (1<<25) /* Fast voltage ramp enable */
  1396. #define   GFXTGHYST             (1<<24) /* Hysteresis to allow trunk gating */
  1397. #define   RCX_SW_EXIT           (1<<23) /* Leave RSx and prevent re-entry */
  1398. #define   RSX_STATUS_MASK       (7<<20)
  1399. #define   RSX_STATUS_ON         (0<<20)
  1400. #define   RSX_STATUS_RC1        (1<<20)
  1401. #define   RSX_STATUS_RC1E       (2<<20)
  1402. #define   RSX_STATUS_RS1        (3<<20)
  1403. #define   RSX_STATUS_RS2        (4<<20) /* aka rc6 */
  1404. #define   RSX_STATUS_RSVD       (5<<20) /* deep rc6 unsupported on ilk */
  1405. #define   RSX_STATUS_RS3        (6<<20) /* rs3 unsupported on ilk */
  1406. #define   RSX_STATUS_RSVD2      (7<<20)
  1407. #define   UWRCRSXE              (1<<19) /* wake counter limit prevents rsx */
  1408. #define   RSCRP                 (1<<18) /* rs requests control on rs1/2 reqs */
  1409. #define   JRSC                  (1<<17) /* rsx coupled to cpu c-state */
  1410. #define   RS2INC0               (1<<16) /* allow rs2 in cpu c0 */
  1411. #define   RS1CONTSAV_MASK       (3<<14)
  1412. #define   RS1CONTSAV_NO_RS1     (0<<14) /* rs1 doesn't save/restore context */
  1413. #define   RS1CONTSAV_RSVD       (1<<14)
  1414. #define   RS1CONTSAV_SAVE_RS1   (2<<14) /* rs1 saves context */
  1415. #define   RS1CONTSAV_FULL_RS1   (3<<14) /* rs1 saves and restores context */
  1416. #define   NORMSLEXLAT_MASK      (3<<12)
  1417. #define   SLOW_RS123            (0<<12)
  1418. #define   SLOW_RS23             (1<<12)
  1419. #define   SLOW_RS3              (2<<12)
  1420. #define   NORMAL_RS123          (3<<12)
  1421. #define   RCMODE_TIMEOUT        (1<<11) /* 0 is eval interval method */
  1422. #define   IMPROMOEN             (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
  1423. #define   RCENTSYNC             (1<<9) /* rs coupled to cpu c-state (3/6/7) */
  1424. #define   STATELOCK             (1<<7) /* locked to rs_cstate if 0 */
  1425. #define   RS_CSTATE_MASK        (3<<4)
  1426. #define   RS_CSTATE_C367_RS1    (0<<4)
  1427. #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
  1428. #define   RS_CSTATE_RSVD        (2<<4)
  1429. #define   RS_CSTATE_C367_RS2    (3<<4)
  1430. #define   REDSAVES              (1<<3) /* no context save if was idle during rs0 */
  1431. #define   REDRESTORES           (1<<2) /* no restore if was idle during rs0 */
  1432. #define VIDCTL                  0x111c0
  1433. #define VIDSTS                  0x111c8
  1434. #define VIDSTART                0x111cc /* 8 bits */
  1435. #define MEMSTAT_ILK                     0x111f8
  1436. #define   MEMSTAT_VID_MASK      0x7f00
  1437. #define   MEMSTAT_VID_SHIFT     8
  1438. #define   MEMSTAT_PSTATE_MASK   0x00f8
  1439. #define   MEMSTAT_PSTATE_SHIFT  3
  1440. #define   MEMSTAT_MON_ACTV      (1<<2)
  1441. #define   MEMSTAT_SRC_CTL_MASK  0x0003
  1442. #define   MEMSTAT_SRC_CTL_CORE  0
  1443. #define   MEMSTAT_SRC_CTL_TRB   1
  1444. #define   MEMSTAT_SRC_CTL_THM   2
  1445. #define   MEMSTAT_SRC_CTL_STDBY 3
  1446. #define RCPREVBSYTUPAVG         0x113b8
  1447. #define RCPREVBSYTDNAVG         0x113bc
  1448. #define PMMISC                  0x11214
  1449. #define   MCPPCE_EN             (1<<0) /* enable PM_MSG from PCH->MPC */
  1450. #define SDEW                    0x1124c
  1451. #define CSIEW0                  0x11250
  1452. #define CSIEW1                  0x11254
  1453. #define CSIEW2                  0x11258
  1454. #define PEW                     0x1125c
  1455. #define DEW                     0x11270
  1456. #define MCHAFE                  0x112c0
  1457. #define CSIEC                   0x112e0
  1458. #define DMIEC                   0x112e4
  1459. #define DDREC                   0x112e8
  1460. #define PEG0EC                  0x112ec
  1461. #define PEG1EC                  0x112f0
  1462. #define GFXEC                   0x112f4
  1463. #define RPPREVBSYTUPAVG         0x113b8
  1464. #define RPPREVBSYTDNAVG         0x113bc
  1465. #define ECR                     0x11600
  1466. #define   ECR_GPFE              (1<<31)
  1467. #define   ECR_IMONE             (1<<30)
  1468. #define   ECR_CAP_MASK          0x0000001f /* Event range, 0-31 */
  1469. #define OGW0                    0x11608
  1470. #define OGW1                    0x1160c
  1471. #define EG0                     0x11610
  1472. #define EG1                     0x11614
  1473. #define EG2                     0x11618
  1474. #define EG3                     0x1161c
  1475. #define EG4                     0x11620
  1476. #define EG5                     0x11624
  1477. #define EG6                     0x11628
  1478. #define EG7                     0x1162c
  1479. #define PXW                     0x11664
  1480. #define PXWL                    0x11680
  1481. #define LCFUSE02                0x116c0
  1482. #define   LCFUSE_HIV_MASK       0x000000ff
  1483. #define CSIPLL0                 0x12c10
  1484. #define DDRMPLL1                0X12c20
  1485. #define PEG_BAND_GAP_DATA       0x14d68
  1486.  
  1487. #define GEN6_GT_THREAD_STATUS_REG 0x13805c
  1488. #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
  1489. #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
  1490.  
  1491. #define GEN6_GT_PERF_STATUS     0x145948
  1492. #define GEN6_RP_STATE_LIMITS    0x145994
  1493. #define GEN6_RP_STATE_CAP       0x145998
  1494.  
  1495. /*
  1496.  * Logical Context regs
  1497.  */
  1498. #define CCID                    0x2180
  1499. #define   CCID_EN               (1<<0)
  1500. #define CXT_SIZE                0x21a0
  1501. #define GEN6_CXT_POWER_SIZE(cxt_reg)    ((cxt_reg >> 24) & 0x3f)
  1502. #define GEN6_CXT_RING_SIZE(cxt_reg)     ((cxt_reg >> 18) & 0x3f)
  1503. #define GEN6_CXT_RENDER_SIZE(cxt_reg)   ((cxt_reg >> 12) & 0x3f)
  1504. #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
  1505. #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
  1506. #define GEN6_CXT_TOTAL_SIZE(cxt_reg)    (GEN6_CXT_POWER_SIZE(cxt_reg) + \
  1507.                                         GEN6_CXT_RING_SIZE(cxt_reg) + \
  1508.                                         GEN6_CXT_RENDER_SIZE(cxt_reg) + \
  1509.                                         GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
  1510.                                         GEN6_CXT_PIPELINE_SIZE(cxt_reg))
  1511. #define GEN7_CXT_SIZE           0x21a8
  1512. #define GEN7_CXT_POWER_SIZE(ctx_reg)    ((ctx_reg >> 25) & 0x7f)
  1513. #define GEN7_CXT_RING_SIZE(ctx_reg)     ((ctx_reg >> 22) & 0x7)
  1514. #define GEN7_CXT_RENDER_SIZE(ctx_reg)   ((ctx_reg >> 16) & 0x3f)
  1515. #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
  1516. #define GEN7_CXT_GT1_SIZE(ctx_reg)      ((ctx_reg >> 6) & 0x7)
  1517. #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)  ((ctx_reg >> 0) & 0x3f)
  1518. #define GEN7_CXT_TOTAL_SIZE(ctx_reg)    (GEN7_CXT_POWER_SIZE(ctx_reg) + \
  1519.                                          GEN7_CXT_RING_SIZE(ctx_reg) + \
  1520.                                          GEN7_CXT_RENDER_SIZE(ctx_reg) + \
  1521.                                          GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
  1522.                                          GEN7_CXT_GT1_SIZE(ctx_reg) + \
  1523.                                          GEN7_CXT_VFSTATE_SIZE(ctx_reg))
  1524. #define HSW_CXT_POWER_SIZE(ctx_reg)     ((ctx_reg >> 26) & 0x3f)
  1525. #define HSW_CXT_RING_SIZE(ctx_reg)      ((ctx_reg >> 23) & 0x7)
  1526. #define HSW_CXT_RENDER_SIZE(ctx_reg)    ((ctx_reg >> 15) & 0xff)
  1527. #define HSW_CXT_TOTAL_SIZE(ctx_reg)     (HSW_CXT_POWER_SIZE(ctx_reg) + \
  1528.                                          HSW_CXT_RING_SIZE(ctx_reg) + \
  1529.                                          HSW_CXT_RENDER_SIZE(ctx_reg) + \
  1530.                                          GEN7_CXT_VFSTATE_SIZE(ctx_reg))
  1531.  
  1532.  
  1533. /*
  1534.  * Overlay regs
  1535.  */
  1536.  
  1537. #define OVADD                   0x30000
  1538. #define DOVSTA                  0x30008
  1539. #define OC_BUF                  (0x3<<20)
  1540. #define OGAMC5                  0x30010
  1541. #define OGAMC4                  0x30014
  1542. #define OGAMC3                  0x30018
  1543. #define OGAMC2                  0x3001c
  1544. #define OGAMC1                  0x30020
  1545. #define OGAMC0                  0x30024
  1546.  
  1547. /*
  1548.  * Display engine regs
  1549.  */
  1550.  
  1551. /* Pipe A timing regs */
  1552. #define _HTOTAL_A       (dev_priv->info->display_mmio_offset + 0x60000)
  1553. #define _HBLANK_A       (dev_priv->info->display_mmio_offset + 0x60004)
  1554. #define _HSYNC_A        (dev_priv->info->display_mmio_offset + 0x60008)
  1555. #define _VTOTAL_A       (dev_priv->info->display_mmio_offset + 0x6000c)
  1556. #define _VBLANK_A       (dev_priv->info->display_mmio_offset + 0x60010)
  1557. #define _VSYNC_A        (dev_priv->info->display_mmio_offset + 0x60014)
  1558. #define _PIPEASRC       (dev_priv->info->display_mmio_offset + 0x6001c)
  1559. #define _BCLRPAT_A      (dev_priv->info->display_mmio_offset + 0x60020)
  1560. #define _VSYNCSHIFT_A   (dev_priv->info->display_mmio_offset + 0x60028)
  1561.  
  1562. /* Pipe B timing regs */
  1563. #define _HTOTAL_B       (dev_priv->info->display_mmio_offset + 0x61000)
  1564. #define _HBLANK_B       (dev_priv->info->display_mmio_offset + 0x61004)
  1565. #define _HSYNC_B        (dev_priv->info->display_mmio_offset + 0x61008)
  1566. #define _VTOTAL_B       (dev_priv->info->display_mmio_offset + 0x6100c)
  1567. #define _VBLANK_B       (dev_priv->info->display_mmio_offset + 0x61010)
  1568. #define _VSYNC_B        (dev_priv->info->display_mmio_offset + 0x61014)
  1569. #define _PIPEBSRC       (dev_priv->info->display_mmio_offset + 0x6101c)
  1570. #define _BCLRPAT_B      (dev_priv->info->display_mmio_offset + 0x61020)
  1571. #define _VSYNCSHIFT_B   (dev_priv->info->display_mmio_offset + 0x61028)
  1572.  
  1573.  
  1574. #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
  1575. #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
  1576. #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
  1577. #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
  1578. #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
  1579. #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
  1580. #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
  1581. #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
  1582.  
  1583. /* VGA port control */
  1584. #define ADPA                    0x61100
  1585. #define PCH_ADPA                0xe1100
  1586. #define VLV_ADPA                (VLV_DISPLAY_BASE + ADPA)
  1587.  
  1588. #define   ADPA_DAC_ENABLE       (1<<31)
  1589. #define   ADPA_DAC_DISABLE      0
  1590. #define   ADPA_PIPE_SELECT_MASK (1<<30)
  1591. #define   ADPA_PIPE_A_SELECT    0
  1592. #define   ADPA_PIPE_B_SELECT    (1<<30)
  1593. #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
  1594. /* CPT uses bits 29:30 for pch transcoder select */
  1595. #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
  1596. #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
  1597. #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
  1598. #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
  1599. #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
  1600. #define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
  1601. #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
  1602. #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
  1603. #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
  1604. #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
  1605. #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
  1606. #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
  1607. #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
  1608. #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
  1609. #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
  1610. #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
  1611. #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
  1612. #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
  1613. #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
  1614. #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
  1615. #define   ADPA_SETS_HVPOLARITY  0
  1616. #define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
  1617. #define   ADPA_VSYNC_CNTL_ENABLE 0
  1618. #define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
  1619. #define   ADPA_HSYNC_CNTL_ENABLE 0
  1620. #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
  1621. #define   ADPA_VSYNC_ACTIVE_LOW 0
  1622. #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
  1623. #define   ADPA_HSYNC_ACTIVE_LOW 0
  1624. #define   ADPA_DPMS_MASK        (~(3<<10))
  1625. #define   ADPA_DPMS_ON          (0<<10)
  1626. #define   ADPA_DPMS_SUSPEND     (1<<10)
  1627. #define   ADPA_DPMS_STANDBY     (2<<10)
  1628. #define   ADPA_DPMS_OFF         (3<<10)
  1629.  
  1630.  
  1631. /* Hotplug control (945+ only) */
  1632. #define PORT_HOTPLUG_EN         (dev_priv->info->display_mmio_offset + 0x61110)
  1633. #define   PORTB_HOTPLUG_INT_EN                  (1 << 29)
  1634. #define   PORTC_HOTPLUG_INT_EN                  (1 << 28)
  1635. #define   PORTD_HOTPLUG_INT_EN                  (1 << 27)
  1636. #define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
  1637. #define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
  1638. #define   TV_HOTPLUG_INT_EN                     (1 << 18)
  1639. #define   CRT_HOTPLUG_INT_EN                    (1 << 9)
  1640. #define   CRT_HOTPLUG_FORCE_DETECT              (1 << 3)
  1641. #define CRT_HOTPLUG_ACTIVATION_PERIOD_32        (0 << 8)
  1642. /* must use period 64 on GM45 according to docs */
  1643. #define CRT_HOTPLUG_ACTIVATION_PERIOD_64        (1 << 8)
  1644. #define CRT_HOTPLUG_DAC_ON_TIME_2M              (0 << 7)
  1645. #define CRT_HOTPLUG_DAC_ON_TIME_4M              (1 << 7)
  1646. #define CRT_HOTPLUG_VOLTAGE_COMPARE_40          (0 << 5)
  1647. #define CRT_HOTPLUG_VOLTAGE_COMPARE_50          (1 << 5)
  1648. #define CRT_HOTPLUG_VOLTAGE_COMPARE_60          (2 << 5)
  1649. #define CRT_HOTPLUG_VOLTAGE_COMPARE_70          (3 << 5)
  1650. #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK        (3 << 5)
  1651. #define CRT_HOTPLUG_DETECT_DELAY_1G             (0 << 4)
  1652. #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
  1653. #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
  1654. #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
  1655.  
  1656. #define PORT_HOTPLUG_STAT       (dev_priv->info->display_mmio_offset + 0x61114)
  1657. /* HDMI/DP bits are gen4+ */
  1658. #define   PORTB_HOTPLUG_LIVE_STATUS               (1 << 29)
  1659. #define   PORTC_HOTPLUG_LIVE_STATUS               (1 << 28)
  1660. #define   PORTD_HOTPLUG_LIVE_STATUS               (1 << 27)
  1661. #define   PORTD_HOTPLUG_INT_STATUS              (3 << 21)
  1662. #define   PORTC_HOTPLUG_INT_STATUS              (3 << 19)
  1663. #define   PORTB_HOTPLUG_INT_STATUS              (3 << 17)
  1664. /* CRT/TV common between gen3+ */
  1665. #define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
  1666. #define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
  1667. #define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
  1668. #define   CRT_HOTPLUG_MONITOR_COLOR             (3 << 8)
  1669. #define   CRT_HOTPLUG_MONITOR_MONO              (2 << 8)
  1670. #define   CRT_HOTPLUG_MONITOR_NONE              (0 << 8)
  1671. /* SDVO is different across gen3/4 */
  1672. #define   SDVOC_HOTPLUG_INT_STATUS_G4X          (1 << 3)
  1673. #define   SDVOB_HOTPLUG_INT_STATUS_G4X          (1 << 2)
  1674. #define   SDVOC_HOTPLUG_INT_STATUS_I965         (3 << 4)
  1675. #define   SDVOB_HOTPLUG_INT_STATUS_I965         (3 << 2)
  1676. #define   SDVOC_HOTPLUG_INT_STATUS_I915         (1 << 7)
  1677. #define   SDVOB_HOTPLUG_INT_STATUS_I915         (1 << 6)
  1678.  
  1679. /* SDVO port control */
  1680. #define SDVOB                   0x61140
  1681. #define SDVOC                   0x61160
  1682. #define   SDVO_ENABLE           (1 << 31)
  1683. #define   SDVO_PIPE_B_SELECT    (1 << 30)
  1684. #define   SDVO_STALL_SELECT     (1 << 29)
  1685. #define   SDVO_INTERRUPT_ENABLE (1 << 26)
  1686. /**
  1687.  * 915G/GM SDVO pixel multiplier.
  1688.  *
  1689.  * Programmed value is multiplier - 1, up to 5x.
  1690.  *
  1691.  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
  1692.  */
  1693. #define   SDVO_PORT_MULTIPLY_MASK       (7 << 23)
  1694. #define   SDVO_PORT_MULTIPLY_SHIFT              23
  1695. #define   SDVO_PHASE_SELECT_MASK        (15 << 19)
  1696. #define   SDVO_PHASE_SELECT_DEFAULT     (6 << 19)
  1697. #define   SDVO_CLOCK_OUTPUT_INVERT      (1 << 18)
  1698. #define   SDVOC_GANG_MODE               (1 << 16)
  1699. #define   SDVO_ENCODING_SDVO            (0x0 << 10)
  1700. #define   SDVO_ENCODING_HDMI            (0x2 << 10)
  1701. /** Requird for HDMI operation */
  1702. #define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
  1703. #define   SDVO_COLOR_RANGE_16_235       (1 << 8)
  1704. #define   SDVO_BORDER_ENABLE            (1 << 7)
  1705. #define   SDVO_AUDIO_ENABLE             (1 << 6)
  1706. /** New with 965, default is to be set */
  1707. #define   SDVO_VSYNC_ACTIVE_HIGH        (1 << 4)
  1708. /** New with 965, default is to be set */
  1709. #define   SDVO_HSYNC_ACTIVE_HIGH        (1 << 3)
  1710. #define   SDVOB_PCIE_CONCURRENCY        (1 << 3)
  1711. #define   SDVO_DETECTED                 (1 << 2)
  1712. /* Bits to be preserved when writing */
  1713. #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
  1714. #define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
  1715.  
  1716. /* DVO port control */
  1717. #define DVOA                    0x61120
  1718. #define DVOB                    0x61140
  1719. #define DVOC                    0x61160
  1720. #define   DVO_ENABLE                    (1 << 31)
  1721. #define   DVO_PIPE_B_SELECT             (1 << 30)
  1722. #define   DVO_PIPE_STALL_UNUSED         (0 << 28)
  1723. #define   DVO_PIPE_STALL                (1 << 28)
  1724. #define   DVO_PIPE_STALL_TV             (2 << 28)
  1725. #define   DVO_PIPE_STALL_MASK           (3 << 28)
  1726. #define   DVO_USE_VGA_SYNC              (1 << 15)
  1727. #define   DVO_DATA_ORDER_I740           (0 << 14)
  1728. #define   DVO_DATA_ORDER_FP             (1 << 14)
  1729. #define   DVO_VSYNC_DISABLE             (1 << 11)
  1730. #define   DVO_HSYNC_DISABLE             (1 << 10)
  1731. #define   DVO_VSYNC_TRISTATE            (1 << 9)
  1732. #define   DVO_HSYNC_TRISTATE            (1 << 8)
  1733. #define   DVO_BORDER_ENABLE             (1 << 7)
  1734. #define   DVO_DATA_ORDER_GBRG           (1 << 6)
  1735. #define   DVO_DATA_ORDER_RGGB           (0 << 6)
  1736. #define   DVO_DATA_ORDER_GBRG_ERRATA    (0 << 6)
  1737. #define   DVO_DATA_ORDER_RGGB_ERRATA    (1 << 6)
  1738. #define   DVO_VSYNC_ACTIVE_HIGH         (1 << 4)
  1739. #define   DVO_HSYNC_ACTIVE_HIGH         (1 << 3)
  1740. #define   DVO_BLANK_ACTIVE_HIGH         (1 << 2)
  1741. #define   DVO_OUTPUT_CSTATE_PIXELS      (1 << 1)        /* SDG only */
  1742. #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)        /* SDG only */
  1743. #define   DVO_PRESERVE_MASK             (0x7<<24)
  1744. #define DVOA_SRCDIM             0x61124
  1745. #define DVOB_SRCDIM             0x61144
  1746. #define DVOC_SRCDIM             0x61164
  1747. #define   DVO_SRCDIM_HORIZONTAL_SHIFT   12
  1748. #define   DVO_SRCDIM_VERTICAL_SHIFT     0
  1749.  
  1750. /* LVDS port control */
  1751. #define LVDS                    0x61180
  1752. /*
  1753.  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
  1754.  * the DPLL semantics change when the LVDS is assigned to that pipe.
  1755.  */
  1756. #define   LVDS_PORT_EN                  (1 << 31)
  1757. /* Selects pipe B for LVDS data.  Must be set on pre-965. */
  1758. #define   LVDS_PIPEB_SELECT             (1 << 30)
  1759. #define   LVDS_PIPE_MASK                (1 << 30)
  1760. #define   LVDS_PIPE(pipe)               ((pipe) << 30)
  1761. /* LVDS dithering flag on 965/g4x platform */
  1762. #define   LVDS_ENABLE_DITHER            (1 << 25)
  1763. /* LVDS sync polarity flags. Set to invert (i.e. negative) */
  1764. #define   LVDS_VSYNC_POLARITY           (1 << 21)
  1765. #define   LVDS_HSYNC_POLARITY           (1 << 20)
  1766.  
  1767. /* Enable border for unscaled (or aspect-scaled) display */
  1768. #define   LVDS_BORDER_ENABLE            (1 << 15)
  1769. /*
  1770.  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
  1771.  * pixel.
  1772.  */
  1773. #define   LVDS_A0A2_CLKA_POWER_MASK     (3 << 8)
  1774. #define   LVDS_A0A2_CLKA_POWER_DOWN     (0 << 8)
  1775. #define   LVDS_A0A2_CLKA_POWER_UP       (3 << 8)
  1776. /*
  1777.  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
  1778.  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
  1779.  * on.
  1780.  */
  1781. #define   LVDS_A3_POWER_MASK            (3 << 6)
  1782. #define   LVDS_A3_POWER_DOWN            (0 << 6)
  1783. #define   LVDS_A3_POWER_UP              (3 << 6)
  1784. /*
  1785.  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
  1786.  * is set.
  1787.  */
  1788. #define   LVDS_CLKB_POWER_MASK          (3 << 4)
  1789. #define   LVDS_CLKB_POWER_DOWN          (0 << 4)
  1790. #define   LVDS_CLKB_POWER_UP            (3 << 4)
  1791. /*
  1792.  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
  1793.  * setting for whether we are in dual-channel mode.  The B3 pair will
  1794.  * additionally only be powered up when LVDS_A3_POWER_UP is set.
  1795.  */
  1796. #define   LVDS_B0B3_POWER_MASK          (3 << 2)
  1797. #define   LVDS_B0B3_POWER_DOWN          (0 << 2)
  1798. #define   LVDS_B0B3_POWER_UP            (3 << 2)
  1799.  
  1800. /* Video Data Island Packet control */
  1801. #define VIDEO_DIP_DATA          0x61178
  1802. /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
  1803.  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  1804.  * of the infoframe structure specified by CEA-861. */
  1805. #define   VIDEO_DIP_DATA_SIZE   32
  1806. #define VIDEO_DIP_CTL           0x61170
  1807. /* Pre HSW: */
  1808. #define   VIDEO_DIP_ENABLE              (1 << 31)
  1809. #define   VIDEO_DIP_PORT_B              (1 << 29)
  1810. #define   VIDEO_DIP_PORT_C              (2 << 29)
  1811. #define   VIDEO_DIP_PORT_D              (3 << 29)
  1812. #define   VIDEO_DIP_PORT_MASK           (3 << 29)
  1813. #define   VIDEO_DIP_ENABLE_GCP          (1 << 25)
  1814. #define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
  1815. #define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
  1816. #define   VIDEO_DIP_ENABLE_GAMUT        (4 << 21)
  1817. #define   VIDEO_DIP_ENABLE_SPD          (8 << 21)
  1818. #define   VIDEO_DIP_SELECT_AVI          (0 << 19)
  1819. #define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
  1820. #define   VIDEO_DIP_SELECT_SPD          (3 << 19)
  1821. #define   VIDEO_DIP_SELECT_MASK         (3 << 19)
  1822. #define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
  1823. #define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
  1824. #define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
  1825. #define   VIDEO_DIP_FREQ_MASK           (3 << 16)
  1826. /* HSW and later: */
  1827. #define   VIDEO_DIP_ENABLE_VSC_HSW      (1 << 20)
  1828. #define   VIDEO_DIP_ENABLE_GCP_HSW      (1 << 16)
  1829. #define   VIDEO_DIP_ENABLE_AVI_HSW      (1 << 12)
  1830. #define   VIDEO_DIP_ENABLE_VS_HSW       (1 << 8)
  1831. #define   VIDEO_DIP_ENABLE_GMP_HSW      (1 << 4)
  1832. #define   VIDEO_DIP_ENABLE_SPD_HSW      (1 << 0)
  1833.  
  1834. /* Panel power sequencing */
  1835. #define PP_STATUS       0x61200
  1836. #define   PP_ON         (1 << 31)
  1837. /*
  1838.  * Indicates that all dependencies of the panel are on:
  1839.  *
  1840.  * - PLL enabled
  1841.  * - pipe enabled
  1842.  * - LVDS/DVOB/DVOC on
  1843.  */
  1844. #define   PP_READY              (1 << 30)
  1845. #define   PP_SEQUENCE_NONE      (0 << 28)
  1846. #define   PP_SEQUENCE_POWER_UP  (1 << 28)
  1847. #define   PP_SEQUENCE_POWER_DOWN (2 << 28)
  1848. #define   PP_SEQUENCE_MASK      (3 << 28)
  1849. #define   PP_SEQUENCE_SHIFT     28
  1850. #define   PP_CYCLE_DELAY_ACTIVE (1 << 27)
  1851. #define   PP_SEQUENCE_STATE_MASK 0x0000000f
  1852. #define   PP_SEQUENCE_STATE_OFF_IDLE    (0x0 << 0)
  1853. #define   PP_SEQUENCE_STATE_OFF_S0_1    (0x1 << 0)
  1854. #define   PP_SEQUENCE_STATE_OFF_S0_2    (0x2 << 0)
  1855. #define   PP_SEQUENCE_STATE_OFF_S0_3    (0x3 << 0)
  1856. #define   PP_SEQUENCE_STATE_ON_IDLE     (0x8 << 0)
  1857. #define   PP_SEQUENCE_STATE_ON_S1_0     (0x9 << 0)
  1858. #define   PP_SEQUENCE_STATE_ON_S1_2     (0xa << 0)
  1859. #define   PP_SEQUENCE_STATE_ON_S1_3     (0xb << 0)
  1860. #define   PP_SEQUENCE_STATE_RESET       (0xf << 0)
  1861. #define PP_CONTROL      0x61204
  1862. #define   POWER_TARGET_ON       (1 << 0)
  1863. #define PP_ON_DELAYS    0x61208
  1864. #define PP_OFF_DELAYS   0x6120c
  1865. #define PP_DIVISOR      0x61210
  1866.  
  1867. /* Panel fitting */
  1868. #define PFIT_CONTROL    (dev_priv->info->display_mmio_offset + 0x61230)
  1869. #define   PFIT_ENABLE           (1 << 31)
  1870. #define   PFIT_PIPE_MASK        (3 << 29)
  1871. #define   PFIT_PIPE_SHIFT       29
  1872. #define   VERT_INTERP_DISABLE   (0 << 10)
  1873. #define   VERT_INTERP_BILINEAR  (1 << 10)
  1874. #define   VERT_INTERP_MASK      (3 << 10)
  1875. #define   VERT_AUTO_SCALE       (1 << 9)
  1876. #define   HORIZ_INTERP_DISABLE  (0 << 6)
  1877. #define   HORIZ_INTERP_BILINEAR (1 << 6)
  1878. #define   HORIZ_INTERP_MASK     (3 << 6)
  1879. #define   HORIZ_AUTO_SCALE      (1 << 5)
  1880. #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
  1881. #define   PFIT_FILTER_FUZZY     (0 << 24)
  1882. #define   PFIT_SCALING_AUTO     (0 << 26)
  1883. #define   PFIT_SCALING_PROGRAMMED (1 << 26)
  1884. #define   PFIT_SCALING_PILLAR   (2 << 26)
  1885. #define   PFIT_SCALING_LETTER   (3 << 26)
  1886. #define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
  1887. /* Pre-965 */
  1888. #define         PFIT_VERT_SCALE_SHIFT           20
  1889. #define         PFIT_VERT_SCALE_MASK            0xfff00000
  1890. #define         PFIT_HORIZ_SCALE_SHIFT          4
  1891. #define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
  1892. /* 965+ */
  1893. #define         PFIT_VERT_SCALE_SHIFT_965       16
  1894. #define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
  1895. #define         PFIT_HORIZ_SCALE_SHIFT_965      0
  1896. #define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff
  1897.  
  1898. #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
  1899.  
  1900. /* Backlight control */
  1901. #define BLC_PWM_CTL2            0x61250 /* 965+ only */
  1902. #define   BLM_PWM_ENABLE                (1 << 31)
  1903. #define   BLM_COMBINATION_MODE          (1 << 30) /* gen4 only */
  1904. #define   BLM_PIPE_SELECT               (1 << 29)
  1905. #define   BLM_PIPE_SELECT_IVB           (3 << 29)
  1906. #define   BLM_PIPE_A                    (0 << 29)
  1907. #define   BLM_PIPE_B                    (1 << 29)
  1908. #define   BLM_PIPE_C                    (2 << 29) /* ivb + */
  1909. #define   BLM_PIPE(pipe)                ((pipe) << 29)
  1910. #define   BLM_POLARITY_I965             (1 << 28) /* gen4 only */
  1911. #define   BLM_PHASE_IN_INTERUPT_STATUS  (1 << 26)
  1912. #define   BLM_PHASE_IN_ENABLE           (1 << 25)
  1913. #define   BLM_PHASE_IN_INTERUPT_ENABL   (1 << 24)
  1914. #define   BLM_PHASE_IN_TIME_BASE_SHIFT  (16)
  1915. #define   BLM_PHASE_IN_TIME_BASE_MASK   (0xff << 16)
  1916. #define   BLM_PHASE_IN_COUNT_SHIFT      (8)
  1917. #define   BLM_PHASE_IN_COUNT_MASK       (0xff << 8)
  1918. #define   BLM_PHASE_IN_INCR_SHIFT       (0)
  1919. #define   BLM_PHASE_IN_INCR_MASK        (0xff << 0)
  1920. #define BLC_PWM_CTL             0x61254
  1921. /*
  1922.  * This is the most significant 15 bits of the number of backlight cycles in a
  1923.  * complete cycle of the modulated backlight control.
  1924.  *
  1925.  * The actual value is this field multiplied by two.
  1926.  */
  1927. #define   BACKLIGHT_MODULATION_FREQ_SHIFT       (17)
  1928. #define   BACKLIGHT_MODULATION_FREQ_MASK                (0x7fff << 17)
  1929. #define   BLM_LEGACY_MODE                       (1 << 16) /* gen2 only */
  1930. /*
  1931.  * This is the number of cycles out of the backlight modulation cycle for which
  1932.  * the backlight is on.
  1933.  *
  1934.  * This field must be no greater than the number of cycles in the complete
  1935.  * backlight modulation cycle.
  1936.  */
  1937. #define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
  1938. #define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
  1939. #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV         (0xfffe)
  1940. #define   BLM_POLARITY_PNV                      (1 << 0) /* pnv only */
  1941.  
  1942. #define BLC_HIST_CTL            0x61260
  1943.  
  1944. /* New registers for PCH-split platforms. Safe where new bits show up, the
  1945.  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
  1946. #define BLC_PWM_CPU_CTL2        0x48250
  1947. #define BLC_PWM_CPU_CTL         0x48254
  1948.  
  1949. /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  1950.  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
  1951. #define BLC_PWM_PCH_CTL1        0xc8250
  1952. #define   BLM_PCH_PWM_ENABLE                    (1 << 31)
  1953. #define   BLM_PCH_OVERRIDE_ENABLE               (1 << 30)
  1954. #define   BLM_PCH_POLARITY                      (1 << 29)
  1955. #define BLC_PWM_PCH_CTL2        0xc8254
  1956.  
  1957. /* TV port control */
  1958. #define TV_CTL                  0x68000
  1959. /** Enables the TV encoder */
  1960. # define TV_ENC_ENABLE                  (1 << 31)
  1961. /** Sources the TV encoder input from pipe B instead of A. */
  1962. # define TV_ENC_PIPEB_SELECT            (1 << 30)
  1963. /** Outputs composite video (DAC A only) */
  1964. # define TV_ENC_OUTPUT_COMPOSITE        (0 << 28)
  1965. /** Outputs SVideo video (DAC B/C) */
  1966. # define TV_ENC_OUTPUT_SVIDEO           (1 << 28)
  1967. /** Outputs Component video (DAC A/B/C) */
  1968. # define TV_ENC_OUTPUT_COMPONENT        (2 << 28)
  1969. /** Outputs Composite and SVideo (DAC A/B/C) */
  1970. # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
  1971. # define TV_TRILEVEL_SYNC               (1 << 21)
  1972. /** Enables slow sync generation (945GM only) */
  1973. # define TV_SLOW_SYNC                   (1 << 20)
  1974. /** Selects 4x oversampling for 480i and 576p */
  1975. # define TV_OVERSAMPLE_4X               (0 << 18)
  1976. /** Selects 2x oversampling for 720p and 1080i */
  1977. # define TV_OVERSAMPLE_2X               (1 << 18)
  1978. /** Selects no oversampling for 1080p */
  1979. # define TV_OVERSAMPLE_NONE             (2 << 18)
  1980. /** Selects 8x oversampling */
  1981. # define TV_OVERSAMPLE_8X               (3 << 18)
  1982. /** Selects progressive mode rather than interlaced */
  1983. # define TV_PROGRESSIVE                 (1 << 17)
  1984. /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
  1985. # define TV_PAL_BURST                   (1 << 16)
  1986. /** Field for setting delay of Y compared to C */
  1987. # define TV_YC_SKEW_MASK                (7 << 12)
  1988. /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
  1989. # define TV_ENC_SDP_FIX                 (1 << 11)
  1990. /**
  1991.  * Enables a fix for the 915GM only.
  1992.  *
  1993.  * Not sure what it does.
  1994.  */
  1995. # define TV_ENC_C0_FIX                  (1 << 10)
  1996. /** Bits that must be preserved by software */
  1997. # define TV_CTL_SAVE                    ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
  1998. # define TV_FUSE_STATE_MASK             (3 << 4)
  1999. /** Read-only state that reports all features enabled */
  2000. # define TV_FUSE_STATE_ENABLED          (0 << 4)
  2001. /** Read-only state that reports that Macrovision is disabled in hardware*/
  2002. # define TV_FUSE_STATE_NO_MACROVISION   (1 << 4)
  2003. /** Read-only state that reports that TV-out is disabled in hardware. */
  2004. # define TV_FUSE_STATE_DISABLED         (2 << 4)
  2005. /** Normal operation */
  2006. # define TV_TEST_MODE_NORMAL            (0 << 0)
  2007. /** Encoder test pattern 1 - combo pattern */
  2008. # define TV_TEST_MODE_PATTERN_1         (1 << 0)
  2009. /** Encoder test pattern 2 - full screen vertical 75% color bars */
  2010. # define TV_TEST_MODE_PATTERN_2         (2 << 0)
  2011. /** Encoder test pattern 3 - full screen horizontal 75% color bars */
  2012. # define TV_TEST_MODE_PATTERN_3         (3 << 0)
  2013. /** Encoder test pattern 4 - random noise */
  2014. # define TV_TEST_MODE_PATTERN_4         (4 << 0)
  2015. /** Encoder test pattern 5 - linear color ramps */
  2016. # define TV_TEST_MODE_PATTERN_5         (5 << 0)
  2017. /**
  2018.  * This test mode forces the DACs to 50% of full output.
  2019.  *
  2020.  * This is used for load detection in combination with TVDAC_SENSE_MASK
  2021.  */
  2022. # define TV_TEST_MODE_MONITOR_DETECT    (7 << 0)
  2023. # define TV_TEST_MODE_MASK              (7 << 0)
  2024.  
  2025. #define TV_DAC                  0x68004
  2026. # define TV_DAC_SAVE            0x00ffff00
  2027. /**
  2028.  * Reports that DAC state change logic has reported change (RO).
  2029.  *
  2030.  * This gets cleared when TV_DAC_STATE_EN is cleared
  2031. */
  2032. # define TVDAC_STATE_CHG                (1 << 31)
  2033. # define TVDAC_SENSE_MASK               (7 << 28)
  2034. /** Reports that DAC A voltage is above the detect threshold */
  2035. # define TVDAC_A_SENSE                  (1 << 30)
  2036. /** Reports that DAC B voltage is above the detect threshold */
  2037. # define TVDAC_B_SENSE                  (1 << 29)
  2038. /** Reports that DAC C voltage is above the detect threshold */
  2039. # define TVDAC_C_SENSE                  (1 << 28)
  2040. /**
  2041.  * Enables DAC state detection logic, for load-based TV detection.
  2042.  *
  2043.  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
  2044.  * to off, for load detection to work.
  2045.  */
  2046. # define TVDAC_STATE_CHG_EN             (1 << 27)
  2047. /** Sets the DAC A sense value to high */
  2048. # define TVDAC_A_SENSE_CTL              (1 << 26)
  2049. /** Sets the DAC B sense value to high */
  2050. # define TVDAC_B_SENSE_CTL              (1 << 25)
  2051. /** Sets the DAC C sense value to high */
  2052. # define TVDAC_C_SENSE_CTL              (1 << 24)
  2053. /** Overrides the ENC_ENABLE and DAC voltage levels */
  2054. # define DAC_CTL_OVERRIDE               (1 << 7)
  2055. /** Sets the slew rate.  Must be preserved in software */
  2056. # define ENC_TVDAC_SLEW_FAST            (1 << 6)
  2057. # define DAC_A_1_3_V                    (0 << 4)
  2058. # define DAC_A_1_1_V                    (1 << 4)
  2059. # define DAC_A_0_7_V                    (2 << 4)
  2060. # define DAC_A_MASK                     (3 << 4)
  2061. # define DAC_B_1_3_V                    (0 << 2)
  2062. # define DAC_B_1_1_V                    (1 << 2)
  2063. # define DAC_B_0_7_V                    (2 << 2)
  2064. # define DAC_B_MASK                     (3 << 2)
  2065. # define DAC_C_1_3_V                    (0 << 0)
  2066. # define DAC_C_1_1_V                    (1 << 0)
  2067. # define DAC_C_0_7_V                    (2 << 0)
  2068. # define DAC_C_MASK                     (3 << 0)
  2069.  
  2070. /**
  2071.  * CSC coefficients are stored in a floating point format with 9 bits of
  2072.  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
  2073.  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
  2074.  * -1 (0x3) being the only legal negative value.
  2075.  */
  2076. #define TV_CSC_Y                0x68010
  2077. # define TV_RY_MASK                     0x07ff0000
  2078. # define TV_RY_SHIFT                    16
  2079. # define TV_GY_MASK                     0x00000fff
  2080. # define TV_GY_SHIFT                    0
  2081.  
  2082. #define TV_CSC_Y2               0x68014
  2083. # define TV_BY_MASK                     0x07ff0000
  2084. # define TV_BY_SHIFT                    16
  2085. /**
  2086.  * Y attenuation for component video.
  2087.  *
  2088.  * Stored in 1.9 fixed point.
  2089.  */
  2090. # define TV_AY_MASK                     0x000003ff
  2091. # define TV_AY_SHIFT                    0
  2092.  
  2093. #define TV_CSC_U                0x68018
  2094. # define TV_RU_MASK                     0x07ff0000
  2095. # define TV_RU_SHIFT                    16
  2096. # define TV_GU_MASK                     0x000007ff
  2097. # define TV_GU_SHIFT                    0
  2098.  
  2099. #define TV_CSC_U2               0x6801c
  2100. # define TV_BU_MASK                     0x07ff0000
  2101. # define TV_BU_SHIFT                    16
  2102. /**
  2103.  * U attenuation for component video.
  2104.  *
  2105.  * Stored in 1.9 fixed point.
  2106.  */
  2107. # define TV_AU_MASK                     0x000003ff
  2108. # define TV_AU_SHIFT                    0
  2109.  
  2110. #define TV_CSC_V                0x68020
  2111. # define TV_RV_MASK                     0x0fff0000
  2112. # define TV_RV_SHIFT                    16
  2113. # define TV_GV_MASK                     0x000007ff
  2114. # define TV_GV_SHIFT                    0
  2115.  
  2116. #define TV_CSC_V2               0x68024
  2117. # define TV_BV_MASK                     0x07ff0000
  2118. # define TV_BV_SHIFT                    16
  2119. /**
  2120.  * V attenuation for component video.
  2121.  *
  2122.  * Stored in 1.9 fixed point.
  2123.  */
  2124. # define TV_AV_MASK                     0x000007ff
  2125. # define TV_AV_SHIFT                    0
  2126.  
  2127. #define TV_CLR_KNOBS            0x68028
  2128. /** 2s-complement brightness adjustment */
  2129. # define TV_BRIGHTNESS_MASK             0xff000000
  2130. # define TV_BRIGHTNESS_SHIFT            24
  2131. /** Contrast adjustment, as a 2.6 unsigned floating point number */
  2132. # define TV_CONTRAST_MASK               0x00ff0000
  2133. # define TV_CONTRAST_SHIFT              16
  2134. /** Saturation adjustment, as a 2.6 unsigned floating point number */
  2135. # define TV_SATURATION_MASK             0x0000ff00
  2136. # define TV_SATURATION_SHIFT            8
  2137. /** Hue adjustment, as an integer phase angle in degrees */
  2138. # define TV_HUE_MASK                    0x000000ff
  2139. # define TV_HUE_SHIFT                   0
  2140.  
  2141. #define TV_CLR_LEVEL            0x6802c
  2142. /** Controls the DAC level for black */
  2143. # define TV_BLACK_LEVEL_MASK            0x01ff0000
  2144. # define TV_BLACK_LEVEL_SHIFT           16
  2145. /** Controls the DAC level for blanking */
  2146. # define TV_BLANK_LEVEL_MASK            0x000001ff
  2147. # define TV_BLANK_LEVEL_SHIFT           0
  2148.  
  2149. #define TV_H_CTL_1              0x68030
  2150. /** Number of pixels in the hsync. */
  2151. # define TV_HSYNC_END_MASK              0x1fff0000
  2152. # define TV_HSYNC_END_SHIFT             16
  2153. /** Total number of pixels minus one in the line (display and blanking). */
  2154. # define TV_HTOTAL_MASK                 0x00001fff
  2155. # define TV_HTOTAL_SHIFT                0
  2156.  
  2157. #define TV_H_CTL_2              0x68034
  2158. /** Enables the colorburst (needed for non-component color) */
  2159. # define TV_BURST_ENA                   (1 << 31)
  2160. /** Offset of the colorburst from the start of hsync, in pixels minus one. */
  2161. # define TV_HBURST_START_SHIFT          16
  2162. # define TV_HBURST_START_MASK           0x1fff0000
  2163. /** Length of the colorburst */
  2164. # define TV_HBURST_LEN_SHIFT            0
  2165. # define TV_HBURST_LEN_MASK             0x0001fff
  2166.  
  2167. #define TV_H_CTL_3              0x68038
  2168. /** End of hblank, measured in pixels minus one from start of hsync */
  2169. # define TV_HBLANK_END_SHIFT            16
  2170. # define TV_HBLANK_END_MASK             0x1fff0000
  2171. /** Start of hblank, measured in pixels minus one from start of hsync */
  2172. # define TV_HBLANK_START_SHIFT          0
  2173. # define TV_HBLANK_START_MASK           0x0001fff
  2174.  
  2175. #define TV_V_CTL_1              0x6803c
  2176. /** XXX */
  2177. # define TV_NBR_END_SHIFT               16
  2178. # define TV_NBR_END_MASK                0x07ff0000
  2179. /** XXX */
  2180. # define TV_VI_END_F1_SHIFT             8
  2181. # define TV_VI_END_F1_MASK              0x00003f00
  2182. /** XXX */
  2183. # define TV_VI_END_F2_SHIFT             0
  2184. # define TV_VI_END_F2_MASK              0x0000003f
  2185.  
  2186. #define TV_V_CTL_2              0x68040
  2187. /** Length of vsync, in half lines */
  2188. # define TV_VSYNC_LEN_MASK              0x07ff0000
  2189. # define TV_VSYNC_LEN_SHIFT             16
  2190. /** Offset of the start of vsync in field 1, measured in one less than the
  2191.  * number of half lines.
  2192.  */
  2193. # define TV_VSYNC_START_F1_MASK         0x00007f00
  2194. # define TV_VSYNC_START_F1_SHIFT        8
  2195. /**
  2196.  * Offset of the start of vsync in field 2, measured in one less than the
  2197.  * number of half lines.
  2198.  */
  2199. # define TV_VSYNC_START_F2_MASK         0x0000007f
  2200. # define TV_VSYNC_START_F2_SHIFT        0
  2201.  
  2202. #define TV_V_CTL_3              0x68044
  2203. /** Enables generation of the equalization signal */
  2204. # define TV_EQUAL_ENA                   (1 << 31)
  2205. /** Length of vsync, in half lines */
  2206. # define TV_VEQ_LEN_MASK                0x007f0000
  2207. # define TV_VEQ_LEN_SHIFT               16
  2208. /** Offset of the start of equalization in field 1, measured in one less than
  2209.  * the number of half lines.
  2210.  */
  2211. # define TV_VEQ_START_F1_MASK           0x0007f00
  2212. # define TV_VEQ_START_F1_SHIFT          8
  2213. /**
  2214.  * Offset of the start of equalization in field 2, measured in one less than
  2215.  * the number of half lines.
  2216.  */
  2217. # define TV_VEQ_START_F2_MASK           0x000007f
  2218. # define TV_VEQ_START_F2_SHIFT          0
  2219.  
  2220. #define TV_V_CTL_4              0x68048
  2221. /**
  2222.  * Offset to start of vertical colorburst, measured in one less than the
  2223.  * number of lines from vertical start.
  2224.  */
  2225. # define TV_VBURST_START_F1_MASK        0x003f0000
  2226. # define TV_VBURST_START_F1_SHIFT       16
  2227. /**
  2228.  * Offset to the end of vertical colorburst, measured in one less than the
  2229.  * number of lines from the start of NBR.
  2230.  */
  2231. # define TV_VBURST_END_F1_MASK          0x000000ff
  2232. # define TV_VBURST_END_F1_SHIFT         0
  2233.  
  2234. #define TV_V_CTL_5              0x6804c
  2235. /**
  2236.  * Offset to start of vertical colorburst, measured in one less than the
  2237.  * number of lines from vertical start.
  2238.  */
  2239. # define TV_VBURST_START_F2_MASK        0x003f0000
  2240. # define TV_VBURST_START_F2_SHIFT       16
  2241. /**
  2242.  * Offset to the end of vertical colorburst, measured in one less than the
  2243.  * number of lines from the start of NBR.
  2244.  */
  2245. # define TV_VBURST_END_F2_MASK          0x000000ff
  2246. # define TV_VBURST_END_F2_SHIFT         0
  2247.  
  2248. #define TV_V_CTL_6              0x68050
  2249. /**
  2250.  * Offset to start of vertical colorburst, measured in one less than the
  2251.  * number of lines from vertical start.
  2252.  */
  2253. # define TV_VBURST_START_F3_MASK        0x003f0000
  2254. # define TV_VBURST_START_F3_SHIFT       16
  2255. /**
  2256.  * Offset to the end of vertical colorburst, measured in one less than the
  2257.  * number of lines from the start of NBR.
  2258.  */
  2259. # define TV_VBURST_END_F3_MASK          0x000000ff
  2260. # define TV_VBURST_END_F3_SHIFT         0
  2261.  
  2262. #define TV_V_CTL_7              0x68054
  2263. /**
  2264.  * Offset to start of vertical colorburst, measured in one less than the
  2265.  * number of lines from vertical start.
  2266.  */
  2267. # define TV_VBURST_START_F4_MASK        0x003f0000
  2268. # define TV_VBURST_START_F4_SHIFT       16
  2269. /**
  2270.  * Offset to the end of vertical colorburst, measured in one less than the
  2271.  * number of lines from the start of NBR.
  2272.  */
  2273. # define TV_VBURST_END_F4_MASK          0x000000ff
  2274. # define TV_VBURST_END_F4_SHIFT         0
  2275.  
  2276. #define TV_SC_CTL_1             0x68060
  2277. /** Turns on the first subcarrier phase generation DDA */
  2278. # define TV_SC_DDA1_EN                  (1 << 31)
  2279. /** Turns on the first subcarrier phase generation DDA */
  2280. # define TV_SC_DDA2_EN                  (1 << 30)
  2281. /** Turns on the first subcarrier phase generation DDA */
  2282. # define TV_SC_DDA3_EN                  (1 << 29)
  2283. /** Sets the subcarrier DDA to reset frequency every other field */
  2284. # define TV_SC_RESET_EVERY_2            (0 << 24)
  2285. /** Sets the subcarrier DDA to reset frequency every fourth field */
  2286. # define TV_SC_RESET_EVERY_4            (1 << 24)
  2287. /** Sets the subcarrier DDA to reset frequency every eighth field */
  2288. # define TV_SC_RESET_EVERY_8            (2 << 24)
  2289. /** Sets the subcarrier DDA to never reset the frequency */
  2290. # define TV_SC_RESET_NEVER              (3 << 24)
  2291. /** Sets the peak amplitude of the colorburst.*/
  2292. # define TV_BURST_LEVEL_MASK            0x00ff0000
  2293. # define TV_BURST_LEVEL_SHIFT           16
  2294. /** Sets the increment of the first subcarrier phase generation DDA */
  2295. # define TV_SCDDA1_INC_MASK             0x00000fff
  2296. # define TV_SCDDA1_INC_SHIFT            0
  2297.  
  2298. #define TV_SC_CTL_2             0x68064
  2299. /** Sets the rollover for the second subcarrier phase generation DDA */
  2300. # define TV_SCDDA2_SIZE_MASK            0x7fff0000
  2301. # define TV_SCDDA2_SIZE_SHIFT           16
  2302. /** Sets the increent of the second subcarrier phase generation DDA */
  2303. # define TV_SCDDA2_INC_MASK             0x00007fff
  2304. # define TV_SCDDA2_INC_SHIFT            0
  2305.  
  2306. #define TV_SC_CTL_3             0x68068
  2307. /** Sets the rollover for the third subcarrier phase generation DDA */
  2308. # define TV_SCDDA3_SIZE_MASK            0x7fff0000
  2309. # define TV_SCDDA3_SIZE_SHIFT           16
  2310. /** Sets the increent of the third subcarrier phase generation DDA */
  2311. # define TV_SCDDA3_INC_MASK             0x00007fff
  2312. # define TV_SCDDA3_INC_SHIFT            0
  2313.  
  2314. #define TV_WIN_POS              0x68070
  2315. /** X coordinate of the display from the start of horizontal active */
  2316. # define TV_XPOS_MASK                   0x1fff0000
  2317. # define TV_XPOS_SHIFT                  16
  2318. /** Y coordinate of the display from the start of vertical active (NBR) */
  2319. # define TV_YPOS_MASK                   0x00000fff
  2320. # define TV_YPOS_SHIFT                  0
  2321.  
  2322. #define TV_WIN_SIZE             0x68074
  2323. /** Horizontal size of the display window, measured in pixels*/
  2324. # define TV_XSIZE_MASK                  0x1fff0000
  2325. # define TV_XSIZE_SHIFT                 16
  2326. /**
  2327.  * Vertical size of the display window, measured in pixels.
  2328.  *
  2329.  * Must be even for interlaced modes.
  2330.  */
  2331. # define TV_YSIZE_MASK                  0x00000fff
  2332. # define TV_YSIZE_SHIFT                 0
  2333.  
  2334. #define TV_FILTER_CTL_1         0x68080
  2335. /**
  2336.  * Enables automatic scaling calculation.
  2337.  *
  2338.  * If set, the rest of the registers are ignored, and the calculated values can
  2339.  * be read back from the register.
  2340.  */
  2341. # define TV_AUTO_SCALE                  (1 << 31)
  2342. /**
  2343.  * Disables the vertical filter.
  2344.  *
  2345.  * This is required on modes more than 1024 pixels wide */
  2346. # define TV_V_FILTER_BYPASS             (1 << 29)
  2347. /** Enables adaptive vertical filtering */
  2348. # define TV_VADAPT                      (1 << 28)
  2349. # define TV_VADAPT_MODE_MASK            (3 << 26)
  2350. /** Selects the least adaptive vertical filtering mode */
  2351. # define TV_VADAPT_MODE_LEAST           (0 << 26)
  2352. /** Selects the moderately adaptive vertical filtering mode */
  2353. # define TV_VADAPT_MODE_MODERATE        (1 << 26)
  2354. /** Selects the most adaptive vertical filtering mode */
  2355. # define TV_VADAPT_MODE_MOST            (3 << 26)
  2356. /**
  2357.  * Sets the horizontal scaling factor.
  2358.  *
  2359.  * This should be the fractional part of the horizontal scaling factor divided
  2360.  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
  2361.  *
  2362.  * (src width - 1) / ((oversample * dest width) - 1)
  2363.  */
  2364. # define TV_HSCALE_FRAC_MASK            0x00003fff
  2365. # define TV_HSCALE_FRAC_SHIFT           0
  2366.  
  2367. #define TV_FILTER_CTL_2         0x68084
  2368. /**
  2369.  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  2370.  *
  2371.  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
  2372.  */
  2373. # define TV_VSCALE_INT_MASK             0x00038000
  2374. # define TV_VSCALE_INT_SHIFT            15
  2375. /**
  2376.  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  2377.  *
  2378.  * \sa TV_VSCALE_INT_MASK
  2379.  */
  2380. # define TV_VSCALE_FRAC_MASK            0x00007fff
  2381. # define TV_VSCALE_FRAC_SHIFT           0
  2382.  
  2383. #define TV_FILTER_CTL_3         0x68088
  2384. /**
  2385.  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  2386.  *
  2387.  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
  2388.  *
  2389.  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  2390.  */
  2391. # define TV_VSCALE_IP_INT_MASK          0x00038000
  2392. # define TV_VSCALE_IP_INT_SHIFT         15
  2393. /**
  2394.  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  2395.  *
  2396.  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  2397.  *
  2398.  * \sa TV_VSCALE_IP_INT_MASK
  2399.  */
  2400. # define TV_VSCALE_IP_FRAC_MASK         0x00007fff
  2401. # define TV_VSCALE_IP_FRAC_SHIFT                0
  2402.  
  2403. #define TV_CC_CONTROL           0x68090
  2404. # define TV_CC_ENABLE                   (1 << 31)
  2405. /**
  2406.  * Specifies which field to send the CC data in.
  2407.  *
  2408.  * CC data is usually sent in field 0.
  2409.  */
  2410. # define TV_CC_FID_MASK                 (1 << 27)
  2411. # define TV_CC_FID_SHIFT                27
  2412. /** Sets the horizontal position of the CC data.  Usually 135. */
  2413. # define TV_CC_HOFF_MASK                0x03ff0000
  2414. # define TV_CC_HOFF_SHIFT               16
  2415. /** Sets the vertical position of the CC data.  Usually 21 */
  2416. # define TV_CC_LINE_MASK                0x0000003f
  2417. # define TV_CC_LINE_SHIFT               0
  2418.  
  2419. #define TV_CC_DATA              0x68094
  2420. # define TV_CC_RDY                      (1 << 31)
  2421. /** Second word of CC data to be transmitted. */
  2422. # define TV_CC_DATA_2_MASK              0x007f0000
  2423. # define TV_CC_DATA_2_SHIFT             16
  2424. /** First word of CC data to be transmitted. */
  2425. # define TV_CC_DATA_1_MASK              0x0000007f
  2426. # define TV_CC_DATA_1_SHIFT             0
  2427.  
  2428. #define TV_H_LUMA_0             0x68100
  2429. #define TV_H_LUMA_59            0x681ec
  2430. #define TV_H_CHROMA_0           0x68200
  2431. #define TV_H_CHROMA_59          0x682ec
  2432. #define TV_V_LUMA_0             0x68300
  2433. #define TV_V_LUMA_42            0x683a8
  2434. #define TV_V_CHROMA_0           0x68400
  2435. #define TV_V_CHROMA_42          0x684a8
  2436.  
  2437. /* Display Port */
  2438. #define DP_A                            0x64000 /* eDP */
  2439. #define DP_B                            0x64100
  2440. #define DP_C                            0x64200
  2441. #define DP_D                            0x64300
  2442.  
  2443. #define   DP_PORT_EN                    (1 << 31)
  2444. #define   DP_PIPEB_SELECT               (1 << 30)
  2445. #define   DP_PIPE_MASK                  (1 << 30)
  2446.  
  2447. /* Link training mode - select a suitable mode for each stage */
  2448. #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
  2449. #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
  2450. #define   DP_LINK_TRAIN_PAT_IDLE        (2 << 28)
  2451. #define   DP_LINK_TRAIN_OFF             (3 << 28)
  2452. #define   DP_LINK_TRAIN_MASK            (3 << 28)
  2453. #define   DP_LINK_TRAIN_SHIFT           28
  2454.  
  2455. /* CPT Link training mode */
  2456. #define   DP_LINK_TRAIN_PAT_1_CPT       (0 << 8)
  2457. #define   DP_LINK_TRAIN_PAT_2_CPT       (1 << 8)
  2458. #define   DP_LINK_TRAIN_PAT_IDLE_CPT    (2 << 8)
  2459. #define   DP_LINK_TRAIN_OFF_CPT         (3 << 8)
  2460. #define   DP_LINK_TRAIN_MASK_CPT        (7 << 8)
  2461. #define   DP_LINK_TRAIN_SHIFT_CPT       8
  2462.  
  2463. /* Signal voltages. These are mostly controlled by the other end */
  2464. #define   DP_VOLTAGE_0_4                (0 << 25)
  2465. #define   DP_VOLTAGE_0_6                (1 << 25)
  2466. #define   DP_VOLTAGE_0_8                (2 << 25)
  2467. #define   DP_VOLTAGE_1_2                (3 << 25)
  2468. #define   DP_VOLTAGE_MASK               (7 << 25)
  2469. #define   DP_VOLTAGE_SHIFT              25
  2470.  
  2471. /* Signal pre-emphasis levels, like voltages, the other end tells us what
  2472.  * they want
  2473.  */
  2474. #define   DP_PRE_EMPHASIS_0             (0 << 22)
  2475. #define   DP_PRE_EMPHASIS_3_5           (1 << 22)
  2476. #define   DP_PRE_EMPHASIS_6             (2 << 22)
  2477. #define   DP_PRE_EMPHASIS_9_5           (3 << 22)
  2478. #define   DP_PRE_EMPHASIS_MASK          (7 << 22)
  2479. #define   DP_PRE_EMPHASIS_SHIFT         22
  2480.  
  2481. /* How many wires to use. I guess 3 was too hard */
  2482. #define   DP_PORT_WIDTH_1               (0 << 19)
  2483. #define   DP_PORT_WIDTH_2               (1 << 19)
  2484. #define   DP_PORT_WIDTH_4               (3 << 19)
  2485. #define   DP_PORT_WIDTH_MASK            (7 << 19)
  2486.  
  2487. /* Mystic DPCD version 1.1 special mode */
  2488. #define   DP_ENHANCED_FRAMING           (1 << 18)
  2489.  
  2490. /* eDP */
  2491. #define   DP_PLL_FREQ_270MHZ            (0 << 16)
  2492. #define   DP_PLL_FREQ_160MHZ            (1 << 16)
  2493. #define   DP_PLL_FREQ_MASK              (3 << 16)
  2494.  
  2495. /** locked once port is enabled */
  2496. #define   DP_PORT_REVERSAL              (1 << 15)
  2497.  
  2498. /* eDP */
  2499. #define   DP_PLL_ENABLE                 (1 << 14)
  2500.  
  2501. /** sends the clock on lane 15 of the PEG for debug */
  2502. #define   DP_CLOCK_OUTPUT_ENABLE        (1 << 13)
  2503.  
  2504. #define   DP_SCRAMBLING_DISABLE         (1 << 12)
  2505. #define   DP_SCRAMBLING_DISABLE_IRONLAKE        (1 << 7)
  2506.  
  2507. /** limit RGB values to avoid confusing TVs */
  2508. #define   DP_COLOR_RANGE_16_235         (1 << 8)
  2509.  
  2510. /** Turn on the audio link */
  2511. #define   DP_AUDIO_OUTPUT_ENABLE        (1 << 6)
  2512.  
  2513. /** vs and hs sync polarity */
  2514. #define   DP_SYNC_VS_HIGH               (1 << 4)
  2515. #define   DP_SYNC_HS_HIGH               (1 << 3)
  2516.  
  2517. /** A fantasy */
  2518. #define   DP_DETECTED                   (1 << 2)
  2519.  
  2520. /** The aux channel provides a way to talk to the
  2521.  * signal sink for DDC etc. Max packet size supported
  2522.  * is 20 bytes in each direction, hence the 5 fixed
  2523.  * data registers
  2524.  */
  2525. #define DPA_AUX_CH_CTL                  0x64010
  2526. #define DPA_AUX_CH_DATA1                0x64014
  2527. #define DPA_AUX_CH_DATA2                0x64018
  2528. #define DPA_AUX_CH_DATA3                0x6401c
  2529. #define DPA_AUX_CH_DATA4                0x64020
  2530. #define DPA_AUX_CH_DATA5                0x64024
  2531.  
  2532. #define DPB_AUX_CH_CTL                  0x64110
  2533. #define DPB_AUX_CH_DATA1                0x64114
  2534. #define DPB_AUX_CH_DATA2                0x64118
  2535. #define DPB_AUX_CH_DATA3                0x6411c
  2536. #define DPB_AUX_CH_DATA4                0x64120
  2537. #define DPB_AUX_CH_DATA5                0x64124
  2538.  
  2539. #define DPC_AUX_CH_CTL                  0x64210
  2540. #define DPC_AUX_CH_DATA1                0x64214
  2541. #define DPC_AUX_CH_DATA2                0x64218
  2542. #define DPC_AUX_CH_DATA3                0x6421c
  2543. #define DPC_AUX_CH_DATA4                0x64220
  2544. #define DPC_AUX_CH_DATA5                0x64224
  2545.  
  2546. #define DPD_AUX_CH_CTL                  0x64310
  2547. #define DPD_AUX_CH_DATA1                0x64314
  2548. #define DPD_AUX_CH_DATA2                0x64318
  2549. #define DPD_AUX_CH_DATA3                0x6431c
  2550. #define DPD_AUX_CH_DATA4                0x64320
  2551. #define DPD_AUX_CH_DATA5                0x64324
  2552.  
  2553. #define   DP_AUX_CH_CTL_SEND_BUSY           (1 << 31)
  2554. #define   DP_AUX_CH_CTL_DONE                (1 << 30)
  2555. #define   DP_AUX_CH_CTL_INTERRUPT           (1 << 29)
  2556. #define   DP_AUX_CH_CTL_TIME_OUT_ERROR      (1 << 28)
  2557. #define   DP_AUX_CH_CTL_TIME_OUT_400us      (0 << 26)
  2558. #define   DP_AUX_CH_CTL_TIME_OUT_600us      (1 << 26)
  2559. #define   DP_AUX_CH_CTL_TIME_OUT_800us      (2 << 26)
  2560. #define   DP_AUX_CH_CTL_TIME_OUT_1600us     (3 << 26)
  2561. #define   DP_AUX_CH_CTL_TIME_OUT_MASK       (3 << 26)
  2562. #define   DP_AUX_CH_CTL_RECEIVE_ERROR       (1 << 25)
  2563. #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
  2564. #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
  2565. #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
  2566. #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
  2567. #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT     (1 << 15)
  2568. #define   DP_AUX_CH_CTL_MANCHESTER_TEST     (1 << 14)
  2569. #define   DP_AUX_CH_CTL_SYNC_TEST           (1 << 13)
  2570. #define   DP_AUX_CH_CTL_DEGLITCH_TEST       (1 << 12)
  2571. #define   DP_AUX_CH_CTL_PRECHARGE_TEST      (1 << 11)
  2572. #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
  2573. #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
  2574.  
  2575. /*
  2576.  * Computing GMCH M and N values for the Display Port link
  2577.  *
  2578.  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
  2579.  *
  2580.  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
  2581.  *
  2582.  * The GMCH value is used internally
  2583.  *
  2584.  * bytes_per_pixel is the number of bytes coming out of the plane,
  2585.  * which is after the LUTs, so we want the bytes for our color format.
  2586.  * For our current usage, this is always 3, one byte for R, G and B.
  2587.  */
  2588. #define _PIPEA_GMCH_DATA_M                      0x70050
  2589. #define _PIPEB_GMCH_DATA_M                      0x71050
  2590.  
  2591. /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
  2592. #define   PIPE_GMCH_DATA_M_TU_SIZE_MASK         (0x3f << 25)
  2593. #define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT        25
  2594.  
  2595. #define   PIPE_GMCH_DATA_M_MASK                 (0xffffff)
  2596.  
  2597. #define _PIPEA_GMCH_DATA_N                      0x70054
  2598. #define _PIPEB_GMCH_DATA_N                      0x71054
  2599. #define   PIPE_GMCH_DATA_N_MASK                 (0xffffff)
  2600.  
  2601. /*
  2602.  * Computing Link M and N values for the Display Port link
  2603.  *
  2604.  * Link M / N = pixel_clock / ls_clk
  2605.  *
  2606.  * (the DP spec calls pixel_clock the 'strm_clk')
  2607.  *
  2608.  * The Link value is transmitted in the Main Stream
  2609.  * Attributes and VB-ID.
  2610.  */
  2611.  
  2612. #define _PIPEA_DP_LINK_M                                0x70060
  2613. #define _PIPEB_DP_LINK_M                                0x71060
  2614. #define   PIPEA_DP_LINK_M_MASK                  (0xffffff)
  2615.  
  2616. #define _PIPEA_DP_LINK_N                                0x70064
  2617. #define _PIPEB_DP_LINK_N                                0x71064
  2618. #define   PIPEA_DP_LINK_N_MASK                  (0xffffff)
  2619.  
  2620. #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
  2621. #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
  2622. #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
  2623. #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
  2624.  
  2625. /* Display & cursor control */
  2626.  
  2627. /* Pipe A */
  2628. #define _PIPEADSL               (dev_priv->info->display_mmio_offset + 0x70000)
  2629. #define   DSL_LINEMASK_GEN2     0x00000fff
  2630. #define   DSL_LINEMASK_GEN3     0x00001fff
  2631. #define _PIPEACONF              (dev_priv->info->display_mmio_offset + 0x70008)
  2632. #define   PIPECONF_ENABLE       (1<<31)
  2633. #define   PIPECONF_DISABLE      0
  2634. #define   PIPECONF_DOUBLE_WIDE  (1<<30)
  2635. #define   I965_PIPECONF_ACTIVE  (1<<30)
  2636. #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
  2637. #define   PIPECONF_SINGLE_WIDE  0
  2638. #define   PIPECONF_PIPE_UNLOCKED 0
  2639. #define   PIPECONF_PIPE_LOCKED  (1<<25)
  2640. #define   PIPECONF_PALETTE      0
  2641. #define   PIPECONF_GAMMA                (1<<24)
  2642. #define   PIPECONF_FORCE_BORDER (1<<25)
  2643. #define   PIPECONF_INTERLACE_MASK       (7 << 21)
  2644. #define   PIPECONF_INTERLACE_MASK_HSW   (3 << 21)
  2645. /* Note that pre-gen3 does not support interlaced display directly. Panel
  2646.  * fitting must be disabled on pre-ilk for interlaced. */
  2647. #define   PIPECONF_PROGRESSIVE  (0 << 21)
  2648. #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
  2649. #define   PIPECONF_INTERLACE_W_SYNC_SHIFT       (5 << 21) /* gen4 only */
  2650. #define   PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
  2651. #define   PIPECONF_INTERLACE_FIELD_0_ONLY       (7 << 21) /* gen3 only */
  2652. /* Ironlake and later have a complete new set of values for interlaced. PFIT
  2653.  * means panel fitter required, PF means progressive fetch, DBL means power
  2654.  * saving pixel doubling. */
  2655. #define   PIPECONF_PFIT_PF_INTERLACED_ILK       (1 << 21)
  2656. #define   PIPECONF_INTERLACED_ILK               (3 << 21)
  2657. #define   PIPECONF_INTERLACED_DBL_ILK           (4 << 21) /* ilk/snb only */
  2658. #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK   (5 << 21) /* ilk/snb only */
  2659. #define   PIPECONF_CXSR_DOWNCLOCK       (1<<16)
  2660. #define   PIPECONF_COLOR_RANGE_SELECT   (1 << 13)
  2661. #define   PIPECONF_BPC_MASK     (0x7 << 5)
  2662. #define   PIPECONF_8BPC         (0<<5)
  2663. #define   PIPECONF_10BPC        (1<<5)
  2664. #define   PIPECONF_6BPC         (2<<5)
  2665. #define   PIPECONF_12BPC        (3<<5)
  2666. #define   PIPECONF_DITHER_EN    (1<<4)
  2667. #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
  2668. #define   PIPECONF_DITHER_TYPE_SP (0<<2)
  2669. #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
  2670. #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
  2671. #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
  2672. #define _PIPEASTAT              (dev_priv->info->display_mmio_offset + 0x70024)
  2673. #define   PIPE_FIFO_UNDERRUN_STATUS             (1UL<<31)
  2674. #define   SPRITE1_FLIPDONE_INT_EN_VLV           (1UL<<30)
  2675. #define   PIPE_CRC_ERROR_ENABLE                 (1UL<<29)
  2676. #define   PIPE_CRC_DONE_ENABLE                  (1UL<<28)
  2677. #define   PIPE_GMBUS_EVENT_ENABLE               (1UL<<27)
  2678. #define   PLANE_FLIP_DONE_INT_EN_VLV            (1UL<<26)
  2679. #define   PIPE_HOTPLUG_INTERRUPT_ENABLE         (1UL<<26)
  2680. #define   PIPE_VSYNC_INTERRUPT_ENABLE           (1UL<<25)
  2681. #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE      (1UL<<24)
  2682. #define   PIPE_DPST_EVENT_ENABLE                (1UL<<23)
  2683. #define   SPRITE0_FLIP_DONE_INT_EN_VLV          (1UL<<22)
  2684. #define   PIPE_LEGACY_BLC_EVENT_ENABLE          (1UL<<22)
  2685. #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE       (1UL<<21)
  2686. #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE      (1UL<<20)
  2687. #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE      (1UL<<18) /* pre-965 */
  2688. #define   PIPE_START_VBLANK_INTERRUPT_ENABLE    (1UL<<18) /* 965 or later */
  2689. #define   PIPE_VBLANK_INTERRUPT_ENABLE          (1UL<<17)
  2690. #define   PIPEA_HBLANK_INT_EN_VLV               (1UL<<16)
  2691. #define   PIPE_OVERLAY_UPDATED_ENABLE           (1UL<<16)
  2692. #define   SPRITE1_FLIPDONE_INT_STATUS_VLV       (1UL<<15)
  2693. #define   SPRITE0_FLIPDONE_INT_STATUS_VLV       (1UL<<14)
  2694. #define   PIPE_CRC_ERROR_INTERRUPT_STATUS       (1UL<<13)
  2695. #define   PIPE_CRC_DONE_INTERRUPT_STATUS        (1UL<<12)
  2696. #define   PIPE_GMBUS_INTERRUPT_STATUS           (1UL<<11)
  2697. #define   PLANE_FLIPDONE_INT_STATUS_VLV         (1UL<<10)
  2698. #define   PIPE_HOTPLUG_INTERRUPT_STATUS         (1UL<<10)
  2699. #define   PIPE_VSYNC_INTERRUPT_STATUS           (1UL<<9)
  2700. #define   PIPE_DISPLAY_LINE_COMPARE_STATUS      (1UL<<8)
  2701. #define   PIPE_DPST_EVENT_STATUS                (1UL<<7)
  2702. #define   PIPE_LEGACY_BLC_EVENT_STATUS          (1UL<<6)
  2703. #define   PIPE_ODD_FIELD_INTERRUPT_STATUS       (1UL<<5)
  2704. #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS      (1UL<<4)
  2705. #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS      (1UL<<2) /* pre-965 */
  2706. #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL<<2) /* 965 or later */
  2707. #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL<<1)
  2708. #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL<<0)
  2709.  
  2710. #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
  2711. #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
  2712. #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
  2713. #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
  2714. #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
  2715. #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
  2716.  
  2717. #define VLV_DPFLIPSTAT                          (VLV_DISPLAY_BASE + 0x70028)
  2718. #define   PIPEB_LINE_COMPARE_INT_EN             (1<<29)
  2719. #define   PIPEB_HLINE_INT_EN                    (1<<28)
  2720. #define   PIPEB_VBLANK_INT_EN                   (1<<27)
  2721. #define   SPRITED_FLIPDONE_INT_EN               (1<<26)
  2722. #define   SPRITEC_FLIPDONE_INT_EN               (1<<25)
  2723. #define   PLANEB_FLIPDONE_INT_EN                (1<<24)
  2724. #define   PIPEA_LINE_COMPARE_INT_EN             (1<<21)
  2725. #define   PIPEA_HLINE_INT_EN                    (1<<20)
  2726. #define   PIPEA_VBLANK_INT_EN                   (1<<19)
  2727. #define   SPRITEB_FLIPDONE_INT_EN               (1<<18)
  2728. #define   SPRITEA_FLIPDONE_INT_EN               (1<<17)
  2729. #define   PLANEA_FLIPDONE_INT_EN                (1<<16)
  2730.  
  2731. #define DPINVGTT                                (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
  2732. #define   CURSORB_INVALID_GTT_INT_EN            (1<<23)
  2733. #define   CURSORA_INVALID_GTT_INT_EN            (1<<22)
  2734. #define   SPRITED_INVALID_GTT_INT_EN            (1<<21)
  2735. #define   SPRITEC_INVALID_GTT_INT_EN            (1<<20)
  2736. #define   PLANEB_INVALID_GTT_INT_EN             (1<<19)
  2737. #define   SPRITEB_INVALID_GTT_INT_EN            (1<<18)
  2738. #define   SPRITEA_INVALID_GTT_INT_EN            (1<<17)
  2739. #define   PLANEA_INVALID_GTT_INT_EN             (1<<16)
  2740. #define   DPINVGTT_EN_MASK                      0xff0000
  2741. #define   CURSORB_INVALID_GTT_STATUS            (1<<7)
  2742. #define   CURSORA_INVALID_GTT_STATUS            (1<<6)
  2743. #define   SPRITED_INVALID_GTT_STATUS            (1<<5)
  2744. #define   SPRITEC_INVALID_GTT_STATUS            (1<<4)
  2745. #define   PLANEB_INVALID_GTT_STATUS             (1<<3)
  2746. #define   SPRITEB_INVALID_GTT_STATUS            (1<<2)
  2747. #define   SPRITEA_INVALID_GTT_STATUS            (1<<1)
  2748. #define   PLANEA_INVALID_GTT_STATUS             (1<<0)
  2749. #define   DPINVGTT_STATUS_MASK                  0xff
  2750.  
  2751. #define DSPARB                  0x70030
  2752. #define   DSPARB_CSTART_MASK    (0x7f << 7)
  2753. #define   DSPARB_CSTART_SHIFT   7
  2754. #define   DSPARB_BSTART_MASK    (0x7f)
  2755. #define   DSPARB_BSTART_SHIFT   0
  2756. #define   DSPARB_BEND_SHIFT     9 /* on 855 */
  2757. #define   DSPARB_AEND_SHIFT     0
  2758.  
  2759. #define DSPFW1                  (dev_priv->info->display_mmio_offset + 0x70034)
  2760. #define   DSPFW_SR_SHIFT        23
  2761. #define   DSPFW_SR_MASK         (0x1ff<<23)
  2762. #define   DSPFW_CURSORB_SHIFT   16
  2763. #define   DSPFW_CURSORB_MASK    (0x3f<<16)
  2764. #define   DSPFW_PLANEB_SHIFT    8
  2765. #define   DSPFW_PLANEB_MASK     (0x7f<<8)
  2766. #define   DSPFW_PLANEA_MASK     (0x7f)
  2767. #define DSPFW2                  (dev_priv->info->display_mmio_offset + 0x70038)
  2768. #define   DSPFW_CURSORA_MASK    0x00003f00
  2769. #define   DSPFW_CURSORA_SHIFT   8
  2770. #define   DSPFW_PLANEC_MASK     (0x7f)
  2771. #define DSPFW3                  (dev_priv->info->display_mmio_offset + 0x7003c)
  2772. #define   DSPFW_HPLL_SR_EN      (1<<31)
  2773. #define   DSPFW_CURSOR_SR_SHIFT 24
  2774. #define   PINEVIEW_SELF_REFRESH_EN      (1<<30)
  2775. #define   DSPFW_CURSOR_SR_MASK          (0x3f<<24)
  2776. #define   DSPFW_HPLL_CURSOR_SHIFT       16
  2777. #define   DSPFW_HPLL_CURSOR_MASK        (0x3f<<16)
  2778. #define   DSPFW_HPLL_SR_MASK            (0x1ff)
  2779.  
  2780. /* drain latency register values*/
  2781. #define DRAIN_LATENCY_PRECISION_32      32
  2782. #define DRAIN_LATENCY_PRECISION_16      16
  2783. #define VLV_DDL1                        (VLV_DISPLAY_BASE + 0x70050)
  2784. #define DDL_CURSORA_PRECISION_32        (1<<31)
  2785. #define DDL_CURSORA_PRECISION_16        (0<<31)
  2786. #define DDL_CURSORA_SHIFT               24
  2787. #define DDL_PLANEA_PRECISION_32         (1<<7)
  2788. #define DDL_PLANEA_PRECISION_16         (0<<7)
  2789. #define VLV_DDL2                        (VLV_DISPLAY_BASE + 0x70054)
  2790. #define DDL_CURSORB_PRECISION_32        (1<<31)
  2791. #define DDL_CURSORB_PRECISION_16        (0<<31)
  2792. #define DDL_CURSORB_SHIFT               24
  2793. #define DDL_PLANEB_PRECISION_32         (1<<7)
  2794. #define DDL_PLANEB_PRECISION_16         (0<<7)
  2795.  
  2796. /* FIFO watermark sizes etc */
  2797. #define G4X_FIFO_LINE_SIZE      64
  2798. #define I915_FIFO_LINE_SIZE     64
  2799. #define I830_FIFO_LINE_SIZE     32
  2800.  
  2801. #define VALLEYVIEW_FIFO_SIZE    255
  2802. #define G4X_FIFO_SIZE           127
  2803. #define I965_FIFO_SIZE          512
  2804. #define I945_FIFO_SIZE          127
  2805. #define I915_FIFO_SIZE          95
  2806. #define I855GM_FIFO_SIZE        127 /* In cachelines */
  2807. #define I830_FIFO_SIZE          95
  2808.  
  2809. #define VALLEYVIEW_MAX_WM       0xff
  2810. #define G4X_MAX_WM              0x3f
  2811. #define I915_MAX_WM             0x3f
  2812.  
  2813. #define PINEVIEW_DISPLAY_FIFO   512 /* in 64byte unit */
  2814. #define PINEVIEW_FIFO_LINE_SIZE 64
  2815. #define PINEVIEW_MAX_WM         0x1ff
  2816. #define PINEVIEW_DFT_WM         0x3f
  2817. #define PINEVIEW_DFT_HPLLOFF_WM 0
  2818. #define PINEVIEW_GUARD_WM               10
  2819. #define PINEVIEW_CURSOR_FIFO            64
  2820. #define PINEVIEW_CURSOR_MAX_WM  0x3f
  2821. #define PINEVIEW_CURSOR_DFT_WM  0
  2822. #define PINEVIEW_CURSOR_GUARD_WM        5
  2823.  
  2824. #define VALLEYVIEW_CURSOR_MAX_WM 64
  2825. #define I965_CURSOR_FIFO        64
  2826. #define I965_CURSOR_MAX_WM      32
  2827. #define I965_CURSOR_DFT_WM      8
  2828.  
  2829. /* define the Watermark register on Ironlake */
  2830. #define WM0_PIPEA_ILK           0x45100
  2831. #define  WM0_PIPE_PLANE_MASK    (0x7f<<16)
  2832. #define  WM0_PIPE_PLANE_SHIFT   16
  2833. #define  WM0_PIPE_SPRITE_MASK   (0x3f<<8)
  2834. #define  WM0_PIPE_SPRITE_SHIFT  8
  2835. #define  WM0_PIPE_CURSOR_MASK   (0x1f)
  2836.  
  2837. #define WM0_PIPEB_ILK           0x45104
  2838. #define WM0_PIPEC_IVB           0x45200
  2839. #define WM1_LP_ILK              0x45108
  2840. #define  WM1_LP_SR_EN           (1<<31)
  2841. #define  WM1_LP_LATENCY_SHIFT   24
  2842. #define  WM1_LP_LATENCY_MASK    (0x7f<<24)
  2843. #define  WM1_LP_FBC_MASK        (0xf<<20)
  2844. #define  WM1_LP_FBC_SHIFT       20
  2845. #define  WM1_LP_SR_MASK         (0x1ff<<8)
  2846. #define  WM1_LP_SR_SHIFT        8
  2847. #define  WM1_LP_CURSOR_MASK     (0x3f)
  2848. #define WM2_LP_ILK              0x4510c
  2849. #define  WM2_LP_EN              (1<<31)
  2850. #define WM3_LP_ILK              0x45110
  2851. #define  WM3_LP_EN              (1<<31)
  2852. #define WM1S_LP_ILK             0x45120
  2853. #define WM2S_LP_IVB             0x45124
  2854. #define WM3S_LP_IVB             0x45128
  2855. #define  WM1S_LP_EN             (1<<31)
  2856.  
  2857. /* Memory latency timer register */
  2858. #define MLTR_ILK                0x11222
  2859. #define  MLTR_WM1_SHIFT         0
  2860. #define  MLTR_WM2_SHIFT         8
  2861. /* the unit of memory self-refresh latency time is 0.5us */
  2862. #define  ILK_SRLT_MASK          0x3f
  2863. #define ILK_LATENCY(shift)      (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
  2864. #define ILK_READ_WM1_LATENCY()  ILK_LATENCY(MLTR_WM1_SHIFT)
  2865. #define ILK_READ_WM2_LATENCY()  ILK_LATENCY(MLTR_WM2_SHIFT)
  2866.  
  2867. /* define the fifo size on Ironlake */
  2868. #define ILK_DISPLAY_FIFO        128
  2869. #define ILK_DISPLAY_MAXWM       64
  2870. #define ILK_DISPLAY_DFTWM       8
  2871. #define ILK_CURSOR_FIFO         32
  2872. #define ILK_CURSOR_MAXWM        16
  2873. #define ILK_CURSOR_DFTWM        8
  2874.  
  2875. #define ILK_DISPLAY_SR_FIFO     512
  2876. #define ILK_DISPLAY_MAX_SRWM    0x1ff
  2877. #define ILK_DISPLAY_DFT_SRWM    0x3f
  2878. #define ILK_CURSOR_SR_FIFO      64
  2879. #define ILK_CURSOR_MAX_SRWM     0x3f
  2880. #define ILK_CURSOR_DFT_SRWM     8
  2881.  
  2882. #define ILK_FIFO_LINE_SIZE      64
  2883.  
  2884. /* define the WM info on Sandybridge */
  2885. #define SNB_DISPLAY_FIFO        128
  2886. #define SNB_DISPLAY_MAXWM       0x7f    /* bit 16:22 */
  2887. #define SNB_DISPLAY_DFTWM       8
  2888. #define SNB_CURSOR_FIFO         32
  2889. #define SNB_CURSOR_MAXWM        0x1f    /* bit 4:0 */
  2890. #define SNB_CURSOR_DFTWM        8
  2891.  
  2892. #define SNB_DISPLAY_SR_FIFO     512
  2893. #define SNB_DISPLAY_MAX_SRWM    0x1ff   /* bit 16:8 */
  2894. #define SNB_DISPLAY_DFT_SRWM    0x3f
  2895. #define SNB_CURSOR_SR_FIFO      64
  2896. #define SNB_CURSOR_MAX_SRWM     0x3f    /* bit 5:0 */
  2897. #define SNB_CURSOR_DFT_SRWM     8
  2898.  
  2899. #define SNB_FBC_MAX_SRWM        0xf     /* bit 23:20 */
  2900.  
  2901. #define SNB_FIFO_LINE_SIZE      64
  2902.  
  2903.  
  2904. /* the address where we get all kinds of latency value */
  2905. #define SSKPD                   0x5d10
  2906. #define SSKPD_WM_MASK           0x3f
  2907. #define SSKPD_WM0_SHIFT         0
  2908. #define SSKPD_WM1_SHIFT         8
  2909. #define SSKPD_WM2_SHIFT         16
  2910. #define SSKPD_WM3_SHIFT         24
  2911.  
  2912. #define SNB_LATENCY(shift)      (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
  2913. #define SNB_READ_WM0_LATENCY()          SNB_LATENCY(SSKPD_WM0_SHIFT)
  2914. #define SNB_READ_WM1_LATENCY()          SNB_LATENCY(SSKPD_WM1_SHIFT)
  2915. #define SNB_READ_WM2_LATENCY()          SNB_LATENCY(SSKPD_WM2_SHIFT)
  2916. #define SNB_READ_WM3_LATENCY()          SNB_LATENCY(SSKPD_WM3_SHIFT)
  2917.  
  2918. /*
  2919.  * The two pipe frame counter registers are not synchronized, so
  2920.  * reading a stable value is somewhat tricky. The following code
  2921.  * should work:
  2922.  *
  2923.  *  do {
  2924.  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  2925.  *             PIPE_FRAME_HIGH_SHIFT;
  2926.  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
  2927.  *             PIPE_FRAME_LOW_SHIFT);
  2928.  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  2929.  *             PIPE_FRAME_HIGH_SHIFT);
  2930.  *  } while (high1 != high2);
  2931.  *  frame = (high1 << 8) | low1;
  2932.  */
  2933. #define _PIPEAFRAMEHIGH          (dev_priv->info->display_mmio_offset + 0x70040)
  2934. #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
  2935. #define   PIPE_FRAME_HIGH_SHIFT   0
  2936. #define _PIPEAFRAMEPIXEL         (dev_priv->info->display_mmio_offset + 0x70044)
  2937. #define   PIPE_FRAME_LOW_MASK     0xff000000
  2938. #define   PIPE_FRAME_LOW_SHIFT    24
  2939. #define   PIPE_PIXEL_MASK         0x00ffffff
  2940. #define   PIPE_PIXEL_SHIFT        0
  2941. /* GM45+ just has to be different */
  2942. #define _PIPEA_FRMCOUNT_GM45    0x70040
  2943. #define _PIPEA_FLIPCOUNT_GM45   0x70044
  2944. #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
  2945.  
  2946. /* Cursor A & B regs */
  2947. #define _CURACNTR               (dev_priv->info->display_mmio_offset + 0x70080)
  2948. /* Old style CUR*CNTR flags (desktop 8xx) */
  2949. #define   CURSOR_ENABLE         0x80000000
  2950. #define   CURSOR_GAMMA_ENABLE   0x40000000
  2951. #define   CURSOR_STRIDE_MASK    0x30000000
  2952. #define   CURSOR_PIPE_CSC_ENABLE (1<<24)
  2953. #define   CURSOR_FORMAT_SHIFT   24
  2954. #define   CURSOR_FORMAT_MASK    (0x07 << CURSOR_FORMAT_SHIFT)
  2955. #define   CURSOR_FORMAT_2C      (0x00 << CURSOR_FORMAT_SHIFT)
  2956. #define   CURSOR_FORMAT_3C      (0x01 << CURSOR_FORMAT_SHIFT)
  2957. #define   CURSOR_FORMAT_4C      (0x02 << CURSOR_FORMAT_SHIFT)
  2958. #define   CURSOR_FORMAT_ARGB    (0x04 << CURSOR_FORMAT_SHIFT)
  2959. #define   CURSOR_FORMAT_XRGB    (0x05 << CURSOR_FORMAT_SHIFT)
  2960. /* New style CUR*CNTR flags */
  2961. #define   CURSOR_MODE           0x27
  2962. #define   CURSOR_MODE_DISABLE   0x00
  2963. #define   CURSOR_MODE_64_32B_AX 0x07
  2964. #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
  2965. #define   MCURSOR_PIPE_SELECT   (1 << 28)
  2966. #define   MCURSOR_PIPE_A        0x00
  2967. #define   MCURSOR_PIPE_B        (1 << 28)
  2968. #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
  2969. #define _CURABASE               (dev_priv->info->display_mmio_offset + 0x70084)
  2970. #define _CURAPOS                (dev_priv->info->display_mmio_offset + 0x70088)
  2971. #define   CURSOR_POS_MASK       0x007FF
  2972. #define   CURSOR_POS_SIGN       0x8000
  2973. #define   CURSOR_X_SHIFT        0
  2974. #define   CURSOR_Y_SHIFT        16
  2975. #define CURSIZE                 0x700a0
  2976. #define _CURBCNTR               (dev_priv->info->display_mmio_offset + 0x700c0)
  2977. #define _CURBBASE               (dev_priv->info->display_mmio_offset + 0x700c4)
  2978. #define _CURBPOS                (dev_priv->info->display_mmio_offset + 0x700c8)
  2979.  
  2980. #define _CURBCNTR_IVB           0x71080
  2981. #define _CURBBASE_IVB           0x71084
  2982. #define _CURBPOS_IVB            0x71088
  2983.  
  2984. #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
  2985. #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
  2986. #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
  2987.  
  2988. #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
  2989. #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
  2990. #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
  2991.  
  2992. /* Display A control */
  2993. #define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
  2994. #define   DISPLAY_PLANE_ENABLE                  (1<<31)
  2995. #define   DISPLAY_PLANE_DISABLE                 0
  2996. #define   DISPPLANE_GAMMA_ENABLE                (1<<30)
  2997. #define   DISPPLANE_GAMMA_DISABLE               0
  2998. #define   DISPPLANE_PIXFORMAT_MASK              (0xf<<26)
  2999. #define   DISPPLANE_YUV422                      (0x0<<26)
  3000. #define   DISPPLANE_8BPP                        (0x2<<26)
  3001. #define   DISPPLANE_BGRA555                     (0x3<<26)
  3002. #define   DISPPLANE_BGRX555                     (0x4<<26)
  3003. #define   DISPPLANE_BGRX565                     (0x5<<26)
  3004. #define   DISPPLANE_BGRX888                     (0x6<<26)
  3005. #define   DISPPLANE_BGRA888                     (0x7<<26)
  3006. #define   DISPPLANE_RGBX101010                  (0x8<<26)
  3007. #define   DISPPLANE_RGBA101010                  (0x9<<26)
  3008. #define   DISPPLANE_BGRX101010                  (0xa<<26)
  3009. #define   DISPPLANE_RGBX161616                  (0xc<<26)
  3010. #define   DISPPLANE_RGBX888                     (0xe<<26)
  3011. #define   DISPPLANE_RGBA888                     (0xf<<26)
  3012. #define   DISPPLANE_STEREO_ENABLE               (1<<25)
  3013. #define   DISPPLANE_STEREO_DISABLE              0
  3014. #define   DISPPLANE_PIPE_CSC_ENABLE             (1<<24)
  3015. #define   DISPPLANE_SEL_PIPE_SHIFT              24
  3016. #define   DISPPLANE_SEL_PIPE_MASK               (3<<DISPPLANE_SEL_PIPE_SHIFT)
  3017. #define   DISPPLANE_SEL_PIPE_A                  0
  3018. #define   DISPPLANE_SEL_PIPE_B                  (1<<DISPPLANE_SEL_PIPE_SHIFT)
  3019. #define   DISPPLANE_SRC_KEY_ENABLE              (1<<22)
  3020. #define   DISPPLANE_SRC_KEY_DISABLE             0
  3021. #define   DISPPLANE_LINE_DOUBLE                 (1<<20)
  3022. #define   DISPPLANE_NO_LINE_DOUBLE              0
  3023. #define   DISPPLANE_STEREO_POLARITY_FIRST       0
  3024. #define   DISPPLANE_STEREO_POLARITY_SECOND      (1<<18)
  3025. #define   DISPPLANE_TRICKLE_FEED_DISABLE        (1<<14) /* Ironlake */
  3026. #define   DISPPLANE_TILED                       (1<<10)
  3027. #define _DSPAADDR               (dev_priv->info->display_mmio_offset + 0x70184)
  3028. #define _DSPASTRIDE             (dev_priv->info->display_mmio_offset + 0x70188)
  3029. #define _DSPAPOS                (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
  3030. #define _DSPASIZE               (dev_priv->info->display_mmio_offset + 0x70190)
  3031. #define _DSPASURF               (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
  3032. #define _DSPATILEOFF            (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
  3033. #define _DSPAOFFSET             (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
  3034. #define _DSPASURFLIVE           (dev_priv->info->display_mmio_offset + 0x701AC)
  3035.  
  3036. #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
  3037. #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
  3038. #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
  3039. #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
  3040. #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
  3041. #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
  3042. #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
  3043. #define DSPLINOFF(plane) DSPADDR(plane)
  3044. #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
  3045. #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
  3046.  
  3047. /* Display/Sprite base address macros */
  3048. #define DISP_BASEADDR_MASK      (0xfffff000)
  3049. #define I915_LO_DISPBASE(val)   (val & ~DISP_BASEADDR_MASK)
  3050. #define I915_HI_DISPBASE(val)   (val & DISP_BASEADDR_MASK)
  3051. #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
  3052.                 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
  3053.  
  3054. /* VBIOS flags */
  3055. #define SWF00                   (dev_priv->info->display_mmio_offset + 0x71410)
  3056. #define SWF01                   (dev_priv->info->display_mmio_offset + 0x71414)
  3057. #define SWF02                   (dev_priv->info->display_mmio_offset + 0x71418)
  3058. #define SWF03                   (dev_priv->info->display_mmio_offset + 0x7141c)
  3059. #define SWF04                   (dev_priv->info->display_mmio_offset + 0x71420)
  3060. #define SWF05                   (dev_priv->info->display_mmio_offset + 0x71424)
  3061. #define SWF06                   (dev_priv->info->display_mmio_offset + 0x71428)
  3062. #define SWF10                   (dev_priv->info->display_mmio_offset + 0x70410)
  3063. #define SWF11                   (dev_priv->info->display_mmio_offset + 0x70414)
  3064. #define SWF14                   (dev_priv->info->display_mmio_offset + 0x71420)
  3065. #define SWF30                   (dev_priv->info->display_mmio_offset + 0x72414)
  3066. #define SWF31                   (dev_priv->info->display_mmio_offset + 0x72418)
  3067. #define SWF32                   (dev_priv->info->display_mmio_offset + 0x7241c)
  3068.  
  3069. /* Pipe B */
  3070. #define _PIPEBDSL               (dev_priv->info->display_mmio_offset + 0x71000)
  3071. #define _PIPEBCONF              (dev_priv->info->display_mmio_offset + 0x71008)
  3072. #define _PIPEBSTAT              (dev_priv->info->display_mmio_offset + 0x71024)
  3073. #define _PIPEBFRAMEHIGH         (dev_priv->info->display_mmio_offset + 0x71040)
  3074. #define _PIPEBFRAMEPIXEL        (dev_priv->info->display_mmio_offset + 0x71044)
  3075. #define _PIPEB_FRMCOUNT_GM45    0x71040
  3076. #define _PIPEB_FLIPCOUNT_GM45   0x71044
  3077.  
  3078.  
  3079. /* Display B control */
  3080. #define _DSPBCNTR               (dev_priv->info->display_mmio_offset + 0x71180)
  3081. #define   DISPPLANE_ALPHA_TRANS_ENABLE          (1<<15)
  3082. #define   DISPPLANE_ALPHA_TRANS_DISABLE         0
  3083. #define   DISPPLANE_SPRITE_ABOVE_DISPLAY        0
  3084. #define   DISPPLANE_SPRITE_ABOVE_OVERLAY        (1)
  3085. #define _DSPBADDR               (dev_priv->info->display_mmio_offset + 0x71184)
  3086. #define _DSPBSTRIDE             (dev_priv->info->display_mmio_offset + 0x71188)
  3087. #define _DSPBPOS                (dev_priv->info->display_mmio_offset + 0x7118C)
  3088. #define _DSPBSIZE               (dev_priv->info->display_mmio_offset + 0x71190)
  3089. #define _DSPBSURF               (dev_priv->info->display_mmio_offset + 0x7119C)
  3090. #define _DSPBTILEOFF            (dev_priv->info->display_mmio_offset + 0x711A4)
  3091. #define _DSPBOFFSET             (dev_priv->info->display_mmio_offset + 0x711A4)
  3092. #define _DSPBSURFLIVE           (dev_priv->info->display_mmio_offset + 0x711AC)
  3093.  
  3094. /* Sprite A control */
  3095. #define _DVSACNTR               0x72180
  3096. #define   DVS_ENABLE            (1<<31)
  3097. #define   DVS_GAMMA_ENABLE      (1<<30)
  3098. #define   DVS_PIXFORMAT_MASK    (3<<25)
  3099. #define   DVS_FORMAT_YUV422     (0<<25)
  3100. #define   DVS_FORMAT_RGBX101010 (1<<25)
  3101. #define   DVS_FORMAT_RGBX888    (2<<25)
  3102. #define   DVS_FORMAT_RGBX161616 (3<<25)
  3103. #define   DVS_PIPE_CSC_ENABLE   (1<<24)
  3104. #define   DVS_SOURCE_KEY        (1<<22)
  3105. #define   DVS_RGB_ORDER_XBGR    (1<<20)
  3106. #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
  3107. #define   DVS_YUV_ORDER_YUYV    (0<<16)
  3108. #define   DVS_YUV_ORDER_UYVY    (1<<16)
  3109. #define   DVS_YUV_ORDER_YVYU    (2<<16)
  3110. #define   DVS_YUV_ORDER_VYUY    (3<<16)
  3111. #define   DVS_DEST_KEY          (1<<2)
  3112. #define   DVS_TRICKLE_FEED_DISABLE (1<<14)
  3113. #define   DVS_TILED             (1<<10)
  3114. #define _DVSALINOFF             0x72184
  3115. #define _DVSASTRIDE             0x72188
  3116. #define _DVSAPOS                0x7218c
  3117. #define _DVSASIZE               0x72190
  3118. #define _DVSAKEYVAL             0x72194
  3119. #define _DVSAKEYMSK             0x72198
  3120. #define _DVSASURF               0x7219c
  3121. #define _DVSAKEYMAXVAL          0x721a0
  3122. #define _DVSATILEOFF            0x721a4
  3123. #define _DVSASURFLIVE           0x721ac
  3124. #define _DVSASCALE              0x72204
  3125. #define   DVS_SCALE_ENABLE      (1<<31)
  3126. #define   DVS_FILTER_MASK       (3<<29)
  3127. #define   DVS_FILTER_MEDIUM     (0<<29)
  3128. #define   DVS_FILTER_ENHANCING  (1<<29)
  3129. #define   DVS_FILTER_SOFTENING  (2<<29)
  3130. #define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
  3131. #define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
  3132. #define _DVSAGAMC               0x72300
  3133.  
  3134. #define _DVSBCNTR               0x73180
  3135. #define _DVSBLINOFF             0x73184
  3136. #define _DVSBSTRIDE             0x73188
  3137. #define _DVSBPOS                0x7318c
  3138. #define _DVSBSIZE               0x73190
  3139. #define _DVSBKEYVAL             0x73194
  3140. #define _DVSBKEYMSK             0x73198
  3141. #define _DVSBSURF               0x7319c
  3142. #define _DVSBKEYMAXVAL          0x731a0
  3143. #define _DVSBTILEOFF            0x731a4
  3144. #define _DVSBSURFLIVE           0x731ac
  3145. #define _DVSBSCALE              0x73204
  3146. #define _DVSBGAMC               0x73300
  3147.  
  3148. #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
  3149. #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
  3150. #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
  3151. #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
  3152. #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
  3153. #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
  3154. #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
  3155. #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
  3156. #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
  3157. #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
  3158. #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
  3159. #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
  3160.  
  3161. #define _SPRA_CTL               0x70280
  3162. #define   SPRITE_ENABLE                 (1<<31)
  3163. #define   SPRITE_GAMMA_ENABLE           (1<<30)
  3164. #define   SPRITE_PIXFORMAT_MASK         (7<<25)
  3165. #define   SPRITE_FORMAT_YUV422          (0<<25)
  3166. #define   SPRITE_FORMAT_RGBX101010      (1<<25)
  3167. #define   SPRITE_FORMAT_RGBX888         (2<<25)
  3168. #define   SPRITE_FORMAT_RGBX161616      (3<<25)
  3169. #define   SPRITE_FORMAT_YUV444          (4<<25)
  3170. #define   SPRITE_FORMAT_XR_BGR101010    (5<<25) /* Extended range */
  3171. #define   SPRITE_PIPE_CSC_ENABLE        (1<<24)
  3172. #define   SPRITE_SOURCE_KEY             (1<<22)
  3173. #define   SPRITE_RGB_ORDER_RGBX         (1<<20) /* only for 888 and 161616 */
  3174. #define   SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
  3175. #define   SPRITE_YUV_CSC_FORMAT_BT709   (1<<18) /* 0 is BT601 */
  3176. #define   SPRITE_YUV_BYTE_ORDER_MASK    (3<<16)
  3177. #define   SPRITE_YUV_ORDER_YUYV         (0<<16)
  3178. #define   SPRITE_YUV_ORDER_UYVY         (1<<16)
  3179. #define   SPRITE_YUV_ORDER_YVYU         (2<<16)
  3180. #define   SPRITE_YUV_ORDER_VYUY         (3<<16)
  3181. #define   SPRITE_TRICKLE_FEED_DISABLE   (1<<14)
  3182. #define   SPRITE_INT_GAMMA_ENABLE       (1<<13)
  3183. #define   SPRITE_TILED                  (1<<10)
  3184. #define   SPRITE_DEST_KEY               (1<<2)
  3185. #define _SPRA_LINOFF            0x70284
  3186. #define _SPRA_STRIDE            0x70288
  3187. #define _SPRA_POS               0x7028c
  3188. #define _SPRA_SIZE              0x70290
  3189. #define _SPRA_KEYVAL            0x70294
  3190. #define _SPRA_KEYMSK            0x70298
  3191. #define _SPRA_SURF              0x7029c
  3192. #define _SPRA_KEYMAX            0x702a0
  3193. #define _SPRA_TILEOFF           0x702a4
  3194. #define _SPRA_OFFSET            0x702a4
  3195. #define _SPRA_SURFLIVE          0x702ac
  3196. #define _SPRA_SCALE             0x70304
  3197. #define   SPRITE_SCALE_ENABLE   (1<<31)
  3198. #define   SPRITE_FILTER_MASK    (3<<29)
  3199. #define   SPRITE_FILTER_MEDIUM  (0<<29)
  3200. #define   SPRITE_FILTER_ENHANCING       (1<<29)
  3201. #define   SPRITE_FILTER_SOFTENING       (2<<29)
  3202. #define   SPRITE_VERTICAL_OFFSET_HALF   (1<<28) /* must be enabled below */
  3203. #define   SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
  3204. #define _SPRA_GAMC              0x70400
  3205.  
  3206. #define _SPRB_CTL               0x71280
  3207. #define _SPRB_LINOFF            0x71284
  3208. #define _SPRB_STRIDE            0x71288
  3209. #define _SPRB_POS               0x7128c
  3210. #define _SPRB_SIZE              0x71290
  3211. #define _SPRB_KEYVAL            0x71294
  3212. #define _SPRB_KEYMSK            0x71298
  3213. #define _SPRB_SURF              0x7129c
  3214. #define _SPRB_KEYMAX            0x712a0
  3215. #define _SPRB_TILEOFF           0x712a4
  3216. #define _SPRB_OFFSET            0x712a4
  3217. #define _SPRB_SURFLIVE          0x712ac
  3218. #define _SPRB_SCALE             0x71304
  3219. #define _SPRB_GAMC              0x71400
  3220.  
  3221. #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
  3222. #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
  3223. #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
  3224. #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
  3225. #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
  3226. #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
  3227. #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
  3228. #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
  3229. #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
  3230. #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
  3231. #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
  3232. #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
  3233. #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
  3234. #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
  3235.  
  3236. /* VBIOS regs */
  3237. #define VGACNTRL                0x71400
  3238. # define VGA_DISP_DISABLE                       (1 << 31)
  3239. # define VGA_2X_MODE                            (1 << 30)
  3240. # define VGA_PIPE_B_SELECT                      (1 << 29)
  3241.  
  3242. #define VLV_VGACNTRL            (VLV_DISPLAY_BASE + 0x71400)
  3243.  
  3244. /* Ironlake */
  3245.  
  3246. #define CPU_VGACNTRL    0x41000
  3247.  
  3248. #define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
  3249. #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
  3250. #define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
  3251. #define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
  3252. #define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
  3253. #define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
  3254. #define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
  3255. #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
  3256. #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
  3257.  
  3258. /* refresh rate hardware control */
  3259. #define RR_HW_CTL       0x45300
  3260. #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
  3261. #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
  3262.  
  3263. #define FDI_PLL_BIOS_0  0x46000
  3264. #define  FDI_PLL_FB_CLOCK_MASK  0xff
  3265. #define FDI_PLL_BIOS_1  0x46004
  3266. #define FDI_PLL_BIOS_2  0x46008
  3267. #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
  3268. #define DISPLAY_PORT_PLL_BIOS_1         0x46010
  3269. #define DISPLAY_PORT_PLL_BIOS_2         0x46014
  3270.  
  3271. #define PCH_3DCGDIS0            0x46020
  3272. # define MARIUNIT_CLOCK_GATE_DISABLE            (1 << 18)
  3273. # define SVSMUNIT_CLOCK_GATE_DISABLE            (1 << 1)
  3274.  
  3275. #define PCH_3DCGDIS1            0x46024
  3276. # define VFMUNIT_CLOCK_GATE_DISABLE             (1 << 11)
  3277.  
  3278. #define FDI_PLL_FREQ_CTL        0x46030
  3279. #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
  3280. #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
  3281. #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
  3282.  
  3283.  
  3284. #define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
  3285. #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
  3286. #define  TU_SIZE_MASK           0x7e000000
  3287. #define  PIPE_DATA_M1_OFFSET    0
  3288. #define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
  3289. #define  PIPE_DATA_N1_OFFSET    0
  3290.  
  3291. #define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
  3292. #define  PIPE_DATA_M2_OFFSET    0
  3293. #define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
  3294. #define  PIPE_DATA_N2_OFFSET    0
  3295.  
  3296. #define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
  3297. #define  PIPE_LINK_M1_OFFSET    0
  3298. #define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
  3299. #define  PIPE_LINK_N1_OFFSET    0
  3300.  
  3301. #define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
  3302. #define  PIPE_LINK_M2_OFFSET    0
  3303. #define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
  3304. #define  PIPE_LINK_N2_OFFSET    0
  3305.  
  3306. /* PIPEB timing regs are same start from 0x61000 */
  3307.  
  3308. #define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
  3309. #define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
  3310.  
  3311. #define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
  3312. #define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
  3313.  
  3314. #define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
  3315. #define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
  3316.  
  3317. #define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
  3318. #define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
  3319.  
  3320. #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
  3321. #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
  3322. #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
  3323. #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
  3324. #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
  3325. #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
  3326. #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
  3327. #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
  3328.  
  3329. /* CPU panel fitter */
  3330. /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
  3331. #define _PFA_CTL_1               0x68080
  3332. #define _PFB_CTL_1               0x68880
  3333. #define  PF_ENABLE              (1<<31)
  3334. #define  PF_PIPE_SEL_MASK_IVB   (3<<29)
  3335. #define  PF_PIPE_SEL_IVB(pipe)  ((pipe)<<29)
  3336. #define  PF_FILTER_MASK         (3<<23)
  3337. #define  PF_FILTER_PROGRAMMED   (0<<23)
  3338. #define  PF_FILTER_MED_3x3      (1<<23)
  3339. #define  PF_FILTER_EDGE_ENHANCE (2<<23)
  3340. #define  PF_FILTER_EDGE_SOFTEN  (3<<23)
  3341. #define _PFA_WIN_SZ             0x68074
  3342. #define _PFB_WIN_SZ             0x68874
  3343. #define _PFA_WIN_POS            0x68070
  3344. #define _PFB_WIN_POS            0x68870
  3345. #define _PFA_VSCALE             0x68084
  3346. #define _PFB_VSCALE             0x68884
  3347. #define _PFA_HSCALE             0x68090
  3348. #define _PFB_HSCALE             0x68890
  3349.  
  3350. #define PF_CTL(pipe)            _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
  3351. #define PF_WIN_SZ(pipe)         _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
  3352. #define PF_WIN_POS(pipe)        _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
  3353. #define PF_VSCALE(pipe)         _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
  3354. #define PF_HSCALE(pipe)         _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
  3355.  
  3356. /* legacy palette */
  3357. #define _LGC_PALETTE_A           0x4a000
  3358. #define _LGC_PALETTE_B           0x4a800
  3359. #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
  3360.  
  3361. /* interrupts */
  3362. #define DE_MASTER_IRQ_CONTROL   (1 << 31)
  3363. #define DE_SPRITEB_FLIP_DONE    (1 << 29)
  3364. #define DE_SPRITEA_FLIP_DONE    (1 << 28)
  3365. #define DE_PLANEB_FLIP_DONE     (1 << 27)
  3366. #define DE_PLANEA_FLIP_DONE     (1 << 26)
  3367. #define DE_PCU_EVENT            (1 << 25)
  3368. #define DE_GTT_FAULT            (1 << 24)
  3369. #define DE_POISON               (1 << 23)
  3370. #define DE_PERFORM_COUNTER      (1 << 22)
  3371. #define DE_PCH_EVENT            (1 << 21)
  3372. #define DE_AUX_CHANNEL_A        (1 << 20)
  3373. #define DE_DP_A_HOTPLUG         (1 << 19)
  3374. #define DE_GSE                  (1 << 18)
  3375. #define DE_PIPEB_VBLANK         (1 << 15)
  3376. #define DE_PIPEB_EVEN_FIELD     (1 << 14)
  3377. #define DE_PIPEB_ODD_FIELD      (1 << 13)
  3378. #define DE_PIPEB_LINE_COMPARE   (1 << 12)
  3379. #define DE_PIPEB_VSYNC          (1 << 11)
  3380. #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
  3381. #define DE_PIPEA_VBLANK         (1 << 7)
  3382. #define DE_PIPEA_EVEN_FIELD     (1 << 6)
  3383. #define DE_PIPEA_ODD_FIELD      (1 << 5)
  3384. #define DE_PIPEA_LINE_COMPARE   (1 << 4)
  3385. #define DE_PIPEA_VSYNC          (1 << 3)
  3386. #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
  3387.  
  3388. /* More Ivybridge lolz */
  3389. #define DE_ERR_DEBUG_IVB                (1<<30)
  3390. #define DE_GSE_IVB                      (1<<29)
  3391. #define DE_PCH_EVENT_IVB                (1<<28)
  3392. #define DE_DP_A_HOTPLUG_IVB             (1<<27)
  3393. #define DE_AUX_CHANNEL_A_IVB            (1<<26)
  3394. #define DE_SPRITEC_FLIP_DONE_IVB        (1<<14)
  3395. #define DE_PLANEC_FLIP_DONE_IVB         (1<<13)
  3396. #define DE_PIPEC_VBLANK_IVB             (1<<10)
  3397. #define DE_SPRITEB_FLIP_DONE_IVB        (1<<9)
  3398. #define DE_PLANEB_FLIP_DONE_IVB         (1<<8)
  3399. #define DE_PIPEB_VBLANK_IVB             (1<<5)
  3400. #define DE_SPRITEA_FLIP_DONE_IVB        (1<<4)
  3401. #define DE_PLANEA_FLIP_DONE_IVB         (1<<3)
  3402. #define DE_PIPEA_VBLANK_IVB             (1<<0)
  3403.  
  3404. #define VLV_MASTER_IER                  0x4400c /* Gunit master IER */
  3405. #define   MASTER_INTERRUPT_ENABLE       (1<<31)
  3406.  
  3407. #define DEISR   0x44000
  3408. #define DEIMR   0x44004
  3409. #define DEIIR   0x44008
  3410. #define DEIER   0x4400c
  3411.  
  3412. /* GT interrupt.
  3413.  * Note that for gen6+ the ring-specific interrupt bits do alias with the
  3414.  * corresponding bits in the per-ring interrupt control registers. */
  3415. #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT    (1 << 26)
  3416. #define GT_GEN6_BLT_CS_ERROR_INTERRUPT          (1 << 25)
  3417. #define GT_GEN6_BLT_USER_INTERRUPT              (1 << 22)
  3418. #define GT_GEN6_BSD_CS_ERROR_INTERRUPT          (1 << 15)
  3419. #define GT_GEN6_BSD_USER_INTERRUPT              (1 << 12)
  3420. #define GT_BSD_USER_INTERRUPT                   (1 << 5) /* ilk only */
  3421. #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT       (1 << 5)
  3422. #define GT_PIPE_NOTIFY          (1 << 4)
  3423. #define GT_RENDER_CS_ERROR_INTERRUPT            (1 << 3)
  3424. #define GT_SYNC_STATUS          (1 << 2)
  3425. #define GT_USER_INTERRUPT       (1 << 0)
  3426.  
  3427. #define GTISR   0x44010
  3428. #define GTIMR   0x44014
  3429. #define GTIIR   0x44018
  3430. #define GTIER   0x4401c
  3431.  
  3432. #define ILK_DISPLAY_CHICKEN2    0x42004
  3433. /* Required on all Ironlake and Sandybridge according to the B-Spec. */
  3434. #define  ILK_ELPIN_409_SELECT   (1 << 25)
  3435. #define  ILK_DPARB_GATE (1<<22)
  3436. #define  ILK_VSDPFD_FULL        (1<<21)
  3437. #define ILK_DISPLAY_CHICKEN_FUSES       0x42014
  3438. #define  ILK_INTERNAL_GRAPHICS_DISABLE  (1<<31)
  3439. #define  ILK_INTERNAL_DISPLAY_DISABLE   (1<<30)
  3440. #define  ILK_DISPLAY_DEBUG_DISABLE      (1<<29)
  3441. #define  ILK_HDCP_DISABLE               (1<<25)
  3442. #define  ILK_eDP_A_DISABLE              (1<<24)
  3443. #define  ILK_DESKTOP                    (1<<23)
  3444.  
  3445. #define ILK_DSPCLK_GATE_D                       0x42020
  3446. #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE        (1 << 28)
  3447. #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE       (1 << 9)
  3448. #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE      (1 << 8)
  3449. #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE        (1 << 7)
  3450. #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE       (1 << 5)
  3451.  
  3452. #define IVB_CHICKEN3    0x4200c
  3453. # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE      (1 << 5)
  3454. # define CHICKEN3_DGMG_DONE_FIX_DISABLE         (1 << 2)
  3455.  
  3456. #define DISP_ARB_CTL    0x45000
  3457. #define  DISP_TILE_SURFACE_SWIZZLING    (1<<13)
  3458. #define  DISP_FBC_WM_DIS                (1<<15)
  3459.  
  3460. /* GEN7 chicken */
  3461. #define GEN7_COMMON_SLICE_CHICKEN1              0x7010
  3462. # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
  3463.  
  3464. #define GEN7_L3CNTLREG1                         0xB01C
  3465. #define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C4FFF8C
  3466. #define  GEN7_L3AGDIS                           (1<<19)
  3467.  
  3468. #define GEN7_L3_CHICKEN_MODE_REGISTER           0xB030
  3469. #define  GEN7_WA_L3_CHICKEN_MODE                                0x20000000
  3470.  
  3471. #define GEN7_L3SQCREG4                          0xb034
  3472. #define  L3SQ_URB_READ_CAM_MATCH_DISABLE        (1<<27)
  3473.  
  3474. /* WaCatErrorRejectionIssue */
  3475. #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          0x9030
  3476. #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB       (1<<11)
  3477.  
  3478. #define HSW_FUSE_STRAP          0x42014
  3479. #define  HSW_CDCLK_LIMIT        (1 << 24)
  3480.  
  3481. /* PCH */
  3482.  
  3483. /* south display engine interrupt: IBX */
  3484. #define SDE_AUDIO_POWER_D       (1 << 27)
  3485. #define SDE_AUDIO_POWER_C       (1 << 26)
  3486. #define SDE_AUDIO_POWER_B       (1 << 25)
  3487. #define SDE_AUDIO_POWER_SHIFT   (25)
  3488. #define SDE_AUDIO_POWER_MASK    (7 << SDE_AUDIO_POWER_SHIFT)
  3489. #define SDE_GMBUS               (1 << 24)
  3490. #define SDE_AUDIO_HDCP_TRANSB   (1 << 23)
  3491. #define SDE_AUDIO_HDCP_TRANSA   (1 << 22)
  3492. #define SDE_AUDIO_HDCP_MASK     (3 << 22)
  3493. #define SDE_AUDIO_TRANSB        (1 << 21)
  3494. #define SDE_AUDIO_TRANSA        (1 << 20)
  3495. #define SDE_AUDIO_TRANS_MASK    (3 << 20)
  3496. #define SDE_POISON              (1 << 19)
  3497. /* 18 reserved */
  3498. #define SDE_FDI_RXB             (1 << 17)
  3499. #define SDE_FDI_RXA             (1 << 16)
  3500. #define SDE_FDI_MASK            (3 << 16)
  3501. #define SDE_AUXD                (1 << 15)
  3502. #define SDE_AUXC                (1 << 14)
  3503. #define SDE_AUXB                (1 << 13)
  3504. #define SDE_AUX_MASK            (7 << 13)
  3505. /* 12 reserved */
  3506. #define SDE_CRT_HOTPLUG         (1 << 11)
  3507. #define SDE_PORTD_HOTPLUG       (1 << 10)
  3508. #define SDE_PORTC_HOTPLUG       (1 << 9)
  3509. #define SDE_PORTB_HOTPLUG       (1 << 8)
  3510. #define SDE_SDVOB_HOTPLUG       (1 << 6)
  3511. #define SDE_HOTPLUG_MASK        (0xf << 8)
  3512. #define SDE_TRANSB_CRC_DONE     (1 << 5)
  3513. #define SDE_TRANSB_CRC_ERR      (1 << 4)
  3514. #define SDE_TRANSB_FIFO_UNDER   (1 << 3)
  3515. #define SDE_TRANSA_CRC_DONE     (1 << 2)
  3516. #define SDE_TRANSA_CRC_ERR      (1 << 1)
  3517. #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
  3518. #define SDE_TRANS_MASK          (0x3f)
  3519.  
  3520. /* south display engine interrupt: CPT/PPT */
  3521. #define SDE_AUDIO_POWER_D_CPT   (1 << 31)
  3522. #define SDE_AUDIO_POWER_C_CPT   (1 << 30)
  3523. #define SDE_AUDIO_POWER_B_CPT   (1 << 29)
  3524. #define SDE_AUDIO_POWER_SHIFT_CPT   29
  3525. #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
  3526. #define SDE_AUXD_CPT            (1 << 27)
  3527. #define SDE_AUXC_CPT            (1 << 26)
  3528. #define SDE_AUXB_CPT            (1 << 25)
  3529. #define SDE_AUX_MASK_CPT        (7 << 25)
  3530. #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
  3531. #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
  3532. #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
  3533. #define SDE_CRT_HOTPLUG_CPT     (1 << 19)
  3534. #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
  3535.                                  SDE_PORTD_HOTPLUG_CPT |        \
  3536.                                  SDE_PORTC_HOTPLUG_CPT |        \
  3537.                                  SDE_PORTB_HOTPLUG_CPT)
  3538. #define SDE_GMBUS_CPT           (1 << 17)
  3539. #define SDE_AUDIO_CP_REQ_C_CPT  (1 << 10)
  3540. #define SDE_AUDIO_CP_CHG_C_CPT  (1 << 9)
  3541. #define SDE_FDI_RXC_CPT         (1 << 8)
  3542. #define SDE_AUDIO_CP_REQ_B_CPT  (1 << 6)
  3543. #define SDE_AUDIO_CP_CHG_B_CPT  (1 << 5)
  3544. #define SDE_FDI_RXB_CPT         (1 << 4)
  3545. #define SDE_AUDIO_CP_REQ_A_CPT  (1 << 2)
  3546. #define SDE_AUDIO_CP_CHG_A_CPT  (1 << 1)
  3547. #define SDE_FDI_RXA_CPT         (1 << 0)
  3548. #define SDE_AUDIO_CP_REQ_CPT    (SDE_AUDIO_CP_REQ_C_CPT | \
  3549.                                  SDE_AUDIO_CP_REQ_B_CPT | \
  3550.                                  SDE_AUDIO_CP_REQ_A_CPT)
  3551. #define SDE_AUDIO_CP_CHG_CPT    (SDE_AUDIO_CP_CHG_C_CPT | \
  3552.                                  SDE_AUDIO_CP_CHG_B_CPT | \
  3553.                                  SDE_AUDIO_CP_CHG_A_CPT)
  3554. #define SDE_FDI_MASK_CPT        (SDE_FDI_RXC_CPT | \
  3555.                                  SDE_FDI_RXB_CPT | \
  3556.                                  SDE_FDI_RXA_CPT)
  3557.  
  3558. #define SDEISR  0xc4000
  3559. #define SDEIMR  0xc4004
  3560. #define SDEIIR  0xc4008
  3561. #define SDEIER  0xc400c
  3562.  
  3563. /* digital port hotplug */
  3564. #define PCH_PORT_HOTPLUG        0xc4030         /* SHOTPLUG_CTL */
  3565. #define PORTD_HOTPLUG_ENABLE            (1 << 20)
  3566. #define PORTD_PULSE_DURATION_2ms        (0)
  3567. #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
  3568. #define PORTD_PULSE_DURATION_6ms        (2 << 18)
  3569. #define PORTD_PULSE_DURATION_100ms      (3 << 18)
  3570. #define PORTD_PULSE_DURATION_MASK       (3 << 18)
  3571. #define PORTD_HOTPLUG_STATUS_MASK       (0x3 << 16)
  3572. #define  PORTD_HOTPLUG_NO_DETECT        (0 << 16)
  3573. #define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
  3574. #define  PORTD_HOTPLUG_LONG_DETECT      (2 << 16)
  3575. #define PORTC_HOTPLUG_ENABLE            (1 << 12)
  3576. #define PORTC_PULSE_DURATION_2ms        (0)
  3577. #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
  3578. #define PORTC_PULSE_DURATION_6ms        (2 << 10)
  3579. #define PORTC_PULSE_DURATION_100ms      (3 << 10)
  3580. #define PORTC_PULSE_DURATION_MASK       (3 << 10)
  3581. #define PORTC_HOTPLUG_STATUS_MASK       (0x3 << 8)
  3582. #define  PORTC_HOTPLUG_NO_DETECT        (0 << 8)
  3583. #define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
  3584. #define  PORTC_HOTPLUG_LONG_DETECT      (2 << 8)
  3585. #define PORTB_HOTPLUG_ENABLE            (1 << 4)
  3586. #define PORTB_PULSE_DURATION_2ms        (0)
  3587. #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
  3588. #define PORTB_PULSE_DURATION_6ms        (2 << 2)
  3589. #define PORTB_PULSE_DURATION_100ms      (3 << 2)
  3590. #define PORTB_PULSE_DURATION_MASK       (3 << 2)
  3591. #define PORTB_HOTPLUG_STATUS_MASK       (0x3 << 0)
  3592. #define  PORTB_HOTPLUG_NO_DETECT        (0 << 0)
  3593. #define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
  3594. #define  PORTB_HOTPLUG_LONG_DETECT      (2 << 0)
  3595.  
  3596. #define PCH_GPIOA               0xc5010
  3597. #define PCH_GPIOB               0xc5014
  3598. #define PCH_GPIOC               0xc5018
  3599. #define PCH_GPIOD               0xc501c
  3600. #define PCH_GPIOE               0xc5020
  3601. #define PCH_GPIOF               0xc5024
  3602.  
  3603. #define PCH_GMBUS0              0xc5100
  3604. #define PCH_GMBUS1              0xc5104
  3605. #define PCH_GMBUS2              0xc5108
  3606. #define PCH_GMBUS3              0xc510c
  3607. #define PCH_GMBUS4              0xc5110
  3608. #define PCH_GMBUS5              0xc5120
  3609.  
  3610. #define _PCH_DPLL_A              0xc6014
  3611. #define _PCH_DPLL_B              0xc6018
  3612. #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
  3613.  
  3614. #define _PCH_FPA0                0xc6040
  3615. #define  FP_CB_TUNE             (0x3<<22)
  3616. #define _PCH_FPA1                0xc6044
  3617. #define _PCH_FPB0                0xc6048
  3618. #define _PCH_FPB1                0xc604c
  3619. #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
  3620. #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
  3621.  
  3622. #define PCH_DPLL_TEST           0xc606c
  3623.  
  3624. #define PCH_DREF_CONTROL        0xC6200
  3625. #define  DREF_CONTROL_MASK      0x7fc3
  3626. #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
  3627. #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
  3628. #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
  3629. #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3<<13)
  3630. #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
  3631. #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
  3632. #define  DREF_SSC_SOURCE_MASK                   (3<<11)
  3633. #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
  3634. #define  DREF_NONSPREAD_CK505_ENABLE            (1<<9)
  3635. #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
  3636. #define  DREF_NONSPREAD_SOURCE_MASK             (3<<9)
  3637. #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
  3638. #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
  3639. #define  DREF_SUPERSPREAD_SOURCE_MASK           (3<<7)
  3640. #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
  3641. #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
  3642. #define  DREF_SSC1_DISABLE                      (0<<1)
  3643. #define  DREF_SSC1_ENABLE                       (1<<1)
  3644. #define  DREF_SSC4_DISABLE                      (0)
  3645. #define  DREF_SSC4_ENABLE                       (1)
  3646.  
  3647. #define PCH_RAWCLK_FREQ         0xc6204
  3648. #define  FDL_TP1_TIMER_SHIFT    12
  3649. #define  FDL_TP1_TIMER_MASK     (3<<12)
  3650. #define  FDL_TP2_TIMER_SHIFT    10
  3651. #define  FDL_TP2_TIMER_MASK     (3<<10)
  3652. #define  RAWCLK_FREQ_MASK       0x3ff
  3653.  
  3654. #define PCH_DPLL_TMR_CFG        0xc6208
  3655.  
  3656. #define PCH_SSC4_PARMS          0xc6210
  3657. #define PCH_SSC4_AUX_PARMS      0xc6214
  3658.  
  3659. #define PCH_DPLL_SEL            0xc7000
  3660. #define  TRANSA_DPLL_ENABLE     (1<<3)
  3661. #define  TRANSA_DPLLB_SEL       (1<<0)
  3662. #define  TRANSA_DPLLA_SEL       0
  3663. #define  TRANSB_DPLL_ENABLE     (1<<7)
  3664. #define  TRANSB_DPLLB_SEL       (1<<4)
  3665. #define  TRANSB_DPLLA_SEL       (0)
  3666. #define  TRANSC_DPLL_ENABLE     (1<<11)
  3667. #define  TRANSC_DPLLB_SEL       (1<<8)
  3668. #define  TRANSC_DPLLA_SEL       (0)
  3669.  
  3670. /* transcoder */
  3671.  
  3672. #define _TRANS_HTOTAL_A          0xe0000
  3673. #define  TRANS_HTOTAL_SHIFT     16
  3674. #define  TRANS_HACTIVE_SHIFT    0
  3675. #define _TRANS_HBLANK_A          0xe0004
  3676. #define  TRANS_HBLANK_END_SHIFT 16
  3677. #define  TRANS_HBLANK_START_SHIFT 0
  3678. #define _TRANS_HSYNC_A           0xe0008
  3679. #define  TRANS_HSYNC_END_SHIFT  16
  3680. #define  TRANS_HSYNC_START_SHIFT 0
  3681. #define _TRANS_VTOTAL_A          0xe000c
  3682. #define  TRANS_VTOTAL_SHIFT     16
  3683. #define  TRANS_VACTIVE_SHIFT    0
  3684. #define _TRANS_VBLANK_A          0xe0010
  3685. #define  TRANS_VBLANK_END_SHIFT 16
  3686. #define  TRANS_VBLANK_START_SHIFT 0
  3687. #define _TRANS_VSYNC_A           0xe0014
  3688. #define  TRANS_VSYNC_END_SHIFT  16
  3689. #define  TRANS_VSYNC_START_SHIFT 0
  3690. #define _TRANS_VSYNCSHIFT_A     0xe0028
  3691.  
  3692. #define _TRANSA_DATA_M1          0xe0030
  3693. #define _TRANSA_DATA_N1          0xe0034
  3694. #define _TRANSA_DATA_M2          0xe0038
  3695. #define _TRANSA_DATA_N2          0xe003c
  3696. #define _TRANSA_DP_LINK_M1       0xe0040
  3697. #define _TRANSA_DP_LINK_N1       0xe0044
  3698. #define _TRANSA_DP_LINK_M2       0xe0048
  3699. #define _TRANSA_DP_LINK_N2       0xe004c
  3700.  
  3701. /* Per-transcoder DIP controls */
  3702.  
  3703. #define _VIDEO_DIP_CTL_A         0xe0200
  3704. #define _VIDEO_DIP_DATA_A        0xe0208
  3705. #define _VIDEO_DIP_GCP_A         0xe0210
  3706.  
  3707. #define _VIDEO_DIP_CTL_B         0xe1200
  3708. #define _VIDEO_DIP_DATA_B        0xe1208
  3709. #define _VIDEO_DIP_GCP_B         0xe1210
  3710.  
  3711. #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
  3712. #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
  3713. #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
  3714.  
  3715. #define VLV_VIDEO_DIP_CTL_A             (VLV_DISPLAY_BASE + 0x60200)
  3716. #define VLV_VIDEO_DIP_DATA_A            (VLV_DISPLAY_BASE + 0x60208)
  3717. #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A    (VLV_DISPLAY_BASE + 0x60210)
  3718.  
  3719. #define VLV_VIDEO_DIP_CTL_B             (VLV_DISPLAY_BASE + 0x61170)
  3720. #define VLV_VIDEO_DIP_DATA_B            (VLV_DISPLAY_BASE + 0x61174)
  3721. #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B    (VLV_DISPLAY_BASE + 0x61178)
  3722.  
  3723. #define VLV_TVIDEO_DIP_CTL(pipe) \
  3724.          _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
  3725. #define VLV_TVIDEO_DIP_DATA(pipe) \
  3726.          _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
  3727. #define VLV_TVIDEO_DIP_GCP(pipe) \
  3728.         _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
  3729.  
  3730. /* Haswell DIP controls */
  3731. #define HSW_VIDEO_DIP_CTL_A             0x60200
  3732. #define HSW_VIDEO_DIP_AVI_DATA_A        0x60220
  3733. #define HSW_VIDEO_DIP_VS_DATA_A         0x60260
  3734. #define HSW_VIDEO_DIP_SPD_DATA_A        0x602A0
  3735. #define HSW_VIDEO_DIP_GMP_DATA_A        0x602E0
  3736. #define HSW_VIDEO_DIP_VSC_DATA_A        0x60320
  3737. #define HSW_VIDEO_DIP_AVI_ECC_A         0x60240
  3738. #define HSW_VIDEO_DIP_VS_ECC_A          0x60280
  3739. #define HSW_VIDEO_DIP_SPD_ECC_A         0x602C0
  3740. #define HSW_VIDEO_DIP_GMP_ECC_A         0x60300
  3741. #define HSW_VIDEO_DIP_VSC_ECC_A         0x60344
  3742. #define HSW_VIDEO_DIP_GCP_A             0x60210
  3743.  
  3744. #define HSW_VIDEO_DIP_CTL_B             0x61200
  3745. #define HSW_VIDEO_DIP_AVI_DATA_B        0x61220
  3746. #define HSW_VIDEO_DIP_VS_DATA_B         0x61260
  3747. #define HSW_VIDEO_DIP_SPD_DATA_B        0x612A0
  3748. #define HSW_VIDEO_DIP_GMP_DATA_B        0x612E0
  3749. #define HSW_VIDEO_DIP_VSC_DATA_B        0x61320
  3750. #define HSW_VIDEO_DIP_BVI_ECC_B         0x61240
  3751. #define HSW_VIDEO_DIP_VS_ECC_B          0x61280
  3752. #define HSW_VIDEO_DIP_SPD_ECC_B         0x612C0
  3753. #define HSW_VIDEO_DIP_GMP_ECC_B         0x61300
  3754. #define HSW_VIDEO_DIP_VSC_ECC_B         0x61344
  3755. #define HSW_VIDEO_DIP_GCP_B             0x61210
  3756.  
  3757. #define HSW_TVIDEO_DIP_CTL(pipe) \
  3758.          _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
  3759. #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
  3760.          _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
  3761. #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
  3762.          _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
  3763. #define HSW_TVIDEO_DIP_GCP(pipe) \
  3764.         _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
  3765.  
  3766. #define _TRANS_HTOTAL_B          0xe1000
  3767. #define _TRANS_HBLANK_B          0xe1004
  3768. #define _TRANS_HSYNC_B           0xe1008
  3769. #define _TRANS_VTOTAL_B          0xe100c
  3770. #define _TRANS_VBLANK_B          0xe1010
  3771. #define _TRANS_VSYNC_B           0xe1014
  3772. #define _TRANS_VSYNCSHIFT_B      0xe1028
  3773.  
  3774. #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
  3775. #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
  3776. #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
  3777. #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
  3778. #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
  3779. #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
  3780. #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
  3781.                                      _TRANS_VSYNCSHIFT_B)
  3782.  
  3783. #define _TRANSB_DATA_M1          0xe1030
  3784. #define _TRANSB_DATA_N1          0xe1034
  3785. #define _TRANSB_DATA_M2          0xe1038
  3786. #define _TRANSB_DATA_N2          0xe103c
  3787. #define _TRANSB_DP_LINK_M1       0xe1040
  3788. #define _TRANSB_DP_LINK_N1       0xe1044
  3789. #define _TRANSB_DP_LINK_M2       0xe1048
  3790. #define _TRANSB_DP_LINK_N2       0xe104c
  3791.  
  3792. #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
  3793. #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
  3794. #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
  3795. #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
  3796. #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
  3797. #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
  3798. #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
  3799. #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
  3800.  
  3801. #define _TRANSACONF              0xf0008
  3802. #define _TRANSBCONF              0xf1008
  3803. #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
  3804. #define  TRANS_DISABLE          (0<<31)
  3805. #define  TRANS_ENABLE           (1<<31)
  3806. #define  TRANS_STATE_MASK       (1<<30)
  3807. #define  TRANS_STATE_DISABLE    (0<<30)
  3808. #define  TRANS_STATE_ENABLE     (1<<30)
  3809. #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
  3810. #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
  3811. #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
  3812. #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
  3813. #define  TRANS_INTERLACE_MASK   (7<<21)
  3814. #define  TRANS_PROGRESSIVE      (0<<21)
  3815. #define  TRANS_INTERLACED       (3<<21)
  3816. #define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
  3817. #define  TRANS_8BPC             (0<<5)
  3818. #define  TRANS_10BPC            (1<<5)
  3819. #define  TRANS_6BPC             (2<<5)
  3820. #define  TRANS_12BPC            (3<<5)
  3821.  
  3822. #define _TRANSA_CHICKEN1         0xf0060
  3823. #define _TRANSB_CHICKEN1         0xf1060
  3824. #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
  3825. #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE      (1<<4)
  3826. #define _TRANSA_CHICKEN2         0xf0064
  3827. #define _TRANSB_CHICKEN2         0xf1064
  3828. #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
  3829. #define  TRANS_CHICKEN2_TIMING_OVERRIDE         (1<<31)
  3830.  
  3831.  
  3832. #define SOUTH_CHICKEN1          0xc2000
  3833. #define  FDIA_PHASE_SYNC_SHIFT_OVR      19
  3834. #define  FDIA_PHASE_SYNC_SHIFT_EN       18
  3835. #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
  3836. #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
  3837. #define  FDI_BC_BIFURCATION_SELECT      (1 << 12)
  3838. #define SOUTH_CHICKEN2          0xc2004
  3839. #define  FDI_MPHY_IOSFSB_RESET_STATUS   (1<<13)
  3840. #define  FDI_MPHY_IOSFSB_RESET_CTL      (1<<12)
  3841. #define  DPLS_EDP_PPS_FIX_DIS   (1<<0)
  3842.  
  3843. #define _FDI_RXA_CHICKEN         0xc200c
  3844. #define _FDI_RXB_CHICKEN         0xc2010
  3845. #define  FDI_RX_PHASE_SYNC_POINTER_OVR  (1<<1)
  3846. #define  FDI_RX_PHASE_SYNC_POINTER_EN   (1<<0)
  3847. #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
  3848.  
  3849. #define SOUTH_DSPCLK_GATE_D     0xc2020
  3850. #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
  3851. #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
  3852.  
  3853. /* CPU: FDI_TX */
  3854. #define _FDI_TXA_CTL             0x60100
  3855. #define _FDI_TXB_CTL             0x61100
  3856. #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
  3857. #define  FDI_TX_DISABLE         (0<<31)
  3858. #define  FDI_TX_ENABLE          (1<<31)
  3859. #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
  3860. #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
  3861. #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
  3862. #define  FDI_LINK_TRAIN_NONE            (3<<28)
  3863. #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
  3864. #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
  3865. #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
  3866. #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
  3867. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
  3868. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
  3869. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
  3870. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
  3871. /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
  3872.    SNB has different settings. */
  3873. /* SNB A-stepping */
  3874. #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
  3875. #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
  3876. #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
  3877. #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
  3878. /* SNB B-stepping */
  3879. #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B         (0x0<<22)
  3880. #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B         (0x3a<<22)
  3881. #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B       (0x39<<22)
  3882. #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B         (0x38<<22)
  3883. #define  FDI_LINK_TRAIN_VOL_EMP_MASK            (0x3f<<22)
  3884. #define  FDI_DP_PORT_WIDTH_X1           (0<<19)
  3885. #define  FDI_DP_PORT_WIDTH_X2           (1<<19)
  3886. #define  FDI_DP_PORT_WIDTH_X3           (2<<19)
  3887. #define  FDI_DP_PORT_WIDTH_X4           (3<<19)
  3888. #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
  3889. /* Ironlake: hardwired to 1 */
  3890. #define  FDI_TX_PLL_ENABLE              (1<<14)
  3891.  
  3892. /* Ivybridge has different bits for lolz */
  3893. #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
  3894. #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
  3895. #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
  3896. #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
  3897.  
  3898. /* both Tx and Rx */
  3899. #define  FDI_COMPOSITE_SYNC             (1<<11)
  3900. #define  FDI_LINK_TRAIN_AUTO            (1<<10)
  3901. #define  FDI_SCRAMBLING_ENABLE          (0<<7)
  3902. #define  FDI_SCRAMBLING_DISABLE         (1<<7)
  3903.  
  3904. /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
  3905. #define _FDI_RXA_CTL             0xf000c
  3906. #define _FDI_RXB_CTL             0xf100c
  3907. #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
  3908. #define  FDI_RX_ENABLE          (1<<31)
  3909. /* train, dp width same as FDI_TX */
  3910. #define  FDI_FS_ERRC_ENABLE             (1<<27)
  3911. #define  FDI_FE_ERRC_ENABLE             (1<<26)
  3912. #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
  3913. #define  FDI_RX_POLARITY_REVERSED_LPT   (1<<16)
  3914. #define  FDI_8BPC                       (0<<16)
  3915. #define  FDI_10BPC                      (1<<16)
  3916. #define  FDI_6BPC                       (2<<16)
  3917. #define  FDI_12BPC                      (3<<16)
  3918. #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
  3919. #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
  3920. #define  FDI_RX_PLL_ENABLE              (1<<13)
  3921. #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
  3922. #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
  3923. #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
  3924. #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
  3925. #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
  3926. #define  FDI_PCDCLK                     (1<<4)
  3927. /* CPT */
  3928. #define  FDI_AUTO_TRAINING                      (1<<10)
  3929. #define  FDI_LINK_TRAIN_PATTERN_1_CPT           (0<<8)
  3930. #define  FDI_LINK_TRAIN_PATTERN_2_CPT           (1<<8)
  3931. #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT        (2<<8)
  3932. #define  FDI_LINK_TRAIN_NORMAL_CPT              (3<<8)
  3933. #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT        (3<<8)
  3934. /* LPT */
  3935. #define  FDI_PORT_WIDTH_2X_LPT                  (1<<19)
  3936. #define  FDI_PORT_WIDTH_1X_LPT                  (0<<19)
  3937.  
  3938. #define _FDI_RXA_MISC            0xf0010
  3939. #define _FDI_RXB_MISC            0xf1010
  3940. #define  FDI_RX_PWRDN_LANE1_MASK        (3<<26)
  3941. #define  FDI_RX_PWRDN_LANE1_VAL(x)      ((x)<<26)
  3942. #define  FDI_RX_PWRDN_LANE0_MASK        (3<<24)
  3943. #define  FDI_RX_PWRDN_LANE0_VAL(x)      ((x)<<24)
  3944. #define  FDI_RX_TP1_TO_TP2_48           (2<<20)
  3945. #define  FDI_RX_TP1_TO_TP2_64           (3<<20)
  3946. #define  FDI_RX_FDI_DELAY_90            (0x90<<0)
  3947. #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
  3948.  
  3949. #define _FDI_RXA_TUSIZE1         0xf0030
  3950. #define _FDI_RXA_TUSIZE2         0xf0038
  3951. #define _FDI_RXB_TUSIZE1         0xf1030
  3952. #define _FDI_RXB_TUSIZE2         0xf1038
  3953. #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
  3954. #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
  3955.  
  3956. /* FDI_RX interrupt register format */
  3957. #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
  3958. #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
  3959. #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
  3960. #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
  3961. #define FDI_RX_FS_CODE_ERR              (1<<6)
  3962. #define FDI_RX_FE_CODE_ERR              (1<<5)
  3963. #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
  3964. #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
  3965. #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
  3966. #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
  3967. #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
  3968.  
  3969. #define _FDI_RXA_IIR             0xf0014
  3970. #define _FDI_RXA_IMR             0xf0018
  3971. #define _FDI_RXB_IIR             0xf1014
  3972. #define _FDI_RXB_IMR             0xf1018
  3973. #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
  3974. #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
  3975.  
  3976. #define FDI_PLL_CTL_1           0xfe000
  3977. #define FDI_PLL_CTL_2           0xfe004
  3978.  
  3979. /* or SDVOB */
  3980. #define HDMIB   0xe1140
  3981. #define  PORT_ENABLE    (1 << 31)
  3982. #define  TRANSCODER(pipe)       ((pipe) << 30)
  3983. #define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
  3984. #define  TRANSCODER_MASK   (1 << 30)
  3985. #define  TRANSCODER_MASK_CPT    (3 << 29)
  3986. #define  COLOR_FORMAT_8bpc      (0)
  3987. #define  COLOR_FORMAT_12bpc     (3 << 26)
  3988. #define  SDVOB_HOTPLUG_ENABLE   (1 << 23)
  3989. #define  SDVO_ENCODING          (0)
  3990. #define  TMDS_ENCODING          (2 << 10)
  3991. #define  NULL_PACKET_VSYNC_ENABLE       (1 << 9)
  3992. /* CPT */
  3993. #define  HDMI_MODE_SELECT       (1 << 9)
  3994. #define  DVI_MODE_SELECT        (0)
  3995. #define  SDVOB_BORDER_ENABLE    (1 << 7)
  3996. #define  AUDIO_ENABLE           (1 << 6)
  3997. #define  VSYNC_ACTIVE_HIGH      (1 << 4)
  3998. #define  HSYNC_ACTIVE_HIGH      (1 << 3)
  3999. #define  PORT_DETECTED          (1 << 2)
  4000.  
  4001. /* PCH SDVOB multiplex with HDMIB */
  4002. #define PCH_SDVOB       HDMIB
  4003.  
  4004. #define HDMIC   0xe1150
  4005. #define HDMID   0xe1160
  4006.  
  4007. #define PCH_LVDS        0xe1180
  4008. #define  LVDS_DETECTED  (1 << 1)
  4009.  
  4010. /* vlv has 2 sets of panel control regs. */
  4011. #define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
  4012. #define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
  4013. #define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
  4014. #define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
  4015. #define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
  4016.  
  4017. #define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
  4018. #define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
  4019. #define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
  4020. #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
  4021. #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
  4022.  
  4023. #define PCH_PP_STATUS           0xc7200
  4024. #define PCH_PP_CONTROL          0xc7204
  4025. #define  PANEL_UNLOCK_REGS      (0xabcd << 16)
  4026. #define  PANEL_UNLOCK_MASK      (0xffff << 16)
  4027. #define  EDP_FORCE_VDD          (1 << 3)
  4028. #define  EDP_BLC_ENABLE         (1 << 2)
  4029. #define  PANEL_POWER_RESET      (1 << 1)
  4030. #define  PANEL_POWER_OFF        (0 << 0)
  4031. #define  PANEL_POWER_ON         (1 << 0)
  4032. #define PCH_PP_ON_DELAYS        0xc7208
  4033. #define  PANEL_PORT_SELECT_MASK (3 << 30)
  4034. #define  PANEL_PORT_SELECT_LVDS (0 << 30)
  4035. #define  PANEL_PORT_SELECT_DPA  (1 << 30)
  4036. #define  EDP_PANEL              (1 << 30)
  4037. #define  PANEL_PORT_SELECT_DPC  (2 << 30)
  4038. #define  PANEL_PORT_SELECT_DPD  (3 << 30)
  4039. #define  PANEL_POWER_UP_DELAY_MASK      (0x1fff0000)
  4040. #define  PANEL_POWER_UP_DELAY_SHIFT     16
  4041. #define  PANEL_LIGHT_ON_DELAY_MASK      (0x1fff)
  4042. #define  PANEL_LIGHT_ON_DELAY_SHIFT     0
  4043.  
  4044. #define PCH_PP_OFF_DELAYS       0xc720c
  4045. #define  PANEL_POWER_PORT_SELECT_MASK   (0x3 << 30)
  4046. #define  PANEL_POWER_PORT_LVDS          (0 << 30)
  4047. #define  PANEL_POWER_PORT_DP_A          (1 << 30)
  4048. #define  PANEL_POWER_PORT_DP_C          (2 << 30)
  4049. #define  PANEL_POWER_PORT_DP_D          (3 << 30)
  4050. #define  PANEL_POWER_DOWN_DELAY_MASK    (0x1fff0000)
  4051. #define  PANEL_POWER_DOWN_DELAY_SHIFT   16
  4052. #define  PANEL_LIGHT_OFF_DELAY_MASK     (0x1fff)
  4053. #define  PANEL_LIGHT_OFF_DELAY_SHIFT    0
  4054.  
  4055. #define PCH_PP_DIVISOR          0xc7210
  4056. #define  PP_REFERENCE_DIVIDER_MASK      (0xffffff00)
  4057. #define  PP_REFERENCE_DIVIDER_SHIFT     8
  4058. #define  PANEL_POWER_CYCLE_DELAY_MASK   (0x1f)
  4059. #define  PANEL_POWER_CYCLE_DELAY_SHIFT  0
  4060.  
  4061. #define PCH_DP_B                0xe4100
  4062. #define PCH_DPB_AUX_CH_CTL      0xe4110
  4063. #define PCH_DPB_AUX_CH_DATA1    0xe4114
  4064. #define PCH_DPB_AUX_CH_DATA2    0xe4118
  4065. #define PCH_DPB_AUX_CH_DATA3    0xe411c
  4066. #define PCH_DPB_AUX_CH_DATA4    0xe4120
  4067. #define PCH_DPB_AUX_CH_DATA5    0xe4124
  4068.  
  4069. #define PCH_DP_C                0xe4200
  4070. #define PCH_DPC_AUX_CH_CTL      0xe4210
  4071. #define PCH_DPC_AUX_CH_DATA1    0xe4214
  4072. #define PCH_DPC_AUX_CH_DATA2    0xe4218
  4073. #define PCH_DPC_AUX_CH_DATA3    0xe421c
  4074. #define PCH_DPC_AUX_CH_DATA4    0xe4220
  4075. #define PCH_DPC_AUX_CH_DATA5    0xe4224
  4076.  
  4077. #define PCH_DP_D                0xe4300
  4078. #define PCH_DPD_AUX_CH_CTL      0xe4310
  4079. #define PCH_DPD_AUX_CH_DATA1    0xe4314
  4080. #define PCH_DPD_AUX_CH_DATA2    0xe4318
  4081. #define PCH_DPD_AUX_CH_DATA3    0xe431c
  4082. #define PCH_DPD_AUX_CH_DATA4    0xe4320
  4083. #define PCH_DPD_AUX_CH_DATA5    0xe4324
  4084.  
  4085. /* CPT */
  4086. #define  PORT_TRANS_A_SEL_CPT   0
  4087. #define  PORT_TRANS_B_SEL_CPT   (1<<29)
  4088. #define  PORT_TRANS_C_SEL_CPT   (2<<29)
  4089. #define  PORT_TRANS_SEL_MASK    (3<<29)
  4090. #define  PORT_TRANS_SEL_CPT(pipe)       ((pipe) << 29)
  4091. #define  PORT_TO_PIPE(val)      (((val) & (1<<30)) >> 30)
  4092. #define  PORT_TO_PIPE_CPT(val)  (((val) & PORT_TRANS_SEL_MASK) >> 29)
  4093.  
  4094. #define TRANS_DP_CTL_A          0xe0300
  4095. #define TRANS_DP_CTL_B          0xe1300
  4096. #define TRANS_DP_CTL_C          0xe2300
  4097. #define TRANS_DP_CTL(pipe)      _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
  4098. #define  TRANS_DP_OUTPUT_ENABLE (1<<31)
  4099. #define  TRANS_DP_PORT_SEL_B    (0<<29)
  4100. #define  TRANS_DP_PORT_SEL_C    (1<<29)
  4101. #define  TRANS_DP_PORT_SEL_D    (2<<29)
  4102. #define  TRANS_DP_PORT_SEL_NONE (3<<29)
  4103. #define  TRANS_DP_PORT_SEL_MASK (3<<29)
  4104. #define  TRANS_DP_AUDIO_ONLY    (1<<26)
  4105. #define  TRANS_DP_ENH_FRAMING   (1<<18)
  4106. #define  TRANS_DP_8BPC          (0<<9)
  4107. #define  TRANS_DP_10BPC         (1<<9)
  4108. #define  TRANS_DP_6BPC          (2<<9)
  4109. #define  TRANS_DP_12BPC         (3<<9)
  4110. #define  TRANS_DP_BPC_MASK      (3<<9)
  4111. #define  TRANS_DP_VSYNC_ACTIVE_HIGH     (1<<4)
  4112. #define  TRANS_DP_VSYNC_ACTIVE_LOW      0
  4113. #define  TRANS_DP_HSYNC_ACTIVE_HIGH     (1<<3)
  4114. #define  TRANS_DP_HSYNC_ACTIVE_LOW      0
  4115. #define  TRANS_DP_SYNC_MASK     (3<<3)
  4116.  
  4117. /* SNB eDP training params */
  4118. /* SNB A-stepping */
  4119. #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
  4120. #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
  4121. #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
  4122. #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
  4123. /* SNB B-stepping */
  4124. #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B     (0x0<<22)
  4125. #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B       (0x1<<22)
  4126. #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B     (0x3a<<22)
  4127. #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B   (0x39<<22)
  4128. #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B    (0x38<<22)
  4129. #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB        (0x3f<<22)
  4130.  
  4131. /* IVB */
  4132. #define EDP_LINK_TRAIN_400MV_0DB_IVB            (0x24 <<22)
  4133. #define EDP_LINK_TRAIN_400MV_3_5DB_IVB          (0x2a <<22)
  4134. #define EDP_LINK_TRAIN_400MV_6DB_IVB            (0x2f <<22)
  4135. #define EDP_LINK_TRAIN_600MV_0DB_IVB            (0x30 <<22)
  4136. #define EDP_LINK_TRAIN_600MV_3_5DB_IVB          (0x36 <<22)
  4137. #define EDP_LINK_TRAIN_800MV_0DB_IVB            (0x38 <<22)
  4138. #define EDP_LINK_TRAIN_800MV_3_5DB_IVB          (0x33 <<22)
  4139.  
  4140. /* legacy values */
  4141. #define EDP_LINK_TRAIN_500MV_0DB_IVB            (0x00 <<22)
  4142. #define EDP_LINK_TRAIN_1000MV_0DB_IVB           (0x20 <<22)
  4143. #define EDP_LINK_TRAIN_500MV_3_5DB_IVB          (0x02 <<22)
  4144. #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB         (0x22 <<22)
  4145. #define EDP_LINK_TRAIN_1000MV_6DB_IVB           (0x23 <<22)
  4146.  
  4147. #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB        (0x3f<<22)
  4148.  
  4149. #define  FORCEWAKE                              0xA18C
  4150. #define  FORCEWAKE_VLV                          0x1300b0
  4151. #define  FORCEWAKE_ACK_VLV                      0x1300b4
  4152. #define  FORCEWAKE_ACK_HSW                      0x130044
  4153. #define  FORCEWAKE_ACK                          0x130090
  4154. #define  FORCEWAKE_MT                           0xa188 /* multi-threaded */
  4155. #define   FORCEWAKE_KERNEL                      0x1
  4156. #define   FORCEWAKE_USER                        0x2
  4157. #define  FORCEWAKE_MT_ACK                       0x130040
  4158. #define  ECOBUS                                 0xa180
  4159. #define    FORCEWAKE_MT_ENABLE                  (1<<5)
  4160.  
  4161. #define  GTFIFODBG                              0x120000
  4162. #define    GT_FIFO_CPU_ERROR_MASK               7
  4163. #define    GT_FIFO_OVFERR                       (1<<2)
  4164. #define    GT_FIFO_IAWRERR                      (1<<1)
  4165. #define    GT_FIFO_IARDERR                      (1<<0)
  4166.  
  4167. #define  GT_FIFO_FREE_ENTRIES                   0x120008
  4168. #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
  4169.  
  4170. #define GEN6_UCGCTL1                            0x9400
  4171. # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE                (1 << 5)
  4172. # define GEN6_CSUNIT_CLOCK_GATE_DISABLE                 (1 << 7)
  4173.  
  4174. #define GEN6_UCGCTL2                            0x9404
  4175. # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE                (1 << 30)
  4176. # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE                (1 << 22)
  4177. # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE                (1 << 13)
  4178. # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
  4179. # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE                (1 << 11)
  4180.  
  4181. #define GEN7_UCGCTL4                            0x940c
  4182. #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE       (1<<25)
  4183.  
  4184. #define GEN6_RPNSWREQ                           0xA008
  4185. #define   GEN6_TURBO_DISABLE                    (1<<31)
  4186. #define   GEN6_FREQUENCY(x)                     ((x)<<25)
  4187. #define   GEN6_OFFSET(x)                        ((x)<<19)
  4188. #define   GEN6_AGGRESSIVE_TURBO                 (0<<15)
  4189. #define GEN6_RC_VIDEO_FREQ                      0xA00C
  4190. #define GEN6_RC_CONTROL                         0xA090
  4191. #define   GEN6_RC_CTL_RC6pp_ENABLE              (1<<16)
  4192. #define   GEN6_RC_CTL_RC6p_ENABLE               (1<<17)
  4193. #define   GEN6_RC_CTL_RC6_ENABLE                (1<<18)
  4194. #define   GEN6_RC_CTL_RC1e_ENABLE               (1<<20)
  4195. #define   GEN6_RC_CTL_RC7_ENABLE                (1<<22)
  4196. #define   GEN6_RC_CTL_EI_MODE(x)                ((x)<<27)
  4197. #define   GEN6_RC_CTL_HW_ENABLE                 (1<<31)
  4198. #define GEN6_RP_DOWN_TIMEOUT                    0xA010
  4199. #define GEN6_RP_INTERRUPT_LIMITS                0xA014
  4200. #define GEN6_RPSTAT1                            0xA01C
  4201. #define   GEN6_CAGF_SHIFT                       8
  4202. #define   HSW_CAGF_SHIFT                        7
  4203. #define   GEN6_CAGF_MASK                        (0x7f << GEN6_CAGF_SHIFT)
  4204. #define   HSW_CAGF_MASK                         (0x7f << HSW_CAGF_SHIFT)
  4205. #define GEN6_RP_CONTROL                         0xA024
  4206. #define   GEN6_RP_MEDIA_TURBO                   (1<<11)
  4207. #define   GEN6_RP_MEDIA_MODE_MASK               (3<<9)
  4208. #define   GEN6_RP_MEDIA_HW_TURBO_MODE           (3<<9)
  4209. #define   GEN6_RP_MEDIA_HW_NORMAL_MODE          (2<<9)
  4210. #define   GEN6_RP_MEDIA_HW_MODE                 (1<<9)
  4211. #define   GEN6_RP_MEDIA_SW_MODE                 (0<<9)
  4212. #define   GEN6_RP_MEDIA_IS_GFX                  (1<<8)
  4213. #define   GEN6_RP_ENABLE                        (1<<7)
  4214. #define   GEN6_RP_UP_IDLE_MIN                   (0x1<<3)
  4215. #define   GEN6_RP_UP_BUSY_AVG                   (0x2<<3)
  4216. #define   GEN6_RP_UP_BUSY_CONT                  (0x4<<3)
  4217. #define   GEN7_RP_DOWN_IDLE_AVG                 (0x2<<0)
  4218. #define   GEN6_RP_DOWN_IDLE_CONT                (0x1<<0)
  4219. #define GEN6_RP_UP_THRESHOLD                    0xA02C
  4220. #define GEN6_RP_DOWN_THRESHOLD                  0xA030
  4221. #define GEN6_RP_CUR_UP_EI                       0xA050
  4222. #define   GEN6_CURICONT_MASK                    0xffffff
  4223. #define GEN6_RP_CUR_UP                          0xA054
  4224. #define   GEN6_CURBSYTAVG_MASK                  0xffffff
  4225. #define GEN6_RP_PREV_UP                         0xA058
  4226. #define GEN6_RP_CUR_DOWN_EI                     0xA05C
  4227. #define   GEN6_CURIAVG_MASK                     0xffffff
  4228. #define GEN6_RP_CUR_DOWN                        0xA060
  4229. #define GEN6_RP_PREV_DOWN                       0xA064
  4230. #define GEN6_RP_UP_EI                           0xA068
  4231. #define GEN6_RP_DOWN_EI                         0xA06C
  4232. #define GEN6_RP_IDLE_HYSTERSIS                  0xA070
  4233. #define GEN6_RC_STATE                           0xA094
  4234. #define GEN6_RC1_WAKE_RATE_LIMIT                0xA098
  4235. #define GEN6_RC6_WAKE_RATE_LIMIT                0xA09C
  4236. #define GEN6_RC6pp_WAKE_RATE_LIMIT              0xA0A0
  4237. #define GEN6_RC_EVALUATION_INTERVAL             0xA0A8
  4238. #define GEN6_RC_IDLE_HYSTERSIS                  0xA0AC
  4239. #define GEN6_RC_SLEEP                           0xA0B0
  4240. #define GEN6_RC1e_THRESHOLD                     0xA0B4
  4241. #define GEN6_RC6_THRESHOLD                      0xA0B8
  4242. #define GEN6_RC6p_THRESHOLD                     0xA0BC
  4243. #define GEN6_RC6pp_THRESHOLD                    0xA0C0
  4244. #define GEN6_PMINTRMSK                          0xA168
  4245.  
  4246. #define GEN6_PMISR                              0x44020
  4247. #define GEN6_PMIMR                              0x44024 /* rps_lock */
  4248. #define GEN6_PMIIR                              0x44028
  4249. #define GEN6_PMIER                              0x4402C
  4250. #define  GEN6_PM_MBOX_EVENT                     (1<<25)
  4251. #define  GEN6_PM_THERMAL_EVENT                  (1<<24)
  4252. #define  GEN6_PM_RP_DOWN_TIMEOUT                (1<<6)
  4253. #define  GEN6_PM_RP_UP_THRESHOLD                (1<<5)
  4254. #define  GEN6_PM_RP_DOWN_THRESHOLD              (1<<4)
  4255. #define  GEN6_PM_RP_UP_EI_EXPIRED               (1<<2)
  4256. #define  GEN6_PM_RP_DOWN_EI_EXPIRED             (1<<1)
  4257. #define  GEN6_PM_DEFERRED_EVENTS                (GEN6_PM_RP_UP_THRESHOLD | \
  4258.                                                  GEN6_PM_RP_DOWN_THRESHOLD | \
  4259.                                                  GEN6_PM_RP_DOWN_TIMEOUT)
  4260.  
  4261. #define GEN6_GT_GFX_RC6_LOCKED                  0x138104
  4262. #define GEN6_GT_GFX_RC6                         0x138108
  4263. #define GEN6_GT_GFX_RC6p                        0x13810C
  4264. #define GEN6_GT_GFX_RC6pp                       0x138110
  4265.  
  4266. #define GEN6_PCODE_MAILBOX                      0x138124
  4267. #define   GEN6_PCODE_READY                      (1<<31)
  4268. #define   GEN6_READ_OC_PARAMS                   0xc
  4269. #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x8
  4270. #define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
  4271. #define   GEN6_PCODE_WRITE_RC6VIDS              0x4
  4272. #define   GEN6_PCODE_READ_RC6VIDS               0x5
  4273. #define   GEN6_ENCODE_RC6_VID(mv)               (((mv) - 245) / 5)
  4274. #define   GEN6_DECODE_RC6_VID(vids)             (((vids) * 5) + 245)
  4275. #define GEN6_PCODE_DATA                         0x138128
  4276. #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT        8
  4277.  
  4278. #define GEN6_GT_CORE_STATUS             0x138060
  4279. #define   GEN6_CORE_CPD_STATE_MASK      (7<<4)
  4280. #define   GEN6_RCn_MASK                 7
  4281. #define   GEN6_RC0                      0
  4282. #define   GEN6_RC3                      2
  4283. #define   GEN6_RC6                      3
  4284. #define   GEN6_RC7                      4
  4285.  
  4286. #define GEN7_MISCCPCTL                  (0x9424)
  4287. #define   GEN7_DOP_CLOCK_GATE_ENABLE    (1<<0)
  4288.  
  4289. /* IVYBRIDGE DPF */
  4290. #define GEN7_L3CDERRST1                 0xB008 /* L3CD Error Status 1 */
  4291. #define   GEN7_L3CDERRST1_ROW_MASK      (0x7ff<<14)
  4292. #define   GEN7_PARITY_ERROR_VALID       (1<<13)
  4293. #define   GEN7_L3CDERRST1_BANK_MASK     (3<<11)
  4294. #define   GEN7_L3CDERRST1_SUBBANK_MASK  (7<<8)
  4295. #define GEN7_PARITY_ERROR_ROW(reg) \
  4296.                 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
  4297. #define GEN7_PARITY_ERROR_BANK(reg) \
  4298.                 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
  4299. #define GEN7_PARITY_ERROR_SUBBANK(reg) \
  4300.                 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
  4301. #define   GEN7_L3CDERRST1_ENABLE        (1<<7)
  4302.  
  4303. #define GEN7_L3LOG_BASE                 0xB070
  4304. #define GEN7_L3LOG_SIZE                 0x80
  4305.  
  4306. #define GEN7_HALF_SLICE_CHICKEN1        0xe100 /* IVB GT1 + VLV */
  4307. #define GEN7_HALF_SLICE_CHICKEN1_GT2    0xf100
  4308. #define   GEN7_MAX_PS_THREAD_DEP                (8<<12)
  4309. #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE  (1<<3)
  4310.  
  4311. #define GEN7_ROW_CHICKEN2               0xe4f4
  4312. #define GEN7_ROW_CHICKEN2_GT2           0xf4f4
  4313. #define   DOP_CLOCK_GATING_DISABLE      (1<<0)
  4314.  
  4315. #define G4X_AUD_VID_DID                 (dev_priv->info->display_mmio_offset + 0x62020)
  4316. #define INTEL_AUDIO_DEVCL               0x808629FB
  4317. #define INTEL_AUDIO_DEVBLC              0x80862801
  4318. #define INTEL_AUDIO_DEVCTG              0x80862802
  4319.  
  4320. #define G4X_AUD_CNTL_ST                 0x620B4
  4321. #define G4X_ELDV_DEVCL_DEVBLC           (1 << 13)
  4322. #define G4X_ELDV_DEVCTG                 (1 << 14)
  4323. #define G4X_ELD_ADDR                    (0xf << 5)
  4324. #define G4X_ELD_ACK                     (1 << 4)
  4325. #define G4X_HDMIW_HDMIEDID              0x6210C
  4326.  
  4327. #define IBX_HDMIW_HDMIEDID_A            0xE2050
  4328. #define IBX_HDMIW_HDMIEDID_B            0xE2150
  4329. #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
  4330.                                         IBX_HDMIW_HDMIEDID_A, \
  4331.                                         IBX_HDMIW_HDMIEDID_B)
  4332. #define IBX_AUD_CNTL_ST_A               0xE20B4
  4333. #define IBX_AUD_CNTL_ST_B               0xE21B4
  4334. #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
  4335.                                         IBX_AUD_CNTL_ST_A, \
  4336.                                         IBX_AUD_CNTL_ST_B)
  4337. #define IBX_ELD_BUFFER_SIZE             (0x1f << 10)
  4338. #define IBX_ELD_ADDRESS                 (0x1f << 5)
  4339. #define IBX_ELD_ACK                     (1 << 4)
  4340. #define IBX_AUD_CNTL_ST2                0xE20C0
  4341. #define IBX_ELD_VALIDB                  (1 << 0)
  4342. #define IBX_CP_READYB                   (1 << 1)
  4343.  
  4344. #define CPT_HDMIW_HDMIEDID_A            0xE5050
  4345. #define CPT_HDMIW_HDMIEDID_B            0xE5150
  4346. #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
  4347.                                         CPT_HDMIW_HDMIEDID_A, \
  4348.                                         CPT_HDMIW_HDMIEDID_B)
  4349. #define CPT_AUD_CNTL_ST_A               0xE50B4
  4350. #define CPT_AUD_CNTL_ST_B               0xE51B4
  4351. #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
  4352.                                         CPT_AUD_CNTL_ST_A, \
  4353.                                         CPT_AUD_CNTL_ST_B)
  4354. #define CPT_AUD_CNTRL_ST2               0xE50C0
  4355.  
  4356. /* These are the 4 32-bit write offset registers for each stream
  4357.  * output buffer.  It determines the offset from the
  4358.  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
  4359.  */
  4360. #define GEN7_SO_WRITE_OFFSET(n)         (0x5280 + (n) * 4)
  4361.  
  4362. #define IBX_AUD_CONFIG_A                        0xe2000
  4363. #define IBX_AUD_CONFIG_B                        0xe2100
  4364. #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
  4365.                                         IBX_AUD_CONFIG_A, \
  4366.                                         IBX_AUD_CONFIG_B)
  4367. #define CPT_AUD_CONFIG_A                        0xe5000
  4368. #define CPT_AUD_CONFIG_B                        0xe5100
  4369. #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
  4370.                                         CPT_AUD_CONFIG_A, \
  4371.                                         CPT_AUD_CONFIG_B)
  4372. #define   AUD_CONFIG_N_VALUE_INDEX              (1 << 29)
  4373. #define   AUD_CONFIG_N_PROG_ENABLE              (1 << 28)
  4374. #define   AUD_CONFIG_UPPER_N_SHIFT              20
  4375. #define   AUD_CONFIG_UPPER_N_VALUE              (0xff << 20)
  4376. #define   AUD_CONFIG_LOWER_N_SHIFT              4
  4377. #define   AUD_CONFIG_LOWER_N_VALUE              (0xfff << 4)
  4378. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT     16
  4379. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI           (0xf << 16)
  4380. #define   AUD_CONFIG_DISABLE_NCTS               (1 << 3)
  4381.  
  4382. /* HSW Audio */
  4383. #define   HSW_AUD_CONFIG_A              0x65000 /* Audio Configuration Transcoder A */
  4384. #define   HSW_AUD_CONFIG_B              0x65100 /* Audio Configuration Transcoder B */
  4385. #define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
  4386.                                         HSW_AUD_CONFIG_A, \
  4387.                                         HSW_AUD_CONFIG_B)
  4388.  
  4389. #define   HSW_AUD_MISC_CTRL_A           0x65010 /* Audio Misc Control Convert 1 */
  4390. #define   HSW_AUD_MISC_CTRL_B           0x65110 /* Audio Misc Control Convert 2 */
  4391. #define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
  4392.                                         HSW_AUD_MISC_CTRL_A, \
  4393.                                         HSW_AUD_MISC_CTRL_B)
  4394.  
  4395. #define   HSW_AUD_DIP_ELD_CTRL_ST_A     0x650b4 /* Audio DIP and ELD Control State Transcoder A */
  4396. #define   HSW_AUD_DIP_ELD_CTRL_ST_B     0x651b4 /* Audio DIP and ELD Control State Transcoder B */
  4397. #define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
  4398.                                         HSW_AUD_DIP_ELD_CTRL_ST_A, \
  4399.                                         HSW_AUD_DIP_ELD_CTRL_ST_B)
  4400.  
  4401. /* Audio Digital Converter */
  4402. #define   HSW_AUD_DIG_CNVT_1            0x65080 /* Audio Converter 1 */
  4403. #define   HSW_AUD_DIG_CNVT_2            0x65180 /* Audio Converter 1 */
  4404. #define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
  4405.                                         HSW_AUD_DIG_CNVT_1, \
  4406.                                         HSW_AUD_DIG_CNVT_2)
  4407. #define   DIP_PORT_SEL_MASK             0x3
  4408.  
  4409. #define   HSW_AUD_EDID_DATA_A           0x65050
  4410. #define   HSW_AUD_EDID_DATA_B           0x65150
  4411. #define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
  4412.                                         HSW_AUD_EDID_DATA_A, \
  4413.                                         HSW_AUD_EDID_DATA_B)
  4414.  
  4415. #define   HSW_AUD_PIPE_CONV_CFG         0x6507c /* Audio pipe and converter configs */
  4416. #define   HSW_AUD_PIN_ELD_CP_VLD        0x650c0 /* Audio ELD and CP Ready Status */
  4417. #define   AUDIO_INACTIVE_C              (1<<11)
  4418. #define   AUDIO_INACTIVE_B              (1<<7)
  4419. #define   AUDIO_INACTIVE_A              (1<<3)
  4420. #define   AUDIO_OUTPUT_ENABLE_A         (1<<2)
  4421. #define   AUDIO_OUTPUT_ENABLE_B         (1<<6)
  4422. #define   AUDIO_OUTPUT_ENABLE_C         (1<<10)
  4423. #define   AUDIO_ELD_VALID_A             (1<<0)
  4424. #define   AUDIO_ELD_VALID_B             (1<<4)
  4425. #define   AUDIO_ELD_VALID_C             (1<<8)
  4426. #define   AUDIO_CP_READY_A              (1<<1)
  4427. #define   AUDIO_CP_READY_B              (1<<5)
  4428. #define   AUDIO_CP_READY_C              (1<<9)
  4429.  
  4430. /* HSW Power Wells */
  4431. #define HSW_PWR_WELL_BIOS                       0x45400 /* CTL1 */
  4432. #define HSW_PWR_WELL_DRIVER                     0x45404 /* CTL2 */
  4433. #define HSW_PWR_WELL_KVMR                       0x45408 /* CTL3 */
  4434. #define HSW_PWR_WELL_DEBUG                      0x4540C /* CTL4 */
  4435. #define   HSW_PWR_WELL_ENABLE                           (1<<31)
  4436. #define   HSW_PWR_WELL_STATE                            (1<<30)
  4437. #define HSW_PWR_WELL_CTL5               0x45410
  4438. #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP       (1<<31)
  4439. #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE        (1<<20)
  4440. #define   HSW_PWR_WELL_FORCE_ON                         (1<<19)
  4441. #define HSW_PWR_WELL_CTL6               0x45414
  4442.  
  4443. /* Per-pipe DDI Function Control */
  4444. #define TRANS_DDI_FUNC_CTL_A            0x60400
  4445. #define TRANS_DDI_FUNC_CTL_B            0x61400
  4446. #define TRANS_DDI_FUNC_CTL_C            0x62400
  4447. #define TRANS_DDI_FUNC_CTL_EDP          0x6F400
  4448. #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
  4449.                                                    TRANS_DDI_FUNC_CTL_B)
  4450. #define  TRANS_DDI_FUNC_ENABLE          (1<<31)
  4451. /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
  4452. #define  TRANS_DDI_PORT_MASK            (7<<28)
  4453. #define  TRANS_DDI_SELECT_PORT(x)       ((x)<<28)
  4454. #define  TRANS_DDI_PORT_NONE            (0<<28)
  4455. #define  TRANS_DDI_MODE_SELECT_MASK     (7<<24)
  4456. #define  TRANS_DDI_MODE_SELECT_HDMI     (0<<24)
  4457. #define  TRANS_DDI_MODE_SELECT_DVI      (1<<24)
  4458. #define  TRANS_DDI_MODE_SELECT_DP_SST   (2<<24)
  4459. #define  TRANS_DDI_MODE_SELECT_DP_MST   (3<<24)
  4460. #define  TRANS_DDI_MODE_SELECT_FDI      (4<<24)
  4461. #define  TRANS_DDI_BPC_MASK             (7<<20)
  4462. #define  TRANS_DDI_BPC_8                (0<<20)
  4463. #define  TRANS_DDI_BPC_10               (1<<20)
  4464. #define  TRANS_DDI_BPC_6                (2<<20)
  4465. #define  TRANS_DDI_BPC_12               (3<<20)
  4466. #define  TRANS_DDI_PVSYNC               (1<<17)
  4467. #define  TRANS_DDI_PHSYNC               (1<<16)
  4468. #define  TRANS_DDI_EDP_INPUT_MASK       (7<<12)
  4469. #define  TRANS_DDI_EDP_INPUT_A_ON       (0<<12)
  4470. #define  TRANS_DDI_EDP_INPUT_A_ONOFF    (4<<12)
  4471. #define  TRANS_DDI_EDP_INPUT_B_ONOFF    (5<<12)
  4472. #define  TRANS_DDI_EDP_INPUT_C_ONOFF    (6<<12)
  4473. #define  TRANS_DDI_BFI_ENABLE           (1<<4)
  4474. #define  TRANS_DDI_PORT_WIDTH_X1        (0<<1)
  4475. #define  TRANS_DDI_PORT_WIDTH_X2        (1<<1)
  4476. #define  TRANS_DDI_PORT_WIDTH_X4        (3<<1)
  4477.  
  4478. /* DisplayPort Transport Control */
  4479. #define DP_TP_CTL_A                     0x64040
  4480. #define DP_TP_CTL_B                     0x64140
  4481. #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
  4482. #define  DP_TP_CTL_ENABLE               (1<<31)
  4483. #define  DP_TP_CTL_MODE_SST     (0<<27)
  4484. #define  DP_TP_CTL_MODE_MST     (1<<27)
  4485. #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE        (1<<18)
  4486. #define  DP_TP_CTL_FDI_AUTOTRAIN        (1<<15)
  4487. #define  DP_TP_CTL_LINK_TRAIN_MASK              (7<<8)
  4488. #define  DP_TP_CTL_LINK_TRAIN_PAT1              (0<<8)
  4489. #define  DP_TP_CTL_LINK_TRAIN_PAT2              (1<<8)
  4490. #define  DP_TP_CTL_LINK_TRAIN_PAT3              (4<<8)
  4491. #define  DP_TP_CTL_LINK_TRAIN_IDLE              (2<<8)
  4492. #define  DP_TP_CTL_LINK_TRAIN_NORMAL    (3<<8)
  4493. #define  DP_TP_CTL_SCRAMBLE_DISABLE             (1<<7)
  4494.  
  4495. /* DisplayPort Transport Status */
  4496. #define DP_TP_STATUS_A                  0x64044
  4497. #define DP_TP_STATUS_B                  0x64144
  4498. #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
  4499. #define  DP_TP_STATUS_IDLE_DONE         (1<<25)
  4500. #define  DP_TP_STATUS_AUTOTRAIN_DONE    (1<<12)
  4501.  
  4502. /* DDI Buffer Control */
  4503. #define DDI_BUF_CTL_A                           0x64000
  4504. #define DDI_BUF_CTL_B                           0x64100
  4505. #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
  4506. #define  DDI_BUF_CTL_ENABLE                             (1<<31)
  4507. #define  DDI_BUF_EMP_400MV_0DB_HSW              (0<<24)   /* Sel0 */
  4508. #define  DDI_BUF_EMP_400MV_3_5DB_HSW    (1<<24)   /* Sel1 */
  4509. #define  DDI_BUF_EMP_400MV_6DB_HSW              (2<<24)   /* Sel2 */
  4510. #define  DDI_BUF_EMP_400MV_9_5DB_HSW    (3<<24)   /* Sel3 */
  4511. #define  DDI_BUF_EMP_600MV_0DB_HSW              (4<<24)   /* Sel4 */
  4512. #define  DDI_BUF_EMP_600MV_3_5DB_HSW    (5<<24)   /* Sel5 */
  4513. #define  DDI_BUF_EMP_600MV_6DB_HSW              (6<<24)   /* Sel6 */
  4514. #define  DDI_BUF_EMP_800MV_0DB_HSW              (7<<24)   /* Sel7 */
  4515. #define  DDI_BUF_EMP_800MV_3_5DB_HSW    (8<<24)   /* Sel8 */
  4516. #define  DDI_BUF_EMP_MASK                               (0xf<<24)
  4517. #define  DDI_BUF_PORT_REVERSAL                  (1<<16)
  4518. #define  DDI_BUF_IS_IDLE                                (1<<7)
  4519. #define  DDI_A_4_LANES                          (1<<4)
  4520. #define  DDI_PORT_WIDTH_X1                              (0<<1)
  4521. #define  DDI_PORT_WIDTH_X2                              (1<<1)
  4522. #define  DDI_PORT_WIDTH_X4                              (3<<1)
  4523. #define  DDI_INIT_DISPLAY_DETECTED              (1<<0)
  4524.  
  4525. /* DDI Buffer Translations */
  4526. #define DDI_BUF_TRANS_A                         0x64E00
  4527. #define DDI_BUF_TRANS_B                         0x64E60
  4528. #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
  4529.  
  4530. /* Sideband Interface (SBI) is programmed indirectly, via
  4531.  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  4532.  * which contains the payload */
  4533. #define SBI_ADDR                                0xC6000
  4534. #define SBI_DATA                                0xC6004
  4535. #define SBI_CTL_STAT                    0xC6008
  4536. #define  SBI_CTL_DEST_ICLK              (0x0<<16)
  4537. #define  SBI_CTL_DEST_MPHY              (0x1<<16)
  4538. #define  SBI_CTL_OP_IORD                (0x2<<8)
  4539. #define  SBI_CTL_OP_IOWR                (0x3<<8)
  4540. #define  SBI_CTL_OP_CRRD                (0x6<<8)
  4541. #define  SBI_CTL_OP_CRWR                (0x7<<8)
  4542. #define  SBI_RESPONSE_FAIL              (0x1<<1)
  4543. #define  SBI_RESPONSE_SUCCESS   (0x0<<1)
  4544. #define  SBI_BUSY                               (0x1<<0)
  4545. #define  SBI_READY                              (0x0<<0)
  4546.  
  4547. /* SBI offsets */
  4548. #define  SBI_SSCDIVINTPHASE6            0x0600
  4549. #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK        ((0x7f)<<1)
  4550. #define   SBI_SSCDIVINTPHASE_DIVSEL(x)          ((x)<<1)
  4551. #define   SBI_SSCDIVINTPHASE_INCVAL_MASK        ((0x7f)<<8)
  4552. #define   SBI_SSCDIVINTPHASE_INCVAL(x)          ((x)<<8)
  4553. #define   SBI_SSCDIVINTPHASE_DIR(x)                     ((x)<<15)
  4554. #define   SBI_SSCDIVINTPHASE_PROPAGATE          (1<<0)
  4555. #define  SBI_SSCCTL                                     0x020c
  4556. #define  SBI_SSCCTL6                            0x060C
  4557. #define   SBI_SSCCTL_PATHALT                    (1<<3)
  4558. #define   SBI_SSCCTL_DISABLE            (1<<0)
  4559. #define  SBI_SSCAUXDIV6                         0x0610
  4560. #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)         ((x)<<4)
  4561. #define  SBI_DBUFF0                                     0x2a00
  4562. #define   SBI_DBUFF0_ENABLE                     (1<<0)
  4563.  
  4564. /* LPT PIXCLK_GATE */
  4565. #define PIXCLK_GATE                             0xC6020
  4566. #define  PIXCLK_GATE_UNGATE             (1<<0)
  4567. #define  PIXCLK_GATE_GATE               (0<<0)
  4568.  
  4569. /* SPLL */
  4570. #define SPLL_CTL                                0x46020
  4571. #define  SPLL_PLL_ENABLE                (1<<31)
  4572. #define  SPLL_PLL_SSC                   (1<<28)
  4573. #define  SPLL_PLL_NON_SSC               (2<<28)
  4574. #define  SPLL_PLL_FREQ_810MHz   (0<<26)
  4575. #define  SPLL_PLL_FREQ_1350MHz  (1<<26)
  4576.  
  4577. /* WRPLL */
  4578. #define WRPLL_CTL1                              0x46040
  4579. #define WRPLL_CTL2                              0x46060
  4580. #define  WRPLL_PLL_ENABLE                               (1<<31)
  4581. #define  WRPLL_PLL_SELECT_SSC                   (0x01<<28)
  4582. #define  WRPLL_PLL_SELECT_NON_SSC       (0x02<<28)
  4583. #define  WRPLL_PLL_SELECT_LCPLL_2700    (0x03<<28)
  4584. /* WRPLL divider programming */
  4585. #define  WRPLL_DIVIDER_REFERENCE(x)             ((x)<<0)
  4586. #define  WRPLL_DIVIDER_POST(x)                  ((x)<<8)
  4587. #define  WRPLL_DIVIDER_FEEDBACK(x)              ((x)<<16)
  4588.  
  4589. /* Port clock selection */
  4590. #define PORT_CLK_SEL_A                  0x46100
  4591. #define PORT_CLK_SEL_B                  0x46104
  4592. #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
  4593. #define  PORT_CLK_SEL_LCPLL_2700        (0<<29)
  4594. #define  PORT_CLK_SEL_LCPLL_1350        (1<<29)
  4595. #define  PORT_CLK_SEL_LCPLL_810         (2<<29)
  4596. #define  PORT_CLK_SEL_SPLL                      (3<<29)
  4597. #define  PORT_CLK_SEL_WRPLL1            (4<<29)
  4598. #define  PORT_CLK_SEL_WRPLL2            (5<<29)
  4599. #define  PORT_CLK_SEL_NONE              (7<<29)
  4600.  
  4601. /* Transcoder clock selection */
  4602. #define TRANS_CLK_SEL_A                 0x46140
  4603. #define TRANS_CLK_SEL_B                 0x46144
  4604. #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
  4605. /* For each transcoder, we need to select the corresponding port clock */
  4606. #define  TRANS_CLK_SEL_DISABLED         (0x0<<29)
  4607. #define  TRANS_CLK_SEL_PORT(x)          ((x+1)<<29)
  4608.  
  4609. #define _TRANSA_MSA_MISC                0x60410
  4610. #define _TRANSB_MSA_MISC                0x61410
  4611. #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
  4612.                                                _TRANSB_MSA_MISC)
  4613. #define  TRANS_MSA_SYNC_CLK             (1<<0)
  4614. #define  TRANS_MSA_6_BPC                (0<<5)
  4615. #define  TRANS_MSA_8_BPC                (1<<5)
  4616. #define  TRANS_MSA_10_BPC               (2<<5)
  4617. #define  TRANS_MSA_12_BPC               (3<<5)
  4618. #define  TRANS_MSA_16_BPC               (4<<5)
  4619.  
  4620. /* LCPLL Control */
  4621. #define LCPLL_CTL                               0x130040
  4622. #define  LCPLL_PLL_DISABLE              (1<<31)
  4623. #define  LCPLL_PLL_LOCK                 (1<<30)
  4624. #define  LCPLL_CLK_FREQ_MASK            (3<<26)
  4625. #define  LCPLL_CLK_FREQ_450             (0<<26)
  4626. #define  LCPLL_CD_CLOCK_DISABLE (1<<25)
  4627. #define  LCPLL_CD2X_CLOCK_DISABLE       (1<<23)
  4628. #define  LCPLL_CD_SOURCE_FCLK           (1<<21)
  4629.  
  4630. /* Pipe WM_LINETIME - watermark line time */
  4631. #define PIPE_WM_LINETIME_A              0x45270
  4632. #define PIPE_WM_LINETIME_B              0x45274
  4633. #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
  4634.                                         PIPE_WM_LINETIME_B)
  4635. #define   PIPE_WM_LINETIME_MASK         (0x1ff)
  4636. #define   PIPE_WM_LINETIME_TIME(x)                      ((x))
  4637. #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK    (0x1ff<<16)
  4638. #define   PIPE_WM_LINETIME_IPS_LINETIME(x)              ((x)<<16)
  4639.  
  4640. /* SFUSE_STRAP */
  4641. #define SFUSE_STRAP                             0xc2014
  4642. #define  SFUSE_STRAP_DDIB_DETECTED      (1<<2)
  4643. #define  SFUSE_STRAP_DDIC_DETECTED      (1<<1)
  4644. #define  SFUSE_STRAP_DDID_DETECTED      (1<<0)
  4645.  
  4646. #define WM_DBG                          0x45280
  4647. #define  WM_DBG_DISALLOW_MULTIPLE_LP    (1<<0)
  4648. #define  WM_DBG_DISALLOW_MAXFIFO        (1<<1)
  4649. #define  WM_DBG_DISALLOW_SPRITE         (1<<2)
  4650.  
  4651. /* pipe CSC */
  4652. #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
  4653. #define _PIPE_A_CSC_COEFF_BY    0x49014
  4654. #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
  4655. #define _PIPE_A_CSC_COEFF_BU    0x4901c
  4656. #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
  4657. #define _PIPE_A_CSC_COEFF_BV    0x49024
  4658. #define _PIPE_A_CSC_MODE        0x49028
  4659. #define _PIPE_A_CSC_PREOFF_HI   0x49030
  4660. #define _PIPE_A_CSC_PREOFF_ME   0x49034
  4661. #define _PIPE_A_CSC_PREOFF_LO   0x49038
  4662. #define _PIPE_A_CSC_POSTOFF_HI  0x49040
  4663. #define _PIPE_A_CSC_POSTOFF_ME  0x49044
  4664. #define _PIPE_A_CSC_POSTOFF_LO  0x49048
  4665.  
  4666. #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
  4667. #define _PIPE_B_CSC_COEFF_BY    0x49114
  4668. #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
  4669. #define _PIPE_B_CSC_COEFF_BU    0x4911c
  4670. #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
  4671. #define _PIPE_B_CSC_COEFF_BV    0x49124
  4672. #define _PIPE_B_CSC_MODE        0x49128
  4673. #define _PIPE_B_CSC_PREOFF_HI   0x49130
  4674. #define _PIPE_B_CSC_PREOFF_ME   0x49134
  4675. #define _PIPE_B_CSC_PREOFF_LO   0x49138
  4676. #define _PIPE_B_CSC_POSTOFF_HI  0x49140
  4677. #define _PIPE_B_CSC_POSTOFF_ME  0x49144
  4678. #define _PIPE_B_CSC_POSTOFF_LO  0x49148
  4679.  
  4680. #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
  4681. #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
  4682. #define CSC_MODE_YUV_TO_RGB (1 << 0)
  4683.  
  4684. #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
  4685. #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
  4686. #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
  4687. #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
  4688. #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
  4689. #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
  4690. #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
  4691. #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
  4692. #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
  4693. #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
  4694. #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
  4695. #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
  4696. #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
  4697.  
  4698. #endif /* _I915_REG_H_ */
  4699.