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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2.  */
  3. /*
  4.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5.  * All Rights Reserved.
  6.  *
  7.  * Permission is hereby granted, free of charge, to any person obtaining a
  8.  * copy of this software and associated documentation files (the
  9.  * "Software"), to deal in the Software without restriction, including
  10.  * without limitation the rights to use, copy, modify, merge, publish,
  11.  * distribute, sub license, and/or sell copies of the Software, and to
  12.  * permit persons to whom the Software is furnished to do so, subject to
  13.  * the following conditions:
  14.  *
  15.  * The above copyright notice and this permission notice (including the
  16.  * next paragraph) shall be included in all copies or substantial portions
  17.  * of the Software.
  18.  *
  19.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26.  *
  27.  */
  28.  
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30.  
  31. #include <linux/slab.h>
  32. #include <drm/drmP.h>
  33. #include <drm/i915_drm.h>
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include "intel_drv.h"
  37.  
  38. /**
  39.  * DOC: interrupt handling
  40.  *
  41.  * These functions provide the basic support for enabling and disabling the
  42.  * interrupt handling support. There's a lot more functionality in i915_irq.c
  43.  * and related files, but that will be described in separate chapters.
  44.  */
  45.  
  46. static const u32 hpd_ilk[HPD_NUM_PINS] = {
  47.         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  48. };
  49.  
  50. static const u32 hpd_ivb[HPD_NUM_PINS] = {
  51.         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  52. };
  53.  
  54. static const u32 hpd_bdw[HPD_NUM_PINS] = {
  55.         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  56. };
  57.  
  58. static const u32 hpd_ibx[HPD_NUM_PINS] = {
  59.         [HPD_CRT] = SDE_CRT_HOTPLUG,
  60.         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  61.         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  62.         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  63.         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  64. };
  65.  
  66. static const u32 hpd_cpt[HPD_NUM_PINS] = {
  67.         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  68.         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  69.         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  70.         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  71.         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  72. };
  73.  
  74. static const u32 hpd_spt[HPD_NUM_PINS] = {
  75.         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  76.         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  77.         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  78.         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  79.         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  80. };
  81.  
  82. static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  83.         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  84.         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  85.         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  86.         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  87.         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  88.         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  89. };
  90.  
  91. static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  92.         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  93.         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  94.         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  95.         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  96.         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  97.         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  98. };
  99.  
  100. static const u32 hpd_status_i915[HPD_NUM_PINS] = {
  101.         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  102.         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  103.         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  104.         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  105.         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  106.         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  107. };
  108.  
  109. /* BXT hpd list */
  110. static const u32 hpd_bxt[HPD_NUM_PINS] = {
  111.         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
  112.         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
  113.         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
  114. };
  115.  
  116. /* IIR can theoretically queue up two events. Be paranoid. */
  117. #define GEN8_IRQ_RESET_NDX(type, which) do { \
  118.         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  119.         POSTING_READ(GEN8_##type##_IMR(which)); \
  120.         I915_WRITE(GEN8_##type##_IER(which), 0); \
  121.         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  122.         POSTING_READ(GEN8_##type##_IIR(which)); \
  123.         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  124.         POSTING_READ(GEN8_##type##_IIR(which)); \
  125. } while (0)
  126.  
  127. #define GEN5_IRQ_RESET(type) do { \
  128.         I915_WRITE(type##IMR, 0xffffffff); \
  129.         POSTING_READ(type##IMR); \
  130.         I915_WRITE(type##IER, 0); \
  131.         I915_WRITE(type##IIR, 0xffffffff); \
  132.         POSTING_READ(type##IIR); \
  133.         I915_WRITE(type##IIR, 0xffffffff); \
  134.         POSTING_READ(type##IIR); \
  135. } while (0)
  136.  
  137. /*
  138.  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  139.  */
  140. static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
  141. {
  142.         u32 val = I915_READ(reg);
  143.  
  144.         if (val == 0)
  145.                 return;
  146.  
  147.         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
  148.              reg, val);
  149.         I915_WRITE(reg, 0xffffffff);
  150.         POSTING_READ(reg);
  151.         I915_WRITE(reg, 0xffffffff);
  152.         POSTING_READ(reg);
  153. }
  154.  
  155. #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
  156.         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
  157.         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
  158.         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
  159.         POSTING_READ(GEN8_##type##_IMR(which)); \
  160. } while (0)
  161.  
  162. #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
  163.         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
  164.         I915_WRITE(type##IER, (ier_val)); \
  165.         I915_WRITE(type##IMR, (imr_val)); \
  166.         POSTING_READ(type##IMR); \
  167. } while (0)
  168.  
  169. static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
  170.  
  171. /* For display hotplug interrupt */
  172. static inline void
  173. i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
  174.                                      uint32_t mask,
  175.                                      uint32_t bits)
  176. {
  177.         uint32_t val;
  178.  
  179.         assert_spin_locked(&dev_priv->irq_lock);
  180.         WARN_ON(bits & ~mask);
  181.  
  182.         val = I915_READ(PORT_HOTPLUG_EN);
  183.         val &= ~mask;
  184.         val |= bits;
  185.         I915_WRITE(PORT_HOTPLUG_EN, val);
  186. }
  187.  
  188. /**
  189.  * i915_hotplug_interrupt_update - update hotplug interrupt enable
  190.  * @dev_priv: driver private
  191.  * @mask: bits to update
  192.  * @bits: bits to enable
  193.  * NOTE: the HPD enable bits are modified both inside and outside
  194.  * of an interrupt context. To avoid that read-modify-write cycles
  195.  * interfer, these bits are protected by a spinlock. Since this
  196.  * function is usually not called from a context where the lock is
  197.  * held already, this function acquires the lock itself. A non-locking
  198.  * version is also available.
  199.  */
  200. void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
  201.                                    uint32_t mask,
  202.                                    uint32_t bits)
  203. {
  204.         spin_lock_irq(&dev_priv->irq_lock);
  205.         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
  206.         spin_unlock_irq(&dev_priv->irq_lock);
  207. }
  208.  
  209. /**
  210.  * ilk_update_display_irq - update DEIMR
  211.  * @dev_priv: driver private
  212.  * @interrupt_mask: mask of interrupt bits to update
  213.  * @enabled_irq_mask: mask of interrupt bits to enable
  214.  */
  215. static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
  216.                                    uint32_t interrupt_mask,
  217.                                    uint32_t enabled_irq_mask)
  218. {
  219.         uint32_t new_val;
  220.  
  221.         assert_spin_locked(&dev_priv->irq_lock);
  222.  
  223.         WARN_ON(enabled_irq_mask & ~interrupt_mask);
  224.  
  225.         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
  226.                 return;
  227.  
  228.         new_val = dev_priv->irq_mask;
  229.         new_val &= ~interrupt_mask;
  230.         new_val |= (~enabled_irq_mask & interrupt_mask);
  231.  
  232.         if (new_val != dev_priv->irq_mask) {
  233.                 dev_priv->irq_mask = new_val;
  234.                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  235.                 POSTING_READ(DEIMR);
  236.         }
  237. }
  238.  
  239. void
  240. ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
  241. {
  242.         ilk_update_display_irq(dev_priv, mask, mask);
  243. }
  244.  
  245. void
  246. ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
  247. {
  248.         ilk_update_display_irq(dev_priv, mask, 0);
  249. }
  250.  
  251. /**
  252.  * ilk_update_gt_irq - update GTIMR
  253.  * @dev_priv: driver private
  254.  * @interrupt_mask: mask of interrupt bits to update
  255.  * @enabled_irq_mask: mask of interrupt bits to enable
  256.  */
  257. static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
  258.                               uint32_t interrupt_mask,
  259.                               uint32_t enabled_irq_mask)
  260. {
  261.         assert_spin_locked(&dev_priv->irq_lock);
  262.  
  263.         WARN_ON(enabled_irq_mask & ~interrupt_mask);
  264.  
  265.         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
  266.                 return;
  267.  
  268.         dev_priv->gt_irq_mask &= ~interrupt_mask;
  269.         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
  270.         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  271.         POSTING_READ(GTIMR);
  272. }
  273.  
  274. void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  275. {
  276.         ilk_update_gt_irq(dev_priv, mask, mask);
  277. }
  278.  
  279. void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  280. {
  281.         ilk_update_gt_irq(dev_priv, mask, 0);
  282. }
  283.  
  284. static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
  285. {
  286.         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
  287. }
  288.  
  289. static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
  290. {
  291.         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
  292. }
  293.  
  294. static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
  295. {
  296.         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
  297. }
  298.  
  299. /**
  300.   * snb_update_pm_irq - update GEN6_PMIMR
  301.   * @dev_priv: driver private
  302.   * @interrupt_mask: mask of interrupt bits to update
  303.   * @enabled_irq_mask: mask of interrupt bits to enable
  304.   */
  305. static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
  306.                               uint32_t interrupt_mask,
  307.                               uint32_t enabled_irq_mask)
  308. {
  309.         uint32_t new_val;
  310.  
  311.         WARN_ON(enabled_irq_mask & ~interrupt_mask);
  312.  
  313.         assert_spin_locked(&dev_priv->irq_lock);
  314.  
  315.         new_val = dev_priv->pm_irq_mask;
  316.         new_val &= ~interrupt_mask;
  317.         new_val |= (~enabled_irq_mask & interrupt_mask);
  318.  
  319.         if (new_val != dev_priv->pm_irq_mask) {
  320.                 dev_priv->pm_irq_mask = new_val;
  321.                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
  322.                 POSTING_READ(gen6_pm_imr(dev_priv));
  323.         }
  324. }
  325.  
  326. void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  327. {
  328.         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
  329.                 return;
  330.  
  331.         snb_update_pm_irq(dev_priv, mask, mask);
  332. }
  333.  
  334. static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
  335.                                   uint32_t mask)
  336. {
  337.         snb_update_pm_irq(dev_priv, mask, 0);
  338. }
  339.  
  340. void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  341. {
  342.         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
  343.                 return;
  344.  
  345.         __gen6_disable_pm_irq(dev_priv, mask);
  346. }
  347.  
  348. void gen6_reset_rps_interrupts(struct drm_device *dev)
  349. {
  350.         struct drm_i915_private *dev_priv = dev->dev_private;
  351.         uint32_t reg = gen6_pm_iir(dev_priv);
  352.  
  353.         spin_lock_irq(&dev_priv->irq_lock);
  354.         I915_WRITE(reg, dev_priv->pm_rps_events);
  355.         I915_WRITE(reg, dev_priv->pm_rps_events);
  356.         POSTING_READ(reg);
  357.         dev_priv->rps.pm_iir = 0;
  358.         spin_unlock_irq(&dev_priv->irq_lock);
  359. }
  360.  
  361. void gen6_enable_rps_interrupts(struct drm_device *dev)
  362. {
  363.         struct drm_i915_private *dev_priv = dev->dev_private;
  364.  
  365.         spin_lock_irq(&dev_priv->irq_lock);
  366.  
  367.         WARN_ON(dev_priv->rps.pm_iir);
  368.         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
  369.         dev_priv->rps.interrupts_enabled = true;
  370.         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
  371.                                 dev_priv->pm_rps_events);
  372.         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
  373.  
  374.         spin_unlock_irq(&dev_priv->irq_lock);
  375. }
  376.  
  377. u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
  378. {
  379.         /*
  380.          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
  381.          * if GEN6_PM_UP_EI_EXPIRED is masked.
  382.          *
  383.          * TODO: verify if this can be reproduced on VLV,CHV.
  384.          */
  385.         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
  386.                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
  387.  
  388.         if (INTEL_INFO(dev_priv)->gen >= 8)
  389.                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
  390.  
  391.         return mask;
  392. }
  393.  
  394. void gen6_disable_rps_interrupts(struct drm_device *dev)
  395. {
  396.         struct drm_i915_private *dev_priv = dev->dev_private;
  397.  
  398.         spin_lock_irq(&dev_priv->irq_lock);
  399.         dev_priv->rps.interrupts_enabled = false;
  400.         spin_unlock_irq(&dev_priv->irq_lock);
  401.  
  402.         cancel_work_sync(&dev_priv->rps.work);
  403.  
  404.         spin_lock_irq(&dev_priv->irq_lock);
  405.  
  406.         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
  407.  
  408.         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
  409.         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
  410.                                 ~dev_priv->pm_rps_events);
  411.  
  412.         spin_unlock_irq(&dev_priv->irq_lock);
  413.  
  414. }
  415.  
  416. /**
  417.   * bdw_update_port_irq - update DE port interrupt
  418.   * @dev_priv: driver private
  419.   * @interrupt_mask: mask of interrupt bits to update
  420.   * @enabled_irq_mask: mask of interrupt bits to enable
  421.   */
  422. static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
  423.                                 uint32_t interrupt_mask,
  424.                                 uint32_t enabled_irq_mask)
  425. {
  426.         uint32_t new_val;
  427.         uint32_t old_val;
  428.  
  429.         assert_spin_locked(&dev_priv->irq_lock);
  430.  
  431.         WARN_ON(enabled_irq_mask & ~interrupt_mask);
  432.  
  433.         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
  434.                 return;
  435.  
  436.         old_val = I915_READ(GEN8_DE_PORT_IMR);
  437.  
  438.         new_val = old_val;
  439.         new_val &= ~interrupt_mask;
  440.         new_val |= (~enabled_irq_mask & interrupt_mask);
  441.  
  442.         if (new_val != old_val) {
  443.                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
  444.                 POSTING_READ(GEN8_DE_PORT_IMR);
  445.         }
  446. }
  447.  
  448. /**
  449.  * ibx_display_interrupt_update - update SDEIMR
  450.  * @dev_priv: driver private
  451.  * @interrupt_mask: mask of interrupt bits to update
  452.  * @enabled_irq_mask: mask of interrupt bits to enable
  453.  */
  454. void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
  455.                                   uint32_t interrupt_mask,
  456.                                   uint32_t enabled_irq_mask)
  457. {
  458.         uint32_t sdeimr = I915_READ(SDEIMR);
  459.         sdeimr &= ~interrupt_mask;
  460.         sdeimr |= (~enabled_irq_mask & interrupt_mask);
  461.  
  462.         WARN_ON(enabled_irq_mask & ~interrupt_mask);
  463.  
  464.         assert_spin_locked(&dev_priv->irq_lock);
  465.  
  466.         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
  467.                 return;
  468.  
  469.         I915_WRITE(SDEIMR, sdeimr);
  470.         POSTING_READ(SDEIMR);
  471. }
  472.  
  473. static void
  474. __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  475.                        u32 enable_mask, u32 status_mask)
  476. {
  477.         u32 reg = PIPESTAT(pipe);
  478.         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
  479.  
  480.         assert_spin_locked(&dev_priv->irq_lock);
  481.         WARN_ON(!intel_irqs_enabled(dev_priv));
  482.  
  483.         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
  484.                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
  485.                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
  486.                       pipe_name(pipe), enable_mask, status_mask))
  487.                 return;
  488.  
  489.         if ((pipestat & enable_mask) == enable_mask)
  490.                 return;
  491.  
  492.         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
  493.  
  494.         /* Enable the interrupt, clear any pending status */
  495.         pipestat |= enable_mask | status_mask;
  496.         I915_WRITE(reg, pipestat);
  497.         POSTING_READ(reg);
  498. }
  499.  
  500. static void
  501. __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  502.                         u32 enable_mask, u32 status_mask)
  503. {
  504.         u32 reg = PIPESTAT(pipe);
  505.         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
  506.  
  507.         assert_spin_locked(&dev_priv->irq_lock);
  508.         WARN_ON(!intel_irqs_enabled(dev_priv));
  509.  
  510.         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
  511.                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
  512.                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
  513.                       pipe_name(pipe), enable_mask, status_mask))
  514.                 return;
  515.  
  516.         if ((pipestat & enable_mask) == 0)
  517.                 return;
  518.  
  519.         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
  520.  
  521.         pipestat &= ~enable_mask;
  522.         I915_WRITE(reg, pipestat);
  523.         POSTING_READ(reg);
  524. }
  525.  
  526. static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
  527. {
  528.         u32 enable_mask = status_mask << 16;
  529.  
  530.         /*
  531.          * On pipe A we don't support the PSR interrupt yet,
  532.          * on pipe B and C the same bit MBZ.
  533.          */
  534.         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
  535.                 return 0;
  536.         /*
  537.          * On pipe B and C we don't support the PSR interrupt yet, on pipe
  538.          * A the same bit is for perf counters which we don't use either.
  539.          */
  540.         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
  541.                 return 0;
  542.  
  543.         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
  544.                          SPRITE0_FLIP_DONE_INT_EN_VLV |
  545.                          SPRITE1_FLIP_DONE_INT_EN_VLV);
  546.         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
  547.                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
  548.         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
  549.                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
  550.  
  551.         return enable_mask;
  552. }
  553.  
  554. void
  555. i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  556.                      u32 status_mask)
  557. {
  558.         u32 enable_mask;
  559.  
  560.         if (IS_VALLEYVIEW(dev_priv->dev))
  561.                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
  562.                                                            status_mask);
  563.         else
  564.                 enable_mask = status_mask << 16;
  565.         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
  566. }
  567.  
  568. void
  569. i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  570.                       u32 status_mask)
  571. {
  572.         u32 enable_mask;
  573.  
  574.         if (IS_VALLEYVIEW(dev_priv->dev))
  575.                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
  576.                                                            status_mask);
  577.         else
  578.                 enable_mask = status_mask << 16;
  579.         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
  580. }
  581.  
  582. /**
  583.  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
  584.  * @dev: drm device
  585.  */
  586. static void i915_enable_asle_pipestat(struct drm_device *dev)
  587. {
  588.         struct drm_i915_private *dev_priv = dev->dev_private;
  589.  
  590.         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
  591.                 return;
  592.  
  593.         spin_lock_irq(&dev_priv->irq_lock);
  594.  
  595.         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
  596.         if (INTEL_INFO(dev)->gen >= 4)
  597.                 i915_enable_pipestat(dev_priv, PIPE_A,
  598.                                      PIPE_LEGACY_BLC_EVENT_STATUS);
  599.  
  600.         spin_unlock_irq(&dev_priv->irq_lock);
  601. }
  602.  
  603. /*
  604.  * This timing diagram depicts the video signal in and
  605.  * around the vertical blanking period.
  606.  *
  607.  * Assumptions about the fictitious mode used in this example:
  608.  *  vblank_start >= 3
  609.  *  vsync_start = vblank_start + 1
  610.  *  vsync_end = vblank_start + 2
  611.  *  vtotal = vblank_start + 3
  612.  *
  613.  *           start of vblank:
  614.  *           latch double buffered registers
  615.  *           increment frame counter (ctg+)
  616.  *           generate start of vblank interrupt (gen4+)
  617.  *           |
  618.  *           |          frame start:
  619.  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
  620.  *           |          may be shifted forward 1-3 extra lines via PIPECONF
  621.  *           |          |
  622.  *           |          |  start of vsync:
  623.  *           |          |  generate vsync interrupt
  624.  *           |          |  |
  625.  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
  626.  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
  627.  * ----va---> <-----------------vb--------------------> <--------va-------------
  628.  *       |          |       <----vs----->                     |
  629.  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
  630.  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
  631.  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
  632.  *       |          |                                         |
  633.  *       last visible pixel                                   first visible pixel
  634.  *                  |                                         increment frame counter (gen3/4)
  635.  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
  636.  *
  637.  * x  = horizontal active
  638.  * _  = horizontal blanking
  639.  * hs = horizontal sync
  640.  * va = vertical active
  641.  * vb = vertical blanking
  642.  * vs = vertical sync
  643.  * vbs = vblank_start (number)
  644.  *
  645.  * Summary:
  646.  * - most events happen at the start of horizontal sync
  647.  * - frame start happens at the start of horizontal blank, 1-4 lines
  648.  *   (depending on PIPECONF settings) after the start of vblank
  649.  * - gen3/4 pixel and frame counter are synchronized with the start
  650.  *   of horizontal active on the first line of vertical active
  651.  */
  652.  
  653. static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
  654. {
  655.         /* Gen2 doesn't have a hardware frame counter */
  656.         return 0;
  657. }
  658.  
  659. /* Called from drm generic code, passed a 'crtc', which
  660.  * we use as a pipe index
  661.  */
  662. static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
  663. {
  664.         struct drm_i915_private *dev_priv = dev->dev_private;
  665.         unsigned long high_frame;
  666.         unsigned long low_frame;
  667.         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
  668.         struct intel_crtc *intel_crtc =
  669.                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  670.         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
  671.  
  672.         htotal = mode->crtc_htotal;
  673.         hsync_start = mode->crtc_hsync_start;
  674.         vbl_start = mode->crtc_vblank_start;
  675.         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  676.                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
  677.  
  678.         /* Convert to pixel count */
  679.         vbl_start *= htotal;
  680.  
  681.         /* Start of vblank event occurs at start of hsync */
  682.         vbl_start -= htotal - hsync_start;
  683.  
  684.         high_frame = PIPEFRAME(pipe);
  685.         low_frame = PIPEFRAMEPIXEL(pipe);
  686.  
  687.         /*
  688.          * High & low register fields aren't synchronized, so make sure
  689.          * we get a low value that's stable across two reads of the high
  690.          * register.
  691.          */
  692.         do {
  693.                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  694.                 low   = I915_READ(low_frame);
  695.                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  696.         } while (high1 != high2);
  697.  
  698.         high1 >>= PIPE_FRAME_HIGH_SHIFT;
  699.         pixel = low & PIPE_PIXEL_MASK;
  700.         low >>= PIPE_FRAME_LOW_SHIFT;
  701.  
  702.         /*
  703.          * The frame counter increments at beginning of active.
  704.          * Cook up a vblank counter by also checking the pixel
  705.          * counter against vblank start.
  706.          */
  707.         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
  708. }
  709.  
  710. static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
  711. {
  712.         struct drm_i915_private *dev_priv = dev->dev_private;
  713.  
  714.         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
  715. }
  716.  
  717. /* raw reads, only for fast reads of display block, no need for forcewake etc. */
  718. #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  719.  
  720. static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
  721. {
  722.         struct drm_device *dev = crtc->base.dev;
  723.         struct drm_i915_private *dev_priv = dev->dev_private;
  724.         const struct drm_display_mode *mode = &crtc->base.hwmode;
  725.         enum pipe pipe = crtc->pipe;
  726.         int position, vtotal;
  727.  
  728.         vtotal = mode->crtc_vtotal;
  729.         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  730.                 vtotal /= 2;
  731.  
  732.         if (IS_GEN2(dev))
  733.                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
  734.         else
  735.                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
  736.  
  737.         /*
  738.          * On HSW, the DSL reg (0x70000) appears to return 0 if we
  739.          * read it just before the start of vblank.  So try it again
  740.          * so we don't accidentally end up spanning a vblank frame
  741.          * increment, causing the pipe_update_end() code to squak at us.
  742.          *
  743.          * The nature of this problem means we can't simply check the ISR
  744.          * bit and return the vblank start value; nor can we use the scanline
  745.          * debug register in the transcoder as it appears to have the same
  746.          * problem.  We may need to extend this to include other platforms,
  747.          * but so far testing only shows the problem on HSW.
  748.          */
  749.         if (HAS_DDI(dev) && !position) {
  750.                 int i, temp;
  751.  
  752.                 for (i = 0; i < 100; i++) {
  753.                         udelay(1);
  754.                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
  755.                                 DSL_LINEMASK_GEN3;
  756.                         if (temp != position) {
  757.                                 position = temp;
  758.                                 break;
  759.                         }
  760.                 }
  761.         }
  762.  
  763.         /*
  764.          * See update_scanline_offset() for the details on the
  765.          * scanline_offset adjustment.
  766.          */
  767.         return (position + crtc->scanline_offset) % vtotal;
  768. }
  769.  
  770. static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
  771.                                     unsigned int flags, int *vpos, int *hpos,
  772.                                     ktime_t *stime, ktime_t *etime,
  773.                                     const struct drm_display_mode *mode)
  774. {
  775.         struct drm_i915_private *dev_priv = dev->dev_private;
  776.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  777.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  778.         int position;
  779.         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
  780.         bool in_vbl = true;
  781.         int ret = 0;
  782.         unsigned long irqflags;
  783.  
  784.         if (WARN_ON(!mode->crtc_clock)) {
  785.                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  786.                                  "pipe %c\n", pipe_name(pipe));
  787.                 return 0;
  788.         }
  789.  
  790.         htotal = mode->crtc_htotal;
  791.         hsync_start = mode->crtc_hsync_start;
  792.         vtotal = mode->crtc_vtotal;
  793.         vbl_start = mode->crtc_vblank_start;
  794.         vbl_end = mode->crtc_vblank_end;
  795.  
  796.         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  797.                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
  798.                 vbl_end /= 2;
  799.                 vtotal /= 2;
  800.         }
  801.  
  802.         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  803.  
  804.         /*
  805.          * Lock uncore.lock, as we will do multiple timing critical raw
  806.          * register reads, potentially with preemption disabled, so the
  807.          * following code must not block on uncore.lock.
  808.          */
  809.         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
  810.  
  811.         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
  812.  
  813.         /* Get optional system timestamp before query. */
  814.         if (stime)
  815.                 *stime = ktime_get();
  816.  
  817.         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  818.                 /* No obvious pixelcount register. Only query vertical
  819.                  * scanout position from Display scan line register.
  820.                  */
  821.                 position = __intel_get_crtc_scanline(intel_crtc);
  822.         } else {
  823.                 /* Have access to pixelcount since start of frame.
  824.                  * We can split this into vertical and horizontal
  825.                  * scanout position.
  826.                  */
  827.                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  828.  
  829.                 /* convert to pixel counts */
  830.                 vbl_start *= htotal;
  831.                 vbl_end *= htotal;
  832.                 vtotal *= htotal;
  833.  
  834.                 /*
  835.                  * In interlaced modes, the pixel counter counts all pixels,
  836.                  * so one field will have htotal more pixels. In order to avoid
  837.                  * the reported position from jumping backwards when the pixel
  838.                  * counter is beyond the length of the shorter field, just
  839.                  * clamp the position the length of the shorter field. This
  840.                  * matches how the scanline counter based position works since
  841.                  * the scanline counter doesn't count the two half lines.
  842.                  */
  843.                 if (position >= vtotal)
  844.                         position = vtotal - 1;
  845.  
  846.                 /*
  847.                  * Start of vblank interrupt is triggered at start of hsync,
  848.                  * just prior to the first active line of vblank. However we
  849.                  * consider lines to start at the leading edge of horizontal
  850.                  * active. So, should we get here before we've crossed into
  851.                  * the horizontal active of the first line in vblank, we would
  852.                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
  853.                  * always add htotal-hsync_start to the current pixel position.
  854.                  */
  855.                 position = (position + htotal - hsync_start) % vtotal;
  856.         }
  857.  
  858.         /* Get optional system timestamp after query. */
  859.         if (etime)
  860.                 *etime = ktime_get();
  861.  
  862.         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
  863.  
  864.         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
  865.  
  866.         in_vbl = position >= vbl_start && position < vbl_end;
  867.  
  868.         /*
  869.          * While in vblank, position will be negative
  870.          * counting up towards 0 at vbl_end. And outside
  871.          * vblank, position will be positive counting
  872.          * up since vbl_end.
  873.          */
  874.         if (position >= vbl_start)
  875.                 position -= vbl_end;
  876.         else
  877.                 position += vtotal - vbl_end;
  878.  
  879.         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  880.                 *vpos = position;
  881.                 *hpos = 0;
  882.         } else {
  883.                 *vpos = position / htotal;
  884.                 *hpos = position - (*vpos * htotal);
  885.         }
  886.  
  887.         /* In vblank? */
  888.         if (in_vbl)
  889.                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
  890.  
  891.         return ret;
  892. }
  893.  
  894. int intel_get_crtc_scanline(struct intel_crtc *crtc)
  895. {
  896.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  897.         unsigned long irqflags;
  898.         int position;
  899.  
  900.         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
  901.         position = __intel_get_crtc_scanline(crtc);
  902.         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
  903.  
  904.         return position;
  905. }
  906.  
  907. static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
  908.                               int *max_error,
  909.                               struct timeval *vblank_time,
  910.                               unsigned flags)
  911. {
  912.         struct drm_crtc *crtc;
  913.  
  914.         if (pipe >= INTEL_INFO(dev)->num_pipes) {
  915.                 DRM_ERROR("Invalid crtc %u\n", pipe);
  916.                 return -EINVAL;
  917.         }
  918.  
  919.         /* Get drm_crtc to timestamp: */
  920.         crtc = intel_get_crtc_for_pipe(dev, pipe);
  921.         if (crtc == NULL) {
  922.                 DRM_ERROR("Invalid crtc %u\n", pipe);
  923.                 return -EINVAL;
  924.         }
  925.  
  926.         if (!crtc->hwmode.crtc_clock) {
  927.                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
  928.                 return -EBUSY;
  929.         }
  930.  
  931.         /* Helper routine in DRM core does all the work: */
  932.         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  933.                                                      vblank_time, flags,
  934.                                                      &crtc->hwmode);
  935. }
  936.  
  937. static void ironlake_rps_change_irq_handler(struct drm_device *dev)
  938. {
  939.         struct drm_i915_private *dev_priv = dev->dev_private;
  940.         u32 busy_up, busy_down, max_avg, min_avg;
  941.         u8 new_delay;
  942.  
  943.         spin_lock(&mchdev_lock);
  944.  
  945.         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  946.  
  947.         new_delay = dev_priv->ips.cur_delay;
  948.  
  949.         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  950.         busy_up = I915_READ(RCPREVBSYTUPAVG);
  951.         busy_down = I915_READ(RCPREVBSYTDNAVG);
  952.         max_avg = I915_READ(RCBMAXAVG);
  953.         min_avg = I915_READ(RCBMINAVG);
  954.  
  955.         /* Handle RCS change request from hw */
  956.         if (busy_up > max_avg) {
  957.                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  958.                         new_delay = dev_priv->ips.cur_delay - 1;
  959.                 if (new_delay < dev_priv->ips.max_delay)
  960.                         new_delay = dev_priv->ips.max_delay;
  961.         } else if (busy_down < min_avg) {
  962.                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  963.                         new_delay = dev_priv->ips.cur_delay + 1;
  964.                 if (new_delay > dev_priv->ips.min_delay)
  965.                         new_delay = dev_priv->ips.min_delay;
  966.         }
  967.  
  968.         if (ironlake_set_drps(dev, new_delay))
  969.                 dev_priv->ips.cur_delay = new_delay;
  970.  
  971.         spin_unlock(&mchdev_lock);
  972.  
  973.         return;
  974. }
  975.  
  976. static void notify_ring(struct intel_engine_cs *ring)
  977. {
  978.         if (!intel_ring_initialized(ring))
  979.                 return;
  980.  
  981.         trace_i915_gem_request_notify(ring);
  982.  
  983.         wake_up_all(&ring->irq_queue);
  984. }
  985.  
  986. static void vlv_c0_read(struct drm_i915_private *dev_priv,
  987.                         struct intel_rps_ei *ei)
  988. {
  989.         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
  990.         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
  991.         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
  992. }
  993.  
  994. static bool vlv_c0_above(struct drm_i915_private *dev_priv,
  995.                          const struct intel_rps_ei *old,
  996.                          const struct intel_rps_ei *now,
  997.                          int threshold)
  998. {
  999.         u64 time, c0;
  1000.         unsigned int mul = 100;
  1001.  
  1002.         if (old->cz_clock == 0)
  1003.                 return false;
  1004.  
  1005.         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
  1006.                 mul <<= 8;
  1007.  
  1008.         time = now->cz_clock - old->cz_clock;
  1009.         time *= threshold * dev_priv->czclk_freq;
  1010.  
  1011.         /* Workload can be split between render + media, e.g. SwapBuffers
  1012.          * being blitted in X after being rendered in mesa. To account for
  1013.          * this we need to combine both engines into our activity counter.
  1014.          */
  1015.         c0 = now->render_c0 - old->render_c0;
  1016.         c0 += now->media_c0 - old->media_c0;
  1017.         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
  1018.  
  1019.         return c0 >= time;
  1020. }
  1021.  
  1022. void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
  1023. {
  1024.         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
  1025.         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
  1026. }
  1027.  
  1028. static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
  1029. {
  1030.         struct intel_rps_ei now;
  1031.         u32 events = 0;
  1032.  
  1033.         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
  1034.                 return 0;
  1035.  
  1036.         vlv_c0_read(dev_priv, &now);
  1037.         if (now.cz_clock == 0)
  1038.                 return 0;
  1039.  
  1040.         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
  1041.                 if (!vlv_c0_above(dev_priv,
  1042.                                   &dev_priv->rps.down_ei, &now,
  1043.                                   dev_priv->rps.down_threshold))
  1044.                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
  1045.                 dev_priv->rps.down_ei = now;
  1046.         }
  1047.  
  1048.         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
  1049.                 if (vlv_c0_above(dev_priv,
  1050.                                  &dev_priv->rps.up_ei, &now,
  1051.                                  dev_priv->rps.up_threshold))
  1052.                         events |= GEN6_PM_RP_UP_THRESHOLD;
  1053.                 dev_priv->rps.up_ei = now;
  1054.         }
  1055.  
  1056.         return events;
  1057. }
  1058.  
  1059. static bool any_waiters(struct drm_i915_private *dev_priv)
  1060. {
  1061.         struct intel_engine_cs *ring;
  1062.         int i;
  1063.  
  1064.         for_each_ring(ring, dev_priv, i)
  1065.                 if (ring->irq_refcount)
  1066.                         return true;
  1067.  
  1068.         return false;
  1069. }
  1070.  
  1071. static void gen6_pm_rps_work(struct work_struct *work)
  1072. {
  1073.         struct drm_i915_private *dev_priv =
  1074.                 container_of(work, struct drm_i915_private, rps.work);
  1075.         bool client_boost;
  1076.         int new_delay, adj, min, max;
  1077.         u32 pm_iir;
  1078.  
  1079.         spin_lock_irq(&dev_priv->irq_lock);
  1080.         /* Speed up work cancelation during disabling rps interrupts. */
  1081.         if (!dev_priv->rps.interrupts_enabled) {
  1082.                 spin_unlock_irq(&dev_priv->irq_lock);
  1083.                 return;
  1084.         }
  1085.         pm_iir = dev_priv->rps.pm_iir;
  1086.         dev_priv->rps.pm_iir = 0;
  1087.         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
  1088.         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
  1089.         client_boost = dev_priv->rps.client_boost;
  1090.         dev_priv->rps.client_boost = false;
  1091.         spin_unlock_irq(&dev_priv->irq_lock);
  1092.  
  1093.         /* Make sure we didn't queue anything we're not going to process. */
  1094.         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
  1095.  
  1096.         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
  1097.                 return;
  1098.  
  1099.         mutex_lock(&dev_priv->rps.hw_lock);
  1100.  
  1101.         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
  1102.  
  1103.         adj = dev_priv->rps.last_adj;
  1104.         new_delay = dev_priv->rps.cur_freq;
  1105.         min = dev_priv->rps.min_freq_softlimit;
  1106.         max = dev_priv->rps.max_freq_softlimit;
  1107.  
  1108.         if (client_boost) {
  1109.                 new_delay = dev_priv->rps.max_freq_softlimit;
  1110.                 adj = 0;
  1111.         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
  1112.                 if (adj > 0)
  1113.                         adj *= 2;
  1114.                 else /* CHV needs even encode values */
  1115.                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
  1116.                 /*
  1117.                  * For better performance, jump directly
  1118.                  * to RPe if we're below it.
  1119.                  */
  1120.                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
  1121.                         new_delay = dev_priv->rps.efficient_freq;
  1122.                         adj = 0;
  1123.                 }
  1124.         } else if (any_waiters(dev_priv)) {
  1125.                 adj = 0;
  1126.         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
  1127.                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
  1128.                         new_delay = dev_priv->rps.efficient_freq;
  1129.                 else
  1130.                         new_delay = dev_priv->rps.min_freq_softlimit;
  1131.                 adj = 0;
  1132.         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
  1133.                 if (adj < 0)
  1134.                         adj *= 2;
  1135.                 else /* CHV needs even encode values */
  1136.                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
  1137.         } else { /* unknown event */
  1138.                 adj = 0;
  1139.         }
  1140.  
  1141.         dev_priv->rps.last_adj = adj;
  1142.  
  1143.         /* sysfs frequency interfaces may have snuck in while servicing the
  1144.          * interrupt
  1145.          */
  1146.         new_delay += adj;
  1147.         new_delay = clamp_t(int, new_delay, min, max);
  1148.  
  1149.         intel_set_rps(dev_priv->dev, new_delay);
  1150.  
  1151.         mutex_unlock(&dev_priv->rps.hw_lock);
  1152. }
  1153.  
  1154.  
  1155. /**
  1156.  * ivybridge_parity_work - Workqueue called when a parity error interrupt
  1157.  * occurred.
  1158.  * @work: workqueue struct
  1159.  *
  1160.  * Doesn't actually do anything except notify userspace. As a consequence of
  1161.  * this event, userspace should try to remap the bad rows since statistically
  1162.  * it is likely the same row is more likely to go bad again.
  1163.  */
  1164. static void ivybridge_parity_work(struct work_struct *work)
  1165. {
  1166.         struct drm_i915_private *dev_priv =
  1167.                 container_of(work, struct drm_i915_private, l3_parity.error_work);
  1168.         u32 error_status, row, bank, subbank;
  1169.         char *parity_event[6];
  1170.         uint32_t misccpctl;
  1171.         uint8_t slice = 0;
  1172.  
  1173.         /* We must turn off DOP level clock gating to access the L3 registers.
  1174.          * In order to prevent a get/put style interface, acquire struct mutex
  1175.          * any time we access those registers.
  1176.          */
  1177.         mutex_lock(&dev_priv->dev->struct_mutex);
  1178.  
  1179.         /* If we've screwed up tracking, just let the interrupt fire again */
  1180.         if (WARN_ON(!dev_priv->l3_parity.which_slice))
  1181.                 goto out;
  1182.  
  1183.         misccpctl = I915_READ(GEN7_MISCCPCTL);
  1184.         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  1185.         POSTING_READ(GEN7_MISCCPCTL);
  1186.  
  1187.         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
  1188.                 u32 reg;
  1189.  
  1190.                 slice--;
  1191.                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
  1192.                         break;
  1193.  
  1194.                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
  1195.  
  1196.                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
  1197.  
  1198.                 error_status = I915_READ(reg);
  1199.                 row = GEN7_PARITY_ERROR_ROW(error_status);
  1200.                 bank = GEN7_PARITY_ERROR_BANK(error_status);
  1201.                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  1202.  
  1203.                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
  1204.                 POSTING_READ(reg);
  1205.  
  1206.                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
  1207.                           slice, row, bank, subbank);
  1208.  
  1209.         }
  1210.  
  1211.         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  1212.  
  1213. out:
  1214.         WARN_ON(dev_priv->l3_parity.which_slice);
  1215.         spin_lock_irq(&dev_priv->irq_lock);
  1216.         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
  1217.         spin_unlock_irq(&dev_priv->irq_lock);
  1218.  
  1219.         mutex_unlock(&dev_priv->dev->struct_mutex);
  1220. }
  1221.  
  1222. static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
  1223. {
  1224.         struct drm_i915_private *dev_priv = dev->dev_private;
  1225.  
  1226.         if (!HAS_L3_DPF(dev))
  1227.                 return;
  1228.  
  1229.         spin_lock(&dev_priv->irq_lock);
  1230.         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
  1231.         spin_unlock(&dev_priv->irq_lock);
  1232.  
  1233.         iir &= GT_PARITY_ERROR(dev);
  1234.         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
  1235.                 dev_priv->l3_parity.which_slice |= 1 << 1;
  1236.  
  1237.         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
  1238.                 dev_priv->l3_parity.which_slice |= 1 << 0;
  1239.  
  1240.         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  1241. }
  1242.  
  1243. static void ilk_gt_irq_handler(struct drm_device *dev,
  1244.                                struct drm_i915_private *dev_priv,
  1245.                                u32 gt_iir)
  1246. {
  1247.         if (gt_iir &
  1248.             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
  1249.                 notify_ring(&dev_priv->ring[RCS]);
  1250.         if (gt_iir & ILK_BSD_USER_INTERRUPT)
  1251.                 notify_ring(&dev_priv->ring[VCS]);
  1252. }
  1253.  
  1254. static void snb_gt_irq_handler(struct drm_device *dev,
  1255.                                struct drm_i915_private *dev_priv,
  1256.                                u32 gt_iir)
  1257. {
  1258.  
  1259.         if (gt_iir &
  1260.             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
  1261.                 notify_ring(&dev_priv->ring[RCS]);
  1262.         if (gt_iir & GT_BSD_USER_INTERRUPT)
  1263.                 notify_ring(&dev_priv->ring[VCS]);
  1264.         if (gt_iir & GT_BLT_USER_INTERRUPT)
  1265.                 notify_ring(&dev_priv->ring[BCS]);
  1266.  
  1267.         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
  1268.                       GT_BSD_CS_ERROR_INTERRUPT |
  1269.                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
  1270.                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
  1271.  
  1272.         if (gt_iir & GT_PARITY_ERROR(dev))
  1273.                 ivybridge_parity_error_irq_handler(dev, gt_iir);
  1274. }
  1275.  
  1276. static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
  1277.                                        u32 master_ctl)
  1278. {
  1279.         irqreturn_t ret = IRQ_NONE;
  1280.  
  1281.         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
  1282.                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
  1283.                 if (tmp) {
  1284.                         I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
  1285.                         ret = IRQ_HANDLED;
  1286.  
  1287.                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
  1288.                                 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
  1289.                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
  1290.                                 notify_ring(&dev_priv->ring[RCS]);
  1291.  
  1292.                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
  1293.                                 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
  1294.                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
  1295.                                 notify_ring(&dev_priv->ring[BCS]);
  1296.                 } else
  1297.                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
  1298.         }
  1299.  
  1300.         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
  1301.                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
  1302.                 if (tmp) {
  1303.                         I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
  1304.                         ret = IRQ_HANDLED;
  1305.  
  1306.                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
  1307.                                 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
  1308.                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
  1309.                                 notify_ring(&dev_priv->ring[VCS]);
  1310.  
  1311.                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
  1312.                                 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
  1313.                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
  1314.                                 notify_ring(&dev_priv->ring[VCS2]);
  1315.                 } else
  1316.                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
  1317.         }
  1318.  
  1319.         if (master_ctl & GEN8_GT_VECS_IRQ) {
  1320.                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
  1321.                 if (tmp) {
  1322.                         I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
  1323.                         ret = IRQ_HANDLED;
  1324.  
  1325.                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
  1326.                                 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
  1327.                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
  1328.                                 notify_ring(&dev_priv->ring[VECS]);
  1329.                 } else
  1330.                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
  1331.         }
  1332.  
  1333.         if (master_ctl & GEN8_GT_PM_IRQ) {
  1334.                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
  1335.                 if (tmp & dev_priv->pm_rps_events) {
  1336.                         I915_WRITE_FW(GEN8_GT_IIR(2),
  1337.                                       tmp & dev_priv->pm_rps_events);
  1338.                         ret = IRQ_HANDLED;
  1339.                         gen6_rps_irq_handler(dev_priv, tmp);
  1340.                 } else
  1341.                         DRM_ERROR("The master control interrupt lied (PM)!\n");
  1342.         }
  1343.  
  1344.         return ret;
  1345. }
  1346.  
  1347. static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
  1348. {
  1349.         switch (port) {
  1350.         case PORT_A:
  1351.                 return val & PORTA_HOTPLUG_LONG_DETECT;
  1352.         case PORT_B:
  1353.                 return val & PORTB_HOTPLUG_LONG_DETECT;
  1354.         case PORT_C:
  1355.                 return val & PORTC_HOTPLUG_LONG_DETECT;
  1356.         default:
  1357.                 return false;
  1358.         }
  1359. }
  1360.  
  1361. static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
  1362. {
  1363.         switch (port) {
  1364.         case PORT_E:
  1365.                 return val & PORTE_HOTPLUG_LONG_DETECT;
  1366.         default:
  1367.                 return false;
  1368.         }
  1369. }
  1370.  
  1371. static bool spt_port_hotplug_long_detect(enum port port, u32 val)
  1372. {
  1373.         switch (port) {
  1374.         case PORT_A:
  1375.                 return val & PORTA_HOTPLUG_LONG_DETECT;
  1376.         case PORT_B:
  1377.                 return val & PORTB_HOTPLUG_LONG_DETECT;
  1378.         case PORT_C:
  1379.                 return val & PORTC_HOTPLUG_LONG_DETECT;
  1380.         case PORT_D:
  1381.                 return val & PORTD_HOTPLUG_LONG_DETECT;
  1382.         default:
  1383.                 return false;
  1384.         }
  1385. }
  1386.  
  1387. static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
  1388. {
  1389.         switch (port) {
  1390.         case PORT_A:
  1391.                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
  1392.         default:
  1393.                 return false;
  1394.         }
  1395. }
  1396.  
  1397. static bool pch_port_hotplug_long_detect(enum port port, u32 val)
  1398. {
  1399.         switch (port) {
  1400.         case PORT_B:
  1401.                 return val & PORTB_HOTPLUG_LONG_DETECT;
  1402.         case PORT_C:
  1403.                 return val & PORTC_HOTPLUG_LONG_DETECT;
  1404.         case PORT_D:
  1405.                 return val & PORTD_HOTPLUG_LONG_DETECT;
  1406.         default:
  1407.                 return false;
  1408.         }
  1409. }
  1410.  
  1411. static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
  1412. {
  1413.         switch (port) {
  1414.         case PORT_B:
  1415.                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
  1416.         case PORT_C:
  1417.                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
  1418.         case PORT_D:
  1419.                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
  1420.         default:
  1421.                 return false;
  1422.         }
  1423. }
  1424.  
  1425. /*
  1426.  * Get a bit mask of pins that have triggered, and which ones may be long.
  1427.  * This can be called multiple times with the same masks to accumulate
  1428.  * hotplug detection results from several registers.
  1429.  *
  1430.  * Note that the caller is expected to zero out the masks initially.
  1431.  */
  1432. static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
  1433.                              u32 hotplug_trigger, u32 dig_hotplug_reg,
  1434.                              const u32 hpd[HPD_NUM_PINS],
  1435.                              bool long_pulse_detect(enum port port, u32 val))
  1436. {
  1437.         enum port port;
  1438.         int i;
  1439.  
  1440.         for_each_hpd_pin(i) {
  1441.                 if ((hpd[i] & hotplug_trigger) == 0)
  1442.                         continue;
  1443.  
  1444.                 *pin_mask |= BIT(i);
  1445.  
  1446. //       if (!intel_hpd_pin_to_port(i, &port))
  1447.                         continue;
  1448.  
  1449.                 if (long_pulse_detect(port, dig_hotplug_reg))
  1450.                         *long_mask |= BIT(i);
  1451.         }
  1452.  
  1453.         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
  1454.                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
  1455.  
  1456. }
  1457.  
  1458. static void gmbus_irq_handler(struct drm_device *dev)
  1459. {
  1460.         struct drm_i915_private *dev_priv = dev->dev_private;
  1461.  
  1462.         wake_up_all(&dev_priv->gmbus_wait_queue);
  1463. }
  1464.  
  1465. static void dp_aux_irq_handler(struct drm_device *dev)
  1466. {
  1467.         struct drm_i915_private *dev_priv = dev->dev_private;
  1468.  
  1469.         wake_up_all(&dev_priv->gmbus_wait_queue);
  1470. }
  1471.  
  1472. #if defined(CONFIG_DEBUG_FS)
  1473. static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
  1474.                                          uint32_t crc0, uint32_t crc1,
  1475.                                          uint32_t crc2, uint32_t crc3,
  1476.                                          uint32_t crc4)
  1477. {
  1478.         struct drm_i915_private *dev_priv = dev->dev_private;
  1479.         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
  1480.         struct intel_pipe_crc_entry *entry;
  1481.         int head, tail;
  1482.  
  1483.         spin_lock(&pipe_crc->lock);
  1484.  
  1485.         if (!pipe_crc->entries) {
  1486.                 spin_unlock(&pipe_crc->lock);
  1487.                 DRM_DEBUG_KMS("spurious interrupt\n");
  1488.                 return;
  1489.         }
  1490.  
  1491.         head = pipe_crc->head;
  1492.         tail = pipe_crc->tail;
  1493.  
  1494.         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
  1495.                 spin_unlock(&pipe_crc->lock);
  1496.                 DRM_ERROR("CRC buffer overflowing\n");
  1497.                 return;
  1498.         }
  1499.  
  1500.         entry = &pipe_crc->entries[head];
  1501.  
  1502.         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
  1503.         entry->crc[0] = crc0;
  1504.         entry->crc[1] = crc1;
  1505.         entry->crc[2] = crc2;
  1506.         entry->crc[3] = crc3;
  1507.         entry->crc[4] = crc4;
  1508.  
  1509.         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
  1510.         pipe_crc->head = head;
  1511.  
  1512.         spin_unlock(&pipe_crc->lock);
  1513.  
  1514.         wake_up_interruptible(&pipe_crc->wq);
  1515. }
  1516. #else
  1517. static inline void
  1518. display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
  1519.                              uint32_t crc0, uint32_t crc1,
  1520.                              uint32_t crc2, uint32_t crc3,
  1521.                              uint32_t crc4) {}
  1522. #endif
  1523.  
  1524.  
  1525. static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
  1526. {
  1527.         struct drm_i915_private *dev_priv = dev->dev_private;
  1528.  
  1529.         display_pipe_crc_irq_handler(dev, pipe,
  1530.                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
  1531.                                      0, 0, 0, 0);
  1532. }
  1533.  
  1534. static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
  1535. {
  1536.         struct drm_i915_private *dev_priv = dev->dev_private;
  1537.  
  1538.         display_pipe_crc_irq_handler(dev, pipe,
  1539.                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
  1540.                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
  1541.                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
  1542.                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
  1543.                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
  1544. }
  1545.  
  1546. static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
  1547. {
  1548.         struct drm_i915_private *dev_priv = dev->dev_private;
  1549.         uint32_t res1, res2;
  1550.  
  1551.         if (INTEL_INFO(dev)->gen >= 3)
  1552.                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
  1553.         else
  1554.                 res1 = 0;
  1555.  
  1556.         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
  1557.                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
  1558.         else
  1559.                 res2 = 0;
  1560.  
  1561.         display_pipe_crc_irq_handler(dev, pipe,
  1562.                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
  1563.                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
  1564.                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
  1565.                                      res1, res2);
  1566. }
  1567.  
  1568. /* The RPS events need forcewake, so we add them to a work queue and mask their
  1569.  * IMR bits until the work is done. Other interrupts can be processed without
  1570.  * the work queue. */
  1571. static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
  1572. {
  1573.         if (pm_iir & dev_priv->pm_rps_events) {
  1574.                 spin_lock(&dev_priv->irq_lock);
  1575.                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
  1576.                 if (dev_priv->rps.interrupts_enabled) {
  1577.                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
  1578.                         queue_work(dev_priv->wq, &dev_priv->rps.work);
  1579.                 }
  1580.                 spin_unlock(&dev_priv->irq_lock);
  1581.         }
  1582.  
  1583.         if (INTEL_INFO(dev_priv)->gen >= 8)
  1584.                 return;
  1585.  
  1586.         if (HAS_VEBOX(dev_priv->dev)) {
  1587.                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
  1588.                         notify_ring(&dev_priv->ring[VECS]);
  1589.  
  1590.                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
  1591.                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
  1592.         }
  1593. }
  1594.  
  1595. static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
  1596. {
  1597. //   if (!drm_handle_vblank(dev, pipe))
  1598. //       return false;
  1599.  
  1600.         return true;
  1601. }
  1602.  
  1603. static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
  1604. {
  1605.         struct drm_i915_private *dev_priv = dev->dev_private;
  1606.         u32 pipe_stats[I915_MAX_PIPES] = { };
  1607.         int pipe;
  1608.  
  1609.         spin_lock(&dev_priv->irq_lock);
  1610.         for_each_pipe(dev_priv, pipe) {
  1611.                 int reg;
  1612.                 u32 mask, iir_bit = 0;
  1613.  
  1614.                 /*
  1615.                  * PIPESTAT bits get signalled even when the interrupt is
  1616.                  * disabled with the mask bits, and some of the status bits do
  1617.                  * not generate interrupts at all (like the underrun bit). Hence
  1618.                  * we need to be careful that we only handle what we want to
  1619.                  * handle.
  1620.                  */
  1621.  
  1622.                 /* fifo underruns are filterered in the underrun handler. */
  1623.                 mask = PIPE_FIFO_UNDERRUN_STATUS;
  1624.  
  1625.                 switch (pipe) {
  1626.                 case PIPE_A:
  1627.                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
  1628.                         break;
  1629.                 case PIPE_B:
  1630.                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
  1631.                         break;
  1632.                 case PIPE_C:
  1633.                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
  1634.                         break;
  1635.                 }
  1636.                 if (iir & iir_bit)
  1637.                         mask |= dev_priv->pipestat_irq_mask[pipe];
  1638.  
  1639.                 if (!mask)
  1640.                         continue;
  1641.  
  1642.                 reg = PIPESTAT(pipe);
  1643.                 mask |= PIPESTAT_INT_ENABLE_MASK;
  1644.                 pipe_stats[pipe] = I915_READ(reg) & mask;
  1645.  
  1646.                 /*
  1647.                  * Clear the PIPE*STAT regs before the IIR
  1648.                  */
  1649.                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
  1650.                                         PIPESTAT_INT_STATUS_MASK))
  1651.                         I915_WRITE(reg, pipe_stats[pipe]);
  1652.         }
  1653.         spin_unlock(&dev_priv->irq_lock);
  1654.  
  1655.         for_each_pipe(dev_priv, pipe) {
  1656.                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  1657.                     intel_pipe_handle_vblank(dev, pipe))
  1658.             /*intel_check_page_flip(dev, pipe)*/;
  1659.  
  1660.                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
  1661. //           intel_prepare_page_flip(dev, pipe);
  1662. //           intel_finish_page_flip(dev, pipe);
  1663.                 }
  1664.  
  1665.                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
  1666.                         i9xx_pipe_crc_irq_handler(dev, pipe);
  1667.  
  1668.                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  1669.                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
  1670.         }
  1671.  
  1672.         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  1673.                 gmbus_irq_handler(dev);
  1674. }
  1675.  
  1676. static void i9xx_hpd_irq_handler(struct drm_device *dev)
  1677. {
  1678.         struct drm_i915_private *dev_priv = dev->dev_private;
  1679.         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  1680.         u32 pin_mask = 0, long_mask = 0;
  1681.  
  1682.         if (!hotplug_status)
  1683.                 return;
  1684.  
  1685.         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  1686.         /*
  1687.          * Make sure hotplug status is cleared before we clear IIR, or else we
  1688.          * may miss hotplug events.
  1689.          */
  1690.         POSTING_READ(PORT_HOTPLUG_STAT);
  1691.  
  1692.         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  1693.                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
  1694.  
  1695.                 if (hotplug_trigger) {
  1696.                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
  1697.                                            hotplug_trigger, hpd_status_g4x,
  1698.                                            i9xx_port_hotplug_long_detect);
  1699.  
  1700. //           intel_hpd_irq_handler(dev, pin_mask, long_mask);
  1701.                 }
  1702.  
  1703.                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
  1704.                         dp_aux_irq_handler(dev);
  1705.         } else {
  1706.                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  1707.  
  1708.                 if (hotplug_trigger) {
  1709.                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
  1710.                                            hotplug_trigger, hpd_status_i915,
  1711.                                            i9xx_port_hotplug_long_detect);
  1712. //           intel_hpd_irq_handler(dev, pin_mask, long_mask);
  1713.                 }
  1714.         }
  1715. }
  1716.  
  1717. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  1718. {
  1719.         struct drm_device *dev = arg;
  1720.         struct drm_i915_private *dev_priv = dev->dev_private;
  1721.         u32 iir, gt_iir, pm_iir;
  1722.         irqreturn_t ret = IRQ_NONE;
  1723.  
  1724.         if (!intel_irqs_enabled(dev_priv))
  1725.                 return IRQ_NONE;
  1726.  
  1727.         while (true) {
  1728.                 /* Find, clear, then process each source of interrupt */
  1729.  
  1730.                 gt_iir = I915_READ(GTIIR);
  1731.                 if (gt_iir)
  1732.                         I915_WRITE(GTIIR, gt_iir);
  1733.  
  1734.                 pm_iir = I915_READ(GEN6_PMIIR);
  1735.                 if (pm_iir)
  1736.                         I915_WRITE(GEN6_PMIIR, pm_iir);
  1737.  
  1738.                 iir = I915_READ(VLV_IIR);
  1739.                 if (iir) {
  1740.                         /* Consume port before clearing IIR or we'll miss events */
  1741.                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
  1742.                                 i9xx_hpd_irq_handler(dev);
  1743.                         I915_WRITE(VLV_IIR, iir);
  1744.                 }
  1745.  
  1746.                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  1747.                         goto out;
  1748.  
  1749.                 ret = IRQ_HANDLED;
  1750.  
  1751.                 if (gt_iir)
  1752.                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
  1753.                 if (pm_iir)
  1754.                         gen6_rps_irq_handler(dev_priv, pm_iir);
  1755.                 /* Call regardless, as some status bits might not be
  1756.                  * signalled in iir */
  1757.                 valleyview_pipestat_irq_handler(dev, iir);
  1758.         }
  1759.  
  1760. out:
  1761.         return ret;
  1762. }
  1763.  
  1764. static irqreturn_t cherryview_irq_handler(int irq, void *arg)
  1765. {
  1766.         struct drm_device *dev = arg;
  1767.         struct drm_i915_private *dev_priv = dev->dev_private;
  1768.         u32 master_ctl, iir;
  1769.         irqreturn_t ret = IRQ_NONE;
  1770.  
  1771.         if (!intel_irqs_enabled(dev_priv))
  1772.                 return IRQ_NONE;
  1773.  
  1774.         for (;;) {
  1775.                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
  1776.                 iir = I915_READ(VLV_IIR);
  1777.  
  1778.                 if (master_ctl == 0 && iir == 0)
  1779.                         break;
  1780.  
  1781.                 ret = IRQ_HANDLED;
  1782.  
  1783.                 I915_WRITE(GEN8_MASTER_IRQ, 0);
  1784.  
  1785.                 /* Find, clear, then process each source of interrupt */
  1786.  
  1787.                 if (iir) {
  1788.                         /* Consume port before clearing IIR or we'll miss events */
  1789.                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
  1790.                                 i9xx_hpd_irq_handler(dev);
  1791.                         I915_WRITE(VLV_IIR, iir);
  1792.                 }
  1793.  
  1794.                 gen8_gt_irq_handler(dev_priv, master_ctl);
  1795.  
  1796.                 /* Call regardless, as some status bits might not be
  1797.                  * signalled in iir */
  1798.                 valleyview_pipestat_irq_handler(dev, iir);
  1799.  
  1800.                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
  1801.                 POSTING_READ(GEN8_MASTER_IRQ);
  1802.         }
  1803.  
  1804.         return ret;
  1805. }
  1806.  
  1807. static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
  1808.                                 const u32 hpd[HPD_NUM_PINS])
  1809. {
  1810.         struct drm_i915_private *dev_priv = to_i915(dev);
  1811.         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
  1812.  
  1813.         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
  1814.         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
  1815.  
  1816.         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
  1817.                            dig_hotplug_reg, hpd,
  1818.                            pch_port_hotplug_long_detect);
  1819.  
  1820. //   intel_hpd_irq_handler(dev, pin_mask, long_mask);
  1821. }
  1822.  
  1823. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  1824. {
  1825.         struct drm_i915_private *dev_priv = dev->dev_private;
  1826.         int pipe;
  1827.         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
  1828.  
  1829.         if (hotplug_trigger)
  1830.                 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
  1831.  
  1832.         if (pch_iir & SDE_AUDIO_POWER_MASK) {
  1833.                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
  1834.                                SDE_AUDIO_POWER_SHIFT);
  1835.                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  1836.                                  port_name(port));
  1837.         }
  1838.  
  1839.         if (pch_iir & SDE_AUX_MASK)
  1840.                 dp_aux_irq_handler(dev);
  1841.  
  1842.         if (pch_iir & SDE_GMBUS)
  1843.                 gmbus_irq_handler(dev);
  1844.  
  1845.         if (pch_iir & SDE_AUDIO_HDCP_MASK)
  1846.                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  1847.  
  1848.         if (pch_iir & SDE_AUDIO_TRANS_MASK)
  1849.                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  1850.  
  1851.         if (pch_iir & SDE_POISON)
  1852.                 DRM_ERROR("PCH poison interrupt\n");
  1853.  
  1854.         if (pch_iir & SDE_FDI_MASK)
  1855.                 for_each_pipe(dev_priv, pipe)
  1856.                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
  1857.                                          pipe_name(pipe),
  1858.                                          I915_READ(FDI_RX_IIR(pipe)));
  1859.  
  1860.         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  1861.                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  1862.  
  1863.         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  1864.                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  1865.  
  1866.         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  1867.                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
  1868.  
  1869.         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  1870.                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
  1871. }
  1872.  
  1873. static void ivb_err_int_handler(struct drm_device *dev)
  1874. {
  1875.         struct drm_i915_private *dev_priv = dev->dev_private;
  1876.         u32 err_int = I915_READ(GEN7_ERR_INT);
  1877.         enum pipe pipe;
  1878.  
  1879.         if (err_int & ERR_INT_POISON)
  1880.                 DRM_ERROR("Poison interrupt\n");
  1881.  
  1882.         for_each_pipe(dev_priv, pipe) {
  1883.                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
  1884.                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
  1885.  
  1886.                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
  1887.                         if (IS_IVYBRIDGE(dev))
  1888.                                 ivb_pipe_crc_irq_handler(dev, pipe);
  1889.                         else
  1890.                                 hsw_pipe_crc_irq_handler(dev, pipe);
  1891.                 }
  1892.         }
  1893.  
  1894.         I915_WRITE(GEN7_ERR_INT, err_int);
  1895. }
  1896.  
  1897. static void cpt_serr_int_handler(struct drm_device *dev)
  1898. {
  1899.         struct drm_i915_private *dev_priv = dev->dev_private;
  1900.         u32 serr_int = I915_READ(SERR_INT);
  1901.  
  1902.         if (serr_int & SERR_INT_POISON)
  1903.                 DRM_ERROR("PCH poison interrupt\n");
  1904.  
  1905.         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
  1906.                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
  1907.  
  1908.         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
  1909.                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
  1910.  
  1911.         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
  1912.                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
  1913.  
  1914.         I915_WRITE(SERR_INT, serr_int);
  1915. }
  1916.  
  1917. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  1918. {
  1919.         struct drm_i915_private *dev_priv = dev->dev_private;
  1920.         int pipe;
  1921.         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
  1922.  
  1923.         if (hotplug_trigger)
  1924.                 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
  1925.  
  1926.         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
  1927.                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  1928.                                SDE_AUDIO_POWER_SHIFT_CPT);
  1929.                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
  1930.                                  port_name(port));
  1931.         }
  1932.  
  1933.         if (pch_iir & SDE_AUX_MASK_CPT)
  1934.                 dp_aux_irq_handler(dev);
  1935.  
  1936.         if (pch_iir & SDE_GMBUS_CPT)
  1937.                 gmbus_irq_handler(dev);
  1938.  
  1939.         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  1940.                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  1941.  
  1942.         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  1943.                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  1944.  
  1945.         if (pch_iir & SDE_FDI_MASK_CPT)
  1946.                 for_each_pipe(dev_priv, pipe)
  1947.                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
  1948.                                          pipe_name(pipe),
  1949.                                          I915_READ(FDI_RX_IIR(pipe)));
  1950.  
  1951.         if (pch_iir & SDE_ERROR_CPT)
  1952.                 cpt_serr_int_handler(dev);
  1953. }
  1954.  
  1955. static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
  1956. {
  1957.         struct drm_i915_private *dev_priv = dev->dev_private;
  1958.         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
  1959.                 ~SDE_PORTE_HOTPLUG_SPT;
  1960.         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
  1961.         u32 pin_mask = 0, long_mask = 0;
  1962.  
  1963.         if (hotplug_trigger) {
  1964.                 u32 dig_hotplug_reg;
  1965.  
  1966.                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
  1967.                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
  1968.  
  1969.                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
  1970.                                    dig_hotplug_reg, hpd_spt,
  1971.                                    spt_port_hotplug_long_detect);
  1972.         }
  1973.  
  1974.         if (hotplug2_trigger) {
  1975.                 u32 dig_hotplug_reg;
  1976.  
  1977.                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
  1978.                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
  1979.  
  1980.                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
  1981.                                    dig_hotplug_reg, hpd_spt,
  1982.                                    spt_port_hotplug2_long_detect);
  1983.         }
  1984.  
  1985.         if (pch_iir & SDE_GMBUS_CPT)
  1986.                 gmbus_irq_handler(dev);
  1987. }
  1988.  
  1989. static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
  1990.                                 const u32 hpd[HPD_NUM_PINS])
  1991. {
  1992.         struct drm_i915_private *dev_priv = to_i915(dev);
  1993.         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
  1994.  
  1995.         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
  1996.         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
  1997.  
  1998.         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
  1999.                            dig_hotplug_reg, hpd,
  2000.                            ilk_port_hotplug_long_detect);
  2001.  
  2002. }
  2003.  
  2004. static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
  2005. {
  2006.         struct drm_i915_private *dev_priv = dev->dev_private;
  2007.         enum pipe pipe;
  2008.         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
  2009.  
  2010.         if (hotplug_trigger)
  2011.                 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
  2012.  
  2013.         if (de_iir & DE_AUX_CHANNEL_A)
  2014.                 dp_aux_irq_handler(dev);
  2015.  
  2016.         if (de_iir & DE_GSE)
  2017.                 intel_opregion_asle_intr(dev);
  2018.  
  2019.         if (de_iir & DE_POISON)
  2020.                 DRM_ERROR("Poison interrupt\n");
  2021.  
  2022.         for_each_pipe(dev_priv, pipe) {
  2023.                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
  2024.                     intel_pipe_handle_vblank(dev, pipe))
  2025.             /*intel_check_page_flip(dev, pipe)*/;
  2026.  
  2027.                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
  2028.                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
  2029.  
  2030.                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
  2031.                         i9xx_pipe_crc_irq_handler(dev, pipe);
  2032.  
  2033.                 /* plane/pipes map 1:1 on ilk+ */
  2034.                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
  2035. //                      intel_prepare_page_flip(dev, pipe);
  2036. //                      intel_finish_page_flip_plane(dev, pipe);
  2037.                 }
  2038.         }
  2039.  
  2040.         /* check event from PCH */
  2041.         if (de_iir & DE_PCH_EVENT) {
  2042.                 u32 pch_iir = I915_READ(SDEIIR);
  2043.  
  2044.                 if (HAS_PCH_CPT(dev))
  2045.                         cpt_irq_handler(dev, pch_iir);
  2046.                 else
  2047.                         ibx_irq_handler(dev, pch_iir);
  2048.  
  2049.                 /* should clear PCH hotplug event before clear CPU irq */
  2050.                 I915_WRITE(SDEIIR, pch_iir);
  2051.         }
  2052.  
  2053.         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  2054.                 ironlake_rps_change_irq_handler(dev);
  2055. }
  2056.  
  2057. static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
  2058. {
  2059.         struct drm_i915_private *dev_priv = dev->dev_private;
  2060.         enum pipe pipe;
  2061.         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
  2062.  
  2063.         if (hotplug_trigger)
  2064.                 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
  2065.  
  2066.         if (de_iir & DE_ERR_INT_IVB)
  2067.                 ivb_err_int_handler(dev);
  2068.  
  2069.         if (de_iir & DE_AUX_CHANNEL_A_IVB)
  2070.                 dp_aux_irq_handler(dev);
  2071.  
  2072.         if (de_iir & DE_GSE_IVB)
  2073.                 intel_opregion_asle_intr(dev);
  2074.  
  2075.         for_each_pipe(dev_priv, pipe) {
  2076.                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
  2077.                     intel_pipe_handle_vblank(dev, pipe))
  2078.             /*intel_check_page_flip(dev, pipe)*/;
  2079.  
  2080.                 /* plane/pipes map 1:1 on ilk+ */
  2081.                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
  2082. //                      intel_prepare_page_flip(dev, pipe);
  2083. //                      intel_finish_page_flip_plane(dev, pipe);
  2084.                 }
  2085.         }
  2086.  
  2087.         /* check event from PCH */
  2088.         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
  2089.                 u32 pch_iir = I915_READ(SDEIIR);
  2090.  
  2091.                 cpt_irq_handler(dev, pch_iir);
  2092.  
  2093.                 /* clear PCH hotplug event before clear CPU irq */
  2094.                 I915_WRITE(SDEIIR, pch_iir);
  2095.         }
  2096. }
  2097.  
  2098. /*
  2099.  * To handle irqs with the minimum potential races with fresh interrupts, we:
  2100.  * 1 - Disable Master Interrupt Control.
  2101.  * 2 - Find the source(s) of the interrupt.
  2102.  * 3 - Clear the Interrupt Identity bits (IIR).
  2103.  * 4 - Process the interrupt(s) that had bits set in the IIRs.
  2104.  * 5 - Re-enable Master Interrupt Control.
  2105.  */
  2106. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  2107. {
  2108.         struct drm_device *dev = arg;
  2109.         struct drm_i915_private *dev_priv = dev->dev_private;
  2110.         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
  2111.         irqreturn_t ret = IRQ_NONE;
  2112.  
  2113.         if (!intel_irqs_enabled(dev_priv))
  2114.                 return IRQ_NONE;
  2115.  
  2116.         /* We get interrupts on unclaimed registers, so check for this before we
  2117.          * do any I915_{READ,WRITE}. */
  2118.         intel_uncore_check_errors(dev);
  2119.  
  2120.         /* disable master interrupt before clearing iir  */
  2121.         de_ier = I915_READ(DEIER);
  2122.         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  2123.         POSTING_READ(DEIER);
  2124.  
  2125.         /* Disable south interrupts. We'll only write to SDEIIR once, so further
  2126.          * interrupts will will be stored on its back queue, and then we'll be
  2127.          * able to process them after we restore SDEIER (as soon as we restore
  2128.          * it, we'll get an interrupt if SDEIIR still has something to process
  2129.          * due to its back queue). */
  2130.         if (!HAS_PCH_NOP(dev)) {
  2131.                 sde_ier = I915_READ(SDEIER);
  2132.                 I915_WRITE(SDEIER, 0);
  2133.                 POSTING_READ(SDEIER);
  2134.         }
  2135.  
  2136.         /* Find, clear, then process each source of interrupt */
  2137.  
  2138.         gt_iir = I915_READ(GTIIR);
  2139.         if (gt_iir) {
  2140.                 I915_WRITE(GTIIR, gt_iir);
  2141.                 ret = IRQ_HANDLED;
  2142.                 if (INTEL_INFO(dev)->gen >= 6)
  2143.                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
  2144.                 else
  2145.                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  2146.         }
  2147.  
  2148.         de_iir = I915_READ(DEIIR);
  2149.         if (de_iir) {
  2150.                 I915_WRITE(DEIIR, de_iir);
  2151.                 ret = IRQ_HANDLED;
  2152.                 if (INTEL_INFO(dev)->gen >= 7)
  2153.                         ivb_display_irq_handler(dev, de_iir);
  2154.                 else
  2155.                         ilk_display_irq_handler(dev, de_iir);
  2156.         }
  2157.  
  2158.         if (INTEL_INFO(dev)->gen >= 6) {
  2159.                 u32 pm_iir = I915_READ(GEN6_PMIIR);
  2160.                 if (pm_iir) {
  2161.                         I915_WRITE(GEN6_PMIIR, pm_iir);
  2162.                         ret = IRQ_HANDLED;
  2163.                         gen6_rps_irq_handler(dev_priv, pm_iir);
  2164.                 }
  2165.         }
  2166.  
  2167.         I915_WRITE(DEIER, de_ier);
  2168.         POSTING_READ(DEIER);
  2169.         if (!HAS_PCH_NOP(dev)) {
  2170.                 I915_WRITE(SDEIER, sde_ier);
  2171.                 POSTING_READ(SDEIER);
  2172.         }
  2173.  
  2174.         return ret;
  2175. }
  2176.  
  2177. static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
  2178.                                 const u32 hpd[HPD_NUM_PINS])
  2179. {
  2180.         struct drm_i915_private *dev_priv = to_i915(dev);
  2181.         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
  2182.  
  2183.         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
  2184.         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
  2185.  
  2186.         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
  2187.                            dig_hotplug_reg, hpd,
  2188.                            bxt_port_hotplug_long_detect);
  2189.  
  2190. }
  2191.  
  2192. static irqreturn_t gen8_irq_handler(int irq, void *arg)
  2193. {
  2194.         struct drm_device *dev = arg;
  2195.         struct drm_i915_private *dev_priv = dev->dev_private;
  2196.         u32 master_ctl;
  2197.         irqreturn_t ret = IRQ_NONE;
  2198.         uint32_t tmp = 0;
  2199.         enum pipe pipe;
  2200.         u32 aux_mask = GEN8_AUX_CHANNEL_A;
  2201.  
  2202.         if (!intel_irqs_enabled(dev_priv))
  2203.                 return IRQ_NONE;
  2204.  
  2205.         if (INTEL_INFO(dev_priv)->gen >= 9)
  2206.                 aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
  2207.                         GEN9_AUX_CHANNEL_D;
  2208.  
  2209.         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
  2210.         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
  2211.         if (!master_ctl)
  2212.                 return IRQ_NONE;
  2213.  
  2214.         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
  2215.  
  2216.         /* Find, clear, then process each source of interrupt */
  2217.  
  2218.         ret = gen8_gt_irq_handler(dev_priv, master_ctl);
  2219.  
  2220.         if (master_ctl & GEN8_DE_MISC_IRQ) {
  2221.                 tmp = I915_READ(GEN8_DE_MISC_IIR);
  2222.                 if (tmp) {
  2223.                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
  2224.                         ret = IRQ_HANDLED;
  2225.                         if (tmp & GEN8_DE_MISC_GSE)
  2226.                                 intel_opregion_asle_intr(dev);
  2227.                         else
  2228.                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
  2229.                 }
  2230.                 else
  2231.                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
  2232.         }
  2233.  
  2234.         if (master_ctl & GEN8_DE_PORT_IRQ) {
  2235.                 tmp = I915_READ(GEN8_DE_PORT_IIR);
  2236.                 if (tmp) {
  2237.                         bool found = false;
  2238.                         u32 hotplug_trigger = 0;
  2239.  
  2240.                         if (IS_BROXTON(dev_priv))
  2241.                                 hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
  2242.                         else if (IS_BROADWELL(dev_priv))
  2243.                                 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
  2244.  
  2245.                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
  2246.                         ret = IRQ_HANDLED;
  2247.  
  2248.                         if (tmp & aux_mask) {
  2249.                                 dp_aux_irq_handler(dev);
  2250.                                 found = true;
  2251.                         }
  2252.  
  2253.                         if (hotplug_trigger) {
  2254.                                 if (IS_BROXTON(dev))
  2255.                                         bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
  2256.                                 else
  2257.                                         ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
  2258.                                 found = true;
  2259.                         }
  2260.  
  2261.                         if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
  2262.                                 gmbus_irq_handler(dev);
  2263.                                 found = true;
  2264.                         }
  2265.  
  2266.                         if (!found)
  2267.                                 DRM_ERROR("Unexpected DE Port interrupt\n");
  2268.                 }
  2269.                 else
  2270.                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
  2271.         }
  2272.  
  2273.         for_each_pipe(dev_priv, pipe) {
  2274.                 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
  2275.  
  2276.                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
  2277.                         continue;
  2278.  
  2279.                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
  2280.                 if (pipe_iir) {
  2281.                         ret = IRQ_HANDLED;
  2282.                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
  2283.  
  2284.  
  2285.                         if (INTEL_INFO(dev_priv)->gen >= 9)
  2286.                                 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
  2287.                         else
  2288.                                 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
  2289.  
  2290.  
  2291.                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
  2292.                                 hsw_pipe_crc_irq_handler(dev, pipe);
  2293.  
  2294.                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
  2295.                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
  2296.                                                                     pipe);
  2297.  
  2298.  
  2299.                         if (INTEL_INFO(dev_priv)->gen >= 9)
  2300.                                 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
  2301.                         else
  2302.                                 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
  2303.  
  2304.                         if (fault_errors)
  2305.                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
  2306.                                           pipe_name(pipe),
  2307.                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
  2308.                 } else
  2309.                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
  2310.         }
  2311.  
  2312.         if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
  2313.             master_ctl & GEN8_DE_PCH_IRQ) {
  2314.                 /*
  2315.                  * FIXME(BDW): Assume for now that the new interrupt handling
  2316.                  * scheme also closed the SDE interrupt handling race we've seen
  2317.                  * on older pch-split platforms. But this needs testing.
  2318.                  */
  2319.                 u32 pch_iir = I915_READ(SDEIIR);
  2320.                 if (pch_iir) {
  2321.                         I915_WRITE(SDEIIR, pch_iir);
  2322.                         ret = IRQ_HANDLED;
  2323.  
  2324.                         if (HAS_PCH_SPT(dev_priv))
  2325.                                 spt_irq_handler(dev, pch_iir);
  2326.                         else
  2327.                                 cpt_irq_handler(dev, pch_iir);
  2328.                 } else
  2329.                         DRM_ERROR("The master control interrupt lied (SDE)!\n");
  2330.  
  2331.         }
  2332.  
  2333.         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
  2334.         POSTING_READ_FW(GEN8_MASTER_IRQ);
  2335.  
  2336.         return ret;
  2337. }
  2338.  
  2339. static void i915_error_wake_up(struct drm_i915_private *dev_priv,
  2340.                                bool reset_completed)
  2341. {
  2342.         struct intel_engine_cs *ring;
  2343.         int i;
  2344.  
  2345.         /*
  2346.          * Notify all waiters for GPU completion events that reset state has
  2347.          * been changed, and that they need to restart their wait after
  2348.          * checking for potential errors (and bail out to drop locks if there is
  2349.          * a gpu reset pending so that i915_error_work_func can acquire them).
  2350.          */
  2351.  
  2352.         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
  2353.         for_each_ring(ring, dev_priv, i)
  2354.                 wake_up_all(&ring->irq_queue);
  2355.  
  2356.  
  2357.         /*
  2358.          * Signal tasks blocked in i915_gem_wait_for_error that the pending
  2359.          * reset state is cleared.
  2360.          */
  2361.         if (reset_completed)
  2362.                 wake_up_all(&dev_priv->gpu_error.reset_queue);
  2363. }
  2364.  
  2365. /**
  2366.  * i915_reset_and_wakeup - do process context error handling work
  2367.  * @dev: drm device
  2368.  *
  2369.  * Fire an error uevent so userspace can see that a hang or error
  2370.  * was detected.
  2371.  */
  2372. static void i915_reset_and_wakeup(struct drm_device *dev)
  2373. {
  2374.         struct drm_i915_private *dev_priv = to_i915(dev);
  2375.         struct i915_gpu_error *error = &dev_priv->gpu_error;
  2376.         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
  2377.         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
  2378.         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
  2379.         int ret;
  2380.  
  2381.         /*
  2382.          * Note that there's only one work item which does gpu resets, so we
  2383.          * need not worry about concurrent gpu resets potentially incrementing
  2384.          * error->reset_counter twice. We only need to take care of another
  2385.          * racing irq/hangcheck declaring the gpu dead for a second time. A
  2386.          * quick check for that is good enough: schedule_work ensures the
  2387.          * correct ordering between hang detection and this work item, and since
  2388.          * the reset in-progress bit is only ever set by code outside of this
  2389.          * work we don't need to worry about any other races.
  2390.          */
  2391.         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
  2392.                 DRM_DEBUG_DRIVER("resetting chip\n");
  2393.                 intel_runtime_pm_get(dev_priv);
  2394.  
  2395.                 /*
  2396.                  * All state reset _must_ be completed before we update the
  2397.                  * reset counter, for otherwise waiters might miss the reset
  2398.                  * pending state and not properly drop locks, resulting in
  2399.                  * deadlocks with the reset work.
  2400.                  */
  2401. //              ret = i915_reset(dev);
  2402.  
  2403. //              intel_finish_reset(dev);
  2404.  
  2405.                 intel_runtime_pm_put(dev_priv);
  2406.  
  2407.                 if (ret == 0) {
  2408.                         /*
  2409.                          * After all the gem state is reset, increment the reset
  2410.                          * counter and wake up everyone waiting for the reset to
  2411.                          * complete.
  2412.                          *
  2413.                          * Since unlock operations are a one-sided barrier only,
  2414.                          * we need to insert a barrier here to order any seqno
  2415.                          * updates before
  2416.                          * the counter increment.
  2417.                          */
  2418.                         smp_mb__before_atomic();
  2419.                         atomic_inc(&dev_priv->gpu_error.reset_counter);
  2420.  
  2421.                 } else {
  2422.                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
  2423.         }
  2424.  
  2425.                 /*
  2426.                  * Note: The wake_up also serves as a memory barrier so that
  2427.                  * waiters see the update value of the reset counter atomic_t.
  2428.                  */
  2429.                 i915_error_wake_up(dev_priv, true);
  2430.         }
  2431. }
  2432.  
  2433. static void i915_report_and_clear_eir(struct drm_device *dev)
  2434. {
  2435.         struct drm_i915_private *dev_priv = dev->dev_private;
  2436.         uint32_t instdone[I915_NUM_INSTDONE_REG];
  2437.         u32 eir = I915_READ(EIR);
  2438.         int pipe, i;
  2439.  
  2440.         if (!eir)
  2441.                 return;
  2442.  
  2443.         pr_err("render error detected, EIR: 0x%08x\n", eir);
  2444.  
  2445.         i915_get_extra_instdone(dev, instdone);
  2446.  
  2447.         if (IS_G4X(dev)) {
  2448.                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  2449.                         u32 ipeir = I915_READ(IPEIR_I965);
  2450.  
  2451.                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  2452.                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  2453.                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
  2454.                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  2455.                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
  2456.                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  2457.                         I915_WRITE(IPEIR_I965, ipeir);
  2458.                         POSTING_READ(IPEIR_I965);
  2459.                 }
  2460.                 if (eir & GM45_ERROR_PAGE_TABLE) {
  2461.                         u32 pgtbl_err = I915_READ(PGTBL_ER);
  2462.                         pr_err("page table error\n");
  2463.                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
  2464.                         I915_WRITE(PGTBL_ER, pgtbl_err);
  2465.                         POSTING_READ(PGTBL_ER);
  2466.                 }
  2467.         }
  2468.  
  2469.         if (!IS_GEN2(dev)) {
  2470.                 if (eir & I915_ERROR_PAGE_TABLE) {
  2471.                         u32 pgtbl_err = I915_READ(PGTBL_ER);
  2472.                         pr_err("page table error\n");
  2473.                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
  2474.                         I915_WRITE(PGTBL_ER, pgtbl_err);
  2475.                         POSTING_READ(PGTBL_ER);
  2476.                 }
  2477.         }
  2478.  
  2479.         if (eir & I915_ERROR_MEMORY_REFRESH) {
  2480.                 pr_err("memory refresh error:\n");
  2481.                 for_each_pipe(dev_priv, pipe)
  2482.                         pr_err("pipe %c stat: 0x%08x\n",
  2483.                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  2484.                 /* pipestat has already been acked */
  2485.         }
  2486.         if (eir & I915_ERROR_INSTRUCTION) {
  2487.                 pr_err("instruction error\n");
  2488.                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
  2489.                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
  2490.                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  2491.                 if (INTEL_INFO(dev)->gen < 4) {
  2492.                         u32 ipeir = I915_READ(IPEIR);
  2493.  
  2494.                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
  2495.                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
  2496.                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
  2497.                         I915_WRITE(IPEIR, ipeir);
  2498.                         POSTING_READ(IPEIR);
  2499.                 } else {
  2500.                         u32 ipeir = I915_READ(IPEIR_I965);
  2501.  
  2502.                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  2503.                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  2504.                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
  2505.                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  2506.                         I915_WRITE(IPEIR_I965, ipeir);
  2507.                         POSTING_READ(IPEIR_I965);
  2508.                 }
  2509.         }
  2510.  
  2511.         I915_WRITE(EIR, eir);
  2512.         POSTING_READ(EIR);
  2513.         eir = I915_READ(EIR);
  2514.         if (eir) {
  2515.                 /*
  2516.                  * some errors might have become stuck,
  2517.                  * mask them.
  2518.                  */
  2519.                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  2520.                 I915_WRITE(EMR, I915_READ(EMR) | eir);
  2521.                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2522.         }
  2523. }
  2524.  
  2525. /**
  2526.  * i915_handle_error - handle a gpu error
  2527.  * @dev: drm device
  2528.  *
  2529.  * Do some basic checking of register state at error time and
  2530.  * dump it to the syslog.  Also call i915_capture_error_state() to make
  2531.  * sure we get a record and make it available in debugfs.  Fire a uevent
  2532.  * so userspace knows something bad happened (should trigger collection
  2533.  * of a ring dump etc.).
  2534.  */
  2535. void i915_handle_error(struct drm_device *dev, bool wedged,
  2536.                        const char *fmt, ...)
  2537. {
  2538.         struct drm_i915_private *dev_priv = dev->dev_private;
  2539.         va_list args;
  2540.         char error_msg[80];
  2541.  
  2542.         va_start(args, fmt);
  2543.         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
  2544.         va_end(args);
  2545.  
  2546. //      i915_capture_error_state(dev);
  2547.         i915_report_and_clear_eir(dev);
  2548.  
  2549.         if (wedged) {
  2550.                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
  2551.                                 &dev_priv->gpu_error.reset_counter);
  2552.  
  2553.                 /*
  2554.                  * Wakeup waiting processes so that the reset function
  2555.                  * i915_reset_and_wakeup doesn't deadlock trying to grab
  2556.                  * various locks. By bumping the reset counter first, the woken
  2557.                  * processes will see a reset in progress and back off,
  2558.                  * releasing their locks and then wait for the reset completion.
  2559.                  * We must do this for _all_ gpu waiters that might hold locks
  2560.                  * that the reset work needs to acquire.
  2561.                  *
  2562.                  * Note: The wake_up serves as the required memory barrier to
  2563.                  * ensure that the waiters see the updated value of the reset
  2564.                  * counter atomic_t.
  2565.                  */
  2566.                 i915_error_wake_up(dev_priv, false);
  2567.         }
  2568.  
  2569.         i915_reset_and_wakeup(dev);
  2570. }
  2571.  
  2572. /* Called from drm generic code, passed 'crtc' which
  2573.  * we use as a pipe index
  2574.  */
  2575. static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
  2576. {
  2577.         struct drm_i915_private *dev_priv = dev->dev_private;
  2578.         unsigned long irqflags;
  2579.  
  2580.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2581.         if (INTEL_INFO(dev)->gen >= 4)
  2582.                 i915_enable_pipestat(dev_priv, pipe,
  2583.                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
  2584.         else
  2585.                 i915_enable_pipestat(dev_priv, pipe,
  2586.                                      PIPE_VBLANK_INTERRUPT_STATUS);
  2587.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2588.  
  2589.         return 0;
  2590. }
  2591.  
  2592. static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
  2593. {
  2594.         struct drm_i915_private *dev_priv = dev->dev_private;
  2595.         unsigned long irqflags;
  2596.         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
  2597.                                                      DE_PIPE_VBLANK(pipe);
  2598.  
  2599.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2600.         ironlake_enable_display_irq(dev_priv, bit);
  2601.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2602.  
  2603.         return 0;
  2604. }
  2605.  
  2606. static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
  2607. {
  2608.         struct drm_i915_private *dev_priv = dev->dev_private;
  2609.         unsigned long irqflags;
  2610.  
  2611.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2612.         i915_enable_pipestat(dev_priv, pipe,
  2613.                              PIPE_START_VBLANK_INTERRUPT_STATUS);
  2614.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2615.  
  2616.         return 0;
  2617. }
  2618.  
  2619. static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
  2620. {
  2621.         struct drm_i915_private *dev_priv = dev->dev_private;
  2622.         unsigned long irqflags;
  2623.  
  2624.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2625.         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
  2626.         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
  2627.         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
  2628.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2629.         return 0;
  2630. }
  2631.  
  2632. /* Called from drm generic code, passed 'crtc' which
  2633.  * we use as a pipe index
  2634.  */
  2635. static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
  2636. {
  2637.         struct drm_i915_private *dev_priv = dev->dev_private;
  2638.         unsigned long irqflags;
  2639.  
  2640.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2641.         i915_disable_pipestat(dev_priv, pipe,
  2642.                               PIPE_VBLANK_INTERRUPT_STATUS |
  2643.                               PIPE_START_VBLANK_INTERRUPT_STATUS);
  2644.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2645. }
  2646.  
  2647. static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
  2648. {
  2649.         struct drm_i915_private *dev_priv = dev->dev_private;
  2650.         unsigned long irqflags;
  2651.         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
  2652.                                                      DE_PIPE_VBLANK(pipe);
  2653.  
  2654.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2655.         ironlake_disable_display_irq(dev_priv, bit);
  2656.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2657. }
  2658.  
  2659. static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
  2660. {
  2661.         struct drm_i915_private *dev_priv = dev->dev_private;
  2662.         unsigned long irqflags;
  2663.  
  2664.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2665.         i915_disable_pipestat(dev_priv, pipe,
  2666.                               PIPE_START_VBLANK_INTERRUPT_STATUS);
  2667.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2668. }
  2669.  
  2670. static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
  2671. {
  2672.         struct drm_i915_private *dev_priv = dev->dev_private;
  2673.         unsigned long irqflags;
  2674.  
  2675.         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2676.         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
  2677.         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
  2678.         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
  2679.         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2680. }
  2681.  
  2682. static bool
  2683. ring_idle(struct intel_engine_cs *ring, u32 seqno)
  2684. {
  2685.         return (list_empty(&ring->request_list) ||
  2686.                 i915_seqno_passed(seqno, ring->last_submitted_seqno));
  2687. }
  2688.  
  2689. static bool
  2690. ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
  2691. {
  2692.         if (INTEL_INFO(dev)->gen >= 8) {
  2693.                 return (ipehr >> 23) == 0x1c;
  2694.         } else {
  2695.                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
  2696.                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
  2697.                                  MI_SEMAPHORE_REGISTER);
  2698.         }
  2699. }
  2700.  
  2701. static struct intel_engine_cs *
  2702. semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
  2703. {
  2704.         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  2705.         struct intel_engine_cs *signaller;
  2706.         int i;
  2707.  
  2708.         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
  2709.                 for_each_ring(signaller, dev_priv, i) {
  2710.                         if (ring == signaller)
  2711.                                 continue;
  2712.  
  2713.                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
  2714.                                 return signaller;
  2715.                 }
  2716.         } else {
  2717.                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
  2718.  
  2719.                 for_each_ring(signaller, dev_priv, i) {
  2720.                         if(ring == signaller)
  2721.                                 continue;
  2722.  
  2723.                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
  2724.                                 return signaller;
  2725.                 }
  2726.         }
  2727.  
  2728.         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
  2729.                   ring->id, ipehr, offset);
  2730.  
  2731.         return NULL;
  2732. }
  2733.  
  2734. static struct intel_engine_cs *
  2735. semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
  2736. {
  2737.         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  2738.         u32 cmd, ipehr, head;
  2739.         u64 offset = 0;
  2740.         int i, backwards;
  2741.  
  2742.         /*
  2743.          * This function does not support execlist mode - any attempt to
  2744.          * proceed further into this function will result in a kernel panic
  2745.          * when dereferencing ring->buffer, which is not set up in execlist
  2746.          * mode.
  2747.          *
  2748.          * The correct way of doing it would be to derive the currently
  2749.          * executing ring buffer from the current context, which is derived
  2750.          * from the currently running request. Unfortunately, to get the
  2751.          * current request we would have to grab the struct_mutex before doing
  2752.          * anything else, which would be ill-advised since some other thread
  2753.          * might have grabbed it already and managed to hang itself, causing
  2754.          * the hang checker to deadlock.
  2755.          *
  2756.          * Therefore, this function does not support execlist mode in its
  2757.          * current form. Just return NULL and move on.
  2758.          */
  2759.         if (ring->buffer == NULL)
  2760.                 return NULL;
  2761.  
  2762.         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
  2763.         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
  2764.                 return NULL;
  2765.  
  2766.         /*
  2767.          * HEAD is likely pointing to the dword after the actual command,
  2768.          * so scan backwards until we find the MBOX. But limit it to just 3
  2769.          * or 4 dwords depending on the semaphore wait command size.
  2770.          * Note that we don't care about ACTHD here since that might
  2771.          * point at at batch, and semaphores are always emitted into the
  2772.          * ringbuffer itself.
  2773.          */
  2774.         head = I915_READ_HEAD(ring) & HEAD_ADDR;
  2775.         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
  2776.  
  2777.         for (i = backwards; i; --i) {
  2778.                 /*
  2779.                  * Be paranoid and presume the hw has gone off into the wild -
  2780.                  * our ring is smaller than what the hardware (and hence
  2781.                  * HEAD_ADDR) allows. Also handles wrap-around.
  2782.                  */
  2783.                 head &= ring->buffer->size - 1;
  2784.  
  2785.                 /* This here seems to blow up */
  2786.                 cmd = ioread32(ring->buffer->virtual_start + head);
  2787.                 if (cmd == ipehr)
  2788.                         break;
  2789.  
  2790.                 head -= 4;
  2791.         }
  2792.  
  2793.         if (!i)
  2794.                 return NULL;
  2795.  
  2796.         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
  2797.         if (INTEL_INFO(ring->dev)->gen >= 8) {
  2798.                 offset = ioread32(ring->buffer->virtual_start + head + 12);
  2799.                 offset <<= 32;
  2800.                 offset = ioread32(ring->buffer->virtual_start + head + 8);
  2801.         }
  2802.         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
  2803. }
  2804.  
  2805. static int semaphore_passed(struct intel_engine_cs *ring)
  2806. {
  2807.         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  2808.         struct intel_engine_cs *signaller;
  2809.         u32 seqno;
  2810.  
  2811.         ring->hangcheck.deadlock++;
  2812.  
  2813.         signaller = semaphore_waits_for(ring, &seqno);
  2814.         if (signaller == NULL)
  2815.                 return -1;
  2816.  
  2817.         /* Prevent pathological recursion due to driver bugs */
  2818.         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
  2819.                 return -1;
  2820.  
  2821.         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
  2822.                 return 1;
  2823.  
  2824.         /* cursory check for an unkickable deadlock */
  2825.         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
  2826.             semaphore_passed(signaller) < 0)
  2827.                 return -1;
  2828.  
  2829.         return 0;
  2830. }
  2831.  
  2832. static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
  2833. {
  2834.         struct intel_engine_cs *ring;
  2835.         int i;
  2836.  
  2837.         for_each_ring(ring, dev_priv, i)
  2838.                 ring->hangcheck.deadlock = 0;
  2839. }
  2840.  
  2841. static enum intel_ring_hangcheck_action
  2842. ring_stuck(struct intel_engine_cs *ring, u64 acthd)
  2843. {
  2844.         struct drm_device *dev = ring->dev;
  2845.         struct drm_i915_private *dev_priv = dev->dev_private;
  2846.         u32 tmp;
  2847.  
  2848.         if (acthd != ring->hangcheck.acthd) {
  2849.                 if (acthd > ring->hangcheck.max_acthd) {
  2850.                         ring->hangcheck.max_acthd = acthd;
  2851.                         return HANGCHECK_ACTIVE;
  2852.                 }
  2853.  
  2854.                 return HANGCHECK_ACTIVE_LOOP;
  2855.         }
  2856.  
  2857.         if (IS_GEN2(dev))
  2858.                 return HANGCHECK_HUNG;
  2859.  
  2860.         /* Is the chip hanging on a WAIT_FOR_EVENT?
  2861.          * If so we can simply poke the RB_WAIT bit
  2862.          * and break the hang. This should work on
  2863.          * all but the second generation chipsets.
  2864.          */
  2865.         tmp = I915_READ_CTL(ring);
  2866.         if (tmp & RING_WAIT) {
  2867.                 i915_handle_error(dev, false,
  2868.                                   "Kicking stuck wait on %s",
  2869.                                   ring->name);
  2870.                 I915_WRITE_CTL(ring, tmp);
  2871.                 return HANGCHECK_KICK;
  2872.         }
  2873.  
  2874.         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
  2875.                 switch (semaphore_passed(ring)) {
  2876.                 default:
  2877.                         return HANGCHECK_HUNG;
  2878.                 case 1:
  2879.                         i915_handle_error(dev, false,
  2880.                                           "Kicking stuck semaphore on %s",
  2881.                                           ring->name);
  2882.                         I915_WRITE_CTL(ring, tmp);
  2883.                         return HANGCHECK_KICK;
  2884.                 case 0:
  2885.                         return HANGCHECK_WAIT;
  2886.                 }
  2887.         }
  2888.  
  2889.         return HANGCHECK_HUNG;
  2890. }
  2891.  
  2892. /*
  2893.  * This is called when the chip hasn't reported back with completed
  2894.  * batchbuffers in a long time. We keep track per ring seqno progress and
  2895.  * if there are no progress, hangcheck score for that ring is increased.
  2896.  * Further, acthd is inspected to see if the ring is stuck. On stuck case
  2897.  * we kick the ring. If we see no progress on three subsequent calls
  2898.  * we assume chip is wedged and try to fix it by resetting the chip.
  2899.  */
  2900. static void i915_hangcheck_elapsed(struct work_struct *work)
  2901. {
  2902.         struct drm_i915_private *dev_priv =
  2903.                 container_of(work, typeof(*dev_priv),
  2904.                              gpu_error.hangcheck_work.work);
  2905.         struct drm_device *dev = dev_priv->dev;
  2906.         struct intel_engine_cs *ring;
  2907.         int i;
  2908.         int busy_count = 0, rings_hung = 0;
  2909.         bool stuck[I915_NUM_RINGS] = { 0 };
  2910. #define BUSY 1
  2911. #define KICK 5
  2912. #define HUNG 20
  2913.  
  2914.         if (!i915.enable_hangcheck)
  2915.                 return;
  2916.  
  2917.         for_each_ring(ring, dev_priv, i) {
  2918.                 u64 acthd;
  2919.                 u32 seqno;
  2920.                 bool busy = true;
  2921.  
  2922.                 semaphore_clear_deadlocks(dev_priv);
  2923.  
  2924.                 seqno = ring->get_seqno(ring, false);
  2925.                 acthd = intel_ring_get_active_head(ring);
  2926.  
  2927.                 if (ring->hangcheck.seqno == seqno) {
  2928.                         if (ring_idle(ring, seqno)) {
  2929.                                 ring->hangcheck.action = HANGCHECK_IDLE;
  2930.  
  2931.                                 if (waitqueue_active(&ring->irq_queue)) {
  2932.                                         /* Issue a wake-up to catch stuck h/w. */
  2933.                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
  2934.                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
  2935.                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  2936.                                                                   ring->name);
  2937.                                                 else
  2938.                                                         DRM_INFO("Fake missed irq on %s\n",
  2939.                                                                  ring->name);
  2940.                                                 wake_up_all(&ring->irq_queue);
  2941.                                         }
  2942.                                         /* Safeguard against driver failure */
  2943.                                         ring->hangcheck.score += BUSY;
  2944.                                 } else
  2945.                                         busy = false;
  2946.                         } else {
  2947.                                 /* We always increment the hangcheck score
  2948.                                  * if the ring is busy and still processing
  2949.                                  * the same request, so that no single request
  2950.                                  * can run indefinitely (such as a chain of
  2951.                                  * batches). The only time we do not increment
  2952.                                  * the hangcheck score on this ring, if this
  2953.                                  * ring is in a legitimate wait for another
  2954.                                  * ring. In that case the waiting ring is a
  2955.                                  * victim and we want to be sure we catch the
  2956.                                  * right culprit. Then every time we do kick
  2957.                                  * the ring, add a small increment to the
  2958.                                  * score so that we can catch a batch that is
  2959.                                  * being repeatedly kicked and so responsible
  2960.                                  * for stalling the machine.
  2961.                                  */
  2962.                                 ring->hangcheck.action = ring_stuck(ring,
  2963.                                                                     acthd);
  2964.  
  2965.                                 switch (ring->hangcheck.action) {
  2966.                                 case HANGCHECK_IDLE:
  2967.                                 case HANGCHECK_WAIT:
  2968.                                 case HANGCHECK_ACTIVE:
  2969.                                         break;
  2970.                                 case HANGCHECK_ACTIVE_LOOP:
  2971.                                         ring->hangcheck.score += BUSY;
  2972.                                         break;
  2973.                                 case HANGCHECK_KICK:
  2974.                                         ring->hangcheck.score += KICK;
  2975.                                         break;
  2976.                                 case HANGCHECK_HUNG:
  2977.                                         ring->hangcheck.score += HUNG;
  2978.                                         stuck[i] = true;
  2979.                                         break;
  2980.                                 }
  2981.                         }
  2982.                 } else {
  2983.                         ring->hangcheck.action = HANGCHECK_ACTIVE;
  2984.  
  2985.                         /* Gradually reduce the count so that we catch DoS
  2986.                          * attempts across multiple batches.
  2987.                          */
  2988.                         if (ring->hangcheck.score > 0)
  2989.                                 ring->hangcheck.score--;
  2990.  
  2991.                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
  2992.                 }
  2993.  
  2994.                 ring->hangcheck.seqno = seqno;
  2995.                 ring->hangcheck.acthd = acthd;
  2996.                 busy_count += busy;
  2997.         }
  2998.  
  2999.         for_each_ring(ring, dev_priv, i) {
  3000.                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
  3001.                         DRM_INFO("%s on %s\n",
  3002.                                  stuck[i] ? "stuck" : "no progress",
  3003.                                  ring->name);
  3004.                         rings_hung++;
  3005.                 }
  3006.         }
  3007.  
  3008. //   if (rings_hung)
  3009. //       return i915_handle_error(dev, true);
  3010.  
  3011. }
  3012. static void ibx_irq_reset(struct drm_device *dev)
  3013. {
  3014.         struct drm_i915_private *dev_priv = dev->dev_private;
  3015.  
  3016.         if (HAS_PCH_NOP(dev))
  3017.                 return;
  3018.  
  3019.         GEN5_IRQ_RESET(SDE);
  3020.  
  3021.         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
  3022.                 I915_WRITE(SERR_INT, 0xffffffff);
  3023. }
  3024.  
  3025. /*
  3026.  * SDEIER is also touched by the interrupt handler to work around missed PCH
  3027.  * interrupts. Hence we can't update it after the interrupt handler is enabled -
  3028.  * instead we unconditionally enable all PCH interrupt sources here, but then
  3029.  * only unmask them as needed with SDEIMR.
  3030.  *
  3031.  * This function needs to be called before interrupts are enabled.
  3032.  */
  3033. static void ibx_irq_pre_postinstall(struct drm_device *dev)
  3034. {
  3035.         struct drm_i915_private *dev_priv = dev->dev_private;
  3036.  
  3037.         if (HAS_PCH_NOP(dev))
  3038.                 return;
  3039.  
  3040.         WARN_ON(I915_READ(SDEIER) != 0);
  3041.         I915_WRITE(SDEIER, 0xffffffff);
  3042.         POSTING_READ(SDEIER);
  3043. }
  3044.  
  3045. static void gen5_gt_irq_reset(struct drm_device *dev)
  3046. {
  3047.         struct drm_i915_private *dev_priv = dev->dev_private;
  3048.  
  3049.         GEN5_IRQ_RESET(GT);
  3050.         if (INTEL_INFO(dev)->gen >= 6)
  3051.                 GEN5_IRQ_RESET(GEN6_PM);
  3052. }
  3053.  
  3054. /* drm_dma.h hooks
  3055. */
  3056. static void ironlake_irq_reset(struct drm_device *dev)
  3057. {
  3058.         struct drm_i915_private *dev_priv = dev->dev_private;
  3059.  
  3060.         I915_WRITE(HWSTAM, 0xffffffff);
  3061.  
  3062.         GEN5_IRQ_RESET(DE);
  3063.         if (IS_GEN7(dev))
  3064.                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
  3065.  
  3066.         gen5_gt_irq_reset(dev);
  3067.  
  3068.         ibx_irq_reset(dev);
  3069. }
  3070.  
  3071. static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
  3072. {
  3073.         enum pipe pipe;
  3074.  
  3075.         i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
  3076.         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  3077.  
  3078.         for_each_pipe(dev_priv, pipe)
  3079.                 I915_WRITE(PIPESTAT(pipe), 0xffff);
  3080.  
  3081.         GEN5_IRQ_RESET(VLV_);
  3082. }
  3083.  
  3084. static void valleyview_irq_preinstall(struct drm_device *dev)
  3085. {
  3086.         struct drm_i915_private *dev_priv = dev->dev_private;
  3087.  
  3088.         /* VLV magic */
  3089.         I915_WRITE(VLV_IMR, 0);
  3090.         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  3091.         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  3092.         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  3093.  
  3094.         gen5_gt_irq_reset(dev);
  3095.  
  3096.         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  3097.  
  3098.         vlv_display_irq_reset(dev_priv);
  3099. }
  3100.  
  3101. static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
  3102. {
  3103.         GEN8_IRQ_RESET_NDX(GT, 0);
  3104.         GEN8_IRQ_RESET_NDX(GT, 1);
  3105.         GEN8_IRQ_RESET_NDX(GT, 2);
  3106.         GEN8_IRQ_RESET_NDX(GT, 3);
  3107. }
  3108.  
  3109. static void gen8_irq_reset(struct drm_device *dev)
  3110. {
  3111.         struct drm_i915_private *dev_priv = dev->dev_private;
  3112.         int pipe;
  3113.  
  3114.         I915_WRITE(GEN8_MASTER_IRQ, 0);
  3115.         POSTING_READ(GEN8_MASTER_IRQ);
  3116.  
  3117.         gen8_gt_irq_reset(dev_priv);
  3118.  
  3119.         for_each_pipe(dev_priv, pipe)
  3120.                 if (intel_display_power_is_enabled(dev_priv,
  3121.                                                    POWER_DOMAIN_PIPE(pipe)))
  3122.                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
  3123.  
  3124.         GEN5_IRQ_RESET(GEN8_DE_PORT_);
  3125.         GEN5_IRQ_RESET(GEN8_DE_MISC_);
  3126.         GEN5_IRQ_RESET(GEN8_PCU_);
  3127.  
  3128.         if (HAS_PCH_SPLIT(dev))
  3129.                 ibx_irq_reset(dev);
  3130. }
  3131.  
  3132. void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
  3133.                                      unsigned int pipe_mask)
  3134. {
  3135.         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
  3136.  
  3137.         spin_lock_irq(&dev_priv->irq_lock);
  3138.         if (pipe_mask & 1 << PIPE_A)
  3139.                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
  3140.                                   dev_priv->de_irq_mask[PIPE_A],
  3141.                                   ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
  3142.         if (pipe_mask & 1 << PIPE_B)
  3143.                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
  3144.                                   dev_priv->de_irq_mask[PIPE_B],
  3145.                                   ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
  3146.         if (pipe_mask & 1 << PIPE_C)
  3147.                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
  3148.                                   dev_priv->de_irq_mask[PIPE_C],
  3149.                                   ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
  3150.         spin_unlock_irq(&dev_priv->irq_lock);
  3151. }
  3152.  
  3153. static void cherryview_irq_preinstall(struct drm_device *dev)
  3154. {
  3155.         struct drm_i915_private *dev_priv = dev->dev_private;
  3156.  
  3157.         I915_WRITE(GEN8_MASTER_IRQ, 0);
  3158.         POSTING_READ(GEN8_MASTER_IRQ);
  3159.  
  3160.         gen8_gt_irq_reset(dev_priv);
  3161.  
  3162.         GEN5_IRQ_RESET(GEN8_PCU_);
  3163.  
  3164.         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
  3165.  
  3166.         vlv_display_irq_reset(dev_priv);
  3167. }
  3168.  
  3169. static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
  3170.                                   const u32 hpd[HPD_NUM_PINS])
  3171. {
  3172.         struct drm_i915_private *dev_priv = to_i915(dev);
  3173.         struct intel_encoder *encoder;
  3174.         u32 enabled_irqs = 0;
  3175.  
  3176.         for_each_intel_encoder(dev, encoder)
  3177.                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
  3178.                         enabled_irqs |= hpd[encoder->hpd_pin];
  3179.  
  3180.         return enabled_irqs;
  3181. }
  3182.  
  3183. static void ibx_hpd_irq_setup(struct drm_device *dev)
  3184. {
  3185.         struct drm_i915_private *dev_priv = dev->dev_private;
  3186.         u32 hotplug_irqs, hotplug, enabled_irqs;
  3187.  
  3188.         if (HAS_PCH_IBX(dev)) {
  3189.                 hotplug_irqs = SDE_HOTPLUG_MASK;
  3190.                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
  3191.         } else {
  3192.                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
  3193.                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
  3194.         }
  3195.  
  3196.         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
  3197.  
  3198.         /*
  3199.          * Enable digital hotplug on the PCH, and configure the DP short pulse
  3200.          * duration to 2ms (which is the minimum in the Display Port spec).
  3201.          * The pulse duration bits are reserved on LPT+.
  3202.          */
  3203.         hotplug = I915_READ(PCH_PORT_HOTPLUG);
  3204.         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  3205.         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  3206.         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  3207.         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  3208.         /*
  3209.          * When CPU and PCH are on the same package, port A
  3210.          * HPD must be enabled in both north and south.
  3211.          */
  3212.         if (HAS_PCH_LPT_LP(dev))
  3213.                 hotplug |= PORTA_HOTPLUG_ENABLE;
  3214.         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  3215. }
  3216.  
  3217. static void spt_hpd_irq_setup(struct drm_device *dev)
  3218. {
  3219.         struct drm_i915_private *dev_priv = dev->dev_private;
  3220.         u32 hotplug_irqs, hotplug, enabled_irqs;
  3221.  
  3222.         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
  3223.         enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
  3224.  
  3225.         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
  3226.  
  3227.         /* Enable digital hotplug on the PCH */
  3228.         hotplug = I915_READ(PCH_PORT_HOTPLUG);
  3229.         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
  3230.                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
  3231.         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  3232.  
  3233.         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
  3234.         hotplug |= PORTE_HOTPLUG_ENABLE;
  3235.         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
  3236. }
  3237.  
  3238. static void ilk_hpd_irq_setup(struct drm_device *dev)
  3239. {
  3240.         struct drm_i915_private *dev_priv = dev->dev_private;
  3241.         u32 hotplug_irqs, hotplug, enabled_irqs;
  3242.  
  3243.         if (INTEL_INFO(dev)->gen >= 8) {
  3244.                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
  3245.                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
  3246.  
  3247.                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
  3248.         } else if (INTEL_INFO(dev)->gen >= 7) {
  3249.                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
  3250.                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
  3251.  
  3252.                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
  3253.         } else {
  3254.                 hotplug_irqs = DE_DP_A_HOTPLUG;
  3255.                 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
  3256.  
  3257.                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
  3258.         }
  3259.  
  3260.         /*
  3261.          * Enable digital hotplug on the CPU, and configure the DP short pulse
  3262.          * duration to 2ms (which is the minimum in the Display Port spec)
  3263.          * The pulse duration bits are reserved on HSW+.
  3264.          */
  3265.         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
  3266.         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
  3267.         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
  3268.         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
  3269.  
  3270.         ibx_hpd_irq_setup(dev);
  3271. }
  3272.  
  3273. static void bxt_hpd_irq_setup(struct drm_device *dev)
  3274. {
  3275.         struct drm_i915_private *dev_priv = dev->dev_private;
  3276.         u32 hotplug_irqs, hotplug, enabled_irqs;
  3277.  
  3278.         enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
  3279.         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
  3280.  
  3281.         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
  3282.  
  3283.         hotplug = I915_READ(PCH_PORT_HOTPLUG);
  3284.         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
  3285.                 PORTA_HOTPLUG_ENABLE;
  3286.         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  3287. }
  3288.  
  3289. static void ibx_irq_postinstall(struct drm_device *dev)
  3290. {
  3291.         struct drm_i915_private *dev_priv = dev->dev_private;
  3292.         u32 mask;
  3293.  
  3294.         if (HAS_PCH_NOP(dev))
  3295.                 return;
  3296.  
  3297.         if (HAS_PCH_IBX(dev))
  3298.                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
  3299.         else
  3300.                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
  3301.  
  3302.         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
  3303.         I915_WRITE(SDEIMR, ~mask);
  3304. }
  3305.  
  3306. static void gen5_gt_irq_postinstall(struct drm_device *dev)
  3307. {
  3308.         struct drm_i915_private *dev_priv = dev->dev_private;
  3309.         u32 pm_irqs, gt_irqs;
  3310.  
  3311.         pm_irqs = gt_irqs = 0;
  3312.  
  3313.         dev_priv->gt_irq_mask = ~0;
  3314.         if (HAS_L3_DPF(dev)) {
  3315.                 /* L3 parity interrupt is always unmasked. */
  3316.                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
  3317.                 gt_irqs |= GT_PARITY_ERROR(dev);
  3318.         }
  3319.  
  3320.         gt_irqs |= GT_RENDER_USER_INTERRUPT;
  3321.         if (IS_GEN5(dev)) {
  3322.                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
  3323.                            ILK_BSD_USER_INTERRUPT;
  3324.         } else {
  3325.                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
  3326.         }
  3327.  
  3328.         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
  3329.  
  3330.         if (INTEL_INFO(dev)->gen >= 6) {
  3331.                 /*
  3332.                  * RPS interrupts will get enabled/disabled on demand when RPS
  3333.                  * itself is enabled/disabled.
  3334.                  */
  3335.                 if (HAS_VEBOX(dev))
  3336.                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
  3337.  
  3338.                 dev_priv->pm_irq_mask = 0xffffffff;
  3339.                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
  3340.         }
  3341. }
  3342.  
  3343. static int ironlake_irq_postinstall(struct drm_device *dev)
  3344. {
  3345.         struct drm_i915_private *dev_priv = dev->dev_private;
  3346.         u32 display_mask, extra_mask;
  3347.  
  3348.         if (INTEL_INFO(dev)->gen >= 7) {
  3349.                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
  3350.                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
  3351.                                 DE_PLANEB_FLIP_DONE_IVB |
  3352.                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
  3353.                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
  3354.                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
  3355.                               DE_DP_A_HOTPLUG_IVB);
  3356.         } else {
  3357.                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  3358.                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
  3359.                                 DE_AUX_CHANNEL_A |
  3360.                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
  3361.                                 DE_POISON);
  3362.                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
  3363.                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
  3364.                               DE_DP_A_HOTPLUG);
  3365.         }
  3366.  
  3367.         dev_priv->irq_mask = ~display_mask;
  3368.  
  3369.         I915_WRITE(HWSTAM, 0xeffe);
  3370.  
  3371.         ibx_irq_pre_postinstall(dev);
  3372.  
  3373.         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
  3374.  
  3375.         gen5_gt_irq_postinstall(dev);
  3376.  
  3377.         ibx_irq_postinstall(dev);
  3378.  
  3379.         if (IS_IRONLAKE_M(dev)) {
  3380.                 /* Enable PCU event interrupts
  3381.                  *
  3382.                  * spinlocking not required here for correctness since interrupt
  3383.                  * setup is guaranteed to run in single-threaded context. But we
  3384.                  * need it to make the assert_spin_locked happy. */
  3385.                 spin_lock_irq(&dev_priv->irq_lock);
  3386.                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  3387.                 spin_unlock_irq(&dev_priv->irq_lock);
  3388.         }
  3389.  
  3390.         return 0;
  3391. }
  3392.  
  3393. static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
  3394. {
  3395.         u32 pipestat_mask;
  3396.         u32 iir_mask;
  3397.         enum pipe pipe;
  3398.  
  3399.         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
  3400.                         PIPE_FIFO_UNDERRUN_STATUS;
  3401.  
  3402.         for_each_pipe(dev_priv, pipe)
  3403.                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
  3404.         POSTING_READ(PIPESTAT(PIPE_A));
  3405.  
  3406.         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
  3407.                         PIPE_CRC_DONE_INTERRUPT_STATUS;
  3408.  
  3409.         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
  3410.         for_each_pipe(dev_priv, pipe)
  3411.                       i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
  3412.  
  3413.         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
  3414.                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  3415.                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
  3416.         if (IS_CHERRYVIEW(dev_priv))
  3417.                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
  3418.         dev_priv->irq_mask &= ~iir_mask;
  3419.  
  3420.         I915_WRITE(VLV_IIR, iir_mask);
  3421.         I915_WRITE(VLV_IIR, iir_mask);
  3422.         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
  3423.         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  3424.         POSTING_READ(VLV_IMR);
  3425. }
  3426.  
  3427. static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
  3428. {
  3429.         u32 pipestat_mask;
  3430.         u32 iir_mask;
  3431.         enum pipe pipe;
  3432.  
  3433.         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
  3434.                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  3435.                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
  3436.         if (IS_CHERRYVIEW(dev_priv))
  3437.                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
  3438.  
  3439.         dev_priv->irq_mask |= iir_mask;
  3440.         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  3441.         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
  3442.         I915_WRITE(VLV_IIR, iir_mask);
  3443.         I915_WRITE(VLV_IIR, iir_mask);
  3444.         POSTING_READ(VLV_IIR);
  3445.  
  3446.         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
  3447.                         PIPE_CRC_DONE_INTERRUPT_STATUS;
  3448.  
  3449.         i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
  3450.         for_each_pipe(dev_priv, pipe)
  3451.                 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
  3452.  
  3453.         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
  3454.                         PIPE_FIFO_UNDERRUN_STATUS;
  3455.  
  3456.         for_each_pipe(dev_priv, pipe)
  3457.                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
  3458.         POSTING_READ(PIPESTAT(PIPE_A));
  3459. }
  3460.  
  3461. void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
  3462. {
  3463.         assert_spin_locked(&dev_priv->irq_lock);
  3464.  
  3465.         if (dev_priv->display_irqs_enabled)
  3466.                 return;
  3467.  
  3468.         dev_priv->display_irqs_enabled = true;
  3469.  
  3470.         if (intel_irqs_enabled(dev_priv))
  3471.                 valleyview_display_irqs_install(dev_priv);
  3472. }
  3473.  
  3474. void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
  3475. {
  3476.         assert_spin_locked(&dev_priv->irq_lock);
  3477.  
  3478.         if (!dev_priv->display_irqs_enabled)
  3479.                 return;
  3480.  
  3481.         dev_priv->display_irqs_enabled = false;
  3482.  
  3483.         if (intel_irqs_enabled(dev_priv))
  3484.                 valleyview_display_irqs_uninstall(dev_priv);
  3485. }
  3486.  
  3487. static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
  3488. {
  3489.         dev_priv->irq_mask = ~0;
  3490.  
  3491.         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  3492.         POSTING_READ(PORT_HOTPLUG_EN);
  3493.  
  3494.         I915_WRITE(VLV_IIR, 0xffffffff);
  3495.         I915_WRITE(VLV_IIR, 0xffffffff);
  3496.         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
  3497.         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  3498.         POSTING_READ(VLV_IMR);
  3499.  
  3500.         /* Interrupt setup is already guaranteed to be single-threaded, this is
  3501.          * just to make the assert_spin_locked check happy. */
  3502.         spin_lock_irq(&dev_priv->irq_lock);
  3503.         if (dev_priv->display_irqs_enabled)
  3504.                 valleyview_display_irqs_install(dev_priv);
  3505.         spin_unlock_irq(&dev_priv->irq_lock);
  3506. }
  3507.  
  3508. static int valleyview_irq_postinstall(struct drm_device *dev)
  3509. {
  3510.         struct drm_i915_private *dev_priv = dev->dev_private;
  3511.  
  3512.         vlv_display_irq_postinstall(dev_priv);
  3513.  
  3514.         gen5_gt_irq_postinstall(dev);
  3515.  
  3516.         /* ack & enable invalid PTE error interrupts */
  3517. #if 0 /* FIXME: add support to irq handler for checking these bits */
  3518.         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  3519.         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  3520. #endif
  3521.  
  3522.         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  3523.  
  3524.         return 0;
  3525. }
  3526.  
  3527. static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
  3528. {
  3529.         /* These are interrupts we'll toggle with the ring mask register */
  3530.         uint32_t gt_interrupts[] = {
  3531.                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  3532.                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  3533.                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
  3534.                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
  3535.                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
  3536.                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
  3537.                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
  3538.                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
  3539.                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
  3540.                 0,
  3541.                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
  3542.                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
  3543.                 };
  3544.  
  3545.         dev_priv->pm_irq_mask = 0xffffffff;
  3546.         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
  3547.         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
  3548.         /*
  3549.          * RPS interrupts will get enabled/disabled on demand when RPS itself
  3550.          * is enabled/disabled.
  3551.          */
  3552.         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
  3553.         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
  3554. }
  3555.  
  3556. static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
  3557. {
  3558.         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
  3559.         uint32_t de_pipe_enables;
  3560.         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
  3561.         u32 de_port_enables;
  3562.         enum pipe pipe;
  3563.  
  3564.         if (INTEL_INFO(dev_priv)->gen >= 9) {
  3565.                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
  3566.                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
  3567.                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
  3568.                                   GEN9_AUX_CHANNEL_D;
  3569.                 if (IS_BROXTON(dev_priv))
  3570.                         de_port_masked |= BXT_DE_PORT_GMBUS;
  3571.         } else {
  3572.                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
  3573.                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
  3574.         }
  3575.  
  3576.         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
  3577.                                            GEN8_PIPE_FIFO_UNDERRUN;
  3578.  
  3579.         de_port_enables = de_port_masked;
  3580.         if (IS_BROXTON(dev_priv))
  3581.                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
  3582.         else if (IS_BROADWELL(dev_priv))
  3583.                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
  3584.  
  3585.         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
  3586.         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
  3587.         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
  3588.  
  3589.         for_each_pipe(dev_priv, pipe)
  3590.                 if (intel_display_power_is_enabled(dev_priv,
  3591.                                 POWER_DOMAIN_PIPE(pipe)))
  3592.                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
  3593.                                           dev_priv->de_irq_mask[pipe],
  3594.                                           de_pipe_enables);
  3595.  
  3596.         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
  3597. }
  3598.  
  3599. static int gen8_irq_postinstall(struct drm_device *dev)
  3600. {
  3601.         struct drm_i915_private *dev_priv = dev->dev_private;
  3602.  
  3603.         if (HAS_PCH_SPLIT(dev))
  3604.                 ibx_irq_pre_postinstall(dev);
  3605.  
  3606.         gen8_gt_irq_postinstall(dev_priv);
  3607.         gen8_de_irq_postinstall(dev_priv);
  3608.  
  3609.         if (HAS_PCH_SPLIT(dev))
  3610.                 ibx_irq_postinstall(dev);
  3611.  
  3612.         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
  3613.         POSTING_READ(GEN8_MASTER_IRQ);
  3614.  
  3615.         return 0;
  3616. }
  3617.  
  3618. static int cherryview_irq_postinstall(struct drm_device *dev)
  3619. {
  3620.         struct drm_i915_private *dev_priv = dev->dev_private;
  3621.  
  3622.         vlv_display_irq_postinstall(dev_priv);
  3623.  
  3624.         gen8_gt_irq_postinstall(dev_priv);
  3625.  
  3626.         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
  3627.         POSTING_READ(GEN8_MASTER_IRQ);
  3628.  
  3629.         return 0;
  3630. }
  3631.  
  3632. static void gen8_irq_uninstall(struct drm_device *dev)
  3633. {
  3634.         struct drm_i915_private *dev_priv = dev->dev_private;
  3635.  
  3636.         if (!dev_priv)
  3637.                 return;
  3638.  
  3639.         gen8_irq_reset(dev);
  3640. }
  3641.  
  3642. static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
  3643. {
  3644.         /* Interrupt setup is already guaranteed to be single-threaded, this is
  3645.          * just to make the assert_spin_locked check happy. */
  3646.         spin_lock_irq(&dev_priv->irq_lock);
  3647.         if (dev_priv->display_irqs_enabled)
  3648.                 valleyview_display_irqs_uninstall(dev_priv);
  3649.         spin_unlock_irq(&dev_priv->irq_lock);
  3650.  
  3651.         vlv_display_irq_reset(dev_priv);
  3652.  
  3653.         dev_priv->irq_mask = ~0;
  3654. }
  3655.  
  3656. static void valleyview_irq_uninstall(struct drm_device *dev)
  3657. {
  3658.         struct drm_i915_private *dev_priv = dev->dev_private;
  3659.  
  3660.         if (!dev_priv)
  3661.                 return;
  3662.  
  3663.         I915_WRITE(VLV_MASTER_IER, 0);
  3664.  
  3665.         gen5_gt_irq_reset(dev);
  3666.  
  3667.         I915_WRITE(HWSTAM, 0xffffffff);
  3668.  
  3669.         vlv_display_irq_uninstall(dev_priv);
  3670. }
  3671.  
  3672. static void cherryview_irq_uninstall(struct drm_device *dev)
  3673. {
  3674.         struct drm_i915_private *dev_priv = dev->dev_private;
  3675.  
  3676.         if (!dev_priv)
  3677.                 return;
  3678.  
  3679.         I915_WRITE(GEN8_MASTER_IRQ, 0);
  3680.         POSTING_READ(GEN8_MASTER_IRQ);
  3681.  
  3682.         gen8_gt_irq_reset(dev_priv);
  3683.  
  3684.         GEN5_IRQ_RESET(GEN8_PCU_);
  3685.  
  3686.         vlv_display_irq_uninstall(dev_priv);
  3687. }
  3688.  
  3689. static void ironlake_irq_uninstall(struct drm_device *dev)
  3690. {
  3691.         struct drm_i915_private *dev_priv = dev->dev_private;
  3692.  
  3693.         if (!dev_priv)
  3694.                 return;
  3695.  
  3696.         ironlake_irq_reset(dev);
  3697. }
  3698.  
  3699. #if 0
  3700. static void i8xx_irq_preinstall(struct drm_device * dev)
  3701. {
  3702.         struct drm_i915_private *dev_priv = dev->dev_private;
  3703.         int pipe;
  3704.  
  3705.         for_each_pipe(dev_priv, pipe)
  3706.                 I915_WRITE(PIPESTAT(pipe), 0);
  3707.         I915_WRITE16(IMR, 0xffff);
  3708.         I915_WRITE16(IER, 0x0);
  3709.         POSTING_READ16(IER);
  3710. }
  3711.  
  3712. static int i8xx_irq_postinstall(struct drm_device *dev)
  3713. {
  3714.         struct drm_i915_private *dev_priv = dev->dev_private;
  3715.  
  3716.         I915_WRITE16(EMR,
  3717.                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  3718.  
  3719.         /* Unmask the interrupts that we always want on. */
  3720.         dev_priv->irq_mask =
  3721.                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  3722.                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  3723.                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  3724.                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  3725.         I915_WRITE16(IMR, dev_priv->irq_mask);
  3726.  
  3727.         I915_WRITE16(IER,
  3728.                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  3729.                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  3730.                      I915_USER_INTERRUPT);
  3731.         POSTING_READ16(IER);
  3732.  
  3733.         /* Interrupt setup is already guaranteed to be single-threaded, this is
  3734.          * just to make the assert_spin_locked check happy. */
  3735.         spin_lock_irq(&dev_priv->irq_lock);
  3736.         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
  3737.         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
  3738.         spin_unlock_irq(&dev_priv->irq_lock);
  3739.  
  3740.         return 0;
  3741. }
  3742.  
  3743. /*
  3744.  * Returns true when a page flip has completed.
  3745.  */
  3746. static bool i8xx_handle_vblank(struct drm_device *dev,
  3747.                                int plane, int pipe, u32 iir)
  3748. {
  3749.         struct drm_i915_private *dev_priv = dev->dev_private;
  3750.         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  3751.  
  3752.         if (!intel_pipe_handle_vblank(dev, pipe))
  3753.                 return false;
  3754.  
  3755.         if ((iir & flip_pending) == 0)
  3756.                 goto check_page_flip;
  3757.  
  3758.         /* We detect FlipDone by looking for the change in PendingFlip from '1'
  3759.          * to '0' on the following vblank, i.e. IIR has the Pendingflip
  3760.          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  3761.          * the flip is completed (no longer pending). Since this doesn't raise
  3762.          * an interrupt per se, we watch for the change at vblank.
  3763.          */
  3764.         if (I915_READ16(ISR) & flip_pending)
  3765.                 goto check_page_flip;
  3766.  
  3767. //   intel_prepare_page_flip(dev, plane);
  3768. //   intel_finish_page_flip(dev, pipe);
  3769.         return true;
  3770.  
  3771. check_page_flip:
  3772. //   intel_check_page_flip(dev, pipe);
  3773.         return false;
  3774. }
  3775.  
  3776. static irqreturn_t i8xx_irq_handler(int irq, void *arg)
  3777. {
  3778.         struct drm_device *dev = arg;
  3779.         struct drm_i915_private *dev_priv = dev->dev_private;
  3780.         u16 iir, new_iir;
  3781.         u32 pipe_stats[2];
  3782.         int pipe;
  3783.         u16 flip_mask =
  3784.                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  3785.                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  3786.  
  3787.         if (!intel_irqs_enabled(dev_priv))
  3788.                 return IRQ_NONE;
  3789.  
  3790.         iir = I915_READ16(IIR);
  3791.         if (iir == 0)
  3792.                 return IRQ_NONE;
  3793.  
  3794.         while (iir & ~flip_mask) {
  3795.                 /* Can't rely on pipestat interrupt bit in iir as it might
  3796.                  * have been cleared after the pipestat interrupt was received.
  3797.                  * It doesn't set the bit in iir again, but it still produces
  3798.                  * interrupts (for non-MSI).
  3799.                  */
  3800.                 spin_lock(&dev_priv->irq_lock);
  3801.                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  3802.                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
  3803.  
  3804.                 for_each_pipe(dev_priv, pipe) {
  3805.                         int reg = PIPESTAT(pipe);
  3806.                         pipe_stats[pipe] = I915_READ(reg);
  3807.  
  3808.                         /*
  3809.                          * Clear the PIPE*STAT regs before the IIR
  3810.                          */
  3811.                         if (pipe_stats[pipe] & 0x8000ffff)
  3812.                                 I915_WRITE(reg, pipe_stats[pipe]);
  3813.                 }
  3814.                 spin_unlock(&dev_priv->irq_lock);
  3815.  
  3816.                 I915_WRITE16(IIR, iir & ~flip_mask);
  3817.                 new_iir = I915_READ16(IIR); /* Flush posted writes */
  3818.  
  3819.                 if (iir & I915_USER_INTERRUPT)
  3820.                         notify_ring(&dev_priv->ring[RCS]);
  3821.  
  3822.                 for_each_pipe(dev_priv, pipe) {
  3823.                         int plane = pipe;
  3824.                         if (HAS_FBC(dev))
  3825.                                 plane = !plane;
  3826.  
  3827.                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  3828.                             i8xx_handle_vblank(dev, plane, pipe, iir))
  3829.                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  3830.  
  3831.                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
  3832.                                 i9xx_pipe_crc_irq_handler(dev, pipe);
  3833.  
  3834.                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  3835.                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
  3836.                                                                     pipe);
  3837.                 }
  3838.  
  3839.                 iir = new_iir;
  3840.         }
  3841.  
  3842.         return IRQ_HANDLED;
  3843. }
  3844.  
  3845. static void i8xx_irq_uninstall(struct drm_device * dev)
  3846. {
  3847.         struct drm_i915_private *dev_priv = dev->dev_private;
  3848.         int pipe;
  3849.  
  3850.         for_each_pipe(dev_priv, pipe) {
  3851.                 /* Clear enable bits; then clear status bits */
  3852.                 I915_WRITE(PIPESTAT(pipe), 0);
  3853.                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  3854.         }
  3855.         I915_WRITE16(IMR, 0xffff);
  3856.         I915_WRITE16(IER, 0x0);
  3857.         I915_WRITE16(IIR, I915_READ16(IIR));
  3858. }
  3859.  
  3860. #endif
  3861.  
  3862. static void i915_irq_preinstall(struct drm_device * dev)
  3863. {
  3864.         struct drm_i915_private *dev_priv = dev->dev_private;
  3865.         int pipe;
  3866.  
  3867.         if (I915_HAS_HOTPLUG(dev)) {
  3868.                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  3869.                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  3870.         }
  3871.  
  3872.         I915_WRITE16(HWSTAM, 0xeffe);
  3873.         for_each_pipe(dev_priv, pipe)
  3874.                 I915_WRITE(PIPESTAT(pipe), 0);
  3875.         I915_WRITE(IMR, 0xffffffff);
  3876.         I915_WRITE(IER, 0x0);
  3877.         POSTING_READ(IER);
  3878. }
  3879.  
  3880. static int i915_irq_postinstall(struct drm_device *dev)
  3881. {
  3882.         struct drm_i915_private *dev_priv = dev->dev_private;
  3883.         u32 enable_mask;
  3884.  
  3885.         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  3886.  
  3887.         /* Unmask the interrupts that we always want on. */
  3888.         dev_priv->irq_mask =
  3889.                 ~(I915_ASLE_INTERRUPT |
  3890.                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  3891.                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  3892.                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  3893.                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  3894.  
  3895.         enable_mask =
  3896.                 I915_ASLE_INTERRUPT |
  3897.                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  3898.                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  3899.                 I915_USER_INTERRUPT;
  3900.  
  3901.         if (I915_HAS_HOTPLUG(dev)) {
  3902.                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  3903.                 POSTING_READ(PORT_HOTPLUG_EN);
  3904.  
  3905.                 /* Enable in IER... */
  3906.                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  3907.                 /* and unmask in IMR */
  3908.                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  3909.         }
  3910.  
  3911.         I915_WRITE(IMR, dev_priv->irq_mask);
  3912.         I915_WRITE(IER, enable_mask);
  3913.         POSTING_READ(IER);
  3914.  
  3915.         i915_enable_asle_pipestat(dev);
  3916.  
  3917.         /* Interrupt setup is already guaranteed to be single-threaded, this is
  3918.          * just to make the assert_spin_locked check happy. */
  3919.         spin_lock_irq(&dev_priv->irq_lock);
  3920.         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
  3921.         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
  3922.         spin_unlock_irq(&dev_priv->irq_lock);
  3923.  
  3924.         return 0;
  3925. }
  3926.  
  3927. /*
  3928.  * Returns true when a page flip has completed.
  3929.  */
  3930. static bool i915_handle_vblank(struct drm_device *dev,
  3931.                                int plane, int pipe, u32 iir)
  3932. {
  3933.         struct drm_i915_private *dev_priv = dev->dev_private;
  3934.         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  3935.  
  3936.         return false;
  3937.  
  3938.         if ((iir & flip_pending) == 0)
  3939.                 goto check_page_flip;
  3940.  
  3941.         /* We detect FlipDone by looking for the change in PendingFlip from '1'
  3942.          * to '0' on the following vblank, i.e. IIR has the Pendingflip
  3943.          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  3944.          * the flip is completed (no longer pending). Since this doesn't raise
  3945.          * an interrupt per se, we watch for the change at vblank.
  3946.          */
  3947.         if (I915_READ(ISR) & flip_pending)
  3948.                 goto check_page_flip;
  3949.  
  3950.         return true;
  3951.  
  3952. check_page_flip:
  3953.         return false;
  3954. }
  3955.  
  3956. static irqreturn_t i915_irq_handler(int irq, void *arg)
  3957. {
  3958.         struct drm_device *dev = arg;
  3959.         struct drm_i915_private *dev_priv = dev->dev_private;
  3960.         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  3961.         u32 flip_mask =
  3962.                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  3963.                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  3964.         int pipe, ret = IRQ_NONE;
  3965.  
  3966.         if (!intel_irqs_enabled(dev_priv))
  3967.                 return IRQ_NONE;
  3968.  
  3969.         iir = I915_READ(IIR);
  3970.         do {
  3971.                 bool irq_received = (iir & ~flip_mask) != 0;
  3972.                 bool blc_event = false;
  3973.  
  3974.                 /* Can't rely on pipestat interrupt bit in iir as it might
  3975.                  * have been cleared after the pipestat interrupt was received.
  3976.                  * It doesn't set the bit in iir again, but it still produces
  3977.                  * interrupts (for non-MSI).
  3978.                  */
  3979.                 spin_lock(&dev_priv->irq_lock);
  3980.                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  3981.                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
  3982.  
  3983.                 for_each_pipe(dev_priv, pipe) {
  3984.                         int reg = PIPESTAT(pipe);
  3985.                         pipe_stats[pipe] = I915_READ(reg);
  3986.  
  3987.                         /* Clear the PIPE*STAT regs before the IIR */
  3988.                         if (pipe_stats[pipe] & 0x8000ffff) {
  3989.                                 I915_WRITE(reg, pipe_stats[pipe]);
  3990.                                 irq_received = true;
  3991.                         }
  3992.                 }
  3993.                 spin_unlock(&dev_priv->irq_lock);
  3994.  
  3995.                 if (!irq_received)
  3996.                         break;
  3997.  
  3998.                 /* Consume port.  Then clear IIR or we'll miss events */
  3999.                 if (I915_HAS_HOTPLUG(dev) &&
  4000.                     iir & I915_DISPLAY_PORT_INTERRUPT)
  4001.                         i9xx_hpd_irq_handler(dev);
  4002.  
  4003.                 I915_WRITE(IIR, iir & ~flip_mask);
  4004.                 new_iir = I915_READ(IIR); /* Flush posted writes */
  4005.  
  4006.                 if (iir & I915_USER_INTERRUPT)
  4007.                         notify_ring(&dev_priv->ring[RCS]);
  4008.  
  4009.                 for_each_pipe(dev_priv, pipe) {
  4010.                         int plane = pipe;
  4011.                         if (HAS_FBC(dev))
  4012.                                 plane = !plane;
  4013.  
  4014.                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  4015.                             i915_handle_vblank(dev, plane, pipe, iir))
  4016.                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  4017.  
  4018.                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  4019.                                 blc_event = true;
  4020.  
  4021.                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
  4022.                                 i9xx_pipe_crc_irq_handler(dev, pipe);
  4023.  
  4024.                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  4025.                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
  4026.                                                                     pipe);
  4027.                 }
  4028.  
  4029.                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
  4030.                         intel_opregion_asle_intr(dev);
  4031.  
  4032.                 /* With MSI, interrupts are only generated when iir
  4033.                  * transitions from zero to nonzero.  If another bit got
  4034.                  * set while we were handling the existing iir bits, then
  4035.                  * we would never get another interrupt.
  4036.                  *
  4037.                  * This is fine on non-MSI as well, as if we hit this path
  4038.                  * we avoid exiting the interrupt handler only to generate
  4039.                  * another one.
  4040.                  *
  4041.                  * Note that for MSI this could cause a stray interrupt report
  4042.                  * if an interrupt landed in the time between writing IIR and
  4043.                  * the posting read.  This should be rare enough to never
  4044.                  * trigger the 99% of 100,000 interrupts test for disabling
  4045.                  * stray interrupts.
  4046.                  */
  4047.                 ret = IRQ_HANDLED;
  4048.                 iir = new_iir;
  4049.         } while (iir & ~flip_mask);
  4050.  
  4051.         return ret;
  4052. }
  4053.  
  4054. static void i915_irq_uninstall(struct drm_device * dev)
  4055. {
  4056.         struct drm_i915_private *dev_priv = dev->dev_private;
  4057.         int pipe;
  4058.  
  4059.         if (I915_HAS_HOTPLUG(dev)) {
  4060.                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  4061.                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  4062.         }
  4063.  
  4064.         I915_WRITE16(HWSTAM, 0xffff);
  4065.         for_each_pipe(dev_priv, pipe) {
  4066.                 /* Clear enable bits; then clear status bits */
  4067.                 I915_WRITE(PIPESTAT(pipe), 0);
  4068.                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  4069.         }
  4070.         I915_WRITE(IMR, 0xffffffff);
  4071.         I915_WRITE(IER, 0x0);
  4072.  
  4073.         I915_WRITE(IIR, I915_READ(IIR));
  4074. }
  4075.  
  4076. static void i965_irq_preinstall(struct drm_device * dev)
  4077. {
  4078.         struct drm_i915_private *dev_priv = dev->dev_private;
  4079.         int pipe;
  4080.  
  4081.         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  4082.         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  4083.  
  4084.         I915_WRITE(HWSTAM, 0xeffe);
  4085.         for_each_pipe(dev_priv, pipe)
  4086.                 I915_WRITE(PIPESTAT(pipe), 0);
  4087.         I915_WRITE(IMR, 0xffffffff);
  4088.         I915_WRITE(IER, 0x0);
  4089.         POSTING_READ(IER);
  4090. }
  4091.  
  4092. static int i965_irq_postinstall(struct drm_device *dev)
  4093. {
  4094.         struct drm_i915_private *dev_priv = dev->dev_private;
  4095.         u32 enable_mask;
  4096.         u32 error_mask;
  4097.  
  4098.         /* Unmask the interrupts that we always want on. */
  4099.         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  4100.                                I915_DISPLAY_PORT_INTERRUPT |
  4101.                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  4102.                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  4103.                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  4104.                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  4105.                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  4106.  
  4107.         enable_mask = ~dev_priv->irq_mask;
  4108.         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  4109.                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  4110.         enable_mask |= I915_USER_INTERRUPT;
  4111.  
  4112.         if (IS_G4X(dev))
  4113.                 enable_mask |= I915_BSD_USER_INTERRUPT;
  4114.  
  4115.         /* Interrupt setup is already guaranteed to be single-threaded, this is
  4116.          * just to make the assert_spin_locked check happy. */
  4117.         spin_lock_irq(&dev_priv->irq_lock);
  4118.         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
  4119.         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
  4120.         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
  4121.         spin_unlock_irq(&dev_priv->irq_lock);
  4122.  
  4123.         /*
  4124.          * Enable some error detection, note the instruction error mask
  4125.          * bit is reserved, so we leave it masked.
  4126.          */
  4127.         if (IS_G4X(dev)) {
  4128.                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
  4129.                                GM45_ERROR_MEM_PRIV |
  4130.                                GM45_ERROR_CP_PRIV |
  4131.                                I915_ERROR_MEMORY_REFRESH);
  4132.         } else {
  4133.                 error_mask = ~(I915_ERROR_PAGE_TABLE |
  4134.                                I915_ERROR_MEMORY_REFRESH);
  4135.         }
  4136.         I915_WRITE(EMR, error_mask);
  4137.  
  4138.         I915_WRITE(IMR, dev_priv->irq_mask);
  4139.         I915_WRITE(IER, enable_mask);
  4140.         POSTING_READ(IER);
  4141.  
  4142.         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  4143.         POSTING_READ(PORT_HOTPLUG_EN);
  4144.  
  4145.         i915_enable_asle_pipestat(dev);
  4146.  
  4147.         return 0;
  4148. }
  4149.  
  4150. static void i915_hpd_irq_setup(struct drm_device *dev)
  4151. {
  4152.         struct drm_i915_private *dev_priv = dev->dev_private;
  4153.         u32 hotplug_en;
  4154.  
  4155.         assert_spin_locked(&dev_priv->irq_lock);
  4156.  
  4157.         /* Note HDMI and DP share hotplug bits */
  4158.         /* enable bits are the same for all generations */
  4159.         hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
  4160.         /* Programming the CRT detection parameters tends
  4161.            to generate a spurious hotplug event about three
  4162.            seconds later.  So just do it once.
  4163.         */
  4164.         if (IS_G4X(dev))
  4165.                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  4166.         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  4167.  
  4168.         /* Ignore TV since it's buggy */
  4169.         i915_hotplug_interrupt_update_locked(dev_priv,
  4170.                                              HOTPLUG_INT_EN_MASK |
  4171.                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
  4172.                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
  4173.                                              hotplug_en);
  4174. }
  4175.  
  4176. static irqreturn_t i965_irq_handler(int irq, void *arg)
  4177. {
  4178.         struct drm_device *dev = arg;
  4179.         struct drm_i915_private *dev_priv = dev->dev_private;
  4180.         u32 iir, new_iir;
  4181.         u32 pipe_stats[I915_MAX_PIPES];
  4182.         int ret = IRQ_NONE, pipe;
  4183.         u32 flip_mask =
  4184.                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  4185.                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  4186.  
  4187.         if (!intel_irqs_enabled(dev_priv))
  4188.                 return IRQ_NONE;
  4189.  
  4190.         iir = I915_READ(IIR);
  4191.  
  4192.         for (;;) {
  4193.                 bool irq_received = (iir & ~flip_mask) != 0;
  4194.                 bool blc_event = false;
  4195.  
  4196.                 /* Can't rely on pipestat interrupt bit in iir as it might
  4197.                  * have been cleared after the pipestat interrupt was received.
  4198.                  * It doesn't set the bit in iir again, but it still produces
  4199.                  * interrupts (for non-MSI).
  4200.                  */
  4201.                 spin_lock(&dev_priv->irq_lock);
  4202.                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  4203.                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
  4204.  
  4205.                 for_each_pipe(dev_priv, pipe) {
  4206.                         int reg = PIPESTAT(pipe);
  4207.                         pipe_stats[pipe] = I915_READ(reg);
  4208.  
  4209.                         /*
  4210.                          * Clear the PIPE*STAT regs before the IIR
  4211.                          */
  4212.                         if (pipe_stats[pipe] & 0x8000ffff) {
  4213.                                 I915_WRITE(reg, pipe_stats[pipe]);
  4214.                                 irq_received = true;
  4215.                         }
  4216.                 }
  4217.                 spin_unlock(&dev_priv->irq_lock);
  4218.  
  4219.                 if (!irq_received)
  4220.                         break;
  4221.  
  4222.                 ret = IRQ_HANDLED;
  4223.  
  4224.                 /* Consume port.  Then clear IIR or we'll miss events */
  4225.                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
  4226.                         i9xx_hpd_irq_handler(dev);
  4227.  
  4228.                 I915_WRITE(IIR, iir & ~flip_mask);
  4229.                 new_iir = I915_READ(IIR); /* Flush posted writes */
  4230.  
  4231.                 if (iir & I915_USER_INTERRUPT)
  4232.                         notify_ring(&dev_priv->ring[RCS]);
  4233.                 if (iir & I915_BSD_USER_INTERRUPT)
  4234.                         notify_ring(&dev_priv->ring[VCS]);
  4235.  
  4236.                 for_each_pipe(dev_priv, pipe) {
  4237.                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  4238.                             i915_handle_vblank(dev, pipe, pipe, iir))
  4239.                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
  4240.  
  4241.                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  4242.                                 blc_event = true;
  4243.  
  4244.                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
  4245.                                 i9xx_pipe_crc_irq_handler(dev, pipe);
  4246.  
  4247.                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  4248.                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
  4249.                 }
  4250.  
  4251.                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
  4252.                         intel_opregion_asle_intr(dev);
  4253.  
  4254.                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  4255.                         gmbus_irq_handler(dev);
  4256.  
  4257.                 /* With MSI, interrupts are only generated when iir
  4258.                  * transitions from zero to nonzero.  If another bit got
  4259.                  * set while we were handling the existing iir bits, then
  4260.                  * we would never get another interrupt.
  4261.                  *
  4262.                  * This is fine on non-MSI as well, as if we hit this path
  4263.                  * we avoid exiting the interrupt handler only to generate
  4264.                  * another one.
  4265.                  *
  4266.                  * Note that for MSI this could cause a stray interrupt report
  4267.                  * if an interrupt landed in the time between writing IIR and
  4268.                  * the posting read.  This should be rare enough to never
  4269.                  * trigger the 99% of 100,000 interrupts test for disabling
  4270.                  * stray interrupts.
  4271.                  */
  4272.                 iir = new_iir;
  4273.         }
  4274.  
  4275.         return ret;
  4276. }
  4277.  
  4278. static void i965_irq_uninstall(struct drm_device * dev)
  4279. {
  4280.         struct drm_i915_private *dev_priv = dev->dev_private;
  4281.         int pipe;
  4282.  
  4283.         if (!dev_priv)
  4284.                 return;
  4285.  
  4286.         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
  4287.         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  4288.  
  4289.         I915_WRITE(HWSTAM, 0xffffffff);
  4290.         for_each_pipe(dev_priv, pipe)
  4291.                 I915_WRITE(PIPESTAT(pipe), 0);
  4292.         I915_WRITE(IMR, 0xffffffff);
  4293.         I915_WRITE(IER, 0x0);
  4294.  
  4295.         for_each_pipe(dev_priv, pipe)
  4296.                 I915_WRITE(PIPESTAT(pipe),
  4297.                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  4298.         I915_WRITE(IIR, I915_READ(IIR));
  4299. }
  4300.  
  4301. /**
  4302.  * intel_irq_init - initializes irq support
  4303.  * @dev_priv: i915 device instance
  4304.  *
  4305.  * This function initializes all the irq support including work items, timers
  4306.  * and all the vtables. It does not setup the interrupt itself though.
  4307.  */
  4308. void intel_irq_init(struct drm_i915_private *dev_priv)
  4309. {
  4310.         struct drm_device *dev = dev_priv->dev;
  4311.  
  4312. //   intel_hpd_init_work(dev_priv);
  4313.  
  4314.         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  4315.         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
  4316.  
  4317.         /* Let's track the enabled rps events */
  4318.         if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
  4319.                 /* WaGsvRC0ResidencyMethod:vlv */
  4320.                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
  4321.         else
  4322.                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
  4323.  
  4324.         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
  4325.                           i915_hangcheck_elapsed);
  4326.  
  4327.  
  4328.         if (IS_GEN2(dev_priv)) {
  4329.                 dev->max_vblank_count = 0;
  4330.                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
  4331.         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
  4332.                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  4333.                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
  4334.         } else {
  4335.                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
  4336.                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  4337.         }
  4338.  
  4339.         /*
  4340.          * Opt out of the vblank disable timer on everything except gen2.
  4341.          * Gen2 doesn't have a hardware frame counter and so depends on
  4342.          * vblank interrupts to produce sane vblank seuquence numbers.
  4343.          */
  4344.         if (!IS_GEN2(dev_priv))
  4345.                 dev->vblank_disable_immediate = true;
  4346.  
  4347.         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  4348.         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  4349.  
  4350.         if (IS_CHERRYVIEW(dev_priv)) {
  4351.                 dev->driver->irq_handler = cherryview_irq_handler;
  4352.                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
  4353.                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
  4354.                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
  4355.                 dev->driver->enable_vblank = valleyview_enable_vblank;
  4356.                 dev->driver->disable_vblank = valleyview_disable_vblank;
  4357.                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  4358.         } else if (IS_VALLEYVIEW(dev_priv)) {
  4359.                 dev->driver->irq_handler = valleyview_irq_handler;
  4360.                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
  4361.                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
  4362.                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
  4363.                 dev->driver->enable_vblank = valleyview_enable_vblank;
  4364.                 dev->driver->disable_vblank = valleyview_disable_vblank;
  4365.                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  4366.         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
  4367.                 dev->driver->irq_handler = gen8_irq_handler;
  4368.                 dev->driver->irq_preinstall = gen8_irq_reset;
  4369.                 dev->driver->irq_postinstall = gen8_irq_postinstall;
  4370.                 dev->driver->irq_uninstall = gen8_irq_uninstall;
  4371.                 dev->driver->enable_vblank = gen8_enable_vblank;
  4372.                 dev->driver->disable_vblank = gen8_disable_vblank;
  4373.                 if (IS_BROXTON(dev))
  4374.                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
  4375.                 else if (HAS_PCH_SPT(dev))
  4376.                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
  4377.                 else
  4378.                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
  4379.         } else if (HAS_PCH_SPLIT(dev)) {
  4380.                 dev->driver->irq_handler = ironlake_irq_handler;
  4381.                 dev->driver->irq_preinstall = ironlake_irq_reset;
  4382.                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
  4383.                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
  4384.                 dev->driver->enable_vblank = ironlake_enable_vblank;
  4385.                 dev->driver->disable_vblank = ironlake_disable_vblank;
  4386.                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
  4387.         } else {
  4388.                 if (INTEL_INFO(dev_priv)->gen == 2) {
  4389.                 } else if (INTEL_INFO(dev_priv)->gen == 3) {
  4390.                         dev->driver->irq_preinstall = i915_irq_preinstall;
  4391.                         dev->driver->irq_postinstall = i915_irq_postinstall;
  4392.                         dev->driver->irq_uninstall = i915_irq_uninstall;
  4393.                         dev->driver->irq_handler = i915_irq_handler;
  4394.                 } else {
  4395.                         dev->driver->irq_preinstall = i965_irq_preinstall;
  4396.                         dev->driver->irq_postinstall = i965_irq_postinstall;
  4397.                         dev->driver->irq_uninstall = i965_irq_uninstall;
  4398.                         dev->driver->irq_handler = i965_irq_handler;
  4399.                 }
  4400.                 if (I915_HAS_HOTPLUG(dev_priv))
  4401.                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  4402.                 dev->driver->enable_vblank = i915_enable_vblank;
  4403.                 dev->driver->disable_vblank = i915_disable_vblank;
  4404.         }
  4405. }
  4406.  
  4407. /**
  4408.  * intel_irq_install - enables the hardware interrupt
  4409.  * @dev_priv: i915 device instance
  4410.  *
  4411.  * This function enables the hardware interrupt handling, but leaves the hotplug
  4412.  * handling still disabled. It is called after intel_irq_init().
  4413.  *
  4414.  * In the driver load and resume code we need working interrupts in a few places
  4415.  * but don't want to deal with the hassle of concurrent probe and hotplug
  4416.  * workers. Hence the split into this two-stage approach.
  4417.  */
  4418. int intel_irq_install(struct drm_i915_private *dev_priv)
  4419. {
  4420.         /*
  4421.          * We enable some interrupt sources in our postinstall hooks, so mark
  4422.          * interrupts as enabled _before_ actually enabling them to avoid
  4423.          * special cases in our ordering checks.
  4424.          */
  4425.         dev_priv->pm.irqs_enabled = true;
  4426.  
  4427.         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
  4428. }
  4429.  
  4430. /**
  4431.  * intel_irq_uninstall - finilizes all irq handling
  4432.  * @dev_priv: i915 device instance
  4433.  *
  4434.  * This stops interrupt and hotplug handling and unregisters and frees all
  4435.  * resources acquired in the init functions.
  4436.  */
  4437. void intel_irq_uninstall(struct drm_i915_private *dev_priv)
  4438. {
  4439. //      drm_irq_uninstall(dev_priv->dev);
  4440. //      intel_hpd_cancel_work(dev_priv);
  4441.         dev_priv->pm.irqs_enabled = false;
  4442. }
  4443.  
  4444. /**
  4445.  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
  4446.  * @dev_priv: i915 device instance
  4447.  *
  4448.  * This function is used to disable interrupts at runtime, both in the runtime
  4449.  * pm and the system suspend/resume code.
  4450.  */
  4451. void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
  4452. {
  4453.         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
  4454.         dev_priv->pm.irqs_enabled = false;
  4455. }
  4456.  
  4457. /**
  4458.  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
  4459.  * @dev_priv: i915 device instance
  4460.  *
  4461.  * This function is used to enable interrupts at runtime, both in the runtime
  4462.  * pm and the system suspend/resume code.
  4463.  */
  4464. void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
  4465. {
  4466.         dev_priv->pm.irqs_enabled = true;
  4467.         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
  4468.         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
  4469. }
  4470.  
  4471. irqreturn_t intel_irq_handler(struct drm_device *dev)
  4472. {
  4473.  
  4474. //    printf("i915 irq\n");
  4475. //    printf("device %p driver %p handler %p\n", dev, dev->driver, dev->driver->irq_handler) ;
  4476.  
  4477.     return dev->driver->irq_handler(0, dev);
  4478. }
  4479.  
  4480.