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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Please try to maintain the following order within this file unless it makes
  24.  * sense to do otherwise. From top to bottom:
  25.  * 1. typedefs
  26.  * 2. #defines, and macros
  27.  * 3. structure definitions
  28.  * 4. function prototypes
  29.  *
  30.  * Within each section, please try to order by generation in ascending order,
  31.  * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
  32.  */
  33.  
  34. #ifndef __I915_GEM_GTT_H__
  35. #define __I915_GEM_GTT_H__
  36.  
  37. struct drm_i915_file_private;
  38.  
  39. typedef uint32_t gen6_pte_t;
  40. typedef uint64_t gen8_pte_t;
  41. typedef uint64_t gen8_pde_t;
  42. typedef uint64_t gen8_ppgtt_pdpe_t;
  43. typedef uint64_t gen8_ppgtt_pml4e_t;
  44.  
  45. #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
  46.  
  47.  
  48. /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
  49. #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  50. #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  51. #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  52. #define GEN6_PTE_CACHE_LLC              (2 << 1)
  53. #define GEN6_PTE_UNCACHED               (1 << 1)
  54. #define GEN6_PTE_VALID                  (1 << 0)
  55.  
  56. #define I915_PTES(pte_len)              (PAGE_SIZE / (pte_len))
  57. #define I915_PTE_MASK(pte_len)          (I915_PTES(pte_len) - 1)
  58. #define I915_PDES                       512
  59. #define I915_PDE_MASK                   (I915_PDES - 1)
  60. #define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))
  61.  
  62. #define GEN6_PTES                       I915_PTES(sizeof(gen6_pte_t))
  63. #define GEN6_PD_SIZE                    (I915_PDES * PAGE_SIZE)
  64. #define GEN6_PD_ALIGN                   (PAGE_SIZE * 16)
  65. #define GEN6_PDE_SHIFT                  22
  66. #define GEN6_PDE_VALID                  (1 << 0)
  67.  
  68. #define GEN7_PTE_CACHE_L3_LLC           (3 << 1)
  69.  
  70. #define BYT_PTE_SNOOPED_BY_CPU_CACHES   (1 << 2)
  71. #define BYT_PTE_WRITEABLE               (1 << 1)
  72.  
  73. /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
  74.  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  75.  */
  76. #define HSW_CACHEABILITY_CONTROL(bits)  ((((bits) & 0x7) << 1) | \
  77.                                          (((bits) & 0x8) << (11 - 3)))
  78. #define HSW_WB_LLC_AGE3                 HSW_CACHEABILITY_CONTROL(0x2)
  79. #define HSW_WB_LLC_AGE0                 HSW_CACHEABILITY_CONTROL(0x3)
  80. #define HSW_WB_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x8)
  81. #define HSW_WB_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0xb)
  82. #define HSW_WT_ELLC_LLC_AGE3            HSW_CACHEABILITY_CONTROL(0x7)
  83. #define HSW_WT_ELLC_LLC_AGE0            HSW_CACHEABILITY_CONTROL(0x6)
  84. #define HSW_PTE_UNCACHED                (0)
  85. #define HSW_GTT_ADDR_ENCODE(addr)       ((addr) | (((addr) >> 28) & 0x7f0))
  86. #define HSW_PTE_ADDR_ENCODE(addr)       HSW_GTT_ADDR_ENCODE(addr)
  87.  
  88. /* GEN8 legacy style address is defined as a 3 level page table:
  89.  * 31:30 | 29:21 | 20:12 |  11:0
  90.  * PDPE  |  PDE  |  PTE  | offset
  91.  * The difference as compared to normal x86 3 level page table is the PDPEs are
  92.  * programmed via register.
  93.  *
  94.  * GEN8 48b legacy style address is defined as a 4 level page table:
  95.  * 47:39 | 38:30 | 29:21 | 20:12 |  11:0
  96.  * PML4E | PDPE  |  PDE  |  PTE  | offset
  97.  */
  98. #define GEN8_PML4ES_PER_PML4            512
  99. #define GEN8_PML4E_SHIFT                39
  100. #define GEN8_PML4E_MASK                 (GEN8_PML4ES_PER_PML4 - 1)
  101. #define GEN8_PDPE_SHIFT                 30
  102. /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
  103.  * tables */
  104. #define GEN8_PDPE_MASK                  0x1ff
  105. #define GEN8_PDE_SHIFT                  21
  106. #define GEN8_PDE_MASK                   0x1ff
  107. #define GEN8_PTE_SHIFT                  12
  108. #define GEN8_PTE_MASK                   0x1ff
  109. #define GEN8_LEGACY_PDPES               4
  110. #define GEN8_PTES                       I915_PTES(sizeof(gen8_pte_t))
  111.  
  112. #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
  113.                                  GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
  114.  
  115. #define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
  116. #define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
  117. #define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
  118. #define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
  119.  
  120. #define CHV_PPAT_SNOOP                  (1<<6)
  121. #define GEN8_PPAT_AGE(x)                (x<<4)
  122. #define GEN8_PPAT_LLCeLLC               (3<<2)
  123. #define GEN8_PPAT_LLCELLC               (2<<2)
  124. #define GEN8_PPAT_LLC                   (1<<2)
  125. #define GEN8_PPAT_WB                    (3<<0)
  126. #define GEN8_PPAT_WT                    (2<<0)
  127. #define GEN8_PPAT_WC                    (1<<0)
  128. #define GEN8_PPAT_UC                    (0<<0)
  129. #define GEN8_PPAT_ELLC_OVERRIDE         (0<<2)
  130. #define GEN8_PPAT(i, x)                 ((uint64_t) (x) << ((i) * 8))
  131.  
  132. enum i915_ggtt_view_type {
  133.         I915_GGTT_VIEW_NORMAL = 0,
  134.         I915_GGTT_VIEW_ROTATED,
  135.         I915_GGTT_VIEW_PARTIAL,
  136. };
  137.  
  138. struct intel_rotation_info {
  139.         unsigned int height;
  140.         unsigned int pitch;
  141.         unsigned int uv_offset;
  142.         uint32_t pixel_format;
  143.         uint64_t fb_modifier;
  144.         unsigned int width_pages, height_pages;
  145.         uint64_t size;
  146.         unsigned int width_pages_uv, height_pages_uv;
  147.         uint64_t size_uv;
  148.         unsigned int uv_start_page;
  149. };
  150.  
  151. struct i915_ggtt_view {
  152.         enum i915_ggtt_view_type type;
  153.  
  154.         union {
  155.                 struct {
  156.                         u64 offset;
  157.                         unsigned int size;
  158.                 } partial;
  159.         } params;
  160.  
  161.         struct sg_table *pages;
  162.  
  163.         union {
  164.                 struct intel_rotation_info rotation_info;
  165.         };
  166. };
  167.  
  168. extern const struct i915_ggtt_view i915_ggtt_view_normal;
  169. extern const struct i915_ggtt_view i915_ggtt_view_rotated;
  170.  
  171. enum i915_cache_level;
  172.  
  173. /**
  174.  * A VMA represents a GEM BO that is bound into an address space. Therefore, a
  175.  * VMA's presence cannot be guaranteed before binding, or after unbinding the
  176.  * object into/from the address space.
  177.  *
  178.  * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
  179.  * will always be <= an objects lifetime. So object refcounting should cover us.
  180.  */
  181. struct i915_vma {
  182.         struct drm_mm_node node;
  183.         struct drm_i915_gem_object *obj;
  184.         struct i915_address_space *vm;
  185.  
  186.         /** Flags and address space this VMA is bound to */
  187. #define GLOBAL_BIND     (1<<0)
  188. #define LOCAL_BIND      (1<<1)
  189.         unsigned int bound : 4;
  190.  
  191.         /**
  192.          * Support different GGTT views into the same object.
  193.          * This means there can be multiple VMA mappings per object and per VM.
  194.          * i915_ggtt_view_type is used to distinguish between those entries.
  195.          * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
  196.          * assumed in GEM functions which take no ggtt view parameter.
  197.          */
  198.         struct i915_ggtt_view ggtt_view;
  199.  
  200.         /** This object's place on the active/inactive lists */
  201.         struct list_head mm_list;
  202.  
  203.         struct list_head vma_link; /* Link in the object's VMA list */
  204.  
  205.         /** This vma's place in the batchbuffer or on the eviction list */
  206.         struct list_head exec_list;
  207.  
  208.         /**
  209.          * Used for performing relocations during execbuffer insertion.
  210.          */
  211.         struct hlist_node exec_node;
  212.         unsigned long exec_handle;
  213.         struct drm_i915_gem_exec_object2 *exec_entry;
  214.  
  215.         /**
  216.          * How many users have pinned this object in GTT space. The following
  217.          * users can each hold at most one reference: pwrite/pread, execbuffer
  218.          * (objects are not allowed multiple times for the same batchbuffer),
  219.          * and the framebuffer code. When switching/pageflipping, the
  220.          * framebuffer code has at most two buffers pinned per crtc.
  221.          *
  222.          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  223.          * bits with absolutely no headroom. So use 4 bits. */
  224.         unsigned int pin_count:4;
  225. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  226. };
  227.  
  228. struct i915_page_dma {
  229.         struct page *page;
  230.         union {
  231.                 dma_addr_t daddr;
  232.  
  233.                 /* For gen6/gen7 only. This is the offset in the GGTT
  234.                  * where the page directory entries for PPGTT begin
  235.                  */
  236.                 uint32_t ggtt_offset;
  237.         };
  238. };
  239.  
  240. #define px_base(px) (&(px)->base)
  241. #define px_page(px) (px_base(px)->page)
  242. #define px_dma(px) (px_base(px)->daddr)
  243.  
  244. struct i915_page_scratch {
  245.         struct i915_page_dma base;
  246. };
  247.  
  248. struct i915_page_table {
  249.         struct i915_page_dma base;
  250.  
  251.         unsigned long *used_ptes;
  252. };
  253.  
  254. struct i915_page_directory {
  255.         struct i915_page_dma base;
  256.  
  257.         unsigned long *used_pdes;
  258.         struct i915_page_table *page_table[I915_PDES]; /* PDEs */
  259. };
  260.  
  261. struct i915_page_directory_pointer {
  262.         struct i915_page_dma base;
  263.  
  264.         unsigned long *used_pdpes;
  265.         struct i915_page_directory **page_directory;
  266. };
  267.  
  268. struct i915_pml4 {
  269.         struct i915_page_dma base;
  270.  
  271.         DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
  272.         struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
  273. };
  274.  
  275. struct i915_address_space {
  276.         struct drm_mm mm;
  277.         struct drm_device *dev;
  278.         struct list_head global_link;
  279.         u64 start;              /* Start offset always 0 for dri2 */
  280.         u64 total;              /* size addr space maps (ex. 2GB for ggtt) */
  281.  
  282.         struct i915_page_scratch *scratch_page;
  283.         struct i915_page_table *scratch_pt;
  284.         struct i915_page_directory *scratch_pd;
  285.         struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
  286.  
  287.         /**
  288.          * List of objects currently involved in rendering.
  289.          *
  290.          * Includes buffers having the contents of their GPU caches
  291.          * flushed, not necessarily primitives. last_read_req
  292.          * represents when the rendering involved will be completed.
  293.          *
  294.          * A reference is held on the buffer while on this list.
  295.          */
  296.         struct list_head active_list;
  297.  
  298.         /**
  299.          * LRU list of objects which are not in the ringbuffer and
  300.          * are ready to unbind, but are still in the GTT.
  301.          *
  302.          * last_read_req is NULL while an object is in this list.
  303.          *
  304.          * A reference is not held on the buffer while on this list,
  305.          * as merely being GTT-bound shouldn't prevent its being
  306.          * freed, and we'll pull it off the list in the free path.
  307.          */
  308.         struct list_head inactive_list;
  309.  
  310.         /* FIXME: Need a more generic return type */
  311.         gen6_pte_t (*pte_encode)(dma_addr_t addr,
  312.                                  enum i915_cache_level level,
  313.                                  bool valid, u32 flags); /* Create a valid PTE */
  314.         /* flags for pte_encode */
  315. #define PTE_READ_ONLY   (1<<0)
  316.         int (*allocate_va_range)(struct i915_address_space *vm,
  317.                                  uint64_t start,
  318.                                  uint64_t length);
  319.         void (*clear_range)(struct i915_address_space *vm,
  320.                             uint64_t start,
  321.                             uint64_t length,
  322.                             bool use_scratch);
  323.         void (*insert_entries)(struct i915_address_space *vm,
  324.                                struct sg_table *st,
  325.                                uint64_t start,
  326.                                enum i915_cache_level cache_level, u32 flags);
  327.         void (*cleanup)(struct i915_address_space *vm);
  328.         /** Unmap an object from an address space. This usually consists of
  329.          * setting the valid PTE entries to a reserved scratch page. */
  330.         void (*unbind_vma)(struct i915_vma *vma);
  331.         /* Map an object into an address space with the given cache flags. */
  332.         int (*bind_vma)(struct i915_vma *vma,
  333.                         enum i915_cache_level cache_level,
  334.                         u32 flags);
  335. };
  336.  
  337. /* The Graphics Translation Table is the way in which GEN hardware translates a
  338.  * Graphics Virtual Address into a Physical Address. In addition to the normal
  339.  * collateral associated with any va->pa translations GEN hardware also has a
  340.  * portion of the GTT which can be mapped by the CPU and remain both coherent
  341.  * and correct (in cases like swizzling). That region is referred to as GMADR in
  342.  * the spec.
  343.  */
  344. struct i915_gtt {
  345.         struct i915_address_space base;
  346.  
  347.         size_t stolen_size;             /* Total size of stolen memory */
  348.         size_t stolen_usable_size;      /* Total size minus BIOS reserved */
  349.         u64 mappable_end;               /* End offset that we can CPU map */
  350.         struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
  351.         phys_addr_t mappable_base;      /* PA of our GMADR */
  352.  
  353.         /** "Graphics Stolen Memory" holds the global PTEs */
  354.         void __iomem *gsm;
  355.  
  356.         bool do_idle_maps;
  357.  
  358.         int mtrr;
  359.  
  360.         /* global gtt ops */
  361.         int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total,
  362.                           size_t *stolen, phys_addr_t *mappable_base,
  363.                           u64 *mappable_end);
  364. };
  365.  
  366. struct i915_hw_ppgtt {
  367.         struct i915_address_space base;
  368.         struct kref ref;
  369.         struct drm_mm_node node;
  370.         unsigned long pd_dirty_rings;
  371.         union {
  372.                 struct i915_pml4 pml4;          /* GEN8+ & 48b PPGTT */
  373.                 struct i915_page_directory_pointer pdp; /* GEN8+ */
  374.                 struct i915_page_directory pd;          /* GEN6-7 */
  375.         };
  376.  
  377.         struct drm_i915_file_private *file_priv;
  378.  
  379.         gen6_pte_t __iomem *pd_addr;
  380.  
  381.         int (*enable)(struct i915_hw_ppgtt *ppgtt);
  382.         int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
  383.                          struct drm_i915_gem_request *req);
  384.         void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
  385. };
  386.  
  387. /* For each pde iterates over every pde between from start until start + length.
  388.  * If start, and start+length are not perfectly divisible, the macro will round
  389.  * down, and up as needed. The macro modifies pde, start, and length. Dev is
  390.  * only used to differentiate shift values. Temp is temp.  On gen6/7, start = 0,
  391.  * and length = 2G effectively iterates over every PDE in the system.
  392.  *
  393.  * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
  394.  */
  395. #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
  396.         for (iter = gen6_pde_index(start); \
  397.              length > 0 && iter < I915_PDES ? \
  398.                         (pt = (pd)->page_table[iter]), 1 : 0; \
  399.              iter++, \
  400.              temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
  401.              temp = min_t(unsigned, temp, length), \
  402.              start += temp, length -= temp)
  403.  
  404. #define gen6_for_all_pdes(pt, ppgtt, iter)  \
  405.         for (iter = 0;          \
  406.              pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \
  407.              iter++)
  408.  
  409. static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
  410. {
  411.         const uint32_t mask = NUM_PTE(pde_shift) - 1;
  412.  
  413.         return (address >> PAGE_SHIFT) & mask;
  414. }
  415.  
  416. /* Helper to counts the number of PTEs within the given length. This count
  417.  * does not cross a page table boundary, so the max value would be
  418.  * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
  419. */
  420. static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
  421.                                       uint32_t pde_shift)
  422. {
  423.         const uint64_t mask = ~((1 << pde_shift) - 1);
  424.         uint64_t end;
  425.  
  426.         WARN_ON(length == 0);
  427.         WARN_ON(offset_in_page(addr|length));
  428.  
  429.         end = addr + length;
  430.  
  431.         if ((addr & mask) != (end & mask))
  432.                 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
  433.  
  434.         return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
  435. }
  436.  
  437. static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
  438. {
  439.         return (addr >> shift) & I915_PDE_MASK;
  440. }
  441.  
  442. static inline uint32_t gen6_pte_index(uint32_t addr)
  443. {
  444.         return i915_pte_index(addr, GEN6_PDE_SHIFT);
  445. }
  446.  
  447. static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
  448. {
  449.         return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
  450. }
  451.  
  452. static inline uint32_t gen6_pde_index(uint32_t addr)
  453. {
  454.         return i915_pde_index(addr, GEN6_PDE_SHIFT);
  455. }
  456.  
  457. /* Equivalent to the gen6 version, For each pde iterates over every pde
  458.  * between from start until start + length. On gen8+ it simply iterates
  459.  * over every page directory entry in a page directory.
  460.  */
  461. #define gen8_for_each_pde(pt, pd, start, length, temp, iter)            \
  462.         for (iter = gen8_pde_index(start); \
  463.              length > 0 && iter < I915_PDES ? \
  464.                         (pt = (pd)->page_table[iter]), 1 : 0; \
  465.              iter++,                            \
  466.              temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start,        \
  467.              temp = min(temp, length),                                  \
  468.              start += temp, length -= temp)
  469.  
  470. #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter)  \
  471.         for (iter = gen8_pdpe_index(start); \
  472.              length > 0 && (iter < I915_PDPES_PER_PDP(dev)) ? \
  473.                         (pd = (pdp)->page_directory[iter]), 1 : 0; \
  474.              iter++,                            \
  475.              temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start,       \
  476.              temp = min(temp, length),                                  \
  477.              start += temp, length -= temp)
  478.  
  479. #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter)       \
  480.         for (iter = gen8_pml4e_index(start);    \
  481.              length > 0 && iter < GEN8_PML4ES_PER_PML4 ? \
  482.                         (pdp = (pml4)->pdps[iter]), 1 : 0; \
  483.              iter++,                            \
  484.              temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start,   \
  485.              temp = min(temp, length),                                  \
  486.              start += temp, length -= temp)
  487.  
  488. static inline uint32_t gen8_pte_index(uint64_t address)
  489. {
  490.         return i915_pte_index(address, GEN8_PDE_SHIFT);
  491. }
  492.  
  493. static inline uint32_t gen8_pde_index(uint64_t address)
  494. {
  495.         return i915_pde_index(address, GEN8_PDE_SHIFT);
  496. }
  497.  
  498. static inline uint32_t gen8_pdpe_index(uint64_t address)
  499. {
  500.         return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
  501. }
  502.  
  503. static inline uint32_t gen8_pml4e_index(uint64_t address)
  504. {
  505.         return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
  506. }
  507.  
  508. static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
  509. {
  510.         return i915_pte_count(address, length, GEN8_PDE_SHIFT);
  511. }
  512.  
  513. static inline dma_addr_t
  514. i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
  515. {
  516.         return test_bit(n, ppgtt->pdp.used_pdpes) ?
  517.                 px_dma(ppgtt->pdp.page_directory[n]) :
  518.                 px_dma(ppgtt->base.scratch_pd);
  519. }
  520.  
  521. int i915_gem_gtt_init(struct drm_device *dev);
  522. void i915_gem_init_global_gtt(struct drm_device *dev);
  523. void i915_global_gtt_cleanup(struct drm_device *dev);
  524.  
  525.  
  526. int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
  527. int i915_ppgtt_init_hw(struct drm_device *dev);
  528. int i915_ppgtt_init_ring(struct drm_i915_gem_request *req);
  529. void i915_ppgtt_release(struct kref *kref);
  530. struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
  531.                                         struct drm_i915_file_private *fpriv);
  532. static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
  533. {
  534.         if (ppgtt)
  535.                 kref_get(&ppgtt->ref);
  536. }
  537. static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
  538. {
  539.         if (ppgtt)
  540.                 kref_put(&ppgtt->ref, i915_ppgtt_release);
  541. }
  542.  
  543. void i915_check_and_clear_faults(struct drm_device *dev);
  544. void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
  545. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  546.  
  547. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  548. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  549.  
  550. static inline bool
  551. i915_ggtt_view_equal(const struct i915_ggtt_view *a,
  552.                      const struct i915_ggtt_view *b)
  553. {
  554.         if (WARN_ON(!a || !b))
  555.                 return false;
  556.  
  557.         if (a->type != b->type)
  558.                 return false;
  559.         if (a->type == I915_GGTT_VIEW_PARTIAL)
  560.                 return !memcmp(&a->params, &b->params, sizeof(a->params));
  561.         return true;
  562. }
  563.  
  564. size_t
  565. i915_ggtt_view_size(struct drm_i915_gem_object *obj,
  566.                     const struct i915_ggtt_view *view);
  567.  
  568. #endif
  569.