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  1. /*
  2.  * Copyright © 2010 Daniel Vetter
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  */
  24.  
  25. #include "drmP.h"
  26. #include "drm.h"
  27. #include "i915_drm.h"
  28. #include "i915_drv.h"
  29. //#include "i915_trace.h"
  30. #include "intel_drv.h"
  31.  
  32. #define AGP_USER_TYPES          (1 << 16)
  33. #define AGP_USER_MEMORY         (AGP_USER_TYPES)
  34. #define AGP_USER_CACHED_MEMORY  (AGP_USER_TYPES + 1)
  35.  
  36. /* XXX kill agp_type! */
  37. static unsigned int cache_level_to_agp_type(struct drm_device *dev,
  38.                                             enum i915_cache_level cache_level)
  39. {
  40.         switch (cache_level) {
  41.         case I915_CACHE_LLC_MLC:
  42.                 if (INTEL_INFO(dev)->gen >= 6)
  43.                         return AGP_USER_CACHED_MEMORY_LLC_MLC;
  44.                 /* Older chipsets do not have this extra level of CPU
  45.                  * cacheing, so fallthrough and request the PTE simply
  46.                  * as cached.
  47.                  */
  48.         case I915_CACHE_LLC:
  49.                 return AGP_USER_CACHED_MEMORY;
  50.         default:
  51.         case I915_CACHE_NONE:
  52.                 return AGP_USER_MEMORY;
  53.         }
  54. }
  55.  
  56. #if 0
  57.  
  58. void i915_gem_restore_gtt_mappings(struct drm_device *dev)
  59. {
  60.         struct drm_i915_private *dev_priv = dev->dev_private;
  61.         struct drm_i915_gem_object *obj;
  62.  
  63.         /* First fill our portion of the GTT with scratch pages */
  64.         intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
  65.                               (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
  66.  
  67.         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  68.                 i915_gem_clflush_object(obj);
  69.                 i915_gem_gtt_rebind_object(obj, obj->cache_level);
  70.         }
  71.  
  72.         intel_gtt_chipset_flush();
  73. }
  74. #endif
  75.  
  76. int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
  77. {
  78.         struct drm_device *dev = obj->base.dev;
  79.         struct drm_i915_private *dev_priv = dev->dev_private;
  80.         unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
  81.         int ret;
  82.  
  83. //   if (dev_priv->mm.gtt->needs_dmar) {
  84. //       ret = intel_gtt_map_memory(obj->pages,
  85. //                      obj->base.size >> PAGE_SHIFT,
  86. //                      &obj->sg_list,
  87. //                      &obj->num_sg);
  88. //       if (ret != 0)
  89. //           return ret;
  90.  
  91. //       intel_gtt_insert_sg_entries(obj->sg_list,
  92. //                       obj->num_sg,
  93. //                       obj->gtt_space->start >> PAGE_SHIFT,
  94. //                       agp_type);
  95. //   } else
  96.                 intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
  97.                                        obj->base.size >> PAGE_SHIFT,
  98.                                        obj->pages,
  99.                                        agp_type);
  100.  
  101.         return 0;
  102. }
  103.  
  104. #if 0
  105. void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
  106.                                 enum i915_cache_level cache_level)
  107. {
  108.         struct drm_device *dev = obj->base.dev;
  109.         struct drm_i915_private *dev_priv = dev->dev_private;
  110.         unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
  111.  
  112.         if (dev_priv->mm.gtt->needs_dmar) {
  113.                 BUG_ON(!obj->sg_list);
  114.  
  115.                 intel_gtt_insert_sg_entries(obj->sg_list,
  116.                                             obj->num_sg,
  117.                                             obj->gtt_space->start >> PAGE_SHIFT,
  118.                                             agp_type);
  119.         } else
  120.                 intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
  121.                                        obj->base.size >> PAGE_SHIFT,
  122.                                        obj->pages,
  123.                                        agp_type);
  124. }
  125.  
  126. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
  127. {
  128.         intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
  129.                               obj->base.size >> PAGE_SHIFT);
  130.  
  131.         if (obj->sg_list) {
  132.                 intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
  133.                 obj->sg_list = NULL;
  134.         }
  135. }
  136.  
  137. #endif
  138.