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  1. /*
  2.  * Copyright © 2011-2012 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Ben Widawsky <ben@bwidawsk.net>
  25.  *
  26.  */
  27.  
  28. /*
  29.  * This file implements HW context support. On gen5+ a HW context consists of an
  30.  * opaque GPU object which is referenced at times of context saves and restores.
  31.  * With RC6 enabled, the context is also referenced as the GPU enters and exists
  32.  * from RC6 (GPU has it's own internal power context, except on gen5). Though
  33.  * something like a context does exist for the media ring, the code only
  34.  * supports contexts for the render ring.
  35.  *
  36.  * In software, there is a distinction between contexts created by the user,
  37.  * and the default HW context. The default HW context is used by GPU clients
  38.  * that do not request setup of their own hardware context. The default
  39.  * context's state is never restored to help prevent programming errors. This
  40.  * would happen if a client ran and piggy-backed off another clients GPU state.
  41.  * The default context only exists to give the GPU some offset to load as the
  42.  * current to invoke a save of the context we actually care about. In fact, the
  43.  * code could likely be constructed, albeit in a more complicated fashion, to
  44.  * never use the default context, though that limits the driver's ability to
  45.  * swap out, and/or destroy other contexts.
  46.  *
  47.  * All other contexts are created as a request by the GPU client. These contexts
  48.  * store GPU state, and thus allow GPU clients to not re-emit state (and
  49.  * potentially query certain state) at any time. The kernel driver makes
  50.  * certain that the appropriate commands are inserted.
  51.  *
  52.  * The context life cycle is semi-complicated in that context BOs may live
  53.  * longer than the context itself because of the way the hardware, and object
  54.  * tracking works. Below is a very crude representation of the state machine
  55.  * describing the context life.
  56.  *                                         refcount     pincount     active
  57.  * S0: initial state                          0            0           0
  58.  * S1: context created                        1            0           0
  59.  * S2: context is currently running           2            1           X
  60.  * S3: GPU referenced, but not current        2            0           1
  61.  * S4: context is current, but destroyed      1            1           0
  62.  * S5: like S3, but destroyed                 1            0           1
  63.  *
  64.  * The most common (but not all) transitions:
  65.  * S0->S1: client creates a context
  66.  * S1->S2: client submits execbuf with context
  67.  * S2->S3: other clients submits execbuf with context
  68.  * S3->S1: context object was retired
  69.  * S3->S2: clients submits another execbuf
  70.  * S2->S4: context destroy called with current context
  71.  * S3->S5->S0: destroy path
  72.  * S4->S5->S0: destroy path on current context
  73.  *
  74.  * There are two confusing terms used above:
  75.  *  The "current context" means the context which is currently running on the
  76.  *  GPU. The GPU has loaded its state already and has stored away the gtt
  77.  *  offset of the BO. The GPU is not actively referencing the data at this
  78.  *  offset, but it will on the next context switch. The only way to avoid this
  79.  *  is to do a GPU reset.
  80.  *
  81.  *  An "active context' is one which was previously the "current context" and is
  82.  *  on the active list waiting for the next context switch to occur. Until this
  83.  *  happens, the object must remain at the same gtt offset. It is therefore
  84.  *  possible to destroy a context, but it is still active.
  85.  *
  86.  */
  87.  
  88. #include <drm/drmP.h>
  89. #include <drm/i915_drm.h>
  90. #include "i915_drv.h"
  91. #include "i915_trace.h"
  92.  
  93. /* This is a HW constraint. The value below is the largest known requirement
  94.  * I've seen in a spec to date, and that was a workaround for a non-shipping
  95.  * part. It should be safe to decrease this, but it's more future proof as is.
  96.  */
  97. #define GEN6_CONTEXT_ALIGN (64<<10)
  98. #define GEN7_CONTEXT_ALIGN 4096
  99.  
  100. static size_t get_context_alignment(struct drm_device *dev)
  101. {
  102.         if (IS_GEN6(dev))
  103.                 return GEN6_CONTEXT_ALIGN;
  104.  
  105.         return GEN7_CONTEXT_ALIGN;
  106. }
  107.  
  108. static int get_context_size(struct drm_device *dev)
  109. {
  110.         struct drm_i915_private *dev_priv = dev->dev_private;
  111.         int ret;
  112.         u32 reg;
  113.  
  114.         switch (INTEL_INFO(dev)->gen) {
  115.         case 6:
  116.                 reg = I915_READ(CXT_SIZE);
  117.                 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
  118.                 break;
  119.         case 7:
  120.                 reg = I915_READ(GEN7_CXT_SIZE);
  121.                 if (IS_HASWELL(dev))
  122.                         ret = HSW_CXT_TOTAL_SIZE;
  123.                 else
  124.                         ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
  125.                 break;
  126.         case 8:
  127.                 ret = GEN8_CXT_TOTAL_SIZE;
  128.                 break;
  129.         default:
  130.                 BUG();
  131.         }
  132.  
  133.         return ret;
  134. }
  135.  
  136. void i915_gem_context_free(struct kref *ctx_ref)
  137. {
  138.         struct intel_context *ctx = container_of(ctx_ref,
  139.                                                    typeof(*ctx), ref);
  140.  
  141.         trace_i915_context_free(ctx);
  142.  
  143.         if (i915.enable_execlists)
  144.                 intel_lr_context_free(ctx);
  145.  
  146.         i915_ppgtt_put(ctx->ppgtt);
  147.  
  148.         if (ctx->legacy_hw_ctx.rcs_state)
  149.                 drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
  150.         list_del(&ctx->link);
  151.         kfree(ctx);
  152. }
  153.  
  154. struct drm_i915_gem_object *
  155. i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
  156. {
  157.         struct drm_i915_gem_object *obj;
  158.         int ret;
  159.  
  160.         obj = i915_gem_alloc_object(dev, size);
  161.         if (obj == NULL)
  162.                 return ERR_PTR(-ENOMEM);
  163.  
  164.         /*
  165.          * Try to make the context utilize L3 as well as LLC.
  166.          *
  167.          * On VLV we don't have L3 controls in the PTEs so we
  168.          * shouldn't touch the cache level, especially as that
  169.          * would make the object snooped which might have a
  170.          * negative performance impact.
  171.          */
  172.         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
  173.                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
  174.                 /* Failure shouldn't ever happen this early */
  175.                 if (WARN_ON(ret)) {
  176.                         drm_gem_object_unreference(&obj->base);
  177.                         return ERR_PTR(ret);
  178.                 }
  179.         }
  180.  
  181.         return obj;
  182. }
  183.  
  184. static struct intel_context *
  185. __create_hw_context(struct drm_device *dev,
  186.                   struct drm_i915_file_private *file_priv)
  187. {
  188.         struct drm_i915_private *dev_priv = dev->dev_private;
  189.         struct intel_context *ctx;
  190.         int ret;
  191.  
  192.         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  193.         if (ctx == NULL)
  194.                 return ERR_PTR(-ENOMEM);
  195.  
  196.         kref_init(&ctx->ref);
  197.         list_add_tail(&ctx->link, &dev_priv->context_list);
  198.  
  199.         if (dev_priv->hw_context_size) {
  200.                 struct drm_i915_gem_object *obj =
  201.                                 i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
  202.                 if (IS_ERR(obj)) {
  203.                         ret = PTR_ERR(obj);
  204.                         goto err_out;
  205.         }
  206.                 ctx->legacy_hw_ctx.rcs_state = obj;
  207.         }
  208.  
  209.         /* Default context will never have a file_priv */
  210.         if (file_priv != NULL) {
  211.                 ret = idr_alloc(&file_priv->context_idr, ctx,
  212.                                 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
  213.         if (ret < 0)
  214.                 goto err_out;
  215.         } else
  216.                 ret = DEFAULT_CONTEXT_HANDLE;
  217.  
  218.         ctx->file_priv = file_priv;
  219.         ctx->user_handle = ret;
  220.         /* NB: Mark all slices as needing a remap so that when the context first
  221.          * loads it will restore whatever remap state already exists. If there
  222.          * is no remap info, it will be a NOP. */
  223.         ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
  224.  
  225.         return ctx;
  226.  
  227. err_out:
  228.         i915_gem_context_unreference(ctx);
  229.         return ERR_PTR(ret);
  230. }
  231.  
  232. /**
  233.  * The default context needs to exist per ring that uses contexts. It stores the
  234.  * context state of the GPU for applications that don't utilize HW contexts, as
  235.  * well as an idle case.
  236.  */
  237. static struct intel_context *
  238. i915_gem_create_context(struct drm_device *dev,
  239.                         struct drm_i915_file_private *file_priv)
  240. {
  241.         const bool is_global_default_ctx = file_priv == NULL;
  242.         struct intel_context *ctx;
  243.         int ret = 0;
  244.  
  245.         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  246.  
  247.         ctx = __create_hw_context(dev, file_priv);
  248.         if (IS_ERR(ctx))
  249.                 return ctx;
  250.  
  251.         if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
  252.                 /* We may need to do things with the shrinker which
  253.                  * require us to immediately switch back to the default
  254.                  * context. This can cause a problem as pinning the
  255.                  * default context also requires GTT space which may not
  256.                  * be available. To avoid this we always pin the default
  257.                  * context.
  258.          */
  259.                 ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
  260.                                             get_context_alignment(dev), 0);
  261.         if (ret) {
  262.                 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
  263.                 goto err_destroy;
  264.         }
  265.         }
  266.  
  267.         if (USES_FULL_PPGTT(dev)) {
  268.                 struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
  269.  
  270.                 if (IS_ERR_OR_NULL(ppgtt)) {
  271.                         DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
  272.                                          PTR_ERR(ppgtt));
  273.                         ret = PTR_ERR(ppgtt);
  274.                         goto err_unpin;
  275.                 }
  276.  
  277.                 ctx->ppgtt = ppgtt;
  278.         }
  279.  
  280.         trace_i915_context_create(ctx);
  281.  
  282.         return ctx;
  283.  
  284. err_unpin:
  285.         if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
  286.                 i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
  287. err_destroy:
  288.         i915_gem_context_unreference(ctx);
  289.         return ERR_PTR(ret);
  290. }
  291.  
  292. void i915_gem_context_reset(struct drm_device *dev)
  293. {
  294.         struct drm_i915_private *dev_priv = dev->dev_private;
  295.         int i;
  296.  
  297.         /* In execlists mode we will unreference the context when the execlist
  298.          * queue is cleared and the requests destroyed.
  299.          */
  300.         if (i915.enable_execlists)
  301.                 return;
  302.  
  303.         for (i = 0; i < I915_NUM_RINGS; i++) {
  304.                 struct intel_engine_cs *ring = &dev_priv->ring[i];
  305.                 struct intel_context *lctx = ring->last_context;
  306.  
  307.                 if (lctx) {
  308.                 if (lctx->legacy_hw_ctx.rcs_state && i == RCS)
  309.                         i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);
  310.  
  311.                 i915_gem_context_unreference(lctx);
  312.                         ring->last_context = NULL;
  313.                 }
  314.         }
  315. }
  316.  
  317. int i915_gem_context_init(struct drm_device *dev)
  318. {
  319.         struct drm_i915_private *dev_priv = dev->dev_private;
  320.         struct intel_context *ctx;
  321.         int i;
  322.  
  323.         /* Init should only be called once per module load. Eventually the
  324.          * restriction on the context_disabled check can be loosened. */
  325.         if (WARN_ON(dev_priv->ring[RCS].default_context))
  326.                 return 0;
  327.  
  328.         if (i915.enable_execlists) {
  329.                 /* NB: intentionally left blank. We will allocate our own
  330.                  * backing objects as we need them, thank you very much */
  331.                 dev_priv->hw_context_size = 0;
  332.         } else if (HAS_HW_CONTEXTS(dev)) {
  333.         dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
  334.         if (dev_priv->hw_context_size > (1<<20)) {
  335.                         DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
  336.                                          dev_priv->hw_context_size);
  337.                         dev_priv->hw_context_size = 0;
  338.                 }
  339.         }
  340.  
  341.         ctx = i915_gem_create_context(dev, NULL);
  342.         if (IS_ERR(ctx)) {
  343.                 DRM_ERROR("Failed to create default global context (error %ld)\n",
  344.                           PTR_ERR(ctx));
  345.                 return PTR_ERR(ctx);
  346.         }
  347.  
  348.         for (i = 0; i < I915_NUM_RINGS; i++) {
  349.                 struct intel_engine_cs *ring = &dev_priv->ring[i];
  350.  
  351.         /* NB: RCS will hold a ref for all rings */
  352.                 ring->default_context = ctx;
  353.         }
  354.  
  355.         DRM_DEBUG_DRIVER("%s context support initialized\n",
  356.                         i915.enable_execlists ? "LR" :
  357.                         dev_priv->hw_context_size ? "HW" : "fake");
  358.         return 0;
  359. }
  360.  
  361. void i915_gem_context_fini(struct drm_device *dev)
  362. {
  363.         struct drm_i915_private *dev_priv = dev->dev_private;
  364.         struct intel_context *dctx = dev_priv->ring[RCS].default_context;
  365.         int i;
  366.  
  367.         if (dctx->legacy_hw_ctx.rcs_state) {
  368.         /* The only known way to stop the gpu from accessing the hw context is
  369.          * to reset it. Do this as the very last operation to avoid confusing
  370.          * other code, leading to spurious errors. */
  371.         intel_gpu_reset(dev);
  372.  
  373.         /* When default context is created and switched to, base object refcount
  374.          * will be 2 (+1 from object creation and +1 from do_switch()).
  375.          * i915_gem_context_fini() will be called after gpu_idle() has switched
  376.          * to default context. So we need to unreference the base object once
  377.          * to offset the do_switch part, so that i915_gem_context_unreference()
  378.          * can then free the base object correctly. */
  379.         WARN_ON(!dev_priv->ring[RCS].last_context);
  380.         if (dev_priv->ring[RCS].last_context == dctx) {
  381.                 /* Fake switch to NULL context */
  382.                         WARN_ON(dctx->legacy_hw_ctx.rcs_state->active);
  383.                         i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
  384.         i915_gem_context_unreference(dctx);
  385.                         dev_priv->ring[RCS].last_context = NULL;
  386.         }
  387.  
  388.                 i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
  389.         }
  390.  
  391.         for (i = 0; i < I915_NUM_RINGS; i++) {
  392.                 struct intel_engine_cs *ring = &dev_priv->ring[i];
  393.  
  394.                 if (ring->last_context)
  395.                         i915_gem_context_unreference(ring->last_context);
  396.  
  397.                 ring->default_context = NULL;
  398.                 ring->last_context = NULL;
  399.         }
  400.  
  401.         i915_gem_context_unreference(dctx);
  402. }
  403.  
  404. int i915_gem_context_enable(struct drm_i915_private *dev_priv)
  405. {
  406.         struct intel_engine_cs *ring;
  407.         int ret, i;
  408.  
  409.         BUG_ON(!dev_priv->ring[RCS].default_context);
  410.  
  411.         if (i915.enable_execlists)
  412.                 return 0;
  413.  
  414.         for_each_ring(ring, dev_priv, i) {
  415.                 ret = i915_switch_context(ring, ring->default_context);
  416.                 if (ret)
  417.                         return ret;
  418.         }
  419.  
  420.         return 0;
  421. }
  422.  
  423. static int context_idr_cleanup(int id, void *p, void *data)
  424. {
  425.         struct intel_context *ctx = p;
  426.  
  427.         i915_gem_context_unreference(ctx);
  428.         return 0;
  429. }
  430.  
  431. int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
  432. {
  433.         struct drm_i915_file_private *file_priv = file->driver_priv;
  434.         struct intel_context *ctx;
  435.  
  436.         idr_init(&file_priv->context_idr);
  437.  
  438.         mutex_lock(&dev->struct_mutex);
  439.         ctx = i915_gem_create_context(dev, file_priv);
  440.         mutex_unlock(&dev->struct_mutex);
  441.  
  442.         if (IS_ERR(ctx)) {
  443.                 idr_destroy(&file_priv->context_idr);
  444.                 return PTR_ERR(ctx);
  445.         }
  446.  
  447.         return 0;
  448. }
  449.  
  450. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
  451. {
  452.         struct drm_i915_file_private *file_priv = file->driver_priv;
  453.  
  454.         idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
  455.         idr_destroy(&file_priv->context_idr);
  456. }
  457.  
  458. struct intel_context *
  459. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
  460. {
  461.         struct intel_context *ctx;
  462.  
  463.         ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
  464.         if (!ctx)
  465.                 return ERR_PTR(-ENOENT);
  466.  
  467.         return ctx;
  468. }
  469.  
  470. static inline int
  471. mi_set_context(struct intel_engine_cs *ring,
  472.                struct intel_context *new_context,
  473.                u32 hw_flags)
  474. {
  475.         u32 flags = hw_flags | MI_MM_SPACE_GTT;
  476.         const int num_rings =
  477.                 /* Use an extended w/a on ivb+ if signalling from other rings */
  478.                 i915_semaphore_is_enabled(ring->dev) ?
  479.                 hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
  480.                 0;
  481.         int len, i, ret;
  482.  
  483.         /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
  484.          * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
  485.          * explicitly, so we rely on the value at ring init, stored in
  486.          * itlb_before_ctx_switch.
  487.          */
  488.         if (IS_GEN6(ring->dev)) {
  489.                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
  490.                 if (ret)
  491.                         return ret;
  492.         }
  493.  
  494.         /* These flags are for resource streamer on HSW+ */
  495.         if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
  496.                 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
  497.  
  498.  
  499.         len = 4;
  500.         if (INTEL_INFO(ring->dev)->gen >= 7)
  501.                 len += 2 + (num_rings ? 4*num_rings + 2 : 0);
  502.  
  503.         ret = intel_ring_begin(ring, len);
  504.         if (ret)
  505.                 return ret;
  506.  
  507.         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
  508.         if (INTEL_INFO(ring->dev)->gen >= 7) {
  509.                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
  510.                 if (num_rings) {
  511.                         struct intel_engine_cs *signaller;
  512.  
  513.                         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
  514.                         for_each_ring(signaller, to_i915(ring->dev), i) {
  515.                                 if (signaller == ring)
  516.                                         continue;
  517.  
  518.                                 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
  519.                                 intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
  520.                         }
  521.                 }
  522.         }
  523.  
  524.         intel_ring_emit(ring, MI_NOOP);
  525.         intel_ring_emit(ring, MI_SET_CONTEXT);
  526.         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) |
  527.                         flags);
  528.         /*
  529.          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
  530.          * WaMiSetContext_Hang:snb,ivb,vlv
  531.          */
  532.         intel_ring_emit(ring, MI_NOOP);
  533.  
  534.         if (INTEL_INFO(ring->dev)->gen >= 7) {
  535.                 if (num_rings) {
  536.                         struct intel_engine_cs *signaller;
  537.  
  538.                         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
  539.                         for_each_ring(signaller, to_i915(ring->dev), i) {
  540.                                 if (signaller == ring)
  541.                                         continue;
  542.  
  543.                                 intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
  544.                                 intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
  545.                         }
  546.                 }
  547.                 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
  548.         }
  549.  
  550.         intel_ring_advance(ring);
  551.  
  552.         return ret;
  553. }
  554.  
  555. static int do_switch(struct intel_engine_cs *ring,
  556.                      struct intel_context *to)
  557. {
  558.         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  559.         struct intel_context *from = ring->last_context;
  560.         u32 hw_flags = 0;
  561.         bool uninitialized = false;
  562.         struct i915_vma *vma;
  563.         int ret, i;
  564.  
  565.         if (from != NULL && ring == &dev_priv->ring[RCS]) {
  566.                 BUG_ON(from->legacy_hw_ctx.rcs_state == NULL);
  567.                 BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state));
  568.         }
  569.  
  570.         if (from == to && !to->remap_slice)
  571.                 return 0;
  572.  
  573.         /* Trying to pin first makes error handling easier. */
  574.         if (ring == &dev_priv->ring[RCS]) {
  575.                 ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
  576.                                             get_context_alignment(ring->dev), 0);
  577.         if (ret)
  578.                 return ret;
  579.         }
  580.  
  581.         /*
  582.          * Pin can switch back to the default context if we end up calling into
  583.          * evict_everything - as a last ditch gtt defrag effort that also
  584.          * switches to the default context. Hence we need to reload from here.
  585.          */
  586.         from = ring->last_context;
  587.  
  588.         if (to->ppgtt) {
  589.                 trace_switch_mm(ring, to);
  590.                 ret = to->ppgtt->switch_mm(to->ppgtt, ring);
  591.                 if (ret)
  592.                         goto unpin_out;
  593.         }
  594.  
  595.         if (ring != &dev_priv->ring[RCS]) {
  596.                 if (from)
  597.                         i915_gem_context_unreference(from);
  598.                 goto done;
  599.         }
  600.  
  601.         /*
  602.          * Clear this page out of any CPU caches for coherent swap-in/out. Note
  603.          * that thanks to write = false in this call and us not setting any gpu
  604.          * write domains when putting a context object onto the active list
  605.          * (when switching away from it), this won't block.
  606.          *
  607.          * XXX: We need a real interface to do this instead of trickery.
  608.          */
  609.         ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
  610.         if (ret)
  611.                 goto unpin_out;
  612.  
  613.         vma = i915_gem_obj_to_ggtt(to->legacy_hw_ctx.rcs_state);
  614.         if (!(vma->bound & GLOBAL_BIND))
  615.                 vma->bind_vma(vma, to->legacy_hw_ctx.rcs_state->cache_level,
  616.                                 GLOBAL_BIND);
  617.  
  618.         if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to))
  619.                 hw_flags |= MI_RESTORE_INHIBIT;
  620.  
  621.         ret = mi_set_context(ring, to, hw_flags);
  622.         if (ret)
  623.                 goto unpin_out;
  624.  
  625.         for (i = 0; i < MAX_L3_SLICES; i++) {
  626.                 if (!(to->remap_slice & (1<<i)))
  627.                         continue;
  628.  
  629.                 ret = i915_gem_l3_remap(ring, i);
  630.                 /* If it failed, try again next round */
  631.                 if (ret)
  632.                         DRM_DEBUG_DRIVER("L3 remapping failed\n");
  633.                 else
  634.                         to->remap_slice &= ~(1<<i);
  635.         }
  636.  
  637.         /* The backing object for the context is done after switching to the
  638.          * *next* context. Therefore we cannot retire the previous context until
  639.          * the next context has already started running. In fact, the below code
  640.          * is a bit suboptimal because the retiring can occur simply after the
  641.          * MI_SET_CONTEXT instead of when the next seqno has completed.
  642.          */
  643.         if (from != NULL) {
  644.                 from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
  645.                 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), ring);
  646.                 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
  647.                  * whole damn pipeline, we don't need to explicitly mark the
  648.                  * object dirty. The only exception is that the context must be
  649.                  * correct in case the object gets swapped out. Ideally we'd be
  650.                  * able to defer doing this until we know the object would be
  651.                  * swapped, but there is no way to do that yet.
  652.                  */
  653.                 from->legacy_hw_ctx.rcs_state->dirty = 1;
  654.                 BUG_ON(from->legacy_hw_ctx.rcs_state->ring != ring);
  655.  
  656.                 /* obj is kept alive until the next request by its active ref */
  657.                 i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
  658.                 i915_gem_context_unreference(from);
  659.         }
  660.  
  661.         uninitialized = !to->legacy_hw_ctx.initialized && from == NULL;
  662.         to->legacy_hw_ctx.initialized = true;
  663.  
  664. done:
  665.         i915_gem_context_reference(to);
  666.         ring->last_context = to;
  667.  
  668.         if (uninitialized) {
  669.                 if (ring->init_context) {
  670.                         ret = ring->init_context(ring, to);
  671.                         if (ret)
  672.                                 DRM_ERROR("ring init context: %d\n", ret);
  673.                 }
  674.  
  675.                 ret = i915_gem_render_state_init(ring);
  676.                 if (ret)
  677.                         DRM_ERROR("init render state: %d\n", ret);
  678.         }
  679.  
  680.         return 0;
  681.  
  682. unpin_out:
  683.         if (ring->id == RCS)
  684.                 i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
  685.         return ret;
  686. }
  687.  
  688. /**
  689.  * i915_switch_context() - perform a GPU context switch.
  690.  * @ring: ring for which we'll execute the context switch
  691.  * @to: the context to switch to
  692.  *
  693.  * The context life cycle is simple. The context refcount is incremented and
  694.  * decremented by 1 and create and destroy. If the context is in use by the GPU,
  695.  * it will have a refcount > 1. This allows us to destroy the context abstract
  696.  * object while letting the normal object tracking destroy the backing BO.
  697.  *
  698.  * This function should not be used in execlists mode.  Instead the context is
  699.  * switched by writing to the ELSP and requests keep a reference to their
  700.  * context.
  701.  */
  702. int i915_switch_context(struct intel_engine_cs *ring,
  703.                         struct intel_context *to)
  704. {
  705.         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  706.  
  707.         WARN_ON(i915.enable_execlists);
  708.         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  709.  
  710.         if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
  711.                 if (to != ring->last_context) {
  712.                         i915_gem_context_reference(to);
  713.                         if (ring->last_context)
  714.                                 i915_gem_context_unreference(ring->last_context);
  715.                         ring->last_context = to;
  716.                 }
  717.                 return 0;
  718.         }
  719.  
  720.         return do_switch(ring, to);
  721. }
  722.  
  723. static bool contexts_enabled(struct drm_device *dev)
  724. {
  725.         return i915.enable_execlists || to_i915(dev)->hw_context_size;
  726. }
  727.  
  728. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  729.                                   struct drm_file *file)
  730. {
  731.         struct drm_i915_gem_context_create *args = data;
  732.         struct drm_i915_file_private *file_priv = file->driver_priv;
  733.         struct intel_context *ctx;
  734.         int ret;
  735.  
  736.         if (!contexts_enabled(dev))
  737.                 return -ENODEV;
  738.  
  739.         ret = i915_mutex_lock_interruptible(dev);
  740.         if (ret)
  741.                 return ret;
  742.  
  743.         ctx = i915_gem_create_context(dev, file_priv);
  744.         mutex_unlock(&dev->struct_mutex);
  745.         if (IS_ERR(ctx))
  746.                 return PTR_ERR(ctx);
  747.  
  748.         args->ctx_id = ctx->user_handle;
  749.         DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
  750.  
  751.         return 0;
  752. }
  753.  
  754. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  755.                                    struct drm_file *file)
  756. {
  757.         struct drm_i915_gem_context_destroy *args = data;
  758.         struct drm_i915_file_private *file_priv = file->driver_priv;
  759.         struct intel_context *ctx;
  760.         int ret;
  761.  
  762.         if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
  763.                 return -ENOENT;
  764.  
  765.         ret = i915_mutex_lock_interruptible(dev);
  766.         if (ret)
  767.                 return ret;
  768.  
  769.         ctx = i915_gem_context_get(file_priv, args->ctx_id);
  770.         if (IS_ERR(ctx)) {
  771.                 mutex_unlock(&dev->struct_mutex);
  772.                 return PTR_ERR(ctx);
  773.         }
  774.  
  775.         idr_remove(&ctx->file_priv->context_idr, ctx->user_handle);
  776.         i915_gem_context_unreference(ctx);
  777.         mutex_unlock(&dev->struct_mutex);
  778.  
  779.         DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
  780.         return 0;
  781. }
  782.