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  1. /*
  2.  * Copyright © 2008 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "i915_drm.h"
  31. #include "i915_drv.h"
  32. //#include "i915_trace.h"
  33. #include "intel_drv.h"
  34. //#include <linux/shmem_fs.h>
  35. #include <linux/slab.h>
  36. //#include <linux/swap.h>
  37. #include <linux/pci.h>
  38.  
  39. #define I915_EXEC_CONSTANTS_MASK        (3<<6)
  40. #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
  41. #define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
  42. #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
  43.  
  44.  
  45. /**
  46.  * i915_gem_clear_fence_reg - clear out fence register info
  47.  * @obj: object to clear
  48.  *
  49.  * Zeroes out the fence register itself and clears out the associated
  50.  * data structures in dev_priv and obj.
  51.  */
  52. static void
  53. i915_gem_clear_fence_reg(struct drm_device *dev,
  54.              struct drm_i915_fence_reg *reg)
  55. {
  56.     drm_i915_private_t *dev_priv = dev->dev_private;
  57.     uint32_t fence_reg = reg - dev_priv->fence_regs;
  58.  
  59.     switch (INTEL_INFO(dev)->gen) {
  60.     case 7:
  61.     case 6:
  62.         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
  63.         break;
  64.     case 5:
  65.     case 4:
  66.         I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
  67.         break;
  68.     case 3:
  69.         if (fence_reg >= 8)
  70.             fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
  71.         else
  72.     case 2:
  73.             fence_reg = FENCE_REG_830_0 + fence_reg * 4;
  74.  
  75.         I915_WRITE(fence_reg, 0);
  76.         break;
  77.     }
  78.  
  79.     list_del_init(&reg->lru_list);
  80.     reg->obj = NULL;
  81.     reg->setup_seqno = 0;
  82. }
  83.  
  84.  
  85. static void
  86. init_ring_lists(struct intel_ring_buffer *ring)
  87. {
  88.     INIT_LIST_HEAD(&ring->active_list);
  89.     INIT_LIST_HEAD(&ring->request_list);
  90.     INIT_LIST_HEAD(&ring->gpu_write_list);
  91. }
  92.  
  93.  
  94. void
  95. i915_gem_load(struct drm_device *dev)
  96. {
  97.     int i;
  98.     drm_i915_private_t *dev_priv = dev->dev_private;
  99.  
  100.     INIT_LIST_HEAD(&dev_priv->mm.active_list);
  101.     INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
  102.     INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
  103.     INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
  104.     INIT_LIST_HEAD(&dev_priv->mm.fence_list);
  105.     INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
  106.     INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
  107.     for (i = 0; i < I915_NUM_RINGS; i++)
  108.         init_ring_lists(&dev_priv->ring[i]);
  109.     for (i = 0; i < 16; i++)
  110.         INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
  111. //    INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
  112. //              i915_gem_retire_work_handler);
  113. //    init_completion(&dev_priv->error_completion);
  114.  
  115.     /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
  116.     if (IS_GEN3(dev)) {
  117.         u32 tmp = I915_READ(MI_ARB_STATE);
  118.         if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
  119.             /* arb state is a masked write, so set bit + bit in mask */
  120.             tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
  121.             I915_WRITE(MI_ARB_STATE, tmp);
  122.         }
  123.     }
  124.  
  125.     dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
  126.  
  127.     if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  128.         dev_priv->num_fence_regs = 16;
  129.     else
  130.         dev_priv->num_fence_regs = 8;
  131.  
  132.     /* Initialize fence registers to zero */
  133.     for (i = 0; i < dev_priv->num_fence_regs; i++) {
  134.         i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
  135.     }
  136.  
  137.     i915_gem_detect_bit_6_swizzle(dev);
  138. //    init_waitqueue_head(&dev_priv->pending_flip_queue);
  139.  
  140.     dev_priv->mm.interruptible = true;
  141.  
  142. //    dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
  143. //    dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
  144. //    register_shrinker(&dev_priv->mm.inactive_shrinker);
  145. }
  146.  
  147.  
  148.  
  149.