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  1. /*
  2.  * Copyright © 2008 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #include <drm/drmP.h>
  29. #include <drm/drm_vma_manager.h>
  30. #include <drm/i915_drm.h>
  31. #include "i915_drv.h"
  32. #include "i915_trace.h"
  33. #include "intel_drv.h"
  34. #include <linux/shmem_fs.h>
  35. #include <linux/slab.h>
  36. //#include <linux/swap.h>
  37. #include <linux/scatterlist.h>
  38. #include <linux/pci.h>
  39.  
  40. extern int x86_clflush_size;
  41.  
  42. #define PROT_READ       0x1             /* page can be read */
  43. #define PROT_WRITE      0x2             /* page can be written */
  44. #define MAP_SHARED      0x01            /* Share changes */
  45.  
  46.  
  47. u64 nsecs_to_jiffies64(u64 n)
  48. {
  49. #if (NSEC_PER_SEC % HZ) == 0
  50.         /* Common case, HZ = 100, 128, 200, 250, 256, 500, 512, 1000 etc. */
  51.         return div_u64(n, NSEC_PER_SEC / HZ);
  52. #elif (HZ % 512) == 0
  53.         /* overflow after 292 years if HZ = 1024 */
  54.         return div_u64(n * HZ / 512, NSEC_PER_SEC / 512);
  55. #else
  56.         /*
  57.          * Generic case - optimized for cases where HZ is a multiple of 3.
  58.          * overflow after 64.99 years, exact for HZ = 60, 72, 90, 120 etc.
  59.          */
  60.         return div_u64(n * 9, (9ull * NSEC_PER_SEC + HZ / 2) / HZ);
  61. #endif
  62. }
  63.  
  64. unsigned long nsecs_to_jiffies(u64 n)
  65. {
  66.     return (unsigned long)nsecs_to_jiffies64(n);
  67. }
  68.  
  69.  
  70. struct drm_i915_gem_object *get_fb_obj();
  71.  
  72. unsigned long vm_mmap(struct file *file, unsigned long addr,
  73.          unsigned long len, unsigned long prot,
  74.          unsigned long flag, unsigned long offset);
  75.  
  76. static inline void clflush(volatile void *__p)
  77. {
  78.     asm volatile("clflush %0" : "+m" (*(volatile char*)__p));
  79. }
  80.  
  81. #define MAX_ERRNO       4095
  82.  
  83. #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
  84.  
  85.  
  86. static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  87. static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  88.                                                    bool force);
  89. static __must_check int
  90. i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  91.                                bool readonly);
  92. static void
  93. i915_gem_object_retire(struct drm_i915_gem_object *obj);
  94.  
  95. static void i915_gem_write_fence(struct drm_device *dev, int reg,
  96.                                  struct drm_i915_gem_object *obj);
  97. static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  98.                                          struct drm_i915_fence_reg *fence,
  99.                                          bool enable);
  100.  
  101. static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  102. static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  103.  
  104. static bool cpu_cache_is_coherent(struct drm_device *dev,
  105.                                   enum i915_cache_level level)
  106. {
  107.         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  108. }
  109.  
  110. static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  111. {
  112.         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  113.                 return true;
  114.  
  115.         return obj->pin_display;
  116. }
  117.  
  118. static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  119. {
  120.         if (obj->tiling_mode)
  121.                 i915_gem_release_mmap(obj);
  122.  
  123.         /* As we do not have an associated fence register, we will force
  124.          * a tiling change if we ever need to acquire one.
  125.          */
  126.         obj->fence_dirty = false;
  127.         obj->fence_reg = I915_FENCE_REG_NONE;
  128. }
  129.  
  130. /* some bookkeeping */
  131. static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  132.                                   size_t size)
  133. {
  134.         spin_lock(&dev_priv->mm.object_stat_lock);
  135.         dev_priv->mm.object_count++;
  136.         dev_priv->mm.object_memory += size;
  137.         spin_unlock(&dev_priv->mm.object_stat_lock);
  138. }
  139.  
  140. static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  141.                                      size_t size)
  142. {
  143.         spin_lock(&dev_priv->mm.object_stat_lock);
  144.         dev_priv->mm.object_count--;
  145.         dev_priv->mm.object_memory -= size;
  146.         spin_unlock(&dev_priv->mm.object_stat_lock);
  147. }
  148.  
  149. static int
  150. i915_gem_wait_for_error(struct i915_gpu_error *error)
  151. {
  152.         int ret;
  153.  
  154. #define EXIT_COND (!i915_reset_in_progress(error))
  155.         if (EXIT_COND)
  156.                 return 0;
  157. #if 0
  158.         /*
  159.          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
  160.          * userspace. If it takes that long something really bad is going on and
  161.          * we should simply try to bail out and fail as gracefully as possible.
  162.          */
  163.         ret = wait_event_interruptible_timeout(error->reset_queue,
  164.                                                EXIT_COND,
  165.                                                10*HZ);
  166.         if (ret == 0) {
  167.                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
  168.                 return -EIO;
  169.         } else if (ret < 0) {
  170.                 return ret;
  171.         }
  172.  
  173. #endif
  174. #undef EXIT_COND
  175.  
  176.         return 0;
  177. }
  178.  
  179. int i915_mutex_lock_interruptible(struct drm_device *dev)
  180. {
  181.         struct drm_i915_private *dev_priv = dev->dev_private;
  182.         int ret;
  183.  
  184.         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
  185.         if (ret)
  186.                 return ret;
  187.  
  188.         ret = mutex_lock_interruptible(&dev->struct_mutex);
  189.         if (ret)
  190.                 return ret;
  191.  
  192.         WARN_ON(i915_verify_lists(dev));
  193.         return 0;
  194. }
  195.  
  196. static inline bool
  197. i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
  198. {
  199.         return i915_gem_obj_bound_any(obj) && !obj->active;
  200. }
  201.  
  202.  
  203. #if 0
  204.  
  205. int
  206. i915_gem_init_ioctl(struct drm_device *dev, void *data,
  207.                     struct drm_file *file)
  208. {
  209.         struct drm_i915_private *dev_priv = dev->dev_private;
  210.         struct drm_i915_gem_init *args = data;
  211.  
  212.         if (drm_core_check_feature(dev, DRIVER_MODESET))
  213.                 return -ENODEV;
  214.  
  215.         if (args->gtt_start >= args->gtt_end ||
  216.             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
  217.                 return -EINVAL;
  218.  
  219.         /* GEM with user mode setting was never supported on ilk and later. */
  220.         if (INTEL_INFO(dev)->gen >= 5)
  221.                 return -ENODEV;
  222.  
  223.         mutex_lock(&dev->struct_mutex);
  224.         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
  225.                                   args->gtt_end);
  226.         dev_priv->gtt.mappable_end = args->gtt_end;
  227.         mutex_unlock(&dev->struct_mutex);
  228.  
  229.         return 0;
  230. }
  231. #endif
  232.  
  233. int
  234. i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  235.                             struct drm_file *file)
  236. {
  237.         struct drm_i915_private *dev_priv = dev->dev_private;
  238.         struct drm_i915_gem_get_aperture *args = data;
  239.         struct drm_i915_gem_object *obj;
  240.         size_t pinned;
  241.  
  242.         pinned = 0;
  243.         mutex_lock(&dev->struct_mutex);
  244.         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
  245.                 if (i915_gem_obj_is_pinned(obj))
  246.                         pinned += i915_gem_obj_ggtt_size(obj);
  247.         mutex_unlock(&dev->struct_mutex);
  248.  
  249.         args->aper_size = dev_priv->gtt.base.total;
  250.         args->aper_available_size = args->aper_size - pinned;
  251.  
  252.         return 0;
  253. }
  254.  
  255. void *i915_gem_object_alloc(struct drm_device *dev)
  256. {
  257.         struct drm_i915_private *dev_priv = dev->dev_private;
  258.         return kmalloc(sizeof(struct drm_i915_gem_object), 0);
  259. }
  260.  
  261. void i915_gem_object_free(struct drm_i915_gem_object *obj)
  262. {
  263.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  264.         kfree(obj);
  265. }
  266.  
  267. static int
  268. i915_gem_create(struct drm_file *file,
  269.                 struct drm_device *dev,
  270.                 uint64_t size,
  271.                 uint32_t *handle_p)
  272. {
  273.         struct drm_i915_gem_object *obj;
  274.         int ret;
  275.         u32 handle;
  276.  
  277.         size = roundup(size, PAGE_SIZE);
  278.         if (size == 0)
  279.                 return -EINVAL;
  280.  
  281.         /* Allocate the new object */
  282.         obj = i915_gem_alloc_object(dev, size);
  283.         if (obj == NULL)
  284.                 return -ENOMEM;
  285.  
  286.         ret = drm_gem_handle_create(file, &obj->base, &handle);
  287.         /* drop reference from allocate - handle holds it now */
  288.         drm_gem_object_unreference_unlocked(&obj->base);
  289.         if (ret)
  290.                 return ret;
  291.  
  292.         *handle_p = handle;
  293.         return 0;
  294. }
  295.  
  296. int
  297. i915_gem_dumb_create(struct drm_file *file,
  298.                      struct drm_device *dev,
  299.                      struct drm_mode_create_dumb *args)
  300. {
  301.         /* have to work out size/pitch and return them */
  302.         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
  303.         args->size = args->pitch * args->height;
  304.         return i915_gem_create(file, dev,
  305.                                args->size, &args->handle);
  306. }
  307.  
  308. /**
  309.  * Creates a new mm object and returns a handle to it.
  310.  */
  311. int
  312. i915_gem_create_ioctl(struct drm_device *dev, void *data,
  313.                       struct drm_file *file)
  314. {
  315.         struct drm_i915_gem_create *args = data;
  316.  
  317.         return i915_gem_create(file, dev,
  318.                                args->size, &args->handle);
  319. }
  320.  
  321.  
  322. #if 0
  323.  
  324. static inline int
  325. __copy_to_user_swizzled(char __user *cpu_vaddr,
  326.                         const char *gpu_vaddr, int gpu_offset,
  327.                 int length)
  328. {
  329.         int ret, cpu_offset = 0;
  330.  
  331.         while (length > 0) {
  332.                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
  333.                 int this_length = min(cacheline_end - gpu_offset, length);
  334.                 int swizzled_gpu_offset = gpu_offset ^ 64;
  335.  
  336.                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
  337.                                      gpu_vaddr + swizzled_gpu_offset,
  338.                                      this_length);
  339.                 if (ret)
  340.                         return ret + length;
  341.  
  342.                 cpu_offset += this_length;
  343.                 gpu_offset += this_length;
  344.                 length -= this_length;
  345.         }
  346.  
  347.         return 0;
  348. }
  349.  
  350. static inline int
  351. __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
  352.                           const char __user *cpu_vaddr,
  353.                           int length)
  354. {
  355.         int ret, cpu_offset = 0;
  356.  
  357.         while (length > 0) {
  358.                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
  359.                 int this_length = min(cacheline_end - gpu_offset, length);
  360.                 int swizzled_gpu_offset = gpu_offset ^ 64;
  361.  
  362.                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
  363.                                cpu_vaddr + cpu_offset,
  364.                                this_length);
  365.                 if (ret)
  366.                         return ret + length;
  367.  
  368.                 cpu_offset += this_length;
  369.                 gpu_offset += this_length;
  370.                 length -= this_length;
  371.         }
  372.  
  373.         return 0;
  374. }
  375.  
  376. /* Per-page copy function for the shmem pread fastpath.
  377.  * Flushes invalid cachelines before reading the target if
  378.  * needs_clflush is set. */
  379. static int
  380. shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
  381.                  char __user *user_data,
  382.                  bool page_do_bit17_swizzling, bool needs_clflush)
  383. {
  384.                 char *vaddr;
  385.                 int ret;
  386.  
  387.         if (unlikely(page_do_bit17_swizzling))
  388.                 return -EINVAL;
  389.  
  390.                 vaddr = kmap_atomic(page);
  391.         if (needs_clflush)
  392.                 drm_clflush_virt_range(vaddr + shmem_page_offset,
  393.                                        page_length);
  394.                 ret = __copy_to_user_inatomic(user_data,
  395.                                       vaddr + shmem_page_offset,
  396.                                               page_length);
  397.                 kunmap_atomic(vaddr);
  398.  
  399.         return ret ? -EFAULT : 0;
  400. }
  401.  
  402. static void
  403. shmem_clflush_swizzled_range(char *addr, unsigned long length,
  404.                              bool swizzled)
  405. {
  406.         if (unlikely(swizzled)) {
  407.                 unsigned long start = (unsigned long) addr;
  408.                 unsigned long end = (unsigned long) addr + length;
  409.  
  410.                 /* For swizzling simply ensure that we always flush both
  411.                  * channels. Lame, but simple and it works. Swizzled
  412.                  * pwrite/pread is far from a hotpath - current userspace
  413.                  * doesn't use it at all. */
  414.                 start = round_down(start, 128);
  415.                 end = round_up(end, 128);
  416.  
  417.                 drm_clflush_virt_range((void *)start, end - start);
  418.         } else {
  419.                 drm_clflush_virt_range(addr, length);
  420.         }
  421.  
  422. }
  423.  
  424. /* Only difference to the fast-path function is that this can handle bit17
  425.  * and uses non-atomic copy and kmap functions. */
  426. static int
  427. shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
  428.                  char __user *user_data,
  429.                  bool page_do_bit17_swizzling, bool needs_clflush)
  430. {
  431.         char *vaddr;
  432.         int ret;
  433.  
  434.         vaddr = kmap(page);
  435.         if (needs_clflush)
  436.                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
  437.                                              page_length,
  438.                                              page_do_bit17_swizzling);
  439.  
  440.         if (page_do_bit17_swizzling)
  441.                 ret = __copy_to_user_swizzled(user_data,
  442.                                               vaddr, shmem_page_offset,
  443.                                               page_length);
  444.         else
  445.                 ret = __copy_to_user(user_data,
  446.                                      vaddr + shmem_page_offset,
  447.                                      page_length);
  448.         kunmap(page);
  449.  
  450.         return ret ? - EFAULT : 0;
  451. }
  452.  
  453. static int
  454. i915_gem_shmem_pread(struct drm_device *dev,
  455.                           struct drm_i915_gem_object *obj,
  456.                           struct drm_i915_gem_pread *args,
  457.                           struct drm_file *file)
  458. {
  459.         char __user *user_data;
  460.         ssize_t remain;
  461.         loff_t offset;
  462.         int shmem_page_offset, page_length, ret = 0;
  463.         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
  464.         int prefaulted = 0;
  465.         int needs_clflush = 0;
  466.         struct sg_page_iter sg_iter;
  467.  
  468.         user_data = to_user_ptr(args->data_ptr);
  469.         remain = args->size;
  470.  
  471.         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
  472.  
  473.         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
  474.         if (ret)
  475.                 return ret;
  476.  
  477.         offset = args->offset;
  478.  
  479.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
  480.                          offset >> PAGE_SHIFT) {
  481.                 struct page *page = sg_page_iter_page(&sg_iter);
  482.  
  483.                 if (remain <= 0)
  484.                         break;
  485.  
  486.                 /* Operation in this page
  487.                  *
  488.                  * shmem_page_offset = offset within page in shmem file
  489.                  * page_length = bytes to copy for this page
  490.                  */
  491.                 shmem_page_offset = offset_in_page(offset);
  492.                 page_length = remain;
  493.                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
  494.                         page_length = PAGE_SIZE - shmem_page_offset;
  495.  
  496.                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
  497.                         (page_to_phys(page) & (1 << 17)) != 0;
  498.  
  499.                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
  500.                                        user_data, page_do_bit17_swizzling,
  501.                                        needs_clflush);
  502.                 if (ret == 0)
  503.                         goto next_page;
  504.  
  505.                 mutex_unlock(&dev->struct_mutex);
  506.  
  507.                 if (likely(!i915.prefault_disable) && !prefaulted) {
  508.                         ret = fault_in_multipages_writeable(user_data, remain);
  509.                         /* Userspace is tricking us, but we've already clobbered
  510.                          * its pages with the prefault and promised to write the
  511.                          * data up to the first fault. Hence ignore any errors
  512.                          * and just continue. */
  513.                         (void)ret;
  514.                         prefaulted = 1;
  515.                 }
  516.  
  517.                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
  518.                                        user_data, page_do_bit17_swizzling,
  519.                                        needs_clflush);
  520.  
  521.                 mutex_lock(&dev->struct_mutex);
  522.  
  523.                 if (ret)
  524.                         goto out;
  525.  
  526. next_page:
  527.                 remain -= page_length;
  528.                 user_data += page_length;
  529.                 offset += page_length;
  530.         }
  531.  
  532. out:
  533.         i915_gem_object_unpin_pages(obj);
  534.  
  535.         return ret;
  536. }
  537.  
  538. /**
  539.  * Reads data from the object referenced by handle.
  540.  *
  541.  * On error, the contents of *data are undefined.
  542.  */
  543. int
  544. i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  545.                      struct drm_file *file)
  546. {
  547.         struct drm_i915_gem_pread *args = data;
  548.         struct drm_i915_gem_object *obj;
  549.         int ret = 0;
  550.  
  551.         if (args->size == 0)
  552.                 return 0;
  553.  
  554.         if (!access_ok(VERIFY_WRITE,
  555.                        to_user_ptr(args->data_ptr),
  556.                        args->size))
  557.                 return -EFAULT;
  558.  
  559.         ret = i915_mutex_lock_interruptible(dev);
  560.         if (ret)
  561.                 return ret;
  562.  
  563.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  564.         if (&obj->base == NULL) {
  565.                 ret = -ENOENT;
  566.                 goto unlock;
  567.         }
  568.  
  569.         /* Bounds check source.  */
  570.         if (args->offset > obj->base.size ||
  571.             args->size > obj->base.size - args->offset) {
  572.                 ret = -EINVAL;
  573.                 goto out;
  574.         }
  575.  
  576.         /* prime objects have no backing filp to GEM pread/pwrite
  577.          * pages from.
  578.          */
  579.         if (!obj->base.filp) {
  580.                 ret = -EINVAL;
  581.                 goto out;
  582.         }
  583.  
  584.         trace_i915_gem_object_pread(obj, args->offset, args->size);
  585.  
  586.         ret = i915_gem_shmem_pread(dev, obj, args, file);
  587.  
  588. out:
  589.         drm_gem_object_unreference(&obj->base);
  590. unlock:
  591.         mutex_unlock(&dev->struct_mutex);
  592.         return ret;
  593. }
  594.  
  595. /* This is the fast write path which cannot handle
  596.  * page faults in the source data
  597.  */
  598.  
  599. static inline int
  600. fast_user_write(struct io_mapping *mapping,
  601.                 loff_t page_base, int page_offset,
  602.                 char __user *user_data,
  603.                 int length)
  604. {
  605.         void __iomem *vaddr_atomic;
  606.         void *vaddr;
  607.         unsigned long unwritten;
  608.  
  609.         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
  610.         /* We can use the cpu mem copy function because this is X86. */
  611.         vaddr = (void __force*)vaddr_atomic + page_offset;
  612.         unwritten = __copy_from_user_inatomic_nocache(vaddr,
  613.                                                       user_data, length);
  614.         io_mapping_unmap_atomic(vaddr_atomic);
  615.         return unwritten;
  616. }
  617. #endif
  618.  
  619. #define offset_in_page(p)       ((unsigned long)(p) & ~PAGE_MASK)
  620. /**
  621.  * This is the fast pwrite path, where we copy the data directly from the
  622.  * user into the GTT, uncached.
  623.  */
  624. static int
  625. i915_gem_gtt_pwrite_fast(struct drm_device *dev,
  626.                          struct drm_i915_gem_object *obj,
  627.                          struct drm_i915_gem_pwrite *args,
  628.                          struct drm_file *file)
  629. {
  630.         struct drm_i915_private *dev_priv = dev->dev_private;
  631.         ssize_t remain;
  632.         loff_t offset, page_base;
  633.         char __user *user_data;
  634.         int page_offset, page_length, ret;
  635.  
  636.         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
  637.         if (ret)
  638.                 goto out;
  639.  
  640.         ret = i915_gem_object_set_to_gtt_domain(obj, true);
  641.         if (ret)
  642.                 goto out_unpin;
  643.  
  644.         ret = i915_gem_object_put_fence(obj);
  645.         if (ret)
  646.                 goto out_unpin;
  647.  
  648.         user_data = to_user_ptr(args->data_ptr);
  649.         remain = args->size;
  650.  
  651.         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
  652.  
  653.         while (remain > 0) {
  654.                 /* Operation in this page
  655.                  *
  656.                  * page_base = page offset within aperture
  657.                  * page_offset = offset within page
  658.                  * page_length = bytes to copy for this page
  659.                  */
  660.                 page_base = offset & PAGE_MASK;
  661.                 page_offset = offset_in_page(offset);
  662.                 page_length = remain;
  663.                 if ((page_offset + remain) > PAGE_SIZE)
  664.                         page_length = PAGE_SIZE - page_offset;
  665.  
  666.         MapPage(dev_priv->gtt.mappable, dev_priv->gtt.mappable_base+page_base, PG_SW);
  667.  
  668.         memcpy((char*)dev_priv->gtt.mappable+page_offset, user_data, page_length);
  669.  
  670.                 remain -= page_length;
  671.                 user_data += page_length;
  672.                 offset += page_length;
  673.         }
  674.  
  675. out_unpin:
  676.         i915_gem_object_ggtt_unpin(obj);
  677. out:
  678.     return ret;
  679. }
  680.  
  681. /* Per-page copy function for the shmem pwrite fastpath.
  682.  * Flushes invalid cachelines before writing to the target if
  683.  * needs_clflush_before is set and flushes out any written cachelines after
  684.  * writing if needs_clflush is set. */
  685. static int
  686. shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
  687.                   char __user *user_data,
  688.                   bool page_do_bit17_swizzling,
  689.                   bool needs_clflush_before,
  690.                   bool needs_clflush_after)
  691. {
  692.         char *vaddr;
  693.         int ret = 0;
  694.  
  695.         if (unlikely(page_do_bit17_swizzling))
  696.                 return -EINVAL;
  697.  
  698.     vaddr = (char *)MapIoMem((addr_t)page, 4096, PG_SW);
  699.         if (needs_clflush_before)
  700.                 drm_clflush_virt_range(vaddr + shmem_page_offset,
  701.                                        page_length);
  702.         memcpy(vaddr + shmem_page_offset,
  703.                                                 user_data,
  704.                                                 page_length);
  705.         if (needs_clflush_after)
  706.                 drm_clflush_virt_range(vaddr + shmem_page_offset,
  707.                                        page_length);
  708.         FreeKernelSpace(vaddr);
  709.  
  710.         return ret ? -EFAULT : 0;
  711. }
  712. #if 0
  713.  
  714. /* Only difference to the fast-path function is that this can handle bit17
  715.  * and uses non-atomic copy and kmap functions. */
  716. static int
  717. shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
  718.                   char __user *user_data,
  719.                   bool page_do_bit17_swizzling,
  720.                   bool needs_clflush_before,
  721.                   bool needs_clflush_after)
  722. {
  723.         char *vaddr;
  724.         int ret;
  725.  
  726.         vaddr = kmap(page);
  727.         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
  728.                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
  729.                                              page_length,
  730.                                              page_do_bit17_swizzling);
  731.         if (page_do_bit17_swizzling)
  732.                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
  733.                                                 user_data,
  734.                                                 page_length);
  735.         else
  736.                 ret = __copy_from_user(vaddr + shmem_page_offset,
  737.                                        user_data,
  738.                                        page_length);
  739.         if (needs_clflush_after)
  740.                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
  741.                                              page_length,
  742.                                              page_do_bit17_swizzling);
  743.         kunmap(page);
  744.  
  745.         return ret ? -EFAULT : 0;
  746. }
  747. #endif
  748.  
  749.  
  750. static int
  751. i915_gem_shmem_pwrite(struct drm_device *dev,
  752.                       struct drm_i915_gem_object *obj,
  753.                       struct drm_i915_gem_pwrite *args,
  754.                       struct drm_file *file)
  755. {
  756.         ssize_t remain;
  757.         loff_t offset;
  758.         char __user *user_data;
  759.         int shmem_page_offset, page_length, ret = 0;
  760.         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
  761.         int hit_slowpath = 0;
  762.         int needs_clflush_after = 0;
  763.         int needs_clflush_before = 0;
  764.         struct sg_page_iter sg_iter;
  765.  
  766.         user_data = to_user_ptr(args->data_ptr);
  767.         remain = args->size;
  768.  
  769.         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
  770.  
  771.         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
  772.                 /* If we're not in the cpu write domain, set ourself into the gtt
  773.                  * write domain and manually flush cachelines (if required). This
  774.                  * optimizes for the case when the gpu will use the data
  775.                  * right away and we therefore have to clflush anyway. */
  776.                 needs_clflush_after = cpu_write_needs_clflush(obj);
  777.                 ret = i915_gem_object_wait_rendering(obj, false);
  778.                         if (ret)
  779.                                 return ret;
  780.  
  781.                 i915_gem_object_retire(obj);
  782.                 }
  783.         /* Same trick applies to invalidate partially written cachelines read
  784.          * before writing. */
  785.         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
  786.                 needs_clflush_before =
  787.                         !cpu_cache_is_coherent(dev, obj->cache_level);
  788.  
  789.         ret = i915_gem_object_get_pages(obj);
  790.         if (ret)
  791.                 return ret;
  792.  
  793.         i915_gem_object_pin_pages(obj);
  794.  
  795.         offset = args->offset;
  796.         obj->dirty = 1;
  797.  
  798.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
  799.                          offset >> PAGE_SHIFT) {
  800.                 struct page *page = sg_page_iter_page(&sg_iter);
  801.                 int partial_cacheline_write;
  802.  
  803.                 if (remain <= 0)
  804.                         break;
  805.  
  806.                 /* Operation in this page
  807.                  *
  808.                  * shmem_page_offset = offset within page in shmem file
  809.                  * page_length = bytes to copy for this page
  810.                  */
  811.                 shmem_page_offset = offset_in_page(offset);
  812.  
  813.                 page_length = remain;
  814.                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
  815.                         page_length = PAGE_SIZE - shmem_page_offset;
  816.  
  817.                 /* If we don't overwrite a cacheline completely we need to be
  818.                  * careful to have up-to-date data by first clflushing. Don't
  819.                  * overcomplicate things and flush the entire patch. */
  820.                 partial_cacheline_write = needs_clflush_before &&
  821.                         ((shmem_page_offset | page_length)
  822.                                 & (x86_clflush_size - 1));
  823.  
  824.                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
  825.                         (page_to_phys(page) & (1 << 17)) != 0;
  826.  
  827.                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
  828.                                         user_data, page_do_bit17_swizzling,
  829.                                         partial_cacheline_write,
  830.                                         needs_clflush_after);
  831.                 if (ret == 0)
  832.                         goto next_page;
  833.  
  834.                 hit_slowpath = 1;
  835.                 mutex_unlock(&dev->struct_mutex);
  836.                 dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__);
  837.  
  838. //              ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
  839. //                                      user_data, page_do_bit17_swizzling,
  840. //                                      partial_cacheline_write,
  841. //                                      needs_clflush_after);
  842.  
  843.                 mutex_lock(&dev->struct_mutex);
  844.  
  845. next_page:
  846.  
  847.                 if (ret)
  848.                         goto out;
  849.  
  850.                 remain -= page_length;
  851.                 user_data += page_length;
  852.                 offset += page_length;
  853.         }
  854.  
  855. out:
  856.         i915_gem_object_unpin_pages(obj);
  857.  
  858.         if (hit_slowpath) {
  859.                 /*
  860.                  * Fixup: Flush cpu caches in case we didn't flush the dirty
  861.                  * cachelines in-line while writing and the object moved
  862.                  * out of the cpu write domain while we've dropped the lock.
  863.                  */
  864.                 if (!needs_clflush_after &&
  865.                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
  866.                         if (i915_gem_clflush_object(obj, obj->pin_display))
  867.                         i915_gem_chipset_flush(dev);
  868.                 }
  869.         }
  870.  
  871.         if (needs_clflush_after)
  872.                 i915_gem_chipset_flush(dev);
  873.  
  874.         return ret;
  875. }
  876.  
  877. /**
  878.  * Writes data to the object referenced by handle.
  879.  *
  880.  * On error, the contents of the buffer that were to be modified are undefined.
  881.  */
  882. int
  883. i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  884.                       struct drm_file *file)
  885. {
  886.         struct drm_i915_gem_pwrite *args = data;
  887.         struct drm_i915_gem_object *obj;
  888.         int ret;
  889.  
  890.         if (args->size == 0)
  891.                 return 0;
  892.  
  893.  
  894.         ret = i915_mutex_lock_interruptible(dev);
  895.         if (ret)
  896.                 return ret;
  897.  
  898.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  899.         if (&obj->base == NULL) {
  900.                 ret = -ENOENT;
  901.                 goto unlock;
  902.         }
  903.  
  904.         /* Bounds check destination. */
  905.         if (args->offset > obj->base.size ||
  906.             args->size > obj->base.size - args->offset) {
  907.                 ret = -EINVAL;
  908.                 goto out;
  909.         }
  910.  
  911.         /* prime objects have no backing filp to GEM pread/pwrite
  912.          * pages from.
  913.          */
  914.         if (!obj->base.filp) {
  915.                 ret = -EINVAL;
  916.                 goto out;
  917.         }
  918.  
  919.         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
  920.  
  921.         ret = -EFAULT;
  922.         /* We can only do the GTT pwrite on untiled buffers, as otherwise
  923.          * it would end up going through the fenced access, and we'll get
  924.          * different detiling behavior between reading and writing.
  925.          * pread/pwrite currently are reading and writing from the CPU
  926.          * perspective, requiring manual detiling by the client.
  927.          */
  928. //   if (obj->phys_obj) {
  929. //       ret = i915_gem_phys_pwrite(dev, obj, args, file);
  930. //       goto out;
  931. //   }
  932.  
  933.         if (obj->tiling_mode == I915_TILING_NONE &&
  934.             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
  935.             cpu_write_needs_clflush(obj)) {
  936.                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
  937.                 /* Note that the gtt paths might fail with non-page-backed user
  938.                  * pointers (e.g. gtt mappings when moving data between
  939.                  * textures). Fallback to the shmem path in that case. */
  940.         }
  941.  
  942.         if (ret == -EFAULT || ret == -ENOSPC)
  943.        ret = i915_gem_shmem_pwrite(dev, obj, args, file);
  944.  
  945. out:
  946.         drm_gem_object_unreference(&obj->base);
  947. unlock:
  948.         mutex_unlock(&dev->struct_mutex);
  949.         return ret;
  950. }
  951.  
  952. int
  953. i915_gem_check_wedge(struct i915_gpu_error *error,
  954.                      bool interruptible)
  955. {
  956.         if (i915_reset_in_progress(error)) {
  957.                 /* Non-interruptible callers can't handle -EAGAIN, hence return
  958.                  * -EIO unconditionally for these. */
  959.                 if (!interruptible)
  960.                         return -EIO;
  961.  
  962.                 /* Recovery complete, but the reset failed ... */
  963.                 if (i915_terminally_wedged(error))
  964.                         return -EIO;
  965.  
  966.                 return -EAGAIN;
  967.         }
  968.  
  969.         return 0;
  970. }
  971.  
  972. /*
  973.  * Compare seqno against outstanding lazy request. Emit a request if they are
  974.  * equal.
  975.  */
  976. int
  977. i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
  978. {
  979.         int ret;
  980.  
  981.         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
  982.  
  983.         ret = 0;
  984.         if (seqno == ring->outstanding_lazy_seqno)
  985.                 ret = i915_add_request(ring, NULL);
  986.  
  987.         return ret;
  988. }
  989.  
  990. static void fake_irq(unsigned long data)
  991. {
  992. //      wake_up_process((struct task_struct *)data);
  993. }
  994.  
  995. static bool missed_irq(struct drm_i915_private *dev_priv,
  996.                        struct intel_engine_cs *ring)
  997. {
  998.         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
  999. }
  1000.  
  1001. static bool can_wait_boost(struct drm_i915_file_private *file_priv)
  1002. {
  1003.         if (file_priv == NULL)
  1004.                 return true;
  1005.  
  1006.         return !atomic_xchg(&file_priv->rps_wait_boost, true);
  1007. }
  1008.  
  1009. /**
  1010.  * __wait_seqno - wait until execution of seqno has finished
  1011.  * @ring: the ring expected to report seqno
  1012.  * @seqno: duh!
  1013.  * @reset_counter: reset sequence associated with the given seqno
  1014.  * @interruptible: do an interruptible wait (normally yes)
  1015.  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
  1016.  *
  1017.  * Note: It is of utmost importance that the passed in seqno and reset_counter
  1018.  * values have been read by the caller in an smp safe manner. Where read-side
  1019.  * locks are involved, it is sufficient to read the reset_counter before
  1020.  * unlocking the lock that protects the seqno. For lockless tricks, the
  1021.  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
  1022.  * inserted.
  1023.  *
  1024.  * Returns 0 if the seqno was found within the alloted time. Else returns the
  1025.  * errno with remaining time filled in timeout argument.
  1026.  */
  1027. static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
  1028.                         unsigned reset_counter,
  1029.                         bool interruptible,
  1030.                         s64 *timeout,
  1031.                         struct drm_i915_file_private *file_priv)
  1032. {
  1033.         struct drm_device *dev = ring->dev;
  1034.         struct drm_i915_private *dev_priv = dev->dev_private;
  1035.         const bool irq_test_in_progress =
  1036.                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
  1037.         unsigned long timeout_expire;
  1038.         s64 before, now;
  1039.  
  1040.     wait_queue_t __wait;
  1041.         int ret;
  1042.  
  1043.         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
  1044.  
  1045.         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
  1046.                 return 0;
  1047.  
  1048.         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
  1049.  
  1050.         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
  1051.                 gen6_rps_boost(dev_priv);
  1052.                 if (file_priv)
  1053.                         mod_delayed_work(dev_priv->wq,
  1054.                                          &file_priv->mm.idle_work,
  1055.                                          msecs_to_jiffies(100));
  1056.         }
  1057.  
  1058.         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
  1059.                 return -ENODEV;
  1060.  
  1061.     INIT_LIST_HEAD(&__wait.task_list);
  1062.     __wait.evnt = CreateEvent(NULL, MANUAL_DESTROY);
  1063.  
  1064.         /* Record current time in case interrupted by signal, or wedged */
  1065.         trace_i915_gem_request_wait_begin(ring, seqno);
  1066.  
  1067.         for (;;) {
  1068.         unsigned long flags;
  1069.  
  1070.                 /* We need to check whether any gpu reset happened in between
  1071.                  * the caller grabbing the seqno and now ... */
  1072.                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
  1073.                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
  1074.                          * is truely gone. */
  1075.                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
  1076.                         if (ret == 0)
  1077.                                 ret = -EAGAIN;
  1078.                         break;
  1079.                 }
  1080.  
  1081.                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
  1082.                         ret = 0;
  1083.                         break;
  1084.                 }
  1085.  
  1086.         if (timeout && time_after_eq(jiffies, timeout_expire)) {
  1087.                         ret = -ETIME;
  1088.                         break;
  1089.                 }
  1090.  
  1091.         spin_lock_irqsave(&ring->irq_queue.lock, flags);
  1092.         if (list_empty(&__wait.task_list))
  1093.             __add_wait_queue(&ring->irq_queue, &__wait);
  1094.         spin_unlock_irqrestore(&ring->irq_queue.lock, flags);
  1095.  
  1096.         WaitEventTimeout(__wait.evnt, 1);
  1097.  
  1098.         if (!list_empty(&__wait.task_list)) {
  1099.             spin_lock_irqsave(&ring->irq_queue.lock, flags);
  1100.             list_del_init(&__wait.task_list);
  1101.             spin_unlock_irqrestore(&ring->irq_queue.lock, flags);
  1102.         }
  1103.     };
  1104.     trace_i915_gem_request_wait_end(ring, seqno);
  1105.  
  1106.     DestroyEvent(__wait.evnt);
  1107.  
  1108.         if (!irq_test_in_progress)
  1109.         ring->irq_put(ring);
  1110.  
  1111. //      finish_wait(&ring->irq_queue, &wait);
  1112.         return ret;
  1113. }
  1114.  
  1115. /**
  1116.  * Waits for a sequence number to be signaled, and cleans up the
  1117.  * request and object lists appropriately for that event.
  1118.  */
  1119. int
  1120. i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
  1121. {
  1122.         struct drm_device *dev = ring->dev;
  1123.         struct drm_i915_private *dev_priv = dev->dev_private;
  1124.         bool interruptible = dev_priv->mm.interruptible;
  1125.         int ret;
  1126.  
  1127.         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  1128.         BUG_ON(seqno == 0);
  1129.  
  1130.         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
  1131.         if (ret)
  1132.                 return ret;
  1133.  
  1134.         ret = i915_gem_check_olr(ring, seqno);
  1135.         if (ret)
  1136.                 return ret;
  1137.  
  1138.         return __wait_seqno(ring, seqno,
  1139.                             atomic_read(&dev_priv->gpu_error.reset_counter),
  1140.                             interruptible, NULL, NULL);
  1141. }
  1142.  
  1143. static int
  1144. i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
  1145.                                      struct intel_engine_cs *ring)
  1146. {
  1147.         if (!obj->active)
  1148.                 return 0;
  1149.  
  1150.         /* Manually manage the write flush as we may have not yet
  1151.          * retired the buffer.
  1152.          *
  1153.          * Note that the last_write_seqno is always the earlier of
  1154.          * the two (read/write) seqno, so if we haved successfully waited,
  1155.          * we know we have passed the last write.
  1156.          */
  1157.         obj->last_write_seqno = 0;
  1158.  
  1159.         return 0;
  1160. }
  1161.  
  1162. /**
  1163.  * Ensures that all rendering to the object has completed and the object is
  1164.  * safe to unbind from the GTT or access from the CPU.
  1165.  */
  1166. static __must_check int
  1167. i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  1168.                                bool readonly)
  1169. {
  1170.         struct intel_engine_cs *ring = obj->ring;
  1171.         u32 seqno;
  1172.         int ret;
  1173.  
  1174.         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
  1175.         if (seqno == 0)
  1176.                 return 0;
  1177.  
  1178.         ret = i915_wait_seqno(ring, seqno);
  1179.     if (ret)
  1180.         return ret;
  1181.  
  1182.         return i915_gem_object_wait_rendering__tail(obj, ring);
  1183. }
  1184.  
  1185. /* A nonblocking variant of the above wait. This is a highly dangerous routine
  1186.  * as the object state may change during this call.
  1187.  */
  1188. static __must_check int
  1189. i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
  1190.                                             struct drm_i915_file_private *file_priv,
  1191.                                             bool readonly)
  1192. {
  1193.         struct drm_device *dev = obj->base.dev;
  1194.         struct drm_i915_private *dev_priv = dev->dev_private;
  1195.         struct intel_engine_cs *ring = obj->ring;
  1196.         unsigned reset_counter;
  1197.         u32 seqno;
  1198.         int ret;
  1199.  
  1200.         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  1201.         BUG_ON(!dev_priv->mm.interruptible);
  1202.  
  1203.         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
  1204.         if (seqno == 0)
  1205.                 return 0;
  1206.  
  1207.         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
  1208.         if (ret)
  1209.                 return ret;
  1210.  
  1211.         ret = i915_gem_check_olr(ring, seqno);
  1212.         if (ret)
  1213.                 return ret;
  1214.  
  1215.         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  1216.         mutex_unlock(&dev->struct_mutex);
  1217.         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
  1218.         mutex_lock(&dev->struct_mutex);
  1219.         if (ret)
  1220.                 return ret;
  1221.  
  1222.         return i915_gem_object_wait_rendering__tail(obj, ring);
  1223. }
  1224.  
  1225. /**
  1226.  * Called when user space prepares to use an object with the CPU, either
  1227.  * through the mmap ioctl's mapping or a GTT mapping.
  1228.  */
  1229. int
  1230. i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1231.                           struct drm_file *file)
  1232. {
  1233.         struct drm_i915_gem_set_domain *args = data;
  1234.         struct drm_i915_gem_object *obj;
  1235.         uint32_t read_domains = args->read_domains;
  1236.         uint32_t write_domain = args->write_domain;
  1237.         int ret;
  1238.  
  1239.         /* Only handle setting domains to types used by the CPU. */
  1240.         if (write_domain & I915_GEM_GPU_DOMAINS)
  1241.                 return -EINVAL;
  1242.  
  1243.         if (read_domains & I915_GEM_GPU_DOMAINS)
  1244.                 return -EINVAL;
  1245.  
  1246.         /* Having something in the write domain implies it's in the read
  1247.          * domain, and only that read domain.  Enforce that in the request.
  1248.          */
  1249.         if (write_domain != 0 && read_domains != write_domain)
  1250.                 return -EINVAL;
  1251.  
  1252.         ret = i915_mutex_lock_interruptible(dev);
  1253.         if (ret)
  1254.                 return ret;
  1255.  
  1256.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  1257.         if (&obj->base == NULL) {
  1258.                 ret = -ENOENT;
  1259.                 goto unlock;
  1260.         }
  1261.  
  1262.         /* Try to flush the object off the GPU without holding the lock.
  1263.          * We will repeat the flush holding the lock in the normal manner
  1264.          * to catch cases where we are gazumped.
  1265.          */
  1266.         ret = i915_gem_object_wait_rendering__nonblocking(obj,
  1267.                                                           file->driver_priv,
  1268.                                                           !write_domain);
  1269.         if (ret)
  1270.                 goto unref;
  1271.  
  1272.         if (read_domains & I915_GEM_DOMAIN_GTT) {
  1273.                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
  1274.  
  1275.                 /* Silently promote "you're not bound, there was nothing to do"
  1276.                  * to success, since the client was just asking us to
  1277.                  * make sure everything was done.
  1278.                  */
  1279.                 if (ret == -EINVAL)
  1280.                         ret = 0;
  1281.         } else {
  1282.                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
  1283.         }
  1284.  
  1285. unref:
  1286.         drm_gem_object_unreference(&obj->base);
  1287. unlock:
  1288.         mutex_unlock(&dev->struct_mutex);
  1289.         return ret;
  1290. }
  1291.  
  1292. /**
  1293.  * Called when user space has done writes to this buffer
  1294.  */
  1295. int
  1296. i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1297.                          struct drm_file *file)
  1298. {
  1299.         struct drm_i915_gem_sw_finish *args = data;
  1300.         struct drm_i915_gem_object *obj;
  1301.         int ret = 0;
  1302.  
  1303.         ret = i915_mutex_lock_interruptible(dev);
  1304.         if (ret)
  1305.                 return ret;
  1306.  
  1307.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  1308.         if (&obj->base == NULL) {
  1309.                 ret = -ENOENT;
  1310.                 goto unlock;
  1311.         }
  1312.  
  1313.         /* Pinned buffers may be scanout, so flush the cache */
  1314.         if (obj->pin_display)
  1315.                 i915_gem_object_flush_cpu_write_domain(obj, true);
  1316.  
  1317.         drm_gem_object_unreference(&obj->base);
  1318. unlock:
  1319.         mutex_unlock(&dev->struct_mutex);
  1320.         return ret;
  1321. }
  1322.  
  1323. /**
  1324.  * Maps the contents of an object, returning the address it is mapped
  1325.  * into.
  1326.  *
  1327.  * While the mapping holds a reference on the contents of the object, it doesn't
  1328.  * imply a ref on the object itself.
  1329.  */
  1330. int
  1331. i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1332.                     struct drm_file *file)
  1333. {
  1334.         struct drm_i915_gem_mmap *args = data;
  1335.         struct drm_gem_object *obj;
  1336.         unsigned long addr;
  1337.  
  1338.         obj = drm_gem_object_lookup(dev, file, args->handle);
  1339.         if (obj == NULL)
  1340.                 return -ENOENT;
  1341.  
  1342.         /* prime objects have no backing filp to GEM mmap
  1343.          * pages from.
  1344.          */
  1345.         if (!obj->filp) {
  1346.                 drm_gem_object_unreference_unlocked(obj);
  1347.                 return -EINVAL;
  1348.         }
  1349.  
  1350.     addr = vm_mmap(obj->filp, 0, args->size,
  1351.               PROT_READ | PROT_WRITE, MAP_SHARED,
  1352.               args->offset);
  1353.         drm_gem_object_unreference_unlocked(obj);
  1354.     if (IS_ERR((void *)addr))
  1355.         return addr;
  1356.  
  1357.         args->addr_ptr = (uint64_t) addr;
  1358.  
  1359.     return 0;
  1360. }
  1361.  
  1362.  
  1363.  
  1364.  
  1365.  
  1366.  
  1367.  
  1368.  
  1369.  
  1370.  
  1371.  
  1372.  
  1373.  
  1374. /**
  1375.  * i915_gem_release_mmap - remove physical page mappings
  1376.  * @obj: obj in question
  1377.  *
  1378.  * Preserve the reservation of the mmapping with the DRM core code, but
  1379.  * relinquish ownership of the pages back to the system.
  1380.  *
  1381.  * It is vital that we remove the page mapping if we have mapped a tiled
  1382.  * object through the GTT and then lose the fence register due to
  1383.  * resource pressure. Similarly if the object has been moved out of the
  1384.  * aperture, than pages mapped into userspace must be revoked. Removing the
  1385.  * mapping will then trigger a page fault on the next user access, allowing
  1386.  * fixup by i915_gem_fault().
  1387.  */
  1388. void
  1389. i915_gem_release_mmap(struct drm_i915_gem_object *obj)
  1390. {
  1391.         if (!obj->fault_mappable)
  1392.                 return;
  1393.  
  1394. //      drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
  1395.         obj->fault_mappable = false;
  1396. }
  1397.  
  1398. uint32_t
  1399. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
  1400. {
  1401.         uint32_t gtt_size;
  1402.  
  1403.         if (INTEL_INFO(dev)->gen >= 4 ||
  1404.             tiling_mode == I915_TILING_NONE)
  1405.                 return size;
  1406.  
  1407.         /* Previous chips need a power-of-two fence region when tiling */
  1408.         if (INTEL_INFO(dev)->gen == 3)
  1409.                 gtt_size = 1024*1024;
  1410.         else
  1411.                 gtt_size = 512*1024;
  1412.  
  1413.         while (gtt_size < size)
  1414.                 gtt_size <<= 1;
  1415.  
  1416.         return gtt_size;
  1417. }
  1418.  
  1419. /**
  1420.  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
  1421.  * @obj: object to check
  1422.  *
  1423.  * Return the required GTT alignment for an object, taking into account
  1424.  * potential fence register mapping.
  1425.  */
  1426. uint32_t
  1427. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  1428.                            int tiling_mode, bool fenced)
  1429. {
  1430.         /*
  1431.          * Minimum alignment is 4k (GTT page size), but might be greater
  1432.          * if a fence register is needed for the object.
  1433.          */
  1434.         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
  1435.             tiling_mode == I915_TILING_NONE)
  1436.                 return 4096;
  1437.  
  1438.         /*
  1439.          * Previous chips need to be aligned to the size of the smallest
  1440.          * fence register that can contain the object.
  1441.          */
  1442.         return i915_gem_get_gtt_size(dev, size, tiling_mode);
  1443. }
  1444.  
  1445.  
  1446.  
  1447. int
  1448. i915_gem_mmap_gtt(struct drm_file *file,
  1449.           struct drm_device *dev,
  1450.           uint32_t handle,
  1451.           uint64_t *offset)
  1452. {
  1453.     struct drm_i915_private *dev_priv = dev->dev_private;
  1454.     struct drm_i915_gem_object *obj;
  1455.     unsigned long pfn;
  1456.     char *mem, *ptr;
  1457.     int ret;
  1458.  
  1459.     ret = i915_mutex_lock_interruptible(dev);
  1460.     if (ret)
  1461.         return ret;
  1462.  
  1463.     obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  1464.     if (&obj->base == NULL) {
  1465.         ret = -ENOENT;
  1466.         goto unlock;
  1467.     }
  1468.  
  1469.     if (obj->base.size > dev_priv->gtt.mappable_end) {
  1470.         ret = -E2BIG;
  1471.         goto out;
  1472.     }
  1473.  
  1474.     if (obj->madv != I915_MADV_WILLNEED) {
  1475.                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
  1476.                 ret = -EFAULT;
  1477.         goto out;
  1478.     }
  1479.     /* Now bind it into the GTT if needed */
  1480.         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
  1481.     if (ret)
  1482.         goto out;
  1483.  
  1484.     ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  1485.     if (ret)
  1486.         goto unpin;
  1487.  
  1488.     ret = i915_gem_object_get_fence(obj);
  1489.     if (ret)
  1490.         goto unpin;
  1491.  
  1492.     obj->fault_mappable = true;
  1493.  
  1494.     pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
  1495.  
  1496.     /* Finally, remap it using the new GTT offset */
  1497.  
  1498.     mem = UserAlloc(obj->base.size);
  1499.     if(unlikely(mem == NULL))
  1500.     {
  1501.         ret = -ENOMEM;
  1502.         goto unpin;
  1503.     }
  1504.  
  1505.     for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096)
  1506.         MapPage(ptr, pfn, PG_SHARED|PG_UW);
  1507.  
  1508. unpin:
  1509.     i915_gem_object_unpin_pages(obj);
  1510.  
  1511.  
  1512.     *offset = mem;
  1513.  
  1514. out:
  1515.     drm_gem_object_unreference(&obj->base);
  1516. unlock:
  1517.     mutex_unlock(&dev->struct_mutex);
  1518.     return ret;
  1519. }
  1520.  
  1521. /**
  1522.  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
  1523.  * @dev: DRM device
  1524.  * @data: GTT mapping ioctl data
  1525.  * @file: GEM object info
  1526.  *
  1527.  * Simply returns the fake offset to userspace so it can mmap it.
  1528.  * The mmap call will end up in drm_gem_mmap(), which will set things
  1529.  * up so we can get faults in the handler above.
  1530.  *
  1531.  * The fault handler will take care of binding the object into the GTT
  1532.  * (since it may have been evicted to make room for something), allocating
  1533.  * a fence register, and mapping the appropriate aperture address into
  1534.  * userspace.
  1535.  */
  1536. int
  1537. i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1538.             struct drm_file *file)
  1539. {
  1540.     struct drm_i915_gem_mmap_gtt *args = data;
  1541.  
  1542.     return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
  1543. }
  1544.  
  1545. static inline int
  1546. i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
  1547. {
  1548.         return obj->madv == I915_MADV_DONTNEED;
  1549. }
  1550.  
  1551. /* Immediately discard the backing storage */
  1552. static void
  1553. i915_gem_object_truncate(struct drm_i915_gem_object *obj)
  1554. {
  1555. //      i915_gem_object_free_mmap_offset(obj);
  1556.  
  1557.         if (obj->base.filp == NULL)
  1558.                 return;
  1559.  
  1560.         /* Our goal here is to return as much of the memory as
  1561.          * is possible back to the system as we are called from OOM.
  1562.          * To do this we must instruct the shmfs to drop all of its
  1563.          * backing pages, *now*.
  1564.          */
  1565. //      shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
  1566.         obj->madv = __I915_MADV_PURGED;
  1567. }
  1568.  
  1569. /* Try to discard unwanted pages */
  1570. static void
  1571. i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
  1572. {
  1573.         struct address_space *mapping;
  1574.  
  1575.         switch (obj->madv) {
  1576.         case I915_MADV_DONTNEED:
  1577.                 i915_gem_object_truncate(obj);
  1578.         case __I915_MADV_PURGED:
  1579.                 return;
  1580.         }
  1581.  
  1582.         if (obj->base.filp == NULL)
  1583.                 return;
  1584.  
  1585. }
  1586.  
  1587. static void
  1588. i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
  1589. {
  1590.         struct sg_page_iter sg_iter;
  1591.         int ret;
  1592.  
  1593.         BUG_ON(obj->madv == __I915_MADV_PURGED);
  1594.  
  1595.         ret = i915_gem_object_set_to_cpu_domain(obj, true);
  1596.         if (ret) {
  1597.                 /* In the event of a disaster, abandon all caches and
  1598.                  * hope for the best.
  1599.                  */
  1600.                 WARN_ON(ret != -EIO);
  1601.                 i915_gem_clflush_object(obj, true);
  1602.                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
  1603.         }
  1604.  
  1605.         if (obj->madv == I915_MADV_DONTNEED)
  1606.                 obj->dirty = 0;
  1607.  
  1608.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
  1609.                 struct page *page = sg_page_iter_page(&sg_iter);
  1610.  
  1611.         page_cache_release(page);
  1612.         }
  1613.     obj->dirty = 0;
  1614.  
  1615.         sg_free_table(obj->pages);
  1616.         kfree(obj->pages);
  1617. }
  1618.  
  1619. int
  1620. i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
  1621. {
  1622.         const struct drm_i915_gem_object_ops *ops = obj->ops;
  1623.  
  1624.         if (obj->pages == NULL)
  1625.                 return 0;
  1626.  
  1627.         if (obj->pages_pin_count)
  1628.                 return -EBUSY;
  1629.  
  1630.         BUG_ON(i915_gem_obj_bound_any(obj));
  1631.  
  1632.         /* ->put_pages might need to allocate memory for the bit17 swizzle
  1633.          * array, hence protect them from being reaped by removing them from gtt
  1634.          * lists early. */
  1635.         list_del(&obj->global_list);
  1636.  
  1637.         ops->put_pages(obj);
  1638.         obj->pages = NULL;
  1639.  
  1640.         i915_gem_object_invalidate(obj);
  1641.  
  1642.         return 0;
  1643. }
  1644.  
  1645.  
  1646.  
  1647.  
  1648.  
  1649.  
  1650.  
  1651.  
  1652. static int
  1653. i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
  1654. {
  1655.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1656.     int page_count, i;
  1657.     struct sg_table *st;
  1658.         struct scatterlist *sg;
  1659.         struct sg_page_iter sg_iter;
  1660.         struct page *page;
  1661.         unsigned long last_pfn = 0;     /* suppress gcc warning */
  1662.         gfp_t gfp;
  1663.  
  1664.         /* Assert that the object is not currently in any GPU domain. As it
  1665.          * wasn't in the GTT, there shouldn't be any way it could have been in
  1666.          * a GPU cache
  1667.          */
  1668.         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
  1669.         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
  1670.  
  1671.         st = kmalloc(sizeof(*st), GFP_KERNEL);
  1672.         if (st == NULL)
  1673.                 return -ENOMEM;
  1674.  
  1675.         page_count = obj->base.size / PAGE_SIZE;
  1676.         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
  1677.                 kfree(st);
  1678.         FAIL();
  1679.                 return -ENOMEM;
  1680.         }
  1681.  
  1682.         /* Get the list of pages out of our struct file.  They'll be pinned
  1683.          * at this point until we release them.
  1684.          *
  1685.          * Fail silently without starting the shrinker
  1686.          */
  1687.         sg = st->sgl;
  1688.         st->nents = 0;
  1689.         for (i = 0; i < page_count; i++) {
  1690.         page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp);
  1691.                 if (IS_ERR(page)) {
  1692.             dbgprintf("%s invalid page %p\n", __FUNCTION__, page);
  1693.                         goto err_pages;
  1694.  
  1695.                 }
  1696.  
  1697.                 if (!i || page_to_pfn(page) != last_pfn + 1) {
  1698.                         if (i)
  1699.                                 sg = sg_next(sg);
  1700.                         st->nents++;
  1701.                 sg_set_page(sg, page, PAGE_SIZE, 0);
  1702.                 } else {
  1703.                         sg->length += PAGE_SIZE;
  1704.                 }
  1705.                 last_pfn = page_to_pfn(page);
  1706.         }
  1707.  
  1708.                 sg_mark_end(sg);
  1709.         obj->pages = st;
  1710.  
  1711.         return 0;
  1712.  
  1713. err_pages:
  1714.         sg_mark_end(sg);
  1715.         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
  1716.                 page_cache_release(sg_page_iter_page(&sg_iter));
  1717.         sg_free_table(st);
  1718.         kfree(st);
  1719.     FAIL();
  1720.         return PTR_ERR(page);
  1721. }
  1722.  
  1723. /* Ensure that the associated pages are gathered from the backing storage
  1724.  * and pinned into our object. i915_gem_object_get_pages() may be called
  1725.  * multiple times before they are released by a single call to
  1726.  * i915_gem_object_put_pages() - once the pages are no longer referenced
  1727.  * either as a result of memory pressure (reaping pages under the shrinker)
  1728.  * or as the object is itself released.
  1729.  */
  1730. int
  1731. i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
  1732. {
  1733.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1734.         const struct drm_i915_gem_object_ops *ops = obj->ops;
  1735.         int ret;
  1736.  
  1737.         if (obj->pages)
  1738.                 return 0;
  1739.  
  1740.         if (obj->madv != I915_MADV_WILLNEED) {
  1741.                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
  1742.                 return -EFAULT;
  1743.         }
  1744.  
  1745.         BUG_ON(obj->pages_pin_count);
  1746.  
  1747.         ret = ops->get_pages(obj);
  1748.         if (ret)
  1749.                 return ret;
  1750.  
  1751.         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
  1752.     return 0;
  1753. }
  1754.  
  1755. static void
  1756. i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1757.                                struct intel_engine_cs *ring)
  1758. {
  1759.         struct drm_device *dev = obj->base.dev;
  1760.         struct drm_i915_private *dev_priv = dev->dev_private;
  1761.         u32 seqno = intel_ring_get_seqno(ring);
  1762.  
  1763.         BUG_ON(ring == NULL);
  1764.         if (obj->ring != ring && obj->last_write_seqno) {
  1765.                 /* Keep the seqno relative to the current ring */
  1766.                 obj->last_write_seqno = seqno;
  1767.         }
  1768.         obj->ring = ring;
  1769.  
  1770.         /* Add a reference if we're newly entering the active list. */
  1771.         if (!obj->active) {
  1772.                 drm_gem_object_reference(&obj->base);
  1773.                 obj->active = 1;
  1774.         }
  1775.  
  1776.         list_move_tail(&obj->ring_list, &ring->active_list);
  1777.  
  1778.         obj->last_read_seqno = seqno;
  1779.  
  1780.         if (obj->fenced_gpu_access) {
  1781.                 obj->last_fenced_seqno = seqno;
  1782.  
  1783.                 /* Bump MRU to take account of the delayed flush */
  1784.                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1785.                 struct drm_i915_fence_reg *reg;
  1786.  
  1787.                 reg = &dev_priv->fence_regs[obj->fence_reg];
  1788.                         list_move_tail(&reg->lru_list,
  1789.                                        &dev_priv->mm.fence_list);
  1790.                 }
  1791.         }
  1792. }
  1793.  
  1794. void i915_vma_move_to_active(struct i915_vma *vma,
  1795.                              struct intel_engine_cs *ring)
  1796. {
  1797.         list_move_tail(&vma->mm_list, &vma->vm->active_list);
  1798.         return i915_gem_object_move_to_active(vma->obj, ring);
  1799. }
  1800.  
  1801. static void
  1802. i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
  1803. {
  1804.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1805.         struct i915_address_space *vm;
  1806.         struct i915_vma *vma;
  1807.  
  1808.         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
  1809.         BUG_ON(!obj->active);
  1810.  
  1811.         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
  1812.                 vma = i915_gem_obj_to_vma(obj, vm);
  1813.                 if (vma && !list_empty(&vma->mm_list))
  1814.                         list_move_tail(&vma->mm_list, &vm->inactive_list);
  1815.         }
  1816.  
  1817.         list_del_init(&obj->ring_list);
  1818.         obj->ring = NULL;
  1819.  
  1820.         obj->last_read_seqno = 0;
  1821.         obj->last_write_seqno = 0;
  1822.         obj->base.write_domain = 0;
  1823.  
  1824.         obj->last_fenced_seqno = 0;
  1825.         obj->fenced_gpu_access = false;
  1826.  
  1827.         obj->active = 0;
  1828.         drm_gem_object_unreference(&obj->base);
  1829.  
  1830.         WARN_ON(i915_verify_lists(dev));
  1831. }
  1832.  
  1833. static void
  1834. i915_gem_object_retire(struct drm_i915_gem_object *obj)
  1835. {
  1836.         struct intel_engine_cs *ring = obj->ring;
  1837.  
  1838.         if (ring == NULL)
  1839.                 return;
  1840.  
  1841.         if (i915_seqno_passed(ring->get_seqno(ring, true),
  1842.                               obj->last_read_seqno))
  1843.                 i915_gem_object_move_to_inactive(obj);
  1844. }
  1845.  
  1846. static int
  1847. i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
  1848. {
  1849.         struct drm_i915_private *dev_priv = dev->dev_private;
  1850.         struct intel_engine_cs *ring;
  1851.         int ret, i, j;
  1852.  
  1853.         /* Carefully retire all requests without writing to the rings */
  1854.         for_each_ring(ring, dev_priv, i) {
  1855.                 ret = intel_ring_idle(ring);
  1856.         if (ret)
  1857.                 return ret;
  1858.         }
  1859.         i915_gem_retire_requests(dev);
  1860.  
  1861.         /* Finally reset hw state */
  1862.         for_each_ring(ring, dev_priv, i) {
  1863.                 intel_ring_init_seqno(ring, seqno);
  1864.  
  1865.                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
  1866.                         ring->semaphore.sync_seqno[j] = 0;
  1867.         }
  1868.  
  1869.         return 0;
  1870. }
  1871.  
  1872. int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
  1873. {
  1874.         struct drm_i915_private *dev_priv = dev->dev_private;
  1875.         int ret;
  1876.  
  1877.         if (seqno == 0)
  1878.                 return -EINVAL;
  1879.  
  1880.         /* HWS page needs to be set less than what we
  1881.          * will inject to ring
  1882.          */
  1883.         ret = i915_gem_init_seqno(dev, seqno - 1);
  1884.         if (ret)
  1885.                 return ret;
  1886.  
  1887.         /* Carefully set the last_seqno value so that wrap
  1888.          * detection still works
  1889.          */
  1890.         dev_priv->next_seqno = seqno;
  1891.         dev_priv->last_seqno = seqno - 1;
  1892.         if (dev_priv->last_seqno == 0)
  1893.                 dev_priv->last_seqno--;
  1894.  
  1895.         return 0;
  1896. }
  1897.  
  1898. int
  1899. i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
  1900. {
  1901.         struct drm_i915_private *dev_priv = dev->dev_private;
  1902.  
  1903.         /* reserve 0 for non-seqno */
  1904.         if (dev_priv->next_seqno == 0) {
  1905.                 int ret = i915_gem_init_seqno(dev, 0);
  1906.                 if (ret)
  1907.                         return ret;
  1908.  
  1909.                 dev_priv->next_seqno = 1;
  1910.         }
  1911.  
  1912.         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
  1913.         return 0;
  1914. }
  1915.  
  1916. int __i915_add_request(struct intel_engine_cs *ring,
  1917.                  struct drm_file *file,
  1918.                        struct drm_i915_gem_object *obj,
  1919.                  u32 *out_seqno)
  1920. {
  1921.         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1922.         struct drm_i915_gem_request *request;
  1923.         u32 request_ring_position, request_start;
  1924.         int ret;
  1925.  
  1926.         request_start = intel_ring_get_tail(ring->buffer);
  1927.         /*
  1928.          * Emit any outstanding flushes - execbuf can fail to emit the flush
  1929.          * after having emitted the batchbuffer command. Hence we need to fix
  1930.          * things up similar to emitting the lazy request. The difference here
  1931.          * is that the flush _must_ happen before the next request, no matter
  1932.          * what.
  1933.          */
  1934.    ret = intel_ring_flush_all_caches(ring);
  1935.    if (ret)
  1936.        return ret;
  1937.  
  1938.         request = ring->preallocated_lazy_request;
  1939.         if (WARN_ON(request == NULL))
  1940.                 return -ENOMEM;
  1941.  
  1942.         /* Record the position of the start of the request so that
  1943.          * should we detect the updated seqno part-way through the
  1944.     * GPU processing the request, we never over-estimate the
  1945.          * position of the head.
  1946.          */
  1947.         request_ring_position = intel_ring_get_tail(ring->buffer);
  1948.  
  1949.         ret = ring->add_request(ring);
  1950.         if (ret)
  1951.                 return ret;
  1952.  
  1953.         request->seqno = intel_ring_get_seqno(ring);
  1954.         request->ring = ring;
  1955.         request->head = request_start;
  1956.         request->tail = request_ring_position;
  1957.  
  1958.         /* Whilst this request exists, batch_obj will be on the
  1959.          * active_list, and so will hold the active reference. Only when this
  1960.          * request is retired will the the batch_obj be moved onto the
  1961.          * inactive_list and lose its active reference. Hence we do not need
  1962.          * to explicitly hold another reference here.
  1963.          */
  1964.         request->batch_obj = obj;
  1965.  
  1966.         /* Hold a reference to the current context so that we can inspect
  1967.          * it later in case a hangcheck error event fires.
  1968.          */
  1969.         request->ctx = ring->last_context;
  1970.         if (request->ctx)
  1971.                 i915_gem_context_reference(request->ctx);
  1972.  
  1973.         request->emitted_jiffies = jiffies;
  1974.         list_add_tail(&request->list, &ring->request_list);
  1975.         request->file_priv = NULL;
  1976.  
  1977.         if (file) {
  1978.                 struct drm_i915_file_private *file_priv = file->driver_priv;
  1979.  
  1980.                 spin_lock(&file_priv->mm.lock);
  1981.                 request->file_priv = file_priv;
  1982.                 list_add_tail(&request->client_list,
  1983.                               &file_priv->mm.request_list);
  1984.                 spin_unlock(&file_priv->mm.lock);
  1985.         }
  1986.  
  1987.         trace_i915_gem_request_add(ring, request->seqno);
  1988.         ring->outstanding_lazy_seqno = 0;
  1989.         ring->preallocated_lazy_request = NULL;
  1990.  
  1991.         if (!dev_priv->ums.mm_suspended) {
  1992. //              i915_queue_hangcheck(ring->dev);
  1993.  
  1994.            queue_delayed_work(dev_priv->wq,
  1995.                                            &dev_priv->mm.retire_work,
  1996.                                            round_jiffies_up_relative(HZ));
  1997.            intel_mark_busy(dev_priv->dev);
  1998.        }
  1999.  
  2000.         if (out_seqno)
  2001.                 *out_seqno = request->seqno;
  2002.         return 0;
  2003. }
  2004.  
  2005. static inline void
  2006. i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
  2007. {
  2008.         struct drm_i915_file_private *file_priv = request->file_priv;
  2009.  
  2010.         if (!file_priv)
  2011.                 return;
  2012.  
  2013.         spin_lock(&file_priv->mm.lock);
  2014.                 list_del(&request->client_list);
  2015.                 request->file_priv = NULL;
  2016.         spin_unlock(&file_priv->mm.lock);
  2017. }
  2018.  
  2019. static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
  2020.                                    const struct intel_context *ctx)
  2021. {
  2022.         unsigned long elapsed;
  2023.  
  2024.     elapsed = GetTimerTicks()/100 - ctx->hang_stats.guilty_ts;
  2025.  
  2026.         if (ctx->hang_stats.banned)
  2027.                 return true;
  2028.  
  2029.         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
  2030.                 if (!i915_gem_context_is_default(ctx)) {
  2031.                         DRM_DEBUG("context hanging too fast, banning!\n");
  2032.                         return true;
  2033.                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
  2034.                         if (i915_stop_ring_allow_warn(dev_priv))
  2035.                         DRM_ERROR("gpu hanging too fast, banning!\n");
  2036.                         return true;
  2037.         }
  2038.         }
  2039.  
  2040.         return false;
  2041. }
  2042.  
  2043. static void i915_set_reset_status(struct drm_i915_private *dev_priv,
  2044.                                   struct intel_context *ctx,
  2045.                                   const bool guilty)
  2046. {
  2047.         struct i915_ctx_hang_stats *hs;
  2048.  
  2049.         if (WARN_ON(!ctx))
  2050.                 return;
  2051.  
  2052.         hs = &ctx->hang_stats;
  2053.  
  2054.         if (guilty) {
  2055.                 hs->banned = i915_context_is_banned(dev_priv, ctx);
  2056.                 hs->batch_active++;
  2057.         hs->guilty_ts = GetTimerTicks()/100;
  2058.         } else {
  2059.                 hs->batch_pending++;
  2060.         }
  2061. }
  2062.  
  2063. static void i915_gem_free_request(struct drm_i915_gem_request *request)
  2064. {
  2065.         list_del(&request->list);
  2066.         i915_gem_request_remove_from_client(request);
  2067.  
  2068.         if (request->ctx)
  2069.                 i915_gem_context_unreference(request->ctx);
  2070.  
  2071.         kfree(request);
  2072. }
  2073.  
  2074. struct drm_i915_gem_request *
  2075. i915_gem_find_active_request(struct intel_engine_cs *ring)
  2076. {
  2077.         struct drm_i915_gem_request *request;
  2078.         u32 completed_seqno;
  2079.  
  2080.         completed_seqno = ring->get_seqno(ring, false);
  2081.  
  2082.         list_for_each_entry(request, &ring->request_list, list) {
  2083.                 if (i915_seqno_passed(completed_seqno, request->seqno))
  2084.                         continue;
  2085.  
  2086.                 return request;
  2087.         }
  2088.  
  2089.         return NULL;
  2090. }
  2091.  
  2092. static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
  2093.                                        struct intel_engine_cs *ring)
  2094. {
  2095.         struct drm_i915_gem_request *request;
  2096.         bool ring_hung;
  2097.  
  2098.         request = i915_gem_find_active_request(ring);
  2099.  
  2100.         if (request == NULL)
  2101.                 return;
  2102.  
  2103.         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
  2104.  
  2105.         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
  2106.  
  2107.         list_for_each_entry_continue(request, &ring->request_list, list)
  2108.                 i915_set_reset_status(dev_priv, request->ctx, false);
  2109. }
  2110.  
  2111. static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
  2112.                                         struct intel_engine_cs *ring)
  2113. {
  2114.         while (!list_empty(&ring->active_list)) {
  2115.                 struct drm_i915_gem_object *obj;
  2116.  
  2117.                 obj = list_first_entry(&ring->active_list,
  2118.                                        struct drm_i915_gem_object,
  2119.                                        ring_list);
  2120.  
  2121.                 i915_gem_object_move_to_inactive(obj);
  2122.         }
  2123.  
  2124.         /*
  2125.          * We must free the requests after all the corresponding objects have
  2126.          * been moved off active lists. Which is the same order as the normal
  2127.          * retire_requests function does. This is important if object hold
  2128.          * implicit references on things like e.g. ppgtt address spaces through
  2129.          * the request.
  2130.          */
  2131.         while (!list_empty(&ring->request_list)) {
  2132.                 struct drm_i915_gem_request *request;
  2133.  
  2134.                 request = list_first_entry(&ring->request_list,
  2135.                                            struct drm_i915_gem_request,
  2136.                                            list);
  2137.  
  2138.                 i915_gem_free_request(request);
  2139.         }
  2140.  
  2141.         /* These may not have been flush before the reset, do so now */
  2142.         kfree(ring->preallocated_lazy_request);
  2143.         ring->preallocated_lazy_request = NULL;
  2144.         ring->outstanding_lazy_seqno = 0;
  2145. }
  2146.  
  2147. void i915_gem_restore_fences(struct drm_device *dev)
  2148. {
  2149.         struct drm_i915_private *dev_priv = dev->dev_private;
  2150.         int i;
  2151.  
  2152.         for (i = 0; i < dev_priv->num_fence_regs; i++) {
  2153.                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
  2154.  
  2155.                 /*
  2156.                  * Commit delayed tiling changes if we have an object still
  2157.                  * attached to the fence, otherwise just clear the fence.
  2158.                  */
  2159.                 if (reg->obj) {
  2160.                         i915_gem_object_update_fence(reg->obj, reg,
  2161.                                                      reg->obj->tiling_mode);
  2162.                 } else {
  2163.                         i915_gem_write_fence(dev, i, NULL);
  2164.                 }
  2165.         }
  2166. }
  2167.  
  2168. void i915_gem_reset(struct drm_device *dev)
  2169. {
  2170.         struct drm_i915_private *dev_priv = dev->dev_private;
  2171.         struct intel_engine_cs *ring;
  2172.         int i;
  2173.  
  2174.         /*
  2175.          * Before we free the objects from the requests, we need to inspect
  2176.          * them for finding the guilty party. As the requests only borrow
  2177.          * their reference to the objects, the inspection must be done first.
  2178.          */
  2179.         for_each_ring(ring, dev_priv, i)
  2180.                 i915_gem_reset_ring_status(dev_priv, ring);
  2181.  
  2182.         for_each_ring(ring, dev_priv, i)
  2183.                 i915_gem_reset_ring_cleanup(dev_priv, ring);
  2184.  
  2185.         i915_gem_context_reset(dev);
  2186.  
  2187.         i915_gem_restore_fences(dev);
  2188. }
  2189.  
  2190. /**
  2191.  * This function clears the request list as sequence numbers are passed.
  2192.  */
  2193. void
  2194. i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
  2195. {
  2196.         uint32_t seqno;
  2197.  
  2198.         if (list_empty(&ring->request_list))
  2199.                 return;
  2200.  
  2201.         WARN_ON(i915_verify_lists(ring->dev));
  2202.  
  2203.         seqno = ring->get_seqno(ring, true);
  2204.  
  2205.         /* Move any buffers on the active list that are no longer referenced
  2206.          * by the ringbuffer to the flushing/inactive lists as appropriate,
  2207.          * before we free the context associated with the requests.
  2208.          */
  2209.         while (!list_empty(&ring->active_list)) {
  2210.                 struct drm_i915_gem_object *obj;
  2211.  
  2212.                 obj = list_first_entry(&ring->active_list,
  2213.                                       struct drm_i915_gem_object,
  2214.                                       ring_list);
  2215.  
  2216.                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
  2217.                         break;
  2218.  
  2219.                 i915_gem_object_move_to_inactive(obj);
  2220.         }
  2221.  
  2222.  
  2223.         while (!list_empty(&ring->request_list)) {
  2224.                 struct drm_i915_gem_request *request;
  2225.  
  2226.                 request = list_first_entry(&ring->request_list,
  2227.                                            struct drm_i915_gem_request,
  2228.                                            list);
  2229.  
  2230.                 if (!i915_seqno_passed(seqno, request->seqno))
  2231.                         break;
  2232.  
  2233.                 trace_i915_gem_request_retire(ring, request->seqno);
  2234.                 /* We know the GPU must have read the request to have
  2235.                  * sent us the seqno + interrupt, so use the position
  2236.                  * of tail of the request to update the last known position
  2237.                  * of the GPU head.
  2238.                  */
  2239.                 ring->buffer->last_retired_head = request->tail;
  2240.  
  2241.                 i915_gem_free_request(request);
  2242.         }
  2243.  
  2244.         if (unlikely(ring->trace_irq_seqno &&
  2245.                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
  2246.                 ring->irq_put(ring);
  2247.                 ring->trace_irq_seqno = 0;
  2248.         }
  2249.  
  2250.         WARN_ON(i915_verify_lists(ring->dev));
  2251. }
  2252.  
  2253. bool
  2254. i915_gem_retire_requests(struct drm_device *dev)
  2255. {
  2256.         struct drm_i915_private *dev_priv = dev->dev_private;
  2257.         struct intel_engine_cs *ring;
  2258.         bool idle = true;
  2259.         int i;
  2260.  
  2261.         for_each_ring(ring, dev_priv, i) {
  2262.                 i915_gem_retire_requests_ring(ring);
  2263.                 idle &= list_empty(&ring->request_list);
  2264.         }
  2265.  
  2266.         if (idle)
  2267.                 mod_delayed_work(dev_priv->wq,
  2268.                                    &dev_priv->mm.idle_work,
  2269.                                    msecs_to_jiffies(100));
  2270.  
  2271.         return idle;
  2272. }
  2273.  
  2274. static void
  2275. i915_gem_retire_work_handler(struct work_struct *work)
  2276. {
  2277.         struct drm_i915_private *dev_priv =
  2278.                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
  2279.         struct drm_device *dev = dev_priv->dev;
  2280.         bool idle;
  2281.  
  2282.         /* Come back later if the device is busy... */
  2283.         idle = false;
  2284.         if (mutex_trylock(&dev->struct_mutex)) {
  2285.                 idle = i915_gem_retire_requests(dev);
  2286.                 mutex_unlock(&dev->struct_mutex);
  2287.         }
  2288.         if (!idle)
  2289.                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
  2290.                                    round_jiffies_up_relative(HZ));
  2291. }
  2292.  
  2293. static void
  2294. i915_gem_idle_work_handler(struct work_struct *work)
  2295. {
  2296.         struct drm_i915_private *dev_priv =
  2297.                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
  2298.  
  2299.         intel_mark_idle(dev_priv->dev);
  2300. }
  2301.  
  2302. /**
  2303.  * Ensures that an object will eventually get non-busy by flushing any required
  2304.  * write domains, emitting any outstanding lazy request and retiring and
  2305.  * completed requests.
  2306.  */
  2307. static int
  2308. i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
  2309. {
  2310.         int ret;
  2311.  
  2312.         if (obj->active) {
  2313.                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
  2314.                 if (ret)
  2315.                         return ret;
  2316.  
  2317.                 i915_gem_retire_requests_ring(obj->ring);
  2318.         }
  2319.  
  2320.         return 0;
  2321. }
  2322.  
  2323. /**
  2324.  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
  2325.  * @DRM_IOCTL_ARGS: standard ioctl arguments
  2326.  *
  2327.  * Returns 0 if successful, else an error is returned with the remaining time in
  2328.  * the timeout parameter.
  2329.  *  -ETIME: object is still busy after timeout
  2330.  *  -ERESTARTSYS: signal interrupted the wait
  2331.  *  -ENONENT: object doesn't exist
  2332.  * Also possible, but rare:
  2333.  *  -EAGAIN: GPU wedged
  2334.  *  -ENOMEM: damn
  2335.  *  -ENODEV: Internal IRQ fail
  2336.  *  -E?: The add request failed
  2337.  *
  2338.  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
  2339.  * non-zero timeout parameter the wait ioctl will wait for the given number of
  2340.  * nanoseconds on an object becoming unbusy. Since the wait itself does so
  2341.  * without holding struct_mutex the object may become re-busied before this
  2342.  * function completes. A similar but shorter * race condition exists in the busy
  2343.  * ioctl
  2344.  */
  2345. int
  2346. i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
  2347. {
  2348.         struct drm_i915_private *dev_priv = dev->dev_private;
  2349.         struct drm_i915_gem_wait *args = data;
  2350.         struct drm_i915_gem_object *obj;
  2351.         struct intel_engine_cs *ring = NULL;
  2352.         unsigned reset_counter;
  2353.         u32 seqno = 0;
  2354.         int ret = 0;
  2355.  
  2356.         ret = i915_mutex_lock_interruptible(dev);
  2357.         if (ret)
  2358.                 return ret;
  2359.  
  2360.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
  2361.         if (&obj->base == NULL) {
  2362.                 mutex_unlock(&dev->struct_mutex);
  2363.                 return -ENOENT;
  2364.         }
  2365.  
  2366.         /* Need to make sure the object gets inactive eventually. */
  2367.         ret = i915_gem_object_flush_active(obj);
  2368.         if (ret)
  2369.                 goto out;
  2370.  
  2371.         if (obj->active) {
  2372.                 seqno = obj->last_read_seqno;
  2373.                 ring = obj->ring;
  2374.         }
  2375.  
  2376.         if (seqno == 0)
  2377.                  goto out;
  2378.  
  2379.         /* Do this after OLR check to make sure we make forward progress polling
  2380.          * on this IOCTL with a timeout <=0 (like busy ioctl)
  2381.          */
  2382.         if (args->timeout_ns <= 0) {
  2383.                 ret = -ETIME;
  2384.                 goto out;
  2385.         }
  2386.  
  2387.         drm_gem_object_unreference(&obj->base);
  2388.         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  2389.         mutex_unlock(&dev->struct_mutex);
  2390.  
  2391.         return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
  2392.                             file->driver_priv);
  2393.  
  2394. out:
  2395.         drm_gem_object_unreference(&obj->base);
  2396.         mutex_unlock(&dev->struct_mutex);
  2397.         return ret;
  2398. }
  2399.  
  2400. /**
  2401.  * i915_gem_object_sync - sync an object to a ring.
  2402.  *
  2403.  * @obj: object which may be in use on another ring.
  2404.  * @to: ring we wish to use the object on. May be NULL.
  2405.  *
  2406.  * This code is meant to abstract object synchronization with the GPU.
  2407.  * Calling with NULL implies synchronizing the object with the CPU
  2408.  * rather than a particular GPU ring.
  2409.  *
  2410.  * Returns 0 if successful, else propagates up the lower layer error.
  2411.  */
  2412. int
  2413. i915_gem_object_sync(struct drm_i915_gem_object *obj,
  2414.                      struct intel_engine_cs *to)
  2415. {
  2416.         struct intel_engine_cs *from = obj->ring;
  2417.         u32 seqno;
  2418.         int ret, idx;
  2419.  
  2420.         if (from == NULL || to == from)
  2421.                 return 0;
  2422.  
  2423.         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
  2424.                 return i915_gem_object_wait_rendering(obj, false);
  2425.  
  2426.         idx = intel_ring_sync_index(from, to);
  2427.  
  2428.         seqno = obj->last_read_seqno;
  2429.         /* Optimization: Avoid semaphore sync when we are sure we already
  2430.          * waited for an object with higher seqno */
  2431.         if (seqno <= from->semaphore.sync_seqno[idx])
  2432.                 return 0;
  2433.  
  2434.         ret = i915_gem_check_olr(obj->ring, seqno);
  2435.         if (ret)
  2436.                 return ret;
  2437.  
  2438.         trace_i915_gem_ring_sync_to(from, to, seqno);
  2439.         ret = to->semaphore.sync_to(to, from, seqno);
  2440.         if (!ret)
  2441.                 /* We use last_read_seqno because sync_to()
  2442.                  * might have just caused seqno wrap under
  2443.                  * the radar.
  2444.                  */
  2445.                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
  2446.  
  2447.         return ret;
  2448. }
  2449.  
  2450. static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
  2451. {
  2452.         u32 old_write_domain, old_read_domains;
  2453.  
  2454.         /* Force a pagefault for domain tracking on next user access */
  2455. //      i915_gem_release_mmap(obj);
  2456.  
  2457.         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
  2458.                 return;
  2459.  
  2460.         /* Wait for any direct GTT access to complete */
  2461.         mb();
  2462.  
  2463.         old_read_domains = obj->base.read_domains;
  2464.         old_write_domain = obj->base.write_domain;
  2465.  
  2466.         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
  2467.         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
  2468.  
  2469.         trace_i915_gem_object_change_domain(obj,
  2470.                                             old_read_domains,
  2471.                                             old_write_domain);
  2472. }
  2473.  
  2474. int i915_vma_unbind(struct i915_vma *vma)
  2475. {
  2476.         struct drm_i915_gem_object *obj = vma->obj;
  2477.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2478.         int ret;
  2479.  
  2480.     if(obj == get_fb_obj())
  2481.         return 0;
  2482.  
  2483.         if (list_empty(&vma->vma_link))
  2484.                 return 0;
  2485.  
  2486.         if (!drm_mm_node_allocated(&vma->node)) {
  2487.                 i915_gem_vma_destroy(vma);
  2488.                 return 0;
  2489.         }
  2490.  
  2491.         if (vma->pin_count)
  2492.                 return -EBUSY;
  2493.  
  2494.         BUG_ON(obj->pages == NULL);
  2495.  
  2496.         ret = i915_gem_object_finish_gpu(obj);
  2497.         if (ret)
  2498.                 return ret;
  2499.         /* Continue on if we fail due to EIO, the GPU is hung so we
  2500.          * should be safe and we need to cleanup or else we might
  2501.          * cause memory corruption through use-after-free.
  2502.          */
  2503.  
  2504.         if (i915_is_ggtt(vma->vm)) {
  2505.         i915_gem_object_finish_gtt(obj);
  2506.  
  2507.         /* release the fence reg _after_ flushing */
  2508.         ret = i915_gem_object_put_fence(obj);
  2509.         if (ret)
  2510.                 return ret;
  2511.         }
  2512.  
  2513.         trace_i915_vma_unbind(vma);
  2514.  
  2515.         vma->unbind_vma(vma);
  2516.  
  2517.         list_del_init(&vma->mm_list);
  2518.         /* Avoid an unnecessary call to unbind on rebind. */
  2519.         if (i915_is_ggtt(vma->vm))
  2520.         obj->map_and_fenceable = true;
  2521.  
  2522.         drm_mm_remove_node(&vma->node);
  2523.         i915_gem_vma_destroy(vma);
  2524.  
  2525.         /* Since the unbound list is global, only move to that list if
  2526.          * no more VMAs exist. */
  2527.         if (list_empty(&obj->vma_list)) {
  2528.                 i915_gem_gtt_finish_object(obj);
  2529.                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
  2530.         }
  2531.  
  2532.         /* And finally now the object is completely decoupled from this vma,
  2533.          * we can drop its hold on the backing storage and allow it to be
  2534.          * reaped by the shrinker.
  2535.          */
  2536.         i915_gem_object_unpin_pages(obj);
  2537.  
  2538.         return 0;
  2539. }
  2540.  
  2541. int i915_gpu_idle(struct drm_device *dev)
  2542. {
  2543.         struct drm_i915_private *dev_priv = dev->dev_private;
  2544.         struct intel_engine_cs *ring;
  2545.         int ret, i;
  2546.  
  2547.         /* Flush everything onto the inactive list. */
  2548.         for_each_ring(ring, dev_priv, i) {
  2549.                 ret = i915_switch_context(ring, ring->default_context);
  2550.                 if (ret)
  2551.                         return ret;
  2552.  
  2553.                 ret = intel_ring_idle(ring);
  2554.                 if (ret)
  2555.                         return ret;
  2556.         }
  2557.  
  2558.         return 0;
  2559. }
  2560.  
  2561. static void i965_write_fence_reg(struct drm_device *dev, int reg,
  2562.                                         struct drm_i915_gem_object *obj)
  2563. {
  2564.         struct drm_i915_private *dev_priv = dev->dev_private;
  2565.         int fence_reg;
  2566.         int fence_pitch_shift;
  2567.  
  2568.         if (INTEL_INFO(dev)->gen >= 6) {
  2569.                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
  2570.                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
  2571.         } else {
  2572.                 fence_reg = FENCE_REG_965_0;
  2573.                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  2574.         }
  2575.  
  2576.         fence_reg += reg * 8;
  2577.  
  2578.         /* To w/a incoherency with non-atomic 64-bit register updates,
  2579.          * we split the 64-bit update into two 32-bit writes. In order
  2580.          * for a partial fence not to be evaluated between writes, we
  2581.          * precede the update with write to turn off the fence register,
  2582.          * and only enable the fence as the last step.
  2583.          *
  2584.          * For extra levels of paranoia, we make sure each step lands
  2585.          * before applying the next step.
  2586.          */
  2587.         I915_WRITE(fence_reg, 0);
  2588.         POSTING_READ(fence_reg);
  2589.  
  2590.         if (obj) {
  2591.                 u32 size = i915_gem_obj_ggtt_size(obj);
  2592.                 uint64_t val;
  2593.  
  2594.                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
  2595.                                  0xfffff000) << 32;
  2596.                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
  2597.                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
  2598.                 if (obj->tiling_mode == I915_TILING_Y)
  2599.                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
  2600.                 val |= I965_FENCE_REG_VALID;
  2601.  
  2602.                 I915_WRITE(fence_reg + 4, val >> 32);
  2603.                 POSTING_READ(fence_reg + 4);
  2604.  
  2605.                 I915_WRITE(fence_reg + 0, val);
  2606.                 POSTING_READ(fence_reg);
  2607.         } else {
  2608.                 I915_WRITE(fence_reg + 4, 0);
  2609.                 POSTING_READ(fence_reg + 4);
  2610.         }
  2611. }
  2612.  
  2613. static void i915_write_fence_reg(struct drm_device *dev, int reg,
  2614.                                  struct drm_i915_gem_object *obj)
  2615. {
  2616.         struct drm_i915_private *dev_priv = dev->dev_private;
  2617.         u32 val;
  2618.  
  2619.         if (obj) {
  2620.                 u32 size = i915_gem_obj_ggtt_size(obj);
  2621.                 int pitch_val;
  2622.                 int tile_width;
  2623.  
  2624.                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
  2625.                      (size & -size) != size ||
  2626.                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
  2627.                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
  2628.                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
  2629.  
  2630.                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
  2631.                         tile_width = 128;
  2632.                 else
  2633.                         tile_width = 512;
  2634.  
  2635.                 /* Note: pitch better be a power of two tile widths */
  2636.                 pitch_val = obj->stride / tile_width;
  2637.                 pitch_val = ffs(pitch_val) - 1;
  2638.  
  2639.                 val = i915_gem_obj_ggtt_offset(obj);
  2640.                 if (obj->tiling_mode == I915_TILING_Y)
  2641.                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
  2642.                 val |= I915_FENCE_SIZE_BITS(size);
  2643.                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
  2644.                 val |= I830_FENCE_REG_VALID;
  2645.         } else
  2646.                 val = 0;
  2647.  
  2648.         if (reg < 8)
  2649.                 reg = FENCE_REG_830_0 + reg * 4;
  2650.         else
  2651.                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
  2652.  
  2653.         I915_WRITE(reg, val);
  2654.         POSTING_READ(reg);
  2655. }
  2656.  
  2657. static void i830_write_fence_reg(struct drm_device *dev, int reg,
  2658.                                 struct drm_i915_gem_object *obj)
  2659. {
  2660.         struct drm_i915_private *dev_priv = dev->dev_private;
  2661.         uint32_t val;
  2662.  
  2663.         if (obj) {
  2664.                 u32 size = i915_gem_obj_ggtt_size(obj);
  2665.                 uint32_t pitch_val;
  2666.  
  2667.                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
  2668.                      (size & -size) != size ||
  2669.                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
  2670.                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
  2671.                      i915_gem_obj_ggtt_offset(obj), size);
  2672.  
  2673.                 pitch_val = obj->stride / 128;
  2674.                 pitch_val = ffs(pitch_val) - 1;
  2675.  
  2676.                 val = i915_gem_obj_ggtt_offset(obj);
  2677.                 if (obj->tiling_mode == I915_TILING_Y)
  2678.                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
  2679.                 val |= I830_FENCE_SIZE_BITS(size);
  2680.                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
  2681.                 val |= I830_FENCE_REG_VALID;
  2682.         } else
  2683.                 val = 0;
  2684.  
  2685.         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
  2686.         POSTING_READ(FENCE_REG_830_0 + reg * 4);
  2687. }
  2688.  
  2689. inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
  2690. {
  2691.         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
  2692. }
  2693.  
  2694. static void i915_gem_write_fence(struct drm_device *dev, int reg,
  2695.                                  struct drm_i915_gem_object *obj)
  2696. {
  2697.         struct drm_i915_private *dev_priv = dev->dev_private;
  2698.  
  2699.         /* Ensure that all CPU reads are completed before installing a fence
  2700.          * and all writes before removing the fence.
  2701.          */
  2702.         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
  2703.                 mb();
  2704.  
  2705.         WARN(obj && (!obj->stride || !obj->tiling_mode),
  2706.              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
  2707.              obj->stride, obj->tiling_mode);
  2708.  
  2709.         switch (INTEL_INFO(dev)->gen) {
  2710.         case 8:
  2711.         case 7:
  2712.         case 6:
  2713.         case 5:
  2714.         case 4: i965_write_fence_reg(dev, reg, obj); break;
  2715.         case 3: i915_write_fence_reg(dev, reg, obj); break;
  2716.         case 2: i830_write_fence_reg(dev, reg, obj); break;
  2717.         default: BUG();
  2718.         }
  2719.  
  2720.         /* And similarly be paranoid that no direct access to this region
  2721.          * is reordered to before the fence is installed.
  2722.          */
  2723.         if (i915_gem_object_needs_mb(obj))
  2724.                 mb();
  2725. }
  2726.  
  2727. static inline int fence_number(struct drm_i915_private *dev_priv,
  2728.                                struct drm_i915_fence_reg *fence)
  2729. {
  2730.         return fence - dev_priv->fence_regs;
  2731. }
  2732.  
  2733. static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  2734.                                          struct drm_i915_fence_reg *fence,
  2735.                                          bool enable)
  2736. {
  2737.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2738.         int reg = fence_number(dev_priv, fence);
  2739.  
  2740.         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
  2741.  
  2742.         if (enable) {
  2743.                 obj->fence_reg = reg;
  2744.                 fence->obj = obj;
  2745.                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
  2746.         } else {
  2747.                 obj->fence_reg = I915_FENCE_REG_NONE;
  2748.                 fence->obj = NULL;
  2749.                 list_del_init(&fence->lru_list);
  2750.         }
  2751.         obj->fence_dirty = false;
  2752. }
  2753.  
  2754. static int
  2755. i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
  2756. {
  2757.         if (obj->last_fenced_seqno) {
  2758.                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
  2759.                         if (ret)
  2760.                                 return ret;
  2761.  
  2762.                 obj->last_fenced_seqno = 0;
  2763.         }
  2764.  
  2765.         obj->fenced_gpu_access = false;
  2766.         return 0;
  2767. }
  2768.  
  2769. int
  2770. i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
  2771. {
  2772.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2773.         struct drm_i915_fence_reg *fence;
  2774.         int ret;
  2775.  
  2776.         ret = i915_gem_object_wait_fence(obj);
  2777.     if (ret)
  2778.        return ret;
  2779.  
  2780.         if (obj->fence_reg == I915_FENCE_REG_NONE)
  2781.                 return 0;
  2782.  
  2783.         fence = &dev_priv->fence_regs[obj->fence_reg];
  2784.  
  2785.         if (WARN_ON(fence->pin_count))
  2786.                 return -EBUSY;
  2787.  
  2788.         i915_gem_object_fence_lost(obj);
  2789.         i915_gem_object_update_fence(obj, fence, false);
  2790.  
  2791.         return 0;
  2792. }
  2793.  
  2794. static struct drm_i915_fence_reg *
  2795. i915_find_fence_reg(struct drm_device *dev)
  2796. {
  2797.         struct drm_i915_private *dev_priv = dev->dev_private;
  2798.         struct drm_i915_fence_reg *reg, *avail;
  2799.         int i;
  2800.  
  2801.         /* First try to find a free reg */
  2802.         avail = NULL;
  2803.         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
  2804.                 reg = &dev_priv->fence_regs[i];
  2805.                 if (!reg->obj)
  2806.                         return reg;
  2807.  
  2808.                 if (!reg->pin_count)
  2809.                         avail = reg;
  2810.         }
  2811.  
  2812.         if (avail == NULL)
  2813.                 goto deadlock;
  2814.  
  2815.         /* None available, try to steal one or wait for a user to finish */
  2816.         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
  2817.                 if (reg->pin_count)
  2818.                         continue;
  2819.  
  2820.                 return reg;
  2821.         }
  2822.  
  2823. deadlock:
  2824.         /* Wait for completion of pending flips which consume fences */
  2825. //   if (intel_has_pending_fb_unpin(dev))
  2826. //       return ERR_PTR(-EAGAIN);
  2827.  
  2828.         return ERR_PTR(-EDEADLK);
  2829. }
  2830.  
  2831. /**
  2832.  * i915_gem_object_get_fence - set up fencing for an object
  2833.  * @obj: object to map through a fence reg
  2834.  *
  2835.  * When mapping objects through the GTT, userspace wants to be able to write
  2836.  * to them without having to worry about swizzling if the object is tiled.
  2837.  * This function walks the fence regs looking for a free one for @obj,
  2838.  * stealing one if it can't find any.
  2839.  *
  2840.  * It then sets up the reg based on the object's properties: address, pitch
  2841.  * and tiling format.
  2842.  *
  2843.  * For an untiled surface, this removes any existing fence.
  2844.  */
  2845. int
  2846. i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
  2847. {
  2848.         struct drm_device *dev = obj->base.dev;
  2849.         struct drm_i915_private *dev_priv = dev->dev_private;
  2850.         bool enable = obj->tiling_mode != I915_TILING_NONE;
  2851.         struct drm_i915_fence_reg *reg;
  2852.         int ret;
  2853.  
  2854.         /* Have we updated the tiling parameters upon the object and so
  2855.          * will need to serialise the write to the associated fence register?
  2856.          */
  2857.         if (obj->fence_dirty) {
  2858.                 ret = i915_gem_object_wait_fence(obj);
  2859.                 if (ret)
  2860.                         return ret;
  2861.         }
  2862.  
  2863.         /* Just update our place in the LRU if our fence is getting reused. */
  2864.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  2865.                 reg = &dev_priv->fence_regs[obj->fence_reg];
  2866.                 if (!obj->fence_dirty) {
  2867.                         list_move_tail(&reg->lru_list,
  2868.                                        &dev_priv->mm.fence_list);
  2869.                         return 0;
  2870.                 }
  2871.         } else if (enable) {
  2872.                 reg = i915_find_fence_reg(dev);
  2873.                 if (IS_ERR(reg))
  2874.                         return PTR_ERR(reg);
  2875.  
  2876.                 if (reg->obj) {
  2877.                         struct drm_i915_gem_object *old = reg->obj;
  2878.  
  2879.                         ret = i915_gem_object_wait_fence(old);
  2880.                         if (ret)
  2881.                                 return ret;
  2882.  
  2883.                         i915_gem_object_fence_lost(old);
  2884.                 }
  2885.         } else
  2886.                 return 0;
  2887.  
  2888.         i915_gem_object_update_fence(obj, reg, enable);
  2889.  
  2890.         return 0;
  2891. }
  2892.  
  2893. static bool i915_gem_valid_gtt_space(struct drm_device *dev,
  2894.                                      struct drm_mm_node *gtt_space,
  2895.                                      unsigned long cache_level)
  2896. {
  2897.         struct drm_mm_node *other;
  2898.  
  2899.         /* On non-LLC machines we have to be careful when putting differing
  2900.          * types of snoopable memory together to avoid the prefetcher
  2901.          * crossing memory domains and dying.
  2902.          */
  2903.         if (HAS_LLC(dev))
  2904.                 return true;
  2905.  
  2906.         if (!drm_mm_node_allocated(gtt_space))
  2907.                 return true;
  2908.  
  2909.         if (list_empty(&gtt_space->node_list))
  2910.                 return true;
  2911.  
  2912.         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
  2913.         if (other->allocated && !other->hole_follows && other->color != cache_level)
  2914.                 return false;
  2915.  
  2916.         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
  2917.         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
  2918.                 return false;
  2919.  
  2920.         return true;
  2921. }
  2922.  
  2923. static void i915_gem_verify_gtt(struct drm_device *dev)
  2924. {
  2925. #if WATCH_GTT
  2926.         struct drm_i915_private *dev_priv = dev->dev_private;
  2927.         struct drm_i915_gem_object *obj;
  2928.         int err = 0;
  2929.  
  2930.         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
  2931.                 if (obj->gtt_space == NULL) {
  2932.                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
  2933.                         err++;
  2934.                         continue;
  2935.                 }
  2936.  
  2937.                 if (obj->cache_level != obj->gtt_space->color) {
  2938.                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
  2939.                                i915_gem_obj_ggtt_offset(obj),
  2940.                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
  2941.                                obj->cache_level,
  2942.                                obj->gtt_space->color);
  2943.                         err++;
  2944.                         continue;
  2945.                 }
  2946.  
  2947.                 if (!i915_gem_valid_gtt_space(dev,
  2948.                                               obj->gtt_space,
  2949.                                               obj->cache_level)) {
  2950.                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
  2951.                                i915_gem_obj_ggtt_offset(obj),
  2952.                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
  2953.                                obj->cache_level);
  2954.                         err++;
  2955.                         continue;
  2956.                 }
  2957.         }
  2958.  
  2959.         WARN_ON(err);
  2960. #endif
  2961. }
  2962.  
  2963. /**
  2964.  * Finds free space in the GTT aperture and binds the object there.
  2965.  */
  2966. static struct i915_vma *
  2967. i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
  2968.                            struct i915_address_space *vm,
  2969.                             unsigned alignment,
  2970.                            uint64_t flags)
  2971. {
  2972.         struct drm_device *dev = obj->base.dev;
  2973.         struct drm_i915_private *dev_priv = dev->dev_private;
  2974.         u32 size, fence_size, fence_alignment, unfenced_alignment;
  2975.         unsigned long start =
  2976.                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
  2977.         unsigned long end =
  2978.                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
  2979.         struct i915_vma *vma;
  2980.         int ret;
  2981.  
  2982.         fence_size = i915_gem_get_gtt_size(dev,
  2983.                                            obj->base.size,
  2984.                                            obj->tiling_mode);
  2985.         fence_alignment = i915_gem_get_gtt_alignment(dev,
  2986.                                                      obj->base.size,
  2987.                                                      obj->tiling_mode, true);
  2988.         unfenced_alignment =
  2989.                 i915_gem_get_gtt_alignment(dev,
  2990.                                                     obj->base.size,
  2991.                                                     obj->tiling_mode, false);
  2992.  
  2993.         if (alignment == 0)
  2994.                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
  2995.                                                 unfenced_alignment;
  2996.         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
  2997.                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
  2998.                 return ERR_PTR(-EINVAL);
  2999.         }
  3000.  
  3001.         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
  3002.  
  3003.         /* If the object is bigger than the entire aperture, reject it early
  3004.          * before evicting everything in a vain attempt to find space.
  3005.          */
  3006.         if (obj->base.size > end) {
  3007.                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
  3008.                           obj->base.size,
  3009.                           flags & PIN_MAPPABLE ? "mappable" : "total",
  3010.                           end);
  3011.                 return ERR_PTR(-E2BIG);
  3012.         }
  3013.  
  3014.         ret = i915_gem_object_get_pages(obj);
  3015.         if (ret)
  3016.                 return ERR_PTR(ret);
  3017.  
  3018.         i915_gem_object_pin_pages(obj);
  3019.  
  3020.         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
  3021.         if (IS_ERR(vma))
  3022.                 goto err_unpin;
  3023.  
  3024. search_free:
  3025.         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
  3026.                                                   size, alignment,
  3027.                                                   obj->cache_level,
  3028.                                                   start, end,
  3029.                                                   DRM_MM_SEARCH_DEFAULT,
  3030.                                                   DRM_MM_CREATE_DEFAULT);
  3031.         if (ret) {
  3032.  
  3033.                 goto err_free_vma;
  3034.         }
  3035.         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
  3036.                                               obj->cache_level))) {
  3037.                 ret = -EINVAL;
  3038.                 goto err_remove_node;
  3039.         }
  3040.  
  3041.         ret = i915_gem_gtt_prepare_object(obj);
  3042.         if (ret)
  3043.                 goto err_remove_node;
  3044.  
  3045.         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
  3046.         list_add_tail(&vma->mm_list, &vm->inactive_list);
  3047.  
  3048.         if (i915_is_ggtt(vm)) {
  3049.                 bool mappable, fenceable;
  3050.  
  3051.                 fenceable = (vma->node.size == fence_size &&
  3052.                              (vma->node.start & (fence_alignment - 1)) == 0);
  3053.  
  3054.                 mappable = (vma->node.start + obj->base.size <=
  3055.                             dev_priv->gtt.mappable_end);
  3056.  
  3057.         obj->map_and_fenceable = mappable && fenceable;
  3058.         }
  3059.  
  3060.         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
  3061.  
  3062.         trace_i915_vma_bind(vma, flags);
  3063.         vma->bind_vma(vma, obj->cache_level,
  3064.                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
  3065.  
  3066.         i915_gem_verify_gtt(dev);
  3067.         return vma;
  3068.  
  3069. err_remove_node:
  3070.         drm_mm_remove_node(&vma->node);
  3071. err_free_vma:
  3072.         i915_gem_vma_destroy(vma);
  3073.         vma = ERR_PTR(ret);
  3074. err_unpin:
  3075.         i915_gem_object_unpin_pages(obj);
  3076.         return vma;
  3077. }
  3078.  
  3079. bool
  3080. i915_gem_clflush_object(struct drm_i915_gem_object *obj,
  3081.                         bool force)
  3082. {
  3083.         /* If we don't have a page list set up, then we're not pinned
  3084.          * to GPU, and we can ignore the cache flush because it'll happen
  3085.          * again at bind time.
  3086.          */
  3087.         if (obj->pages == NULL)
  3088.                 return false;
  3089.  
  3090.         /*
  3091.          * Stolen memory is always coherent with the GPU as it is explicitly
  3092.          * marked as wc by the system, or the system is cache-coherent.
  3093.          */
  3094.         if (obj->stolen)
  3095.                 return false;
  3096.  
  3097.         /* If the GPU is snooping the contents of the CPU cache,
  3098.          * we do not need to manually clear the CPU cache lines.  However,
  3099.          * the caches are only snooped when the render cache is
  3100.          * flushed/invalidated.  As we always have to emit invalidations
  3101.          * and flushes when moving into and out of the RENDER domain, correct
  3102.          * snooping behaviour occurs naturally as the result of our domain
  3103.          * tracking.
  3104.          */
  3105.         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  3106.                 return false;
  3107.  
  3108.         trace_i915_gem_object_clflush(obj);
  3109.         drm_clflush_sg(obj->pages);
  3110.  
  3111.         return true;
  3112. }
  3113.  
  3114. /** Flushes the GTT write domain for the object if it's dirty. */
  3115. static void
  3116. i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
  3117. {
  3118.         uint32_t old_write_domain;
  3119.  
  3120.         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
  3121.                 return;
  3122.  
  3123.         /* No actual flushing is required for the GTT write domain.  Writes
  3124.          * to it immediately go to main memory as far as we know, so there's
  3125.          * no chipset flush.  It also doesn't land in render cache.
  3126.          *
  3127.          * However, we do have to enforce the order so that all writes through
  3128.          * the GTT land before any writes to the device, such as updates to
  3129.          * the GATT itself.
  3130.          */
  3131.         wmb();
  3132.  
  3133.         old_write_domain = obj->base.write_domain;
  3134.         obj->base.write_domain = 0;
  3135.  
  3136.         trace_i915_gem_object_change_domain(obj,
  3137.                                             obj->base.read_domains,
  3138.                                             old_write_domain);
  3139. }
  3140.  
  3141. /** Flushes the CPU write domain for the object if it's dirty. */
  3142. static void
  3143. i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  3144.                                        bool force)
  3145. {
  3146.         uint32_t old_write_domain;
  3147.  
  3148.         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
  3149.                 return;
  3150.  
  3151.         if (i915_gem_clflush_object(obj, force))
  3152.         i915_gem_chipset_flush(obj->base.dev);
  3153.  
  3154.         old_write_domain = obj->base.write_domain;
  3155.         obj->base.write_domain = 0;
  3156.  
  3157.         trace_i915_gem_object_change_domain(obj,
  3158.                                             obj->base.read_domains,
  3159.                                             old_write_domain);
  3160. }
  3161.  
  3162. /**
  3163.  * Moves a single object to the GTT read, and possibly write domain.
  3164.  *
  3165.  * This function returns when the move is complete, including waiting on
  3166.  * flushes to occur.
  3167.  */
  3168. int
  3169. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
  3170. {
  3171.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  3172.         uint32_t old_write_domain, old_read_domains;
  3173.         int ret;
  3174.  
  3175.         /* Not valid to be called on unbound objects. */
  3176.         if (!i915_gem_obj_bound_any(obj))
  3177.                 return -EINVAL;
  3178.  
  3179.         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
  3180.                 return 0;
  3181.  
  3182.         ret = i915_gem_object_wait_rendering(obj, !write);
  3183.                 if (ret)
  3184.                         return ret;
  3185.  
  3186.         i915_gem_object_retire(obj);
  3187.         i915_gem_object_flush_cpu_write_domain(obj, false);
  3188.  
  3189.         /* Serialise direct access to this object with the barriers for
  3190.          * coherent writes from the GPU, by effectively invalidating the
  3191.          * GTT domain upon first access.
  3192.          */
  3193.         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
  3194.                 mb();
  3195.  
  3196.         old_write_domain = obj->base.write_domain;
  3197.         old_read_domains = obj->base.read_domains;
  3198.  
  3199.         /* It should now be out of any other write domains, and we can update
  3200.          * the domain values for our changes.
  3201.          */
  3202.         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
  3203.         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
  3204.         if (write) {
  3205.                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
  3206.                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
  3207.                 obj->dirty = 1;
  3208.         }
  3209.  
  3210.         trace_i915_gem_object_change_domain(obj,
  3211.                                             old_read_domains,
  3212.                                             old_write_domain);
  3213.  
  3214.         /* And bump the LRU for this access */
  3215.         if (i915_gem_object_is_inactive(obj)) {
  3216.                 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
  3217.                 if (vma)
  3218.                         list_move_tail(&vma->mm_list,
  3219.                                        &dev_priv->gtt.base.inactive_list);
  3220.  
  3221.         }
  3222.  
  3223.         return 0;
  3224. }
  3225.  
  3226. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  3227.                                     enum i915_cache_level cache_level)
  3228. {
  3229.         struct drm_device *dev = obj->base.dev;
  3230.         struct i915_vma *vma, *next;
  3231.         int ret;
  3232.  
  3233.         if (obj->cache_level == cache_level)
  3234.                 return 0;
  3235.  
  3236.         if (i915_gem_obj_is_pinned(obj)) {
  3237.                 DRM_DEBUG("can not change the cache level of pinned objects\n");
  3238.                 return -EBUSY;
  3239.         }
  3240.  
  3241.         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
  3242.                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
  3243.                         ret = i915_vma_unbind(vma);
  3244.                 if (ret)
  3245.                         return ret;
  3246.                 }
  3247.         }
  3248.  
  3249.         if (i915_gem_obj_bound_any(obj)) {
  3250.                 ret = i915_gem_object_finish_gpu(obj);
  3251.                 if (ret)
  3252.                         return ret;
  3253.  
  3254.                 i915_gem_object_finish_gtt(obj);
  3255.  
  3256.                 /* Before SandyBridge, you could not use tiling or fence
  3257.                  * registers with snooped memory, so relinquish any fences
  3258.                  * currently pointing to our region in the aperture.
  3259.                  */
  3260.                 if (INTEL_INFO(dev)->gen < 6) {
  3261.                         ret = i915_gem_object_put_fence(obj);
  3262.                         if (ret)
  3263.                                 return ret;
  3264.             }
  3265.  
  3266.                 list_for_each_entry(vma, &obj->vma_list, vma_link)
  3267.                         if (drm_mm_node_allocated(&vma->node))
  3268.                                 vma->bind_vma(vma, cache_level,
  3269.                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
  3270.         }
  3271.  
  3272.         list_for_each_entry(vma, &obj->vma_list, vma_link)
  3273.                 vma->node.color = cache_level;
  3274.         obj->cache_level = cache_level;
  3275.  
  3276.         if (cpu_write_needs_clflush(obj)) {
  3277.                 u32 old_read_domains, old_write_domain;
  3278.  
  3279.                 /* If we're coming from LLC cached, then we haven't
  3280.                  * actually been tracking whether the data is in the
  3281.                  * CPU cache or not, since we only allow one bit set
  3282.                  * in obj->write_domain and have been skipping the clflushes.
  3283.                  * Just set it to the CPU cache for now.
  3284.                  */
  3285.                 i915_gem_object_retire(obj);
  3286.                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
  3287.  
  3288.                 old_read_domains = obj->base.read_domains;
  3289.                 old_write_domain = obj->base.write_domain;
  3290.  
  3291.                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
  3292.                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
  3293.  
  3294.                 trace_i915_gem_object_change_domain(obj,
  3295.                                                     old_read_domains,
  3296.                                                     old_write_domain);
  3297.     }
  3298.  
  3299.         i915_gem_verify_gtt(dev);
  3300.         return 0;
  3301. }
  3302.  
  3303. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  3304.                                struct drm_file *file)
  3305. {
  3306.         struct drm_i915_gem_caching *args = data;
  3307.         struct drm_i915_gem_object *obj;
  3308.         int ret;
  3309.  
  3310.         ret = i915_mutex_lock_interruptible(dev);
  3311.         if (ret)
  3312.                 return ret;
  3313.  
  3314.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  3315.         if (&obj->base == NULL) {
  3316.                 ret = -ENOENT;
  3317.                 goto unlock;
  3318.         }
  3319.  
  3320.         switch (obj->cache_level) {
  3321.         case I915_CACHE_LLC:
  3322.         case I915_CACHE_L3_LLC:
  3323.                 args->caching = I915_CACHING_CACHED;
  3324.                 break;
  3325.  
  3326.         case I915_CACHE_WT:
  3327.                 args->caching = I915_CACHING_DISPLAY;
  3328.                 break;
  3329.  
  3330.         default:
  3331.                 args->caching = I915_CACHING_NONE;
  3332.                 break;
  3333.         }
  3334.  
  3335.         drm_gem_object_unreference(&obj->base);
  3336. unlock:
  3337.         mutex_unlock(&dev->struct_mutex);
  3338.         return ret;
  3339. }
  3340.  
  3341. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  3342.                                struct drm_file *file)
  3343. {
  3344.         struct drm_i915_gem_caching *args = data;
  3345.         struct drm_i915_gem_object *obj;
  3346.         enum i915_cache_level level;
  3347.         int ret;
  3348.  
  3349.         switch (args->caching) {
  3350.         case I915_CACHING_NONE:
  3351.                 level = I915_CACHE_NONE;
  3352.                 break;
  3353.         case I915_CACHING_CACHED:
  3354.                 level = I915_CACHE_LLC;
  3355.                 break;
  3356.         case I915_CACHING_DISPLAY:
  3357.                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
  3358.                 break;
  3359.         default:
  3360.                 return -EINVAL;
  3361.         }
  3362.  
  3363.         ret = i915_mutex_lock_interruptible(dev);
  3364.         if (ret)
  3365.                 return ret;
  3366.  
  3367.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  3368.         if (&obj->base == NULL) {
  3369.                 ret = -ENOENT;
  3370.                 goto unlock;
  3371.         }
  3372.  
  3373.         ret = i915_gem_object_set_cache_level(obj, level);
  3374.  
  3375.         drm_gem_object_unreference(&obj->base);
  3376. unlock:
  3377.         mutex_unlock(&dev->struct_mutex);
  3378.         return ret;
  3379. }
  3380.  
  3381. static bool is_pin_display(struct drm_i915_gem_object *obj)
  3382. {
  3383.         struct i915_vma *vma;
  3384.  
  3385.         if (list_empty(&obj->vma_list))
  3386.                 return false;
  3387.  
  3388.         vma = i915_gem_obj_to_ggtt(obj);
  3389.         if (!vma)
  3390.                 return false;
  3391.  
  3392.         /* There are 3 sources that pin objects:
  3393.          *   1. The display engine (scanouts, sprites, cursors);
  3394.          *   2. Reservations for execbuffer;
  3395.          *   3. The user.
  3396.          *
  3397.          * We can ignore reservations as we hold the struct_mutex and
  3398.          * are only called outside of the reservation path.  The user
  3399.          * can only increment pin_count once, and so if after
  3400.          * subtracting the potential reference by the user, any pin_count
  3401.          * remains, it must be due to another use by the display engine.
  3402.          */
  3403.         return vma->pin_count - !!obj->user_pin_count;
  3404. }
  3405.  
  3406. /*
  3407.  * Prepare buffer for display plane (scanout, cursors, etc).
  3408.  * Can be called from an uninterruptible phase (modesetting) and allows
  3409.  * any flushes to be pipelined (for pageflips).
  3410.  */
  3411. int
  3412. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  3413.                                      u32 alignment,
  3414.                                      struct intel_engine_cs *pipelined)
  3415. {
  3416.         u32 old_read_domains, old_write_domain;
  3417.         bool was_pin_display;
  3418.         int ret;
  3419.  
  3420.         if (pipelined != obj->ring) {
  3421.                 ret = i915_gem_object_sync(obj, pipelined);
  3422.         if (ret)
  3423.                 return ret;
  3424.         }
  3425.  
  3426.         /* Mark the pin_display early so that we account for the
  3427.          * display coherency whilst setting up the cache domains.
  3428.          */
  3429.         was_pin_display = obj->pin_display;
  3430.         obj->pin_display = true;
  3431.  
  3432.         /* The display engine is not coherent with the LLC cache on gen6.  As
  3433.          * a result, we make sure that the pinning that is about to occur is
  3434.          * done with uncached PTEs. This is lowest common denominator for all
  3435.          * chipsets.
  3436.          *
  3437.          * However for gen6+, we could do better by using the GFDT bit instead
  3438.          * of uncaching, which would allow us to flush all the LLC-cached data
  3439.          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
  3440.          */
  3441.         ret = i915_gem_object_set_cache_level(obj,
  3442.                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
  3443.         if (ret)
  3444.                 goto err_unpin_display;
  3445.  
  3446.         /* As the user may map the buffer once pinned in the display plane
  3447.          * (e.g. libkms for the bootup splash), we have to ensure that we
  3448.          * always use map_and_fenceable for all scanout buffers.
  3449.          */
  3450.         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
  3451.         if (ret)
  3452.                 goto err_unpin_display;
  3453.  
  3454.         i915_gem_object_flush_cpu_write_domain(obj, true);
  3455.  
  3456.         old_write_domain = obj->base.write_domain;
  3457.         old_read_domains = obj->base.read_domains;
  3458.  
  3459.         /* It should now be out of any other write domains, and we can update
  3460.          * the domain values for our changes.
  3461.          */
  3462.         obj->base.write_domain = 0;
  3463.         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
  3464.  
  3465.         trace_i915_gem_object_change_domain(obj,
  3466.                                             old_read_domains,
  3467.                                             old_write_domain);
  3468.  
  3469.         return 0;
  3470.  
  3471. err_unpin_display:
  3472.         WARN_ON(was_pin_display != is_pin_display(obj));
  3473.         obj->pin_display = was_pin_display;
  3474.         return ret;
  3475. }
  3476.  
  3477. void
  3478. i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
  3479. {
  3480.         i915_gem_object_ggtt_unpin(obj);
  3481.         obj->pin_display = is_pin_display(obj);
  3482. }
  3483.  
  3484. int
  3485. i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
  3486. {
  3487.         int ret;
  3488.  
  3489.         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
  3490.                 return 0;
  3491.  
  3492.         ret = i915_gem_object_wait_rendering(obj, false);
  3493.     if (ret)
  3494.         return ret;
  3495.  
  3496.         /* Ensure that we invalidate the GPU's caches and TLBs. */
  3497.         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
  3498.         return 0;
  3499. }
  3500.  
  3501. /**
  3502.  * Moves a single object to the CPU read, and possibly write domain.
  3503.  *
  3504.  * This function returns when the move is complete, including waiting on
  3505.  * flushes to occur.
  3506.  */
  3507. int
  3508. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
  3509. {
  3510.         uint32_t old_write_domain, old_read_domains;
  3511.         int ret;
  3512.  
  3513.         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
  3514.                 return 0;
  3515.  
  3516.         ret = i915_gem_object_wait_rendering(obj, !write);
  3517.         if (ret)
  3518.                 return ret;
  3519.  
  3520.         i915_gem_object_retire(obj);
  3521.         i915_gem_object_flush_gtt_write_domain(obj);
  3522.  
  3523.         old_write_domain = obj->base.write_domain;
  3524.         old_read_domains = obj->base.read_domains;
  3525.  
  3526.         /* Flush the CPU cache if it's still invalid. */
  3527.         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
  3528.                 i915_gem_clflush_object(obj, false);
  3529.  
  3530.                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
  3531.         }
  3532.  
  3533.         /* It should now be out of any other write domains, and we can update
  3534.          * the domain values for our changes.
  3535.          */
  3536.         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
  3537.  
  3538.         /* If we're writing through the CPU, then the GPU read domains will
  3539.          * need to be invalidated at next use.
  3540.          */
  3541.         if (write) {
  3542.                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
  3543.                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
  3544.         }
  3545.  
  3546.         trace_i915_gem_object_change_domain(obj,
  3547.                                             old_read_domains,
  3548.                                             old_write_domain);
  3549.  
  3550.         return 0;
  3551. }
  3552.  
  3553. /* Throttle our rendering by waiting until the ring has completed our requests
  3554.  * emitted over 20 msec ago.
  3555.  *
  3556.  * Note that if we were to use the current jiffies each time around the loop,
  3557.  * we wouldn't escape the function with any frames outstanding if the time to
  3558.  * render a frame was over 20ms.
  3559.  *
  3560.  * This should get us reasonable parallelism between CPU and GPU but also
  3561.  * relatively low latency when blocking on a particular request to finish.
  3562.  */
  3563. static int
  3564. i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
  3565. {
  3566.         struct drm_i915_private *dev_priv = dev->dev_private;
  3567.         struct drm_i915_file_private *file_priv = file->driver_priv;
  3568.         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
  3569.         struct drm_i915_gem_request *request;
  3570.         struct intel_engine_cs *ring = NULL;
  3571.         unsigned reset_counter;
  3572.         u32 seqno = 0;
  3573.         int ret;
  3574.  
  3575.         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
  3576.         if (ret)
  3577.                 return ret;
  3578.  
  3579.         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
  3580.         if (ret)
  3581.                 return ret;
  3582.  
  3583.         spin_lock(&file_priv->mm.lock);
  3584.         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
  3585.                 if (time_after_eq(request->emitted_jiffies, recent_enough))
  3586.                         break;
  3587.  
  3588.                 ring = request->ring;
  3589.                 seqno = request->seqno;
  3590.         }
  3591.         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  3592.         spin_unlock(&file_priv->mm.lock);
  3593.  
  3594.         if (seqno == 0)
  3595.                 return 0;
  3596.  
  3597.         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
  3598.         if (ret == 0)
  3599.                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
  3600.  
  3601.         return ret;
  3602. }
  3603.  
  3604. static bool
  3605. i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
  3606. {
  3607.         struct drm_i915_gem_object *obj = vma->obj;
  3608.  
  3609.         if (alignment &&
  3610.             vma->node.start & (alignment - 1))
  3611.                 return true;
  3612.  
  3613.         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
  3614.                 return true;
  3615.  
  3616.         if (flags & PIN_OFFSET_BIAS &&
  3617.             vma->node.start < (flags & PIN_OFFSET_MASK))
  3618.                 return true;
  3619.  
  3620.         return false;
  3621. }
  3622.  
  3623. int
  3624. i915_gem_object_pin(struct drm_i915_gem_object *obj,
  3625.                     struct i915_address_space *vm,
  3626.                     uint32_t alignment,
  3627.                     uint64_t flags)
  3628. {
  3629.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  3630.         struct i915_vma *vma;
  3631.         int ret;
  3632.  
  3633.         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
  3634.                 return -ENODEV;
  3635.  
  3636.         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
  3637.                 return -EINVAL;
  3638.  
  3639.         vma = i915_gem_obj_to_vma(obj, vm);
  3640.         if (vma) {
  3641.                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
  3642.                         return -EBUSY;
  3643.  
  3644.                 if (i915_vma_misplaced(vma, alignment, flags)) {
  3645.                         WARN(vma->pin_count,
  3646.                              "bo is already pinned with incorrect alignment:"
  3647.                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
  3648.                              " obj->map_and_fenceable=%d\n",
  3649.                              i915_gem_obj_offset(obj, vm), alignment,
  3650.                              !!(flags & PIN_MAPPABLE),
  3651.                              obj->map_and_fenceable);
  3652.                         ret = i915_vma_unbind(vma);
  3653.                         if (ret)
  3654.                                 return ret;
  3655.  
  3656.                         vma = NULL;
  3657.                 }
  3658.         }
  3659.  
  3660.         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
  3661.                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
  3662.                 if (IS_ERR(vma))
  3663.                         return PTR_ERR(vma);
  3664.         }
  3665.  
  3666.         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
  3667.                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
  3668.  
  3669.         vma->pin_count++;
  3670.         if (flags & PIN_MAPPABLE)
  3671.                 obj->pin_mappable |= true;
  3672.  
  3673.         return 0;
  3674. }
  3675.  
  3676. void
  3677. i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
  3678. {
  3679.         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
  3680.  
  3681.         BUG_ON(!vma);
  3682.         BUG_ON(vma->pin_count == 0);
  3683.         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
  3684.  
  3685.         if (--vma->pin_count == 0)
  3686.                 obj->pin_mappable = false;
  3687. }
  3688.  
  3689. bool
  3690. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  3691. {
  3692.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  3693.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  3694.                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
  3695.  
  3696.                 WARN_ON(!ggtt_vma ||
  3697.                         dev_priv->fence_regs[obj->fence_reg].pin_count >
  3698.                         ggtt_vma->pin_count);
  3699.                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
  3700.                 return true;
  3701.         } else
  3702.                 return false;
  3703. }
  3704.  
  3705. void
  3706. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  3707. {
  3708.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  3709.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  3710.                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
  3711.                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
  3712.         }
  3713. }
  3714.  
  3715. int
  3716. i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  3717.                    struct drm_file *file)
  3718. {
  3719.         struct drm_i915_gem_pin *args = data;
  3720.         struct drm_i915_gem_object *obj;
  3721.         int ret;
  3722.  
  3723.         if (INTEL_INFO(dev)->gen >= 6)
  3724.                 return -ENODEV;
  3725.  
  3726.         ret = i915_mutex_lock_interruptible(dev);
  3727.         if (ret)
  3728.                 return ret;
  3729.  
  3730.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  3731.         if (&obj->base == NULL) {
  3732.                 ret = -ENOENT;
  3733.                 goto unlock;
  3734.         }
  3735.  
  3736.         if (obj->madv != I915_MADV_WILLNEED) {
  3737.                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
  3738.                 ret = -EFAULT;
  3739.                 goto out;
  3740.         }
  3741.  
  3742.         if (obj->pin_filp != NULL && obj->pin_filp != file) {
  3743.                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
  3744.                           args->handle);
  3745.                 ret = -EINVAL;
  3746.                 goto out;
  3747.         }
  3748.  
  3749.         if (obj->user_pin_count == ULONG_MAX) {
  3750.                 ret = -EBUSY;
  3751.                 goto out;
  3752.         }
  3753.  
  3754.         if (obj->user_pin_count == 0) {
  3755.                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
  3756.                 if (ret)
  3757.                         goto out;
  3758.         }
  3759.  
  3760.         obj->user_pin_count++;
  3761.         obj->pin_filp = file;
  3762.  
  3763.         args->offset = i915_gem_obj_ggtt_offset(obj);
  3764. out:
  3765.         drm_gem_object_unreference(&obj->base);
  3766. unlock:
  3767.         mutex_unlock(&dev->struct_mutex);
  3768.         return ret;
  3769. }
  3770.  
  3771. int
  3772. i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  3773.                      struct drm_file *file)
  3774. {
  3775.         struct drm_i915_gem_pin *args = data;
  3776.         struct drm_i915_gem_object *obj;
  3777.         int ret;
  3778.  
  3779.         ret = i915_mutex_lock_interruptible(dev);
  3780.         if (ret)
  3781.                 return ret;
  3782.  
  3783.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  3784.         if (&obj->base == NULL) {
  3785.                 ret = -ENOENT;
  3786.                 goto unlock;
  3787.         }
  3788.  
  3789.         if (obj->pin_filp != file) {
  3790.                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
  3791.                           args->handle);
  3792.                 ret = -EINVAL;
  3793.                 goto out;
  3794.         }
  3795.         obj->user_pin_count--;
  3796.         if (obj->user_pin_count == 0) {
  3797.                 obj->pin_filp = NULL;
  3798.                 i915_gem_object_ggtt_unpin(obj);
  3799.         }
  3800.  
  3801. out:
  3802.         drm_gem_object_unreference(&obj->base);
  3803. unlock:
  3804.         mutex_unlock(&dev->struct_mutex);
  3805.         return ret;
  3806. }
  3807.  
  3808. int
  3809. i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  3810.                     struct drm_file *file)
  3811. {
  3812.         struct drm_i915_gem_busy *args = data;
  3813.         struct drm_i915_gem_object *obj;
  3814.         int ret;
  3815.  
  3816.         ret = i915_mutex_lock_interruptible(dev);
  3817.         if (ret)
  3818.                 return ret;
  3819.  
  3820.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  3821.         if (&obj->base == NULL) {
  3822.                 ret = -ENOENT;
  3823.                 goto unlock;
  3824.         }
  3825.  
  3826.         /* Count all active objects as busy, even if they are currently not used
  3827.          * by the gpu. Users of this interface expect objects to eventually
  3828.          * become non-busy without any further actions, therefore emit any
  3829.          * necessary flushes here.
  3830.          */
  3831.         ret = i915_gem_object_flush_active(obj);
  3832.  
  3833.         args->busy = obj->active;
  3834.         if (obj->ring) {
  3835.                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
  3836.                 args->busy |= intel_ring_flag(obj->ring) << 16;
  3837.         }
  3838.  
  3839.         drm_gem_object_unreference(&obj->base);
  3840. unlock:
  3841.         mutex_unlock(&dev->struct_mutex);
  3842.         return ret;
  3843. }
  3844.  
  3845. int
  3846. i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  3847.                         struct drm_file *file_priv)
  3848. {
  3849.         return i915_gem_ring_throttle(dev, file_priv);
  3850. }
  3851.  
  3852. #if 0
  3853.  
  3854. int
  3855. i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  3856.                        struct drm_file *file_priv)
  3857. {
  3858.         struct drm_i915_gem_madvise *args = data;
  3859.         struct drm_i915_gem_object *obj;
  3860.         int ret;
  3861.  
  3862.         switch (args->madv) {
  3863.         case I915_MADV_DONTNEED:
  3864.         case I915_MADV_WILLNEED:
  3865.             break;
  3866.         default:
  3867.             return -EINVAL;
  3868.         }
  3869.  
  3870.         ret = i915_mutex_lock_interruptible(dev);
  3871.         if (ret)
  3872.                 return ret;
  3873.  
  3874.         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
  3875.         if (&obj->base == NULL) {
  3876.                 ret = -ENOENT;
  3877.                 goto unlock;
  3878.         }
  3879.  
  3880.         if (i915_gem_obj_is_pinned(obj)) {
  3881.                 ret = -EINVAL;
  3882.                 goto out;
  3883.         }
  3884.  
  3885.         if (obj->madv != __I915_MADV_PURGED)
  3886.                 obj->madv = args->madv;
  3887.  
  3888.         /* if the object is no longer attached, discard its backing storage */
  3889.         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
  3890.                 i915_gem_object_truncate(obj);
  3891.  
  3892.         args->retained = obj->madv != __I915_MADV_PURGED;
  3893.  
  3894. out:
  3895.         drm_gem_object_unreference(&obj->base);
  3896. unlock:
  3897.         mutex_unlock(&dev->struct_mutex);
  3898.         return ret;
  3899. }
  3900. #endif
  3901.  
  3902. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  3903.                           const struct drm_i915_gem_object_ops *ops)
  3904. {
  3905.         INIT_LIST_HEAD(&obj->global_list);
  3906.         INIT_LIST_HEAD(&obj->ring_list);
  3907.         INIT_LIST_HEAD(&obj->obj_exec_link);
  3908.         INIT_LIST_HEAD(&obj->vma_list);
  3909.  
  3910.         obj->ops = ops;
  3911.  
  3912.         obj->fence_reg = I915_FENCE_REG_NONE;
  3913.         obj->madv = I915_MADV_WILLNEED;
  3914.         /* Avoid an unnecessary call to unbind on the first bind. */
  3915.         obj->map_and_fenceable = true;
  3916.  
  3917.         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
  3918. }
  3919.  
  3920. static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
  3921.         .get_pages = i915_gem_object_get_pages_gtt,
  3922.         .put_pages = i915_gem_object_put_pages_gtt,
  3923. };
  3924.  
  3925. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  3926.                                                   size_t size)
  3927. {
  3928.         struct drm_i915_gem_object *obj;
  3929.         struct address_space *mapping;
  3930.         gfp_t mask;
  3931.  
  3932.         obj = i915_gem_object_alloc(dev);
  3933.         if (obj == NULL)
  3934.                 return NULL;
  3935.  
  3936.         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
  3937.                 i915_gem_object_free(obj);
  3938.                 return NULL;
  3939.         }
  3940.  
  3941.  
  3942.         i915_gem_object_init(obj, &i915_gem_object_ops);
  3943.  
  3944.         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
  3945.         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
  3946.  
  3947.         if (HAS_LLC(dev)) {
  3948.                 /* On some devices, we can have the GPU use the LLC (the CPU
  3949.                  * cache) for about a 10% performance improvement
  3950.                  * compared to uncached.  Graphics requests other than
  3951.                  * display scanout are coherent with the CPU in
  3952.                  * accessing this cache.  This means in this mode we
  3953.                  * don't need to clflush on the CPU side, and on the
  3954.                  * GPU side we only need to flush internal caches to
  3955.                  * get data visible to the CPU.
  3956.                  *
  3957.                  * However, we maintain the display planes as UC, and so
  3958.                  * need to rebind when first used as such.
  3959.                  */
  3960.                 obj->cache_level = I915_CACHE_LLC;
  3961.         } else
  3962.                 obj->cache_level = I915_CACHE_NONE;
  3963.  
  3964.         trace_i915_gem_object_create(obj);
  3965.  
  3966.         return obj;
  3967. }
  3968.  
  3969. void i915_gem_free_object(struct drm_gem_object *gem_obj)
  3970. {
  3971.         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
  3972.         struct drm_device *dev = obj->base.dev;
  3973.         struct drm_i915_private *dev_priv = dev->dev_private;
  3974.         struct i915_vma *vma, *next;
  3975.  
  3976.         intel_runtime_pm_get(dev_priv);
  3977.  
  3978.         trace_i915_gem_object_destroy(obj);
  3979.  
  3980.         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
  3981.                 int ret;
  3982.  
  3983.                 vma->pin_count = 0;
  3984.                 ret = i915_vma_unbind(vma);
  3985.                 if (WARN_ON(ret == -ERESTARTSYS)) {
  3986.                 bool was_interruptible;
  3987.  
  3988.                 was_interruptible = dev_priv->mm.interruptible;
  3989.                 dev_priv->mm.interruptible = false;
  3990.  
  3991.                         WARN_ON(i915_vma_unbind(vma));
  3992.  
  3993.                 dev_priv->mm.interruptible = was_interruptible;
  3994.         }
  3995.         }
  3996.  
  3997.         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
  3998.          * before progressing. */
  3999.         if (obj->stolen)
  4000.                 i915_gem_object_unpin_pages(obj);
  4001.  
  4002.         WARN_ON(obj->frontbuffer_bits);
  4003.  
  4004.         if (WARN_ON(obj->pages_pin_count))
  4005.         obj->pages_pin_count = 0;
  4006.         i915_gem_object_put_pages(obj);
  4007. //   i915_gem_object_free_mmap_offset(obj);
  4008.  
  4009.         BUG_ON(obj->pages);
  4010.  
  4011.  
  4012.     if(obj->base.filp != NULL)
  4013.     {
  4014. //        printf("filp %p\n", obj->base.filp);
  4015.         shmem_file_delete(obj->base.filp);
  4016.     }
  4017.  
  4018.         drm_gem_object_release(&obj->base);
  4019.         i915_gem_info_remove_obj(dev_priv, obj->base.size);
  4020.  
  4021.         kfree(obj->bit_17);
  4022.         i915_gem_object_free(obj);
  4023.  
  4024.         intel_runtime_pm_put(dev_priv);
  4025. }
  4026.  
  4027. struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
  4028.                                      struct i915_address_space *vm)
  4029. {
  4030.         struct i915_vma *vma;
  4031.         list_for_each_entry(vma, &obj->vma_list, vma_link)
  4032.                 if (vma->vm == vm)
  4033.                         return vma;
  4034.  
  4035.         return NULL;
  4036. }
  4037.  
  4038. void i915_gem_vma_destroy(struct i915_vma *vma)
  4039. {
  4040.         WARN_ON(vma->node.allocated);
  4041.  
  4042.         /* Keep the vma as a placeholder in the execbuffer reservation lists */
  4043.         if (!list_empty(&vma->exec_list))
  4044.                 return;
  4045.  
  4046.         list_del(&vma->vma_link);
  4047.  
  4048.         kfree(vma);
  4049. }
  4050.  
  4051. #if 0
  4052. int
  4053. i915_gem_suspend(struct drm_device *dev)
  4054. {
  4055.         struct drm_i915_private *dev_priv = dev->dev_private;
  4056.         int ret = 0;
  4057.  
  4058.         mutex_lock(&dev->struct_mutex);
  4059.         if (dev_priv->ums.mm_suspended)
  4060.                 goto err;
  4061.  
  4062.         ret = i915_gpu_idle(dev);
  4063.         if (ret)
  4064.                 goto err;
  4065.  
  4066.         i915_gem_retire_requests(dev);
  4067.  
  4068.         /* Under UMS, be paranoid and evict. */
  4069.         if (!drm_core_check_feature(dev, DRIVER_MODESET))
  4070.                 i915_gem_evict_everything(dev);
  4071.  
  4072.         i915_kernel_lost_context(dev);
  4073.         i915_gem_stop_ringbuffers(dev);
  4074.  
  4075.         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
  4076.          * We need to replace this with a semaphore, or something.
  4077.          * And not confound ums.mm_suspended!
  4078.          */
  4079.         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
  4080.                                                              DRIVER_MODESET);
  4081.         mutex_unlock(&dev->struct_mutex);
  4082.  
  4083.         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
  4084.         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
  4085.         flush_delayed_work(&dev_priv->mm.idle_work);
  4086.  
  4087.         return 0;
  4088.  
  4089. err:
  4090.         mutex_unlock(&dev->struct_mutex);
  4091.         return ret;
  4092. }
  4093. #endif
  4094.  
  4095. int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
  4096. {
  4097.         struct drm_device *dev = ring->dev;
  4098.         struct drm_i915_private *dev_priv = dev->dev_private;
  4099.         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
  4100.         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
  4101.         int i, ret;
  4102.  
  4103.         if (!HAS_L3_DPF(dev) || !remap_info)
  4104.                 return 0;
  4105.  
  4106.         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
  4107.         if (ret)
  4108.                 return ret;
  4109.  
  4110.         /*
  4111.          * Note: We do not worry about the concurrent register cacheline hang
  4112.          * here because no other code should access these registers other than
  4113.          * at initialization time.
  4114.          */
  4115.         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
  4116.                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  4117.                 intel_ring_emit(ring, reg_base + i);
  4118.                 intel_ring_emit(ring, remap_info[i/4]);
  4119.         }
  4120.  
  4121.         intel_ring_advance(ring);
  4122.  
  4123.         return ret;
  4124. }
  4125.  
  4126. void i915_gem_init_swizzling(struct drm_device *dev)
  4127. {
  4128.         struct drm_i915_private *dev_priv = dev->dev_private;
  4129.  
  4130.         if (INTEL_INFO(dev)->gen < 5 ||
  4131.             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
  4132.                 return;
  4133.  
  4134.         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  4135.                                  DISP_TILE_SURFACE_SWIZZLING);
  4136.  
  4137.         if (IS_GEN5(dev))
  4138.                 return;
  4139.  
  4140.         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
  4141.         if (IS_GEN6(dev))
  4142.                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
  4143.         else if (IS_GEN7(dev))
  4144.                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
  4145.         else if (IS_GEN8(dev))
  4146.                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
  4147.         else
  4148.                 BUG();
  4149. }
  4150.  
  4151. static bool
  4152. intel_enable_blt(struct drm_device *dev)
  4153. {
  4154.         if (!HAS_BLT(dev))
  4155.                 return false;
  4156.  
  4157.         /* The blitter was dysfunctional on early prototypes */
  4158.         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
  4159.                 DRM_INFO("BLT not supported on this pre-production hardware;"
  4160.                          " graphics performance will be degraded.\n");
  4161.                 return false;
  4162.         }
  4163.  
  4164.         return true;
  4165. }
  4166.  
  4167. static int i915_gem_init_rings(struct drm_device *dev)
  4168. {
  4169.         struct drm_i915_private *dev_priv = dev->dev_private;
  4170.         int ret;
  4171.  
  4172.         ret = intel_init_render_ring_buffer(dev);
  4173.         if (ret)
  4174.                 return ret;
  4175.  
  4176.     if (HAS_BSD(dev)) {
  4177.                 ret = intel_init_bsd_ring_buffer(dev);
  4178.                 if (ret)
  4179.                         goto cleanup_render_ring;
  4180.         }
  4181.  
  4182.         if (intel_enable_blt(dev)) {
  4183.                 ret = intel_init_blt_ring_buffer(dev);
  4184.                 if (ret)
  4185.                         goto cleanup_bsd_ring;
  4186.         }
  4187.  
  4188.         if (HAS_VEBOX(dev)) {
  4189.                 ret = intel_init_vebox_ring_buffer(dev);
  4190.                 if (ret)
  4191.                         goto cleanup_blt_ring;
  4192.         }
  4193.  
  4194.         if (HAS_BSD2(dev)) {
  4195.                 ret = intel_init_bsd2_ring_buffer(dev);
  4196.                 if (ret)
  4197.                         goto cleanup_vebox_ring;
  4198.         }
  4199.  
  4200.         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
  4201.         if (ret)
  4202.                 goto cleanup_bsd2_ring;
  4203.  
  4204.         return 0;
  4205.  
  4206. cleanup_bsd2_ring:
  4207.         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
  4208. cleanup_vebox_ring:
  4209.         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
  4210. cleanup_blt_ring:
  4211.         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
  4212. cleanup_bsd_ring:
  4213.         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
  4214. cleanup_render_ring:
  4215.         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
  4216.  
  4217.         return ret;
  4218. }
  4219.  
  4220. int
  4221. i915_gem_init_hw(struct drm_device *dev)
  4222. {
  4223.         struct drm_i915_private *dev_priv = dev->dev_private;
  4224.         int ret, i;
  4225.  
  4226.         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
  4227.                 return -EIO;
  4228.  
  4229.         if (dev_priv->ellc_size)
  4230.                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
  4231.  
  4232.         if (IS_HASWELL(dev))
  4233.                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
  4234.                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
  4235.  
  4236.         if (HAS_PCH_NOP(dev)) {
  4237.                 if (IS_IVYBRIDGE(dev)) {
  4238.                 u32 temp = I915_READ(GEN7_MSG_CTL);
  4239.                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
  4240.                 I915_WRITE(GEN7_MSG_CTL, temp);
  4241.                 } else if (INTEL_INFO(dev)->gen >= 7) {
  4242.                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
  4243.                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
  4244.                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
  4245.                 }
  4246.         }
  4247.  
  4248.         i915_gem_init_swizzling(dev);
  4249.  
  4250.         ret = i915_gem_init_rings(dev);
  4251.         if (ret)
  4252.                 return ret;
  4253.  
  4254.         for (i = 0; i < NUM_L3_SLICES(dev); i++)
  4255.                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
  4256.  
  4257.         /*
  4258.          * XXX: Contexts should only be initialized once. Doing a switch to the
  4259.          * default context switch however is something we'd like to do after
  4260.          * reset or thaw (the latter may not actually be necessary for HW, but
  4261.          * goes with our code better). Context switching requires rings (for
  4262.          * the do_switch), but before enabling PPGTT. So don't move this.
  4263.          */
  4264.         ret = i915_gem_context_enable(dev_priv);
  4265.         if (ret && ret != -EIO) {
  4266.                 DRM_ERROR("Context enable failed %d\n", ret);
  4267.                 i915_gem_cleanup_ringbuffer(dev);
  4268.         }
  4269.  
  4270.         return ret;
  4271. }
  4272.  
  4273. int i915_gem_init(struct drm_device *dev)
  4274. {
  4275.         struct drm_i915_private *dev_priv = dev->dev_private;
  4276.         int ret;
  4277.  
  4278.         mutex_lock(&dev->struct_mutex);
  4279.  
  4280.         if (IS_VALLEYVIEW(dev)) {
  4281.                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
  4282.                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
  4283.                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
  4284.                               VLV_GTLC_ALLOWWAKEACK), 10))
  4285.                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
  4286.         }
  4287.  
  4288.     i915_gem_init_global_gtt(dev);
  4289.  
  4290.         ret = i915_gem_context_init(dev);
  4291.         if (ret) {
  4292.                 mutex_unlock(&dev->struct_mutex);
  4293.                 return ret;
  4294.         }
  4295.  
  4296.         ret = i915_gem_init_hw(dev);
  4297.         if (ret == -EIO) {
  4298.                 /* Allow ring initialisation to fail by marking the GPU as
  4299.                  * wedged. But we only want to do this where the GPU is angry,
  4300.                  * for all other failure, such as an allocation failure, bail.
  4301.                  */
  4302.                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
  4303.                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
  4304.                 ret = 0;
  4305.         }
  4306.         mutex_unlock(&dev->struct_mutex);
  4307.  
  4308.                 return ret;
  4309. }
  4310.  
  4311. void
  4312. i915_gem_cleanup_ringbuffer(struct drm_device *dev)
  4313. {
  4314.         struct drm_i915_private *dev_priv = dev->dev_private;
  4315.         struct intel_engine_cs *ring;
  4316.         int i;
  4317.  
  4318.         for_each_ring(ring, dev_priv, i)
  4319.                 intel_cleanup_ring_buffer(ring);
  4320. }
  4321.  
  4322. #if 0
  4323.  
  4324. int
  4325. i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  4326.                        struct drm_file *file_priv)
  4327. {
  4328.         struct drm_i915_private *dev_priv = dev->dev_private;
  4329.         int ret;
  4330.  
  4331.         if (drm_core_check_feature(dev, DRIVER_MODESET))
  4332.                 return 0;
  4333.  
  4334.         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
  4335.                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
  4336.                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
  4337.         }
  4338.  
  4339.         mutex_lock(&dev->struct_mutex);
  4340.         dev_priv->ums.mm_suspended = 0;
  4341.  
  4342.         ret = i915_gem_init_hw(dev);
  4343.         if (ret != 0) {
  4344.                 mutex_unlock(&dev->struct_mutex);
  4345.                 return ret;
  4346.         }
  4347.  
  4348.         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
  4349.  
  4350.         ret = drm_irq_install(dev, dev->pdev->irq);
  4351.         if (ret)
  4352.                 goto cleanup_ringbuffer;
  4353.         mutex_unlock(&dev->struct_mutex);
  4354.  
  4355.         return 0;
  4356.  
  4357. cleanup_ringbuffer:
  4358.         i915_gem_cleanup_ringbuffer(dev);
  4359.         dev_priv->ums.mm_suspended = 1;
  4360.         mutex_unlock(&dev->struct_mutex);
  4361.  
  4362.         return ret;
  4363. }
  4364.  
  4365. int
  4366. i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  4367.                        struct drm_file *file_priv)
  4368. {
  4369.         if (drm_core_check_feature(dev, DRIVER_MODESET))
  4370.                 return 0;
  4371.  
  4372.         mutex_lock(&dev->struct_mutex);
  4373.         drm_irq_uninstall(dev);
  4374.         mutex_unlock(&dev->struct_mutex);
  4375.  
  4376.         return i915_gem_suspend(dev);
  4377. }
  4378.  
  4379. void
  4380. i915_gem_lastclose(struct drm_device *dev)
  4381. {
  4382.         int ret;
  4383.  
  4384.         if (drm_core_check_feature(dev, DRIVER_MODESET))
  4385.                 return;
  4386.  
  4387.         ret = i915_gem_suspend(dev);
  4388.         if (ret)
  4389.                 DRM_ERROR("failed to idle hardware: %d\n", ret);
  4390. }
  4391. #endif
  4392.  
  4393. static void
  4394. init_ring_lists(struct intel_engine_cs *ring)
  4395. {
  4396.     INIT_LIST_HEAD(&ring->active_list);
  4397.     INIT_LIST_HEAD(&ring->request_list);
  4398. }
  4399.  
  4400. void i915_init_vm(struct drm_i915_private *dev_priv,
  4401.                          struct i915_address_space *vm)
  4402. {
  4403.         if (!i915_is_ggtt(vm))
  4404.                 drm_mm_init(&vm->mm, vm->start, vm->total);
  4405.         vm->dev = dev_priv->dev;
  4406.         INIT_LIST_HEAD(&vm->active_list);
  4407.         INIT_LIST_HEAD(&vm->inactive_list);
  4408.         INIT_LIST_HEAD(&vm->global_link);
  4409.         list_add_tail(&vm->global_link, &dev_priv->vm_list);
  4410. }
  4411.  
  4412. void
  4413. i915_gem_load(struct drm_device *dev)
  4414. {
  4415.         struct drm_i915_private *dev_priv = dev->dev_private;
  4416.     int i;
  4417.  
  4418.         INIT_LIST_HEAD(&dev_priv->vm_list);
  4419.         i915_init_vm(dev_priv, &dev_priv->gtt.base);
  4420.  
  4421.         INIT_LIST_HEAD(&dev_priv->context_list);
  4422.         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
  4423.         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
  4424.     INIT_LIST_HEAD(&dev_priv->mm.fence_list);
  4425.     for (i = 0; i < I915_NUM_RINGS; i++)
  4426.         init_ring_lists(&dev_priv->ring[i]);
  4427.         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
  4428.         INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
  4429.         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
  4430.                           i915_gem_retire_work_handler);
  4431.         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
  4432.                           i915_gem_idle_work_handler);
  4433.         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
  4434.  
  4435.     /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
  4436.     if (IS_GEN3(dev)) {
  4437.                 I915_WRITE(MI_ARB_STATE,
  4438.                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
  4439.     }
  4440.  
  4441.     dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
  4442.  
  4443.         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
  4444.                 dev_priv->num_fence_regs = 32;
  4445.         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  4446.         dev_priv->num_fence_regs = 16;
  4447.     else
  4448.         dev_priv->num_fence_regs = 8;
  4449.  
  4450.     /* Initialize fence registers to zero */
  4451.         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
  4452.         i915_gem_restore_fences(dev);
  4453.  
  4454.     i915_gem_detect_bit_6_swizzle(dev);
  4455.  
  4456.     dev_priv->mm.interruptible = true;
  4457.  
  4458.         mutex_init(&dev_priv->fb_tracking.lock);
  4459. }
  4460.  
  4461. int i915_gem_open(struct drm_device *dev, struct drm_file *file)
  4462. {
  4463.         struct drm_i915_file_private *file_priv;
  4464.         int ret;
  4465.  
  4466.         DRM_DEBUG_DRIVER("\n");
  4467.  
  4468.         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
  4469.         if (!file_priv)
  4470.                 return -ENOMEM;
  4471.  
  4472.         file->driver_priv = file_priv;
  4473.         file_priv->dev_priv = dev->dev_private;
  4474.         file_priv->file = file;
  4475.  
  4476.         spin_lock_init(&file_priv->mm.lock);
  4477.         INIT_LIST_HEAD(&file_priv->mm.request_list);
  4478. //      INIT_DELAYED_WORK(&file_priv->mm.idle_work,
  4479. //                        i915_gem_file_idle_work_handler);
  4480.  
  4481.         ret = i915_gem_context_open(dev, file);
  4482.         if (ret)
  4483.                 kfree(file_priv);
  4484.  
  4485.         return ret;
  4486. }
  4487.  
  4488. void i915_gem_track_fb(struct drm_i915_gem_object *old,
  4489.                        struct drm_i915_gem_object *new,
  4490.                        unsigned frontbuffer_bits)
  4491. {
  4492.         if (old) {
  4493.                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
  4494.                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
  4495.                 old->frontbuffer_bits &= ~frontbuffer_bits;
  4496.         }
  4497.  
  4498.         if (new) {
  4499.                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
  4500.                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
  4501.                 new->frontbuffer_bits |= frontbuffer_bits;
  4502.         }
  4503. }
  4504.  
  4505. static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
  4506. {
  4507.         if (!mutex_is_locked(mutex))
  4508.                 return false;
  4509.  
  4510. #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
  4511.         return mutex->owner == task;
  4512. #else
  4513.         /* Since UP may be pre-empted, we cannot assume that we own the lock */
  4514.         return false;
  4515. #endif
  4516. }
  4517.  
  4518. /* All the new VM stuff */
  4519. unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
  4520.                                   struct i915_address_space *vm)
  4521. {
  4522.         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
  4523.         struct i915_vma *vma;
  4524.  
  4525.         if (!dev_priv->mm.aliasing_ppgtt ||
  4526.             vm == &dev_priv->mm.aliasing_ppgtt->base)
  4527.                 vm = &dev_priv->gtt.base;
  4528.  
  4529.         list_for_each_entry(vma, &o->vma_list, vma_link) {
  4530.                 if (vma->vm == vm)
  4531.                         return vma->node.start;
  4532.  
  4533.         }
  4534.         WARN(1, "%s vma for this object not found.\n",
  4535.              i915_is_ggtt(vm) ? "global" : "ppgtt");
  4536.         return -1;
  4537. }
  4538.  
  4539. bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
  4540.                         struct i915_address_space *vm)
  4541. {
  4542.         struct i915_vma *vma;
  4543.  
  4544.         list_for_each_entry(vma, &o->vma_list, vma_link)
  4545.                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
  4546.                         return true;
  4547.  
  4548.         return false;
  4549. }
  4550.  
  4551. bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
  4552. {
  4553.         struct i915_vma *vma;
  4554.  
  4555.         list_for_each_entry(vma, &o->vma_list, vma_link)
  4556.                 if (drm_mm_node_allocated(&vma->node))
  4557.                         return true;
  4558.  
  4559.         return false;
  4560. }
  4561.  
  4562. unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
  4563.                                 struct i915_address_space *vm)
  4564. {
  4565.         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
  4566.         struct i915_vma *vma;
  4567.  
  4568.         if (!dev_priv->mm.aliasing_ppgtt ||
  4569.             vm == &dev_priv->mm.aliasing_ppgtt->base)
  4570.                 vm = &dev_priv->gtt.base;
  4571.  
  4572.         BUG_ON(list_empty(&o->vma_list));
  4573.  
  4574.         list_for_each_entry(vma, &o->vma_list, vma_link)
  4575.                 if (vma->vm == vm)
  4576.                         return vma->node.size;
  4577.  
  4578.         return 0;
  4579. }
  4580.  
  4581.  
  4582.  
  4583. struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
  4584. {
  4585.         struct i915_vma *vma;
  4586.  
  4587.         /* This WARN has probably outlived its usefulness (callers already
  4588.          * WARN if they don't find the GGTT vma they expect). When removing,
  4589.          * remember to remove the pre-check in is_pin_display() as well */
  4590.         if (WARN_ON(list_empty(&obj->vma_list)))
  4591.                 return NULL;
  4592.  
  4593.         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
  4594.         if (vma->vm != obj_to_ggtt(obj))
  4595.                 return NULL;
  4596.  
  4597.         return vma;
  4598. }
  4599.