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static inline const char *yesno(bool v)

        return v ? "yes" : "no";

 

static inline const char *onoff(bool v)

        return v ? "on" : "off";

 

enum pipe {

        INVALID_PIPE = -1,

        PIPE_A = 0,

        PIPE_B,

        PIPE_C,

        _PIPE_EDP,

        I915_MAX_PIPES = _PIPE_EDP

 

enum transcoder {

        TRANSCODER_A = 0,

        TRANSCODER_B,

        TRANSCODER_C,

        TRANSCODER_EDP,

        I915_MAX_TRANSCODERS

 

enum plane {

        PLANE_A = 0,

        PLANE_B,

        PLANE_C,

        PLANE_CURSOR,

        I915_MAX_PLANES,

 

 

enum port {

        PORT_A = 0,

        PORT_B,

        PORT_C,

        PORT_D,

        PORT_E,

        I915_MAX_PORTS

 

 

enum dpio_channel {

        DPIO_CH0,

        DPIO_CH1

 

enum dpio_phy {

        DPIO_PHY0,

        DPIO_PHY1

 

enum intel_display_power_domain {

        POWER_DOMAIN_PIPE_A,

        POWER_DOMAIN_PIPE_B,

        POWER_DOMAIN_PIPE_C,

        POWER_DOMAIN_PIPE_A_PANEL_FITTER,

        POWER_DOMAIN_PIPE_B_PANEL_FITTER,

        POWER_DOMAIN_PIPE_C_PANEL_FITTER,

        POWER_DOMAIN_TRANSCODER_A,

        POWER_DOMAIN_TRANSCODER_B,

        POWER_DOMAIN_TRANSCODER_C,

        POWER_DOMAIN_TRANSCODER_EDP,

        POWER_DOMAIN_PORT_DDI_A_LANES,

        POWER_DOMAIN_PORT_DDI_B_LANES,

        POWER_DOMAIN_PORT_DDI_C_LANES,

        POWER_DOMAIN_PORT_DDI_D_LANES,

        POWER_DOMAIN_PORT_DDI_E_LANES,

        POWER_DOMAIN_PORT_DSI,

        POWER_DOMAIN_PORT_CRT,

        POWER_DOMAIN_PORT_OTHER,

        POWER_DOMAIN_VGA,

        POWER_DOMAIN_AUDIO,

        POWER_DOMAIN_PLLS,

        POWER_DOMAIN_AUX_A,

        POWER_DOMAIN_AUX_B,

        POWER_DOMAIN_AUX_C,

        POWER_DOMAIN_AUX_D,

        POWER_DOMAIN_GMBUS,

        POWER_DOMAIN_MODESET,

        POWER_DOMAIN_INIT,

 

        POWER_DOMAIN_NUM,

 

 

enum hpd_pin {

        HPD_NONE = 0,

        HPD_TV = HPD_NONE,     /* TV is known to be unreliable */

        HPD_CRT,

        HPD_SDVO_B,

        HPD_SDVO_C,

        HPD_PORT_A,

        HPD_PORT_B,

        HPD_PORT_C,

        HPD_PORT_D,

        HPD_PORT_E,

        HPD_NUM_PINS

 

 

struct i915_hotplug {

        struct work_struct hotplug_work;

 

        struct {

                unsigned long last_jiffies;

                int count;

                enum {

                        HPD_ENABLED = 0,

                        HPD_DISABLED = 1,

                        HPD_MARK_DISABLED = 2

                } state;

        } stats[HPD_NUM_PINS];

        u32 event_bits;

        struct delayed_work reenable_work;

 

        struct intel_digital_port *irq_port[I915_MAX_PORTS];

        u32 long_port_mask;

        u32 short_port_mask;

        struct work_struct dig_port_work;

 

        /*

        struct workqueue_struct *dp_wq;

 

 

 

 

 

 

 

 

 

 

 

 

struct drm_i915_private;

struct i915_mm_struct;

struct i915_mmu_object;

 

struct drm_i915_file_private {

        struct drm_i915_private *dev_priv;

        struct drm_file *file;

 

        struct {

                spinlock_t lock;

                struct list_head request_list;

        } mm;

        struct idr context_idr;

 

        struct intel_rps_client {

                struct list_head link;

                unsigned boosts;

        } rps;

 

        unsigned int bsd_ring;

 

enum intel_dpll_id {

        DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */

        /* real shared dpll ids must be >= 0 */

        DPLL_ID_PCH_PLL_A = 0,

        DPLL_ID_PCH_PLL_B = 1,

        /* hsw/bdw */

        DPLL_ID_WRPLL1 = 0,

        DPLL_ID_WRPLL2 = 1,

        DPLL_ID_SPLL = 2,

 

        /* skl */

        DPLL_ID_SKL_DPLL1 = 0,

        DPLL_ID_SKL_DPLL2 = 1,

        DPLL_ID_SKL_DPLL3 = 2,

 

struct intel_dpll_hw_state {

        /* i9xx, pch plls */

        uint32_t dpll;

        uint32_t dpll_md;

        uint32_t fp0;

        uint32_t fp1;

 

        /* hsw, bdw */

        uint32_t wrpll;

        uint32_t spll;

 

        /* skl */

        /*

        uint32_t ctrl1;

        /* HDMI only, 0 when used for DP */

        uint32_t cfgcr1, cfgcr2;

 

        /* bxt */

        uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,

                 pcsdw12;

 

struct intel_shared_dpll_config {

        unsigned crtc_mask; /* mask of CRTCs sharing this PLL */

        struct intel_dpll_hw_state hw_state;

 

struct intel_shared_dpll {

        struct intel_shared_dpll_config config;

 

        int active; /* count of number of active CRTCs (i.e. DPMS on) */

        bool on; /* is the PLL actually active? Disabled during modeset */

        const char *name;

        /* should match the index in the dev_priv->shared_dplls array */

        enum intel_dpll_id id;

        /* The mode_set hook is optional and should be used together with the

        void (*mode_set)(struct drm_i915_private *dev_priv,

                         struct intel_shared_dpll *pll);

        void (*enable)(struct drm_i915_private *dev_priv,

                       struct intel_shared_dpll *pll);

        void (*disable)(struct drm_i915_private *dev_priv,

                        struct intel_shared_dpll *pll);

        bool (*get_hw_state)(struct drm_i915_private *dev_priv,

                             struct intel_shared_dpll *pll,

                             struct intel_dpll_hw_state *hw_state);

 

 

struct intel_link_m_n {

        uint32_t        tu;

        uint32_t        gmch_m;

        uint32_t        gmch_n;

        uint32_t        link_m;

        uint32_t        link_n;

 

void intel_link_compute_m_n(int bpp, int nlanes,

                            int pixel_clock, int link_clock,

                            struct intel_link_m_n *m_n);

 

 

 

struct opregion_header;

struct opregion_acpi;

struct opregion_swsci;

struct opregion_asle;

 

struct intel_opregion {

        struct opregion_header *header;

        struct opregion_acpi *acpi;

        struct opregion_swsci *swsci;

        u32 swsci_gbda_sub_functions;

        u32 swsci_sbcb_sub_functions;

        struct opregion_asle *asle;

        void *rvda;

        const void *vbt;

        u32 vbt_size;

        u32 *lid_state;

        struct work_struct asle_work;

 

struct intel_overlay;

struct intel_overlay_error_state;

 

 

struct drm_i915_fence_reg {

        struct list_head lru_list;

        struct drm_i915_gem_object *obj;

        int pin_count;

 

struct sdvo_device_mapping {

        u8 initialized;

        u8 dvo_port;

        u8 slave_addr;

        u8 dvo_wiring;

        u8 i2c_pin;

        u8 ddc_pin;

 

struct intel_display_error_state;

 

struct drm_i915_error_state {

        struct kref ref;

        struct timeval time;

 

        char error_msg[128];

        int iommu;

        u32 reset_count;

        u32 suspend_count;

 

        /* Generic register state */

        u32 eir;

        u32 pgtbl_er;

        u32 ier;

        u32 gtier[4];

        u32 ccid;

        u32 derrmr;

        u32 forcewake;

        u32 error; /* gen6+ */

        u32 err_int; /* gen7 */

        u32 fault_data0; /* gen8, gen9 */

        u32 fault_data1; /* gen8, gen9 */

        u32 done_reg;

        u32 gac_eco;

        u32 gam_ecochk;

        u32 gab_ctl;

        u32 gfx_mode;

        u32 extra_instdone[I915_NUM_INSTDONE_REG];

        u64 fence[I915_MAX_NUM_FENCES];

        struct intel_overlay_error_state *overlay;

        struct intel_display_error_state *display;

        struct drm_i915_error_object *semaphore_obj;

 

        struct drm_i915_error_ring {

                bool valid;

                /* Software tracked state */

                bool waiting;

                int hangcheck_score;

                enum intel_ring_hangcheck_action hangcheck_action;

                int num_requests;

 

                /* our own tracking of ring head and tail */

                u32 cpu_ring_head;

                u32 cpu_ring_tail;

 

                u32 semaphore_seqno[I915_NUM_RINGS - 1];

 

                /* Register state */

                u32 start;

                u32 tail;

                u32 head;

                u32 ctl;

                u32 hws;

                u32 ipeir;

                u32 ipehr;

                u32 instdone;

                u32 bbstate;

                u32 instpm;

                u32 instps;

                u32 seqno;

                u64 bbaddr;

                u64 acthd;

                u32 fault_reg;

                u64 faddr;

                u32 rc_psmi; /* sleep state */

                u32 semaphore_mboxes[I915_NUM_RINGS - 1];

 

                struct drm_i915_error_object {

                        int page_count;

                        u64 gtt_offset;

                        u32 *pages[0];

                } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

 

                struct drm_i915_error_request {

                        long jiffies;

                        u32 seqno;

                        u32 tail;

                } *requests;

 

                struct {

                        u32 gfx_mode;

                        union {

                                u64 pdp[4];

                                u32 pp_dir_base;

                        };

                } vm_info;

 

                pid_t pid;

                char comm[TASK_COMM_LEN];

        } ring[I915_NUM_RINGS];

 

        struct drm_i915_error_buffer {

                u32 size;

                u32 name;

                u32 rseqno[I915_NUM_RINGS], wseqno;

                u64 gtt_offset;

                u32 read_domains;

                u32 write_domain;

                s32 fence_reg:I915_MAX_NUM_FENCE_BITS;

                s32 pinned:2;

                u32 tiling:2;

                u32 dirty:1;

                u32 purgeable:1;

                u32 userptr:1;

                s32 ring:4;

                u32 cache_level:3;

        } **active_bo, **pinned_bo;

 

        u32 *active_bo_count, *pinned_bo_count;

        u32 vm_count;

 

struct intel_connector;

struct intel_encoder;

struct intel_crtc_state;

struct intel_initial_plane_config;

struct intel_crtc;

struct intel_limit;

struct dpll;

 

struct drm_i915_display_funcs {

        int (*get_display_clock_speed)(struct drm_device *dev);

        int (*get_fifo_size)(struct drm_device *dev, int plane);

        /**

        bool (*find_dpll)(const struct intel_limit *limit,

                          struct intel_crtc_state *crtc_state,

                          int target, int refclk,

                          struct dpll *match_clock,

                          struct dpll *best_clock);

        int (*compute_pipe_wm)(struct intel_crtc *crtc,

                               struct drm_atomic_state *state);

        void (*program_watermarks)(struct intel_crtc_state *cstate);

        void (*update_wm)(struct drm_crtc *crtc);

        int (*modeset_calc_cdclk)(struct drm_atomic_state *state);

        void (*modeset_commit_cdclk)(struct drm_atomic_state *state);

        /* Returns the active state of the crtc, and if the crtc is active,

        bool (*get_pipe_config)(struct intel_crtc *,

                                struct intel_crtc_state *);

        void (*get_initial_plane_config)(struct intel_crtc *,

                                         struct intel_initial_plane_config *);

        int (*crtc_compute_clock)(struct intel_crtc *crtc,

                                  struct intel_crtc_state *crtc_state);

        void (*crtc_enable)(struct drm_crtc *crtc);

        void (*crtc_disable)(struct drm_crtc *crtc);

        void (*audio_codec_enable)(struct drm_connector *connector,

                                   struct intel_encoder *encoder,

                                   const struct drm_display_mode *adjusted_mode);

        void (*audio_codec_disable)(struct intel_encoder *encoder);

        void (*fdi_link_train)(struct drm_crtc *crtc);

        void (*init_clock_gating)(struct drm_device *dev);

        int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,

                          struct drm_framebuffer *fb,

                          struct drm_i915_gem_object *obj,

                          struct drm_i915_gem_request *req,

                          uint32_t flags);

        void (*hpd_irq_setup)(struct drm_device *dev);

        /* clock updates for mode set */

        /* cursor updates */

        /* render clock increase/decrease */

        /* display clock increase/decrease */

        /* pll clock increase/decrease */

 

enum forcewake_domain_id {

        FW_DOMAIN_ID_RENDER = 0,

        FW_DOMAIN_ID_BLITTER,

        FW_DOMAIN_ID_MEDIA,

 

        FW_DOMAIN_ID_COUNT

 

enum forcewake_domains {

        FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),

        FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),

        FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),

        FORCEWAKE_ALL = (FORCEWAKE_RENDER |

                         FORCEWAKE_BLITTER |

                         FORCEWAKE_MEDIA)

 

struct intel_uncore_funcs {

        void (*force_wake_get)(struct drm_i915_private *dev_priv,

                                                        enum forcewake_domains domains);

        void (*force_wake_put)(struct drm_i915_private *dev_priv,

                                                        enum forcewake_domains domains);

 

        uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);

        uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);

        uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);

        uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);

 

        void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,

                                uint8_t val, bool trace);

        void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,

                                uint16_t val, bool trace);

        void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,

                                uint32_t val, bool trace);

        void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,

                                uint64_t val, bool trace);

 

struct intel_uncore {

        spinlock_t lock; /** lock is also taken in irq contexts. */

 

        struct intel_uncore_funcs funcs;

 

        unsigned fifo_count;

        enum forcewake_domains fw_domains;

 

        struct intel_uncore_forcewake_domain {

                struct drm_i915_private *i915;

                enum forcewake_domain_id id;

                unsigned wake_count;

                struct timer_list timer;

                i915_reg_t reg_set;

                u32 val_set;

                u32 val_clear;

                i915_reg_t reg_ack;

                i915_reg_t reg_post;

                u32 val_reset;

        } fw_domain[FW_DOMAIN_ID_COUNT];

 

        int unclaimed_mmio_check;

 

 

 

 

struct intel_csr {

        struct work_struct work;

        const char *fw_path;

        uint32_t *dmc_payload;

        uint32_t dmc_fw_size;

        uint32_t version;

        uint32_t mmio_count;

        i915_reg_t mmioaddr[8];

        uint32_t mmiodata[8];

        uint32_t dc_state;

 

 

 

struct intel_device_info {

        u32 display_mmio_offset;

        u16 device_id;

        u8 num_pipes:3;

        u8 num_sprites[I915_MAX_PIPES];

        u8 gen;

        u8 ring_mask; /* Rings supported by the HW */

        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);

        /* Register offsets for the various display pipes and transcoders */

        int pipe_offsets[I915_MAX_TRANSCODERS];

        int trans_offsets[I915_MAX_TRANSCODERS];

        int palette_offsets[I915_MAX_PIPES];

        int cursor_offsets[I915_MAX_PIPES];

 

        /* Slice/subslice/EU info */

        u8 slice_total;

        u8 subslice_total;

        u8 subslice_per_slice;

        u8 eu_total;

        u8 eu_per_subslice;

        /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */

        u8 subslice_7eu[3];

        u8 has_slice_pg:1;

        u8 has_subslice_pg:1;

        u8 has_eu_pg:1;

 

 

enum i915_cache_level {

        I915_CACHE_NONE = 0,

        I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */

        I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc

        I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */

 

struct i915_ctx_hang_stats {

        /* This context had batch pending when hang was declared */

        unsigned batch_pending;

 

        /* This context had batch active when hang was declared */

        unsigned batch_active;

 

        /* Time when this context was last blamed for a GPU reset */

        unsigned long guilty_ts;

 

        /* If the contexts causes a second GPU hang within this time,

        unsigned long ban_period_seconds;

 

        /* This context is banned to submit more work */

        bool banned;

 

 

struct intel_context {

        struct kref ref;

        int user_handle;

        uint8_t remap_slice;

        struct drm_i915_private *i915;

        int flags;

        struct drm_i915_file_private *file_priv;

        struct i915_ctx_hang_stats hang_stats;

        struct i915_hw_ppgtt *ppgtt;

 

        /* Legacy ring buffer submission */

        struct {

                struct drm_i915_gem_object *rcs_state;

                bool initialized;

        } legacy_hw_ctx;

 

        /* Execlists */

        struct {

                struct drm_i915_gem_object *state;

                struct intel_ringbuffer *ringbuf;

                int pin_count;

                struct i915_vma *lrc_vma;

                u64 lrc_desc;

                uint32_t *lrc_reg_state;

        } engine[I915_NUM_RINGS];

 

        struct list_head link;

 

enum fb_op_origin {

        ORIGIN_GTT,

        ORIGIN_CPU,

        ORIGIN_CS,

        ORIGIN_FLIP,

        ORIGIN_DIRTYFB,

 

struct intel_fbc {

        /* This is always the inner lock when overlapping with struct_mutex and

        struct mutex lock;

        unsigned threshold;

        unsigned int possible_framebuffer_bits;

        unsigned int busy_bits;

        unsigned int visible_pipes_mask;

        struct intel_crtc *crtc;

 

        struct drm_mm_node compressed_fb;

        struct drm_mm_node *compressed_llb;

 

        bool false_color;

 

        bool enabled;

        bool active;

 

        struct intel_fbc_state_cache {

                struct {

                        unsigned int mode_flags;

                        uint32_t hsw_bdw_pixel_rate;

                } crtc;

 

                struct {

                        unsigned int rotation;

                        int src_w;

                        int src_h;

                        bool visible;

                } plane;

 

                struct {

                        u64 ilk_ggtt_offset;

                        uint32_t pixel_format;

                        unsigned int stride;

                        int fence_reg;

                        unsigned int tiling_mode;

                } fb;

        } state_cache;

 

        struct intel_fbc_reg_params {

                struct {

                        enum pipe pipe;

                        enum plane plane;

                        unsigned int fence_y_offset;

                } crtc;

 

                struct {

                        u64 ggtt_offset;

                        uint32_t pixel_format;

                        unsigned int stride;

                        int fence_reg;

                } fb;

 

                int cfb_size;

        } params;

 

        struct intel_fbc_work {

                bool scheduled;

                u32 scheduled_vblank;

                struct work_struct work;

        } work;

 

        const char *no_fbc_reason;

 

enum drrs_refresh_rate_type {

        DRRS_HIGH_RR,

        DRRS_LOW_RR,

        DRRS_MAX_RR, /* RR count */

 

enum drrs_support_type {

        DRRS_NOT_SUPPORTED = 0,

        STATIC_DRRS_SUPPORT = 1,

        SEAMLESS_DRRS_SUPPORT = 2

 

struct intel_dp;

struct i915_drrs {

        struct mutex mutex;

        struct delayed_work work;

        struct intel_dp *dp;

        unsigned busy_frontbuffer_bits;

        enum drrs_refresh_rate_type refresh_rate_type;

        enum drrs_support_type type;

 

struct i915_psr {

        struct mutex lock;

        bool sink_support;

        bool source_ok;

        struct intel_dp *enabled;

        bool active;

        struct delayed_work work;

        unsigned busy_frontbuffer_bits;

        bool psr2_support;

        bool aux_frame_sync;

        bool link_standby;

 

enum intel_pch {

        PCH_NONE = 0,   /* No PCH present */

        PCH_IBX,        /* Ibexpeak PCH */

        PCH_CPT,        /* Cougarpoint PCH */

        PCH_LPT,        /* Lynxpoint PCH */

        PCH_SPT,        /* Sunrisepoint PCH */

        PCH_NOP,

 

enum intel_sbi_destination {

        SBI_ICLK,

        SBI_MPHY,

 

 

struct intel_fbdev;

struct intel_fbc_work;

 

struct intel_gmbus {

        struct i2c_adapter adapter;

        u32 force_bit;

        u32 reg0;

        i915_reg_t gpio_reg;

        struct i2c_algo_bit_data bit_algo;

        struct drm_i915_private *dev_priv;

 

struct i915_suspend_saved_registers {

        u32 saveDSPARB;

        u32 saveLVDS;

        u32 savePP_ON_DELAYS;

        u32 savePP_OFF_DELAYS;

        u32 savePP_ON;

        u32 savePP_OFF;

        u32 savePP_CONTROL;

        u32 savePP_DIVISOR;

        u32 saveFBC_CONTROL;

        u32 saveCACHE_MODE_0;

        u32 saveMI_ARB_STATE;

        u32 saveSWF0[16];

        u32 saveSWF1[16];

        u32 saveSWF3[3];

        uint64_t saveFENCE[I915_MAX_NUM_FENCES];

        u32 savePCH_PORT_HOTPLUG;

        u16 saveGCDGMBUS;

 

struct vlv_s0ix_state {

        /* GAM */

        u32 wr_watermark;

        u32 gfx_prio_ctrl;

        u32 arb_mode;

        u32 gfx_pend_tlb0;

        u32 gfx_pend_tlb1;

        u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];

        u32 media_max_req_count;

        u32 gfx_max_req_count;

        u32 render_hwsp;

        u32 ecochk;

        u32 bsd_hwsp;

        u32 blt_hwsp;

        u32 tlb_rd_addr;

 

        /* MBC */

        u32 g3dctl;

        u32 gsckgctl;

        u32 mbctl;

 

        /* GCP */

        u32 ucgctl1;

        u32 ucgctl3;

        u32 rcgctl1;

        u32 rcgctl2;

        u32 rstctl;

        u32 misccpctl;

 

        /* GPM */

        u32 gfxpause;

        u32 rpdeuhwtc;

        u32 rpdeuc;

        u32 ecobus;

        u32 pwrdwnupctl;

        u32 rp_down_timeout;

        u32 rp_deucsw;

        u32 rcubmabdtmr;

        u32 rcedata;

        u32 spare2gh;

 

        /* Display 1 CZ domain */

        u32 gt_imr;

        u32 gt_ier;

        u32 pm_imr;

        u32 pm_ier;

        u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

 

        /* GT SA CZ domain */

        u32 tilectl;

        u32 gt_fifoctl;

        u32 gtlc_wake_ctrl;

        u32 gtlc_survive;

        u32 pmwgicz;

 

        /* Display 2 CZ domain */

        u32 gu_ctl0;

        u32 gu_ctl1;

        u32 pcbr;

        u32 clock_gate_dis2;

 

struct intel_rps_ei {

        u32 cz_clock;

        u32 render_c0;

        u32 media_c0;

 

struct intel_gen6_power_mgmt {

        /*

        struct work_struct work;

        bool interrupts_enabled;

        u32 pm_iir;

 

        /* Frequencies are stored in potentially platform dependent multiples.

        u8 cur_freq;            /* Current frequency (cached, may not == HW) */

        u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */

        u8 max_freq_softlimit;  /* Max frequency permitted by the driver */

        u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */

        u8 min_freq;            /* AKA RPn. Minimum frequency */

        u8 idle_freq;           /* Frequency to request when we are idle */

        u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */

        u8 rp1_freq;            /* "less than" RP0 power/freqency */

        u8 rp0_freq;            /* Non-overclocked max frequency. */

 

        u8 up_threshold; /* Current %busy required to uplock */

        u8 down_threshold; /* Current %busy required to downclock */

 

        int last_adj;

        enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

 

        spinlock_t client_lock;

        struct list_head clients;

        bool client_boost;

 

        bool enabled;

        struct delayed_work delayed_resume_work;

        unsigned boosts;

 

        struct intel_rps_client semaphores, mmioflips;

 

        /* manual wa residency calculations */

        struct intel_rps_ei up_ei, down_ei;

 

        /*

        struct mutex hw_lock;

 

extern spinlock_t mchdev_lock;

 

struct intel_ilk_power_mgmt {

        u8 cur_delay;

        u8 min_delay;

        u8 max_delay;

        u8 fmax;

        u8 fstart;

 

        u64 last_count1;

        unsigned long last_time1;

        unsigned long chipset_power;

        u64 last_count2;

        u64 last_time2;

        unsigned long gfx_power;

        u8 corr;

 

        int c_m;

        int r_t;

 

struct drm_i915_private;

struct i915_power_well;

 

struct i915_power_well_ops {

        /*

        void (*sync_hw)(struct drm_i915_private *dev_priv,

                        struct i915_power_well *power_well);

        /*

        void (*enable)(struct drm_i915_private *dev_priv,

                       struct i915_power_well *power_well);

        /*

        void (*disable)(struct drm_i915_private *dev_priv,

                        struct i915_power_well *power_well);

        /* Returns the hw enabled state. */

        bool (*is_enabled)(struct drm_i915_private *dev_priv,

                           struct i915_power_well *power_well);

 

struct i915_power_well {

        const char *name;

        bool always_on;

        /* power well enable/disable usage count */

        int count;

        /* cached hw enabled state */

        bool hw_enabled;

        unsigned long domains;

        unsigned long data;

        const struct i915_power_well_ops *ops;

 

struct i915_power_domains {

        /*

        bool init_power_on;

        bool initializing;

        int power_well_count;

 

        struct mutex lock;

        int domain_use_count[POWER_DOMAIN_NUM];

        struct i915_power_well *power_wells;

 

struct intel_l3_parity {

        u32 *remap_info[MAX_L3_SLICES];

        struct work_struct error_work;

        int which_slice;

 

struct i915_gem_mm {

        /** Memory allocator for GTT stolen memory */

        struct drm_mm stolen;

        /** Protects the usage of the GTT stolen memory allocator. This is

        struct mutex stolen_lock;

 

        /** List of all objects in gtt_space. Used to restore gtt

        struct list_head bound_list;

        /**

        struct list_head unbound_list;

 

        /** Usable portion of the GTT for GEM */

        unsigned long stolen_base; /* limited to low memory (32-bit) */

 

        /** PPGTT used for aliasing the PPGTT with the GTT */

        struct i915_hw_ppgtt *aliasing_ppgtt;

 

        struct notifier_block oom_notifier;

        /** LRU list of objects with fence regs on them. */

        struct list_head fence_list;

 

        /**

        struct delayed_work retire_work;

 

        /**

        struct delayed_work idle_work;

 

        /**

        bool interruptible;

 

        /**

        bool busy;

 

        /* the indicator for dispatch video commands on two BSD rings */

        unsigned int bsd_ring_dispatch_index;

 

        /** Bit 6 swizzling required for X tiling */

        uint32_t bit_6_swizzle_x;

        /** Bit 6 swizzling required for Y tiling */

        uint32_t bit_6_swizzle_y;

 

        /* accounting, useful for userland debugging */

        spinlock_t object_stat_lock;

        size_t object_memory;

        u32 object_count;

 

struct drm_i915_error_state_buf {

        struct drm_i915_private *i915;

        unsigned bytes;

        unsigned size;

        int err;

        u8 *buf;

        loff_t start;

        loff_t pos;

 

struct i915_error_state_file_priv {

        struct drm_device *dev;

        struct drm_i915_error_state *error;

 

struct i915_gpu_error {

        /* For hangcheck timer */

        /* Hang gpu twice in this window and your context gets banned */

 

        struct workqueue_struct *hangcheck_wq;

        struct delayed_work hangcheck_work;

 

        /* For reset and error_state handling. */

        spinlock_t lock;

        /* Protected by the above dev->gpu_error.lock. */

        struct drm_i915_error_state *first_error;

 

        unsigned long missed_irq_rings;

 

        /**

        atomic_t reset_counter;

 

 

        /**

        wait_queue_head_t reset_queue;

 

        /* Userspace knobs for gpu hang simulation;

        u32 stop_rings;

 

        /* For missed irq/seqno simulation. */

        unsigned int test_irq_rings;

 

        /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */

        bool reload_in_reset;

 

enum modeset_restore {

        MODESET_ON_LID_OPEN,

        MODESET_DONE,

        MODESET_SUSPENDED,

 

 

 

struct ddi_vbt_port_info {

        /*

        uint8_t hdmi_level_shift;

 

        uint8_t supports_dvi:1;

        uint8_t supports_hdmi:1;

        uint8_t supports_dp:1;

 

        uint8_t alternate_aux_channel;

        uint8_t alternate_ddc_pin;

 

        uint8_t dp_boost_level;

        uint8_t hdmi_boost_level;

 

enum psr_lines_to_wait {

        PSR_0_LINES_TO_WAIT = 0,

        PSR_1_LINE_TO_WAIT,

        PSR_4_LINES_TO_WAIT,

        PSR_8_LINES_TO_WAIT

 

struct intel_vbt_data {

        struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */

        struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

 

        /* Feature bits */

        unsigned int int_tv_support:1;

        unsigned int lvds_dither:1;

        unsigned int lvds_vbt:1;

        unsigned int int_crt_support:1;

        unsigned int lvds_use_ssc:1;

        unsigned int display_clock_mode:1;

        unsigned int fdi_rx_polarity_inverted:1;

        unsigned int has_mipi:1;

        int lvds_ssc_freq;

        unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

 

        enum drrs_support_type drrs_type;

 

        /* eDP */

        int edp_rate;

        int edp_lanes;

        int edp_preemphasis;

        int edp_vswing;

        bool edp_initialized;

        bool edp_support;

        int edp_bpp;

        struct edp_power_seq edp_pps;

 

        struct {

                bool full_link;

                bool require_aux_wakeup;

                int idle_frames;

                enum psr_lines_to_wait lines_to_wait;

                int tp1_wakeup_time;

                int tp2_tp3_wakeup_time;

        } psr;

 

        struct {

                u16 pwm_freq_hz;

                bool present;

                bool active_low_pwm;

                u8 min_brightness;      /* min_brightness/255 of max */

        } backlight;

 

        /* MIPI DSI */

        struct {

                u16 port;

                u16 panel_id;

                struct mipi_config *config;

                struct mipi_pps_data *pps;

                u8 seq_version;

                u32 size;

                u8 *data;

                const u8 *sequence[MIPI_SEQ_MAX];

        } dsi;

 

        int crt_ddc_pin;

 

        int child_dev_num;

        union child_device_config *child_dev;

 

        struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];

 

enum intel_ddb_partitioning {

        INTEL_DDB_PART_1_2,

        INTEL_DDB_PART_5_6, /* IVB+ */

 

struct intel_wm_level {

        bool enable;

        uint32_t pri_val;

        uint32_t spr_val;

        uint32_t cur_val;

        uint32_t fbc_val;

 

struct ilk_wm_values {

        uint32_t wm_pipe[3];

        uint32_t wm_lp[3];

        uint32_t wm_lp_spr[3];

        uint32_t wm_linetime[3];

        bool enable_fbc_wm;

        enum intel_ddb_partitioning partitioning;

 

struct vlv_pipe_wm {

        uint16_t primary;

        uint16_t sprite[2];

        uint8_t cursor;

 

struct vlv_sr_wm {

        uint16_t plane;

        uint8_t cursor;

 

struct vlv_wm_values {

        struct vlv_pipe_wm pipe[3];

        struct vlv_sr_wm sr;

        struct {

                uint8_t cursor;

                uint8_t sprite[2];

                uint8_t primary;

        } ddl[3];

        uint8_t level;

        bool cxsr;

 

struct skl_ddb_entry {

        uint16_t start, end;    /* in number of blocks, 'end' is exclusive */

 

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)

        return entry->end - entry->start;

 

static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,

                                       const struct skl_ddb_entry *e2)

        if (e1->start == e2->start && e1->end == e2->end)

                return true;

 

        return false;

 

struct skl_ddb_allocation {

        struct skl_ddb_entry pipe[I915_MAX_PIPES];

        struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */

        struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];

 

struct skl_wm_values {

        bool dirty[I915_MAX_PIPES];

        struct skl_ddb_allocation ddb;

        uint32_t wm_linetime[I915_MAX_PIPES];

        uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];

        uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];

 

struct skl_wm_level {

        bool plane_en[I915_MAX_PLANES];

        uint16_t plane_res_b[I915_MAX_PLANES];

        uint8_t plane_res_l[I915_MAX_PLANES];

 

struct i915_runtime_pm {

        atomic_t wakeref_count;

        atomic_t atomic_seq;

        bool suspended;

        bool irqs_enabled;

 

enum intel_pipe_crc_source {

        INTEL_PIPE_CRC_SOURCE_NONE,

        INTEL_PIPE_CRC_SOURCE_PLANE1,

        INTEL_PIPE_CRC_SOURCE_PLANE2,

        INTEL_PIPE_CRC_SOURCE_PF,

        INTEL_PIPE_CRC_SOURCE_PIPE,

        /* TV/DP on pre-gen5/vlv can't use the pipe source. */

        INTEL_PIPE_CRC_SOURCE_TV,

        INTEL_PIPE_CRC_SOURCE_DP_B,

        INTEL_PIPE_CRC_SOURCE_DP_C,

        INTEL_PIPE_CRC_SOURCE_DP_D,

        INTEL_PIPE_CRC_SOURCE_AUTO,

        INTEL_PIPE_CRC_SOURCE_MAX,

 

struct intel_pipe_crc_entry {

        uint32_t frame;

        uint32_t crc[5];

 

struct intel_pipe_crc {

        spinlock_t lock;

        bool opened;            /* exclusive access to the result file */

        struct intel_pipe_crc_entry *entries;

        enum intel_pipe_crc_source source;

        int head, tail;

        wait_queue_head_t wq;

 

struct i915_frontbuffer_tracking {

        struct mutex lock;

 

        /*

        unsigned busy_bits;

        unsigned flip_bits;

 

struct i915_wa_reg {

        i915_reg_t addr;

        u32 value;

        /* bitmask representing WA bits */

        u32 mask;

 

 

struct i915_workarounds {

        struct i915_wa_reg reg[I915_MAX_WA_REGS];

        u32 count;

        u32 hw_whitelist_count[I915_NUM_RINGS];

 

struct i915_virtual_gpu {

        bool active;

 

struct i915_execbuffer_params {

        struct drm_device               *dev;

        struct drm_file                 *file;

        uint32_t                        dispatch_flags;

        uint32_t                        args_batch_start_offset;

        uint64_t                        batch_obj_vm_offset;

        struct intel_engine_cs          *ring;

        struct drm_i915_gem_object      *batch_obj;

        struct intel_context            *ctx;

        struct drm_i915_gem_request     *request;

 

struct intel_wm_config {

        unsigned int num_pipes_active;

        bool sprites_enabled;

        bool sprites_scaled;

 

struct drm_i915_private {

        struct drm_device *dev;

        struct kmem_cache *objects;

        struct kmem_cache *vmas;

        struct kmem_cache *requests;

 

        const struct intel_device_info info;

 

        int relative_constants_mode;

 

        void __iomem *regs;

 

        struct intel_uncore uncore;

 

        struct i915_virtual_gpu vgpu;

 

        struct intel_guc guc;

 

        struct intel_csr csr;

 

        struct intel_gmbus gmbus[GMBUS_NUM_PINS];

 

        /** gmbus_mutex protects against concurrent usage of the single hw gmbus

        struct mutex gmbus_mutex;

 

        /**

        uint32_t gpio_mmio_base;

 

        /* MMIO base address for MIPI regs */

        uint32_t mipi_mmio_base;

 

        uint32_t psr_mmio_base;

 

        wait_queue_head_t gmbus_wait_queue;

 

        struct pci_dev *bridge_dev;

        struct intel_engine_cs ring[I915_NUM_RINGS];

        struct drm_i915_gem_object *semaphore_obj;

        uint32_t last_seqno, next_seqno;

 

        struct drm_dma_handle *status_page_dmah;

        struct resource mch_res;

 

        /* protects the irq masks */

        spinlock_t irq_lock;

 

        /* protects the mmio flip data */

        spinlock_t mmio_flip_lock;

 

        bool display_irqs_enabled;

 

 

        /* Sideband mailbox protection */

        struct mutex sb_lock;

 

        /** Cached value of IMR to avoid reads in updating the bitfield */

        union {

                u32 irq_mask;

                u32 de_irq_mask[I915_MAX_PIPES];

        };

        u32 gt_irq_mask;

        u32 pm_irq_mask;

        u32 pm_rps_events;

        u32 pipestat_irq_mask[I915_MAX_PIPES];

 

        struct i915_hotplug hotplug;

        struct intel_fbc fbc;

        struct i915_drrs drrs;

        struct intel_opregion opregion;

        struct intel_vbt_data vbt;

 

        bool preserve_bios_swizzle;

 

        /* overlay */

        struct intel_overlay *overlay;

 

        /* backlight registers and fields in struct intel_panel */

        struct mutex backlight_lock;

 

        /* LVDS info */

        bool no_aux_handshake;

 

        /* protects panel power sequencer state */

        struct mutex pps_mutex;

 

        struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */

        int num_fence_regs; /* 8 on pre-965, 16 otherwise */

 

        unsigned int fsb_freq, mem_freq, is_ddr3;

        unsigned int skl_boot_cdclk;

        unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;

        unsigned int max_dotclk_freq;

        unsigned int hpll_freq;

        unsigned int czclk_freq;

 

        /**

        struct workqueue_struct *wq;

 

        /* Display functions */

        struct drm_i915_display_funcs display;

 

        /* PCH chipset type */

        enum intel_pch pch_type;

        unsigned short pch_id;

 

        unsigned long quirks;

 

        enum modeset_restore modeset_restore;

        struct mutex modeset_restore_lock;

        struct drm_atomic_state *modeset_restore_state;

 

        struct list_head vm_list; /* Global list of all address spaces */

        struct i915_gtt gtt; /* VM representing the global address space */

 

        struct i915_gem_mm mm;

        DECLARE_HASHTABLE(mm_structs, 7);

        struct mutex mm_lock;

 

        /* Kernel Modesetting */

 

        struct sdvo_device_mapping sdvo_mappings[2];

 

        struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];

        struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];

        wait_queue_head_t pending_flip_queue;

 

        struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];

 

        /* dpll and cdclk state is protected by connection_mutex */

        int num_shared_dpll;

        struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];

 

        unsigned int active_crtcs;

        unsigned int min_pixclk[I915_MAX_PIPES];

 

        int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];

 

        struct i915_workarounds workarounds;

 

        /* Reclocking support */

        bool render_reclock_avail;

 

        struct i915_frontbuffer_tracking fb_tracking;

 

        u16 orig_clock;

 

        bool mchbar_need_disable;

 

        struct intel_l3_parity l3_parity;

 

        /* Cannot be determined by PCIID. You must always read a register. */

        size_t ellc_size;

 

        /* gen6+ rps state */

        struct intel_gen6_power_mgmt rps;

 

        /* ilk-only ips/rps state. Everything in here is protected by the global

        struct intel_ilk_power_mgmt ips;

 

        struct i915_power_domains power_domains;

 

        struct i915_psr psr;

 

        struct i915_gpu_error gpu_error;

 

        struct drm_i915_gem_object *vlv_pctx;

 

        /* list of fbdev register on this device */

        struct intel_fbdev *fbdev;

        struct work_struct fbdev_suspend_work;

 

        struct drm_property *broadcast_rgb_property;

        struct drm_property *force_audio_property;

 

        /* hda/i915 audio component */

        struct i915_audio_component *audio_component;

        bool audio_component_registered;

        /**

        struct mutex av_mutex;

 

        uint32_t hw_context_size;

        struct list_head context_list;

 

        u32 fdi_rx_config;

 

        u32 chv_phy_control;

 

        u32 suspend_count;

        bool suspended_to_idle;

        struct i915_suspend_saved_registers regfile;

        struct vlv_s0ix_state vlv_s0ix_state;

 

        struct {

                /*

                /* primary */

                uint16_t pri_latency[5];

                /* sprite */

                uint16_t spr_latency[5];

                /* cursor */

                uint16_t cur_latency[5];

                /*

                uint16_t skl_latency[8];

 

                /* Committed wm config */

                struct intel_wm_config config;

 

                /*

                struct skl_wm_values skl_results;

 

                /* current hardware state */

                union {

                        struct ilk_wm_values hw;

                        struct skl_wm_values skl_hw;

                        struct vlv_wm_values vlv;

                };

 

                uint8_t max_level;

        } wm;

 

        struct i915_runtime_pm pm;

 

        /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */

        struct {

                int (*execbuf_submit)(struct i915_execbuffer_params *params,

                                      struct drm_i915_gem_execbuffer2 *args,

                                      struct list_head *vmas);

                int (*init_rings)(struct drm_device *dev);

                void (*cleanup_ring)(struct intel_engine_cs *ring);

                void (*stop_ring)(struct intel_engine_cs *ring);

        } gt;

 

        struct intel_context *kernel_context;

 

        bool edp_low_vswing;

 

        /* perform PHY state sanity checks? */

        bool chv_phy_assert[2];

 

        struct intel_encoder *dig_port_map[I915_MAX_PORTS];

 

        /*

 

static inline struct drm_i915_private *to_i915(const struct drm_device *dev)

        return dev->dev_private;

 

static inline struct drm_i915_private *dev_to_i915(struct device *dev)

        return to_i915(dev_get_drvdata(dev));

 

static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)

        return container_of(guc, struct drm_i915_private, guc);

 

 

enum hdmi_force_audio {

        HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */

        HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */

        HDMI_AUDIO_AUTO,                /* trust EDID */

        HDMI_AUDIO_ON,                  /* force turn on HDMI audio */

 

 

struct drm_i915_gem_object_ops {

        unsigned int flags;

 

        /* Interface between the GEM object and its backing storage.

        int (*get_pages)(struct drm_i915_gem_object *);

        void (*put_pages)(struct drm_i915_gem_object *);

 

        int (*dmabuf_export)(struct drm_i915_gem_object *);

        void (*release)(struct drm_i915_gem_object *);

 

 

struct drm_i915_gem_object {

        struct drm_gem_object base;

 

        const struct drm_i915_gem_object_ops *ops;

 

        /** List of VMAs backed by this object */

        struct list_head vma_list;

 

        /** Stolen memory for this object, instead of being backed by shmem. */

        struct drm_mm_node *stolen;

        struct list_head global_list;

 

        struct list_head ring_list[I915_NUM_RINGS];

        /** Used in execbuf to temporarily hold a ref */

        struct list_head obj_exec_link;

 

        struct list_head batch_pool_link;

 

        /**

        unsigned int active:I915_NUM_RINGS;

 

        /**

        unsigned int dirty:1;

 

        /**

        signed int fence_reg:I915_MAX_NUM_FENCE_BITS;

 

        /**

        unsigned int madv:2;

 

        /**

        unsigned int tiling_mode:2;

        /**

        unsigned int fence_dirty:1;

 

        /**

        unsigned int map_and_fenceable:1;

 

        /**

        unsigned int fault_mappable:1;

 

        /*

        unsigned long gt_ro:1;

        unsigned int cache_level:3;

        unsigned int cache_dirty:1;

 

        unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

 

        unsigned int pin_display;

 

        struct sg_table *pages;

        int pages_pin_count;

        struct get_page {

                struct scatterlist *sg;

                int last;

        } get_page;

 

        /* prime dma-buf support */

        void *dma_buf_vmapping;

        int vmapping_count;

 

        /** Breadcrumb of last rendering to the buffer.

        struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];

        struct drm_i915_gem_request *last_write_req;

        /** Breadcrumb of last fenced GPU access to the buffer. */

        struct drm_i915_gem_request *last_fenced_req;

 

        /** Current tiling stride for the object, if it's tiled. */

        uint32_t stride;

 

        /** References from framebuffers, locks out tiling changes. */

        unsigned long framebuffer_references;

 

        /** Record of address bit 17 of each page at last unbind. */

        unsigned long *bit_17;

 

        union {

                /** for phy allocated objects */

                struct drm_dma_handle *phys_handle;

 

                struct i915_gem_userptr {

                        uintptr_t ptr;

                        unsigned read_only :1;

                        unsigned workers :4;

 

                        struct i915_mm_struct *mm;

                        struct i915_mmu_object *mmu_object;

                        struct work_struct *work;