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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include <uapi/drm/i915_drm.h>
  34.  
  35. #include "i915_reg.h"
  36. #include "intel_bios.h"
  37. #include "intel_ringbuffer.h"
  38. #include "intel_lrc.h"
  39. #include "i915_gem_gtt.h"
  40. #include "i915_gem_render_state.h"
  41. //#include <linux/io-mapping.h>
  42. #include <linux/i2c.h>
  43. #include <linux/i2c-algo-bit.h>
  44. #include <drm/intel-gtt.h>
  45. #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  46. #include <drm/drm_gem.h>
  47. //#include <linux/backlight.h>
  48. #include <linux/hashtable.h>
  49.  
  50. #include <linux/spinlock.h>
  51. #include <linux/err.h>
  52.  
  53.  
  54. /* General customization:
  55.  */
  56.  
  57. #define DRIVER_NAME             "i915"
  58. #define DRIVER_DESC             "Intel Graphics"
  59. #define DRIVER_DATE             "20141121"
  60.  
  61. #undef WARN_ON
  62. #define WARN_ON(x)              WARN(x, "WARN_ON(" #x ")")
  63.  
  64. enum pipe {
  65.         INVALID_PIPE = -1,
  66.         PIPE_A = 0,
  67.         PIPE_B,
  68.         PIPE_C,
  69.         _PIPE_EDP,
  70.         I915_MAX_PIPES = _PIPE_EDP
  71. };
  72. #define pipe_name(p) ((p) + 'A')
  73.  
  74. enum transcoder {
  75.         TRANSCODER_A = 0,
  76.         TRANSCODER_B,
  77.         TRANSCODER_C,
  78.         TRANSCODER_EDP,
  79.         I915_MAX_TRANSCODERS
  80. };
  81. #define transcoder_name(t) ((t) + 'A')
  82.  
  83. /*
  84.  * This is the maximum (across all platforms) number of planes (primary +
  85.  * sprites) that can be active at the same time on one pipe.
  86.  *
  87.  * This value doesn't count the cursor plane.
  88.  */
  89. #define I915_MAX_PLANES 3
  90.  
  91. enum plane {
  92.         PLANE_A = 0,
  93.         PLANE_B,
  94.         PLANE_C,
  95. };
  96. #define plane_name(p) ((p) + 'A')
  97.  
  98. #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
  99.  
  100. enum port {
  101.         PORT_A = 0,
  102.         PORT_B,
  103.         PORT_C,
  104.         PORT_D,
  105.         PORT_E,
  106.         I915_MAX_PORTS
  107. };
  108. #define port_name(p) ((p) + 'A')
  109.  
  110. #define I915_NUM_PHYS_VLV 2
  111.  
  112. enum dpio_channel {
  113.         DPIO_CH0,
  114.         DPIO_CH1
  115. };
  116.  
  117. enum dpio_phy {
  118.         DPIO_PHY0,
  119.         DPIO_PHY1
  120. };
  121.  
  122. enum intel_display_power_domain {
  123.         POWER_DOMAIN_PIPE_A,
  124.         POWER_DOMAIN_PIPE_B,
  125.         POWER_DOMAIN_PIPE_C,
  126.         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  127.         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  128.         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  129.         POWER_DOMAIN_TRANSCODER_A,
  130.         POWER_DOMAIN_TRANSCODER_B,
  131.         POWER_DOMAIN_TRANSCODER_C,
  132.         POWER_DOMAIN_TRANSCODER_EDP,
  133.         POWER_DOMAIN_PORT_DDI_A_2_LANES,
  134.         POWER_DOMAIN_PORT_DDI_A_4_LANES,
  135.         POWER_DOMAIN_PORT_DDI_B_2_LANES,
  136.         POWER_DOMAIN_PORT_DDI_B_4_LANES,
  137.         POWER_DOMAIN_PORT_DDI_C_2_LANES,
  138.         POWER_DOMAIN_PORT_DDI_C_4_LANES,
  139.         POWER_DOMAIN_PORT_DDI_D_2_LANES,
  140.         POWER_DOMAIN_PORT_DDI_D_4_LANES,
  141.         POWER_DOMAIN_PORT_DSI,
  142.         POWER_DOMAIN_PORT_CRT,
  143.         POWER_DOMAIN_PORT_OTHER,
  144.         POWER_DOMAIN_VGA,
  145.         POWER_DOMAIN_AUDIO,
  146.         POWER_DOMAIN_PLLS,
  147.         POWER_DOMAIN_INIT,
  148.  
  149.         POWER_DOMAIN_NUM,
  150. };
  151.  
  152. #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
  153. #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
  154.                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
  155. #define POWER_DOMAIN_TRANSCODER(tran) \
  156.         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
  157.          (tran) + POWER_DOMAIN_TRANSCODER_A)
  158.  
  159. enum hpd_pin {
  160.         HPD_NONE = 0,
  161.         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
  162.         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
  163.         HPD_CRT,
  164.         HPD_SDVO_B,
  165.         HPD_SDVO_C,
  166.         HPD_PORT_B,
  167.         HPD_PORT_C,
  168.         HPD_PORT_D,
  169.         HPD_NUM_PINS
  170. };
  171.  
  172. #define I915_GEM_GPU_DOMAINS \
  173.         (I915_GEM_DOMAIN_RENDER | \
  174.          I915_GEM_DOMAIN_SAMPLER | \
  175.          I915_GEM_DOMAIN_COMMAND | \
  176.          I915_GEM_DOMAIN_INSTRUCTION | \
  177.          I915_GEM_DOMAIN_VERTEX)
  178.  
  179. #define for_each_pipe(__dev_priv, __p) \
  180.         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
  181. #define for_each_plane(pipe, p) \
  182.         for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
  183. #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
  184.  
  185. #define for_each_crtc(dev, crtc) \
  186.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
  187.  
  188. #define for_each_intel_crtc(dev, intel_crtc) \
  189.         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
  190.  
  191. #define for_each_intel_encoder(dev, intel_encoder)              \
  192.         list_for_each_entry(intel_encoder,                      \
  193.                             &(dev)->mode_config.encoder_list,   \
  194.                             base.head)
  195.  
  196. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  197.         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  198.                 if ((intel_encoder)->base.crtc == (__crtc))
  199.  
  200. #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
  201.         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
  202.                 if ((intel_connector)->base.encoder == (__encoder))
  203.  
  204. #define for_each_power_domain(domain, mask)                             \
  205.         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
  206.                 if ((1 << (domain)) & (mask))
  207.  
  208. struct drm_i915_private;
  209. struct i915_mm_struct;
  210. struct i915_mmu_object;
  211.  
  212. enum intel_dpll_id {
  213.         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
  214.         /* real shared dpll ids must be >= 0 */
  215.         DPLL_ID_PCH_PLL_A = 0,
  216.         DPLL_ID_PCH_PLL_B = 1,
  217.         /* hsw/bdw */
  218.         DPLL_ID_WRPLL1 = 0,
  219.         DPLL_ID_WRPLL2 = 1,
  220.         /* skl */
  221.         DPLL_ID_SKL_DPLL1 = 0,
  222.         DPLL_ID_SKL_DPLL2 = 1,
  223.         DPLL_ID_SKL_DPLL3 = 2,
  224. };
  225. #define I915_NUM_PLLS 3
  226.  
  227. struct intel_dpll_hw_state {
  228.         /* i9xx, pch plls */
  229.         uint32_t dpll;
  230.         uint32_t dpll_md;
  231.         uint32_t fp0;
  232.         uint32_t fp1;
  233.  
  234.         /* hsw, bdw */
  235.         uint32_t wrpll;
  236.  
  237.         /* skl */
  238.         /*
  239.          * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
  240.          * lower part of crtl1 and they get shifted into position when writing
  241.          * the register.  This allows us to easily compare the state to share
  242.          * the DPLL.
  243.          */
  244.         uint32_t ctrl1;
  245.         /* HDMI only, 0 when used for DP */
  246.         uint32_t cfgcr1, cfgcr2;
  247. };
  248.  
  249. struct intel_shared_dpll_config {
  250.         unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
  251.         struct intel_dpll_hw_state hw_state;
  252. };
  253.  
  254. struct intel_shared_dpll {
  255.         struct intel_shared_dpll_config config;
  256.         struct intel_shared_dpll_config *new_config;
  257.  
  258.         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  259.         bool on; /* is the PLL actually active? Disabled during modeset */
  260.         const char *name;
  261.         /* should match the index in the dev_priv->shared_dplls array */
  262.         enum intel_dpll_id id;
  263.         /* The mode_set hook is optional and should be used together with the
  264.          * intel_prepare_shared_dpll function. */
  265.         void (*mode_set)(struct drm_i915_private *dev_priv,
  266.                          struct intel_shared_dpll *pll);
  267.         void (*enable)(struct drm_i915_private *dev_priv,
  268.                        struct intel_shared_dpll *pll);
  269.         void (*disable)(struct drm_i915_private *dev_priv,
  270.                         struct intel_shared_dpll *pll);
  271.         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
  272.                              struct intel_shared_dpll *pll,
  273.                              struct intel_dpll_hw_state *hw_state);
  274. };
  275.  
  276. #define SKL_DPLL0 0
  277. #define SKL_DPLL1 1
  278. #define SKL_DPLL2 2
  279. #define SKL_DPLL3 3
  280.  
  281. /* Used by dp and fdi links */
  282. struct intel_link_m_n {
  283.         uint32_t        tu;
  284.         uint32_t        gmch_m;
  285.         uint32_t        gmch_n;
  286.         uint32_t        link_m;
  287.         uint32_t        link_n;
  288. };
  289.  
  290. void intel_link_compute_m_n(int bpp, int nlanes,
  291.                             int pixel_clock, int link_clock,
  292.                             struct intel_link_m_n *m_n);
  293.  
  294. /* Interface history:
  295.  *
  296.  * 1.1: Original.
  297.  * 1.2: Add Power Management
  298.  * 1.3: Add vblank support
  299.  * 1.4: Fix cmdbuffer path, add heap destroy
  300.  * 1.5: Add vblank pipe configuration
  301.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  302.  *      - Support vertical blank on secondary display pipe
  303.  */
  304. #define DRIVER_MAJOR            1
  305. #define DRIVER_MINOR            6
  306. #define DRIVER_PATCHLEVEL       0
  307.  
  308. #define WATCH_LISTS     0
  309.  
  310. struct opregion_header;
  311. struct opregion_acpi;
  312. struct opregion_swsci;
  313. struct opregion_asle;
  314.  
  315. struct intel_opregion {
  316.         struct opregion_header __iomem *header;
  317.         struct opregion_acpi __iomem *acpi;
  318.         struct opregion_swsci __iomem *swsci;
  319.         u32 swsci_gbda_sub_functions;
  320.         u32 swsci_sbcb_sub_functions;
  321.         struct opregion_asle __iomem *asle;
  322.         void __iomem *vbt;
  323.         u32 __iomem *lid_state;
  324.         struct work_struct asle_work;
  325. };
  326. #define OPREGION_SIZE            (8*1024)
  327.  
  328. struct intel_overlay;
  329. struct intel_overlay_error_state;
  330.  
  331. #define I915_FENCE_REG_NONE -1
  332. #define I915_MAX_NUM_FENCES 32
  333. /* 32 fences + sign bit for FENCE_REG_NONE */
  334. #define I915_MAX_NUM_FENCE_BITS 6
  335.  
  336. struct drm_i915_fence_reg {
  337.         struct list_head lru_list;
  338.         struct drm_i915_gem_object *obj;
  339.         int pin_count;
  340. };
  341.  
  342. struct sdvo_device_mapping {
  343.         u8 initialized;
  344.         u8 dvo_port;
  345.         u8 slave_addr;
  346.         u8 dvo_wiring;
  347.         u8 i2c_pin;
  348.         u8 ddc_pin;
  349. };
  350.  
  351. struct intel_display_error_state;
  352.  
  353. struct drm_i915_error_state {
  354.         struct kref ref;
  355.         struct timeval time;
  356.  
  357.         char error_msg[128];
  358.         u32 reset_count;
  359.         u32 suspend_count;
  360.  
  361.         /* Generic register state */
  362.         u32 eir;
  363.         u32 pgtbl_er;
  364.         u32 ier;
  365.         u32 gtier[4];
  366.         u32 ccid;
  367.         u32 derrmr;
  368.         u32 forcewake;
  369.         u32 error; /* gen6+ */
  370.         u32 err_int; /* gen7 */
  371.         u32 done_reg;
  372.         u32 gac_eco;
  373.         u32 gam_ecochk;
  374.         u32 gab_ctl;
  375.         u32 gfx_mode;
  376.         u32 extra_instdone[I915_NUM_INSTDONE_REG];
  377.         u64 fence[I915_MAX_NUM_FENCES];
  378.         struct intel_overlay_error_state *overlay;
  379.         struct intel_display_error_state *display;
  380.  
  381.         struct drm_i915_error_ring {
  382.                 bool valid;
  383.                 /* Software tracked state */
  384.                 bool waiting;
  385.                 int hangcheck_score;
  386.                 enum intel_ring_hangcheck_action hangcheck_action;
  387.                 int num_requests;
  388.  
  389.                 /* our own tracking of ring head and tail */
  390.                 u32 cpu_ring_head;
  391.                 u32 cpu_ring_tail;
  392.  
  393.                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
  394.  
  395.                 /* Register state */
  396.                 u32 tail;
  397.                 u32 head;
  398.                 u32 ctl;
  399.                 u32 hws;
  400.                 u32 ipeir;
  401.                 u32 ipehr;
  402.                 u32 instdone;
  403.                 u32 bbstate;
  404.                 u32 instpm;
  405.                 u32 instps;
  406.                 u32 seqno;
  407.                 u64 bbaddr;
  408.                 u64 acthd;
  409.                 u32 fault_reg;
  410.                 u64 faddr;
  411.                 u32 rc_psmi; /* sleep state */
  412.                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
  413.  
  414.         struct drm_i915_error_object {
  415.                 int page_count;
  416.                 u32 gtt_offset;
  417.                 u32 *pages[0];
  418.                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
  419.  
  420.                 struct drm_i915_error_request {
  421.                         long jiffies;
  422.                         u32 seqno;
  423.                         u32 tail;
  424.                 } *requests;
  425.  
  426.                 struct {
  427.                         u32 gfx_mode;
  428.                         union {
  429.                                 u64 pdp[4];
  430.                                 u32 pp_dir_base;
  431.                         };
  432.                 } vm_info;
  433.  
  434.                 pid_t pid;
  435.                 char comm[TASK_COMM_LEN];
  436.         } ring[I915_NUM_RINGS];
  437.  
  438.         struct drm_i915_error_buffer {
  439.                 u32 size;
  440.                 u32 name;
  441.                 u32 rseqno, wseqno;
  442.                 u32 gtt_offset;
  443.                 u32 read_domains;
  444.                 u32 write_domain;
  445.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  446.                 s32 pinned:2;
  447.                 u32 tiling:2;
  448.                 u32 dirty:1;
  449.                 u32 purgeable:1;
  450.                 u32 userptr:1;
  451.                 s32 ring:4;
  452.                 u32 cache_level:3;
  453.         } **active_bo, **pinned_bo;
  454.  
  455.         u32 *active_bo_count, *pinned_bo_count;
  456.         u32 vm_count;
  457. };
  458.  
  459. struct intel_connector;
  460. struct intel_encoder;
  461. struct intel_crtc_config;
  462. struct intel_plane_config;
  463. struct intel_crtc;
  464. struct intel_limit;
  465. struct dpll;
  466.  
  467. struct drm_i915_display_funcs {
  468.         bool (*fbc_enabled)(struct drm_device *dev);
  469.         void (*enable_fbc)(struct drm_crtc *crtc);
  470.         void (*disable_fbc)(struct drm_device *dev);
  471.         int (*get_display_clock_speed)(struct drm_device *dev);
  472.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  473.         /**
  474.          * find_dpll() - Find the best values for the PLL
  475.          * @limit: limits for the PLL
  476.          * @crtc: current CRTC
  477.          * @target: target frequency in kHz
  478.          * @refclk: reference clock frequency in kHz
  479.          * @match_clock: if provided, @best_clock P divider must
  480.          *               match the P divider from @match_clock
  481.          *               used for LVDS downclocking
  482.          * @best_clock: best PLL values found
  483.          *
  484.          * Returns true on success, false on failure.
  485.          */
  486.         bool (*find_dpll)(const struct intel_limit *limit,
  487.                           struct intel_crtc *crtc,
  488.                           int target, int refclk,
  489.                           struct dpll *match_clock,
  490.                           struct dpll *best_clock);
  491.         void (*update_wm)(struct drm_crtc *crtc);
  492.         void (*update_sprite_wm)(struct drm_plane *plane,
  493.                                  struct drm_crtc *crtc,
  494.                                  uint32_t sprite_width, uint32_t sprite_height,
  495.                                  int pixel_size, bool enable, bool scaled);
  496.         void (*modeset_global_resources)(struct drm_device *dev);
  497.         /* Returns the active state of the crtc, and if the crtc is active,
  498.          * fills out the pipe-config with the hw state. */
  499.         bool (*get_pipe_config)(struct intel_crtc *,
  500.                                 struct intel_crtc_config *);
  501.         void (*get_plane_config)(struct intel_crtc *,
  502.                                  struct intel_plane_config *);
  503.         int (*crtc_compute_clock)(struct intel_crtc *crtc);
  504.         void (*crtc_enable)(struct drm_crtc *crtc);
  505.         void (*crtc_disable)(struct drm_crtc *crtc);
  506.         void (*off)(struct drm_crtc *crtc);
  507.         void (*audio_codec_enable)(struct drm_connector *connector,
  508.                                    struct intel_encoder *encoder,
  509.                           struct drm_display_mode *mode);
  510.         void (*audio_codec_disable)(struct intel_encoder *encoder);
  511.         void (*fdi_link_train)(struct drm_crtc *crtc);
  512.         void (*init_clock_gating)(struct drm_device *dev);
  513.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  514.                           struct drm_framebuffer *fb,
  515.                           struct drm_i915_gem_object *obj,
  516.                           struct intel_engine_cs *ring,
  517.                           uint32_t flags);
  518.         void (*update_primary_plane)(struct drm_crtc *crtc,
  519.                                     struct drm_framebuffer *fb,
  520.                             int x, int y);
  521.         void (*hpd_irq_setup)(struct drm_device *dev);
  522.         /* clock updates for mode set */
  523.         /* cursor updates */
  524.         /* render clock increase/decrease */
  525.         /* display clock increase/decrease */
  526.         /* pll clock increase/decrease */
  527.  
  528.         int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
  529.         uint32_t (*get_backlight)(struct intel_connector *connector);
  530.         void (*set_backlight)(struct intel_connector *connector,
  531.                               uint32_t level);
  532.         void (*disable_backlight)(struct intel_connector *connector);
  533.         void (*enable_backlight)(struct intel_connector *connector);
  534. };
  535.  
  536. struct intel_uncore_funcs {
  537.         void (*force_wake_get)(struct drm_i915_private *dev_priv,
  538.                                                         int fw_engine);
  539.         void (*force_wake_put)(struct drm_i915_private *dev_priv,
  540.                                                         int fw_engine);
  541.  
  542.         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  543.         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  544.         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  545.         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  546.  
  547.         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
  548.                                 uint8_t val, bool trace);
  549.         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
  550.                                 uint16_t val, bool trace);
  551.         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
  552.                                 uint32_t val, bool trace);
  553.         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
  554.                                 uint64_t val, bool trace);
  555. };
  556.  
  557. struct intel_uncore {
  558.         spinlock_t lock; /** lock is also taken in irq contexts. */
  559.  
  560.         struct intel_uncore_funcs funcs;
  561.  
  562.         unsigned fifo_count;
  563.         unsigned forcewake_count;
  564.  
  565.         unsigned fw_rendercount;
  566.         unsigned fw_mediacount;
  567.         unsigned fw_blittercount;
  568.  
  569.         struct timer_list force_wake_timer;
  570. };
  571.  
  572. #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
  573.         func(is_mobile) sep \
  574.         func(is_i85x) sep \
  575.         func(is_i915g) sep \
  576.         func(is_i945gm) sep \
  577.         func(is_g33) sep \
  578.         func(need_gfx_hws) sep \
  579.         func(is_g4x) sep \
  580.         func(is_pineview) sep \
  581.         func(is_broadwater) sep \
  582.         func(is_crestline) sep \
  583.         func(is_ivybridge) sep \
  584.         func(is_valleyview) sep \
  585.         func(is_haswell) sep \
  586.         func(is_skylake) sep \
  587.         func(is_preliminary) sep \
  588.         func(has_fbc) sep \
  589.         func(has_pipe_cxsr) sep \
  590.         func(has_hotplug) sep \
  591.         func(cursor_needs_physical) sep \
  592.         func(has_overlay) sep \
  593.         func(overlay_needs_physical) sep \
  594.         func(supports_tv) sep \
  595.         func(has_llc) sep \
  596.         func(has_ddi) sep \
  597.         func(has_fpga_dbg)
  598.  
  599. #define DEFINE_FLAG(name) u8 name:1
  600. #define SEP_SEMICOLON ;
  601.  
  602. struct intel_device_info {
  603.         u32 display_mmio_offset;
  604.         u16 device_id;
  605.         u8 num_pipes:3;
  606.         u8 num_sprites[I915_MAX_PIPES];
  607.         u8 gen;
  608.         u8 ring_mask; /* Rings supported by the HW */
  609.         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
  610.         /* Register offsets for the various display pipes and transcoders */
  611.         int pipe_offsets[I915_MAX_TRANSCODERS];
  612.         int trans_offsets[I915_MAX_TRANSCODERS];
  613.         int palette_offsets[I915_MAX_PIPES];
  614.         int cursor_offsets[I915_MAX_PIPES];
  615. };
  616.  
  617. #undef DEFINE_FLAG
  618. #undef SEP_SEMICOLON
  619.  
  620. enum i915_cache_level {
  621.         I915_CACHE_NONE = 0,
  622.         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
  623.         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
  624.                               caches, eg sampler/render caches, and the
  625.                               large Last-Level-Cache. LLC is coherent with
  626.                               the CPU, but L3 is only visible to the GPU. */
  627.         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
  628. };
  629.  
  630. struct i915_ctx_hang_stats {
  631.         /* This context had batch pending when hang was declared */
  632.         unsigned batch_pending;
  633.  
  634.         /* This context had batch active when hang was declared */
  635.         unsigned batch_active;
  636.  
  637.         /* Time when this context was last blamed for a GPU reset */
  638.         unsigned long guilty_ts;
  639.  
  640.         /* This context is banned to submit more work */
  641.         bool banned;
  642. };
  643.  
  644. /* This must match up with the value previously used for execbuf2.rsvd1. */
  645. #define DEFAULT_CONTEXT_HANDLE 0
  646. /**
  647.  * struct intel_context - as the name implies, represents a context.
  648.  * @ref: reference count.
  649.  * @user_handle: userspace tracking identity for this context.
  650.  * @remap_slice: l3 row remapping information.
  651.  * @file_priv: filp associated with this context (NULL for global default
  652.  *             context).
  653.  * @hang_stats: information about the role of this context in possible GPU
  654.  *              hangs.
  655.  * @vm: virtual memory space used by this context.
  656.  * @legacy_hw_ctx: render context backing object and whether it is correctly
  657.  *                initialized (legacy ring submission mechanism only).
  658.  * @link: link in the global list of contexts.
  659.  *
  660.  * Contexts are memory images used by the hardware to store copies of their
  661.  * internal state.
  662.  */
  663. struct intel_context {
  664.         struct kref ref;
  665.         int user_handle;
  666.         uint8_t remap_slice;
  667.         struct drm_i915_file_private *file_priv;
  668.         struct i915_ctx_hang_stats hang_stats;
  669.         struct i915_hw_ppgtt *ppgtt;
  670.  
  671.         /* Legacy ring buffer submission */
  672.         struct {
  673.                 struct drm_i915_gem_object *rcs_state;
  674.                 bool initialized;
  675.         } legacy_hw_ctx;
  676.  
  677.         /* Execlists */
  678.         bool rcs_initialized;
  679.         struct {
  680.                 struct drm_i915_gem_object *state;
  681.                 struct intel_ringbuffer *ringbuf;
  682.                 int unpin_count;
  683.         } engine[I915_NUM_RINGS];
  684.  
  685.         struct list_head link;
  686. };
  687.  
  688. struct i915_fbc {
  689.         unsigned long size;
  690.         unsigned threshold;
  691.         unsigned int fb_id;
  692.         enum plane plane;
  693.         int y;
  694.  
  695.         struct drm_mm_node compressed_fb;
  696.         struct drm_mm_node *compressed_llb;
  697.  
  698.         bool false_color;
  699.  
  700.         /* Tracks whether the HW is actually enabled, not whether the feature is
  701.          * possible. */
  702.         bool enabled;
  703.  
  704.         /* On gen8 some rings cannont perform fbc clean operation so for now
  705.          * we are doing this on SW with mmio.
  706.          * This variable works in the opposite information direction
  707.          * of ring->fbc_dirty telling software on frontbuffer tracking
  708.          * to perform the cache clean on sw side.
  709.          */
  710.         bool need_sw_cache_clean;
  711.  
  712.         struct intel_fbc_work {
  713.                 struct delayed_work work;
  714.                 struct drm_crtc *crtc;
  715.                 struct drm_framebuffer *fb;
  716.         } *fbc_work;
  717.  
  718.         enum no_fbc_reason {
  719.                 FBC_OK, /* FBC is enabled */
  720.                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
  721.         FBC_NO_OUTPUT, /* no outputs enabled to compress */
  722.                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
  723.         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  724.         FBC_MODE_TOO_LARGE, /* mode too large for compression */
  725.         FBC_BAD_PLANE, /* fbc not supported on plane */
  726.         FBC_NOT_TILED, /* buffer not tiled */
  727.         FBC_MULTIPLE_PIPES, /* more than one pipe active */
  728.         FBC_MODULE_PARAM,
  729.                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
  730.         } no_fbc_reason;
  731. };
  732.  
  733. struct i915_drrs {
  734.         struct intel_connector *connector;
  735. };
  736.  
  737. struct intel_dp;
  738. struct i915_psr {
  739.         struct mutex lock;
  740.         bool sink_support;
  741.         bool source_ok;
  742.         struct intel_dp *enabled;
  743.         bool active;
  744.         struct delayed_work work;
  745.         unsigned busy_frontbuffer_bits;
  746. };
  747.  
  748. enum intel_pch {
  749.         PCH_NONE = 0,   /* No PCH present */
  750.         PCH_IBX,        /* Ibexpeak PCH */
  751.         PCH_CPT,        /* Cougarpoint PCH */
  752.         PCH_LPT,        /* Lynxpoint PCH */
  753.         PCH_SPT,        /* Sunrisepoint PCH */
  754.         PCH_NOP,
  755. };
  756.  
  757. enum intel_sbi_destination {
  758.         SBI_ICLK,
  759.         SBI_MPHY,
  760. };
  761.  
  762. #define QUIRK_PIPEA_FORCE (1<<0)
  763. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  764. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  765. #define QUIRK_BACKLIGHT_PRESENT (1<<3)
  766. #define QUIRK_PIPEB_FORCE (1<<4)
  767. #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
  768.  
  769. struct intel_fbdev;
  770. struct intel_fbc_work;
  771.  
  772. struct intel_gmbus {
  773.         struct i2c_adapter adapter;
  774.         u32 force_bit;
  775.         u32 reg0;
  776.         u32 gpio_reg;
  777.         struct i2c_algo_bit_data bit_algo;
  778.         struct drm_i915_private *dev_priv;
  779. };
  780.  
  781. struct i915_suspend_saved_registers {
  782.         u8 saveLBB;
  783.         u32 saveDSPACNTR;
  784.         u32 saveDSPBCNTR;
  785.         u32 saveDSPARB;
  786.         u32 savePIPEACONF;
  787.         u32 savePIPEBCONF;
  788.         u32 savePIPEASRC;
  789.         u32 savePIPEBSRC;
  790.         u32 saveFPA0;
  791.         u32 saveFPA1;
  792.         u32 saveDPLL_A;
  793.         u32 saveDPLL_A_MD;
  794.         u32 saveHTOTAL_A;
  795.         u32 saveHBLANK_A;
  796.         u32 saveHSYNC_A;
  797.         u32 saveVTOTAL_A;
  798.         u32 saveVBLANK_A;
  799.         u32 saveVSYNC_A;
  800.         u32 saveBCLRPAT_A;
  801.         u32 saveTRANSACONF;
  802.         u32 saveTRANS_HTOTAL_A;
  803.         u32 saveTRANS_HBLANK_A;
  804.         u32 saveTRANS_HSYNC_A;
  805.         u32 saveTRANS_VTOTAL_A;
  806.         u32 saveTRANS_VBLANK_A;
  807.         u32 saveTRANS_VSYNC_A;
  808.         u32 savePIPEASTAT;
  809.         u32 saveDSPASTRIDE;
  810.         u32 saveDSPASIZE;
  811.         u32 saveDSPAPOS;
  812.         u32 saveDSPAADDR;
  813.         u32 saveDSPASURF;
  814.         u32 saveDSPATILEOFF;
  815.         u32 savePFIT_PGM_RATIOS;
  816.         u32 saveBLC_HIST_CTL;
  817.         u32 saveBLC_PWM_CTL;
  818.         u32 saveBLC_PWM_CTL2;
  819.         u32 saveBLC_CPU_PWM_CTL;
  820.         u32 saveBLC_CPU_PWM_CTL2;
  821.         u32 saveFPB0;
  822.         u32 saveFPB1;
  823.         u32 saveDPLL_B;
  824.         u32 saveDPLL_B_MD;
  825.         u32 saveHTOTAL_B;
  826.         u32 saveHBLANK_B;
  827.         u32 saveHSYNC_B;
  828.         u32 saveVTOTAL_B;
  829.         u32 saveVBLANK_B;
  830.         u32 saveVSYNC_B;
  831.         u32 saveBCLRPAT_B;
  832.         u32 saveTRANSBCONF;
  833.         u32 saveTRANS_HTOTAL_B;
  834.         u32 saveTRANS_HBLANK_B;
  835.         u32 saveTRANS_HSYNC_B;
  836.         u32 saveTRANS_VTOTAL_B;
  837.         u32 saveTRANS_VBLANK_B;
  838.         u32 saveTRANS_VSYNC_B;
  839.         u32 savePIPEBSTAT;
  840.         u32 saveDSPBSTRIDE;
  841.         u32 saveDSPBSIZE;
  842.         u32 saveDSPBPOS;
  843.         u32 saveDSPBADDR;
  844.         u32 saveDSPBSURF;
  845.         u32 saveDSPBTILEOFF;
  846.         u32 saveVGA0;
  847.         u32 saveVGA1;
  848.         u32 saveVGA_PD;
  849.         u32 saveVGACNTRL;
  850.         u32 saveADPA;
  851.         u32 saveLVDS;
  852.         u32 savePP_ON_DELAYS;
  853.         u32 savePP_OFF_DELAYS;
  854.         u32 saveDVOA;
  855.         u32 saveDVOB;
  856.         u32 saveDVOC;
  857.         u32 savePP_ON;
  858.         u32 savePP_OFF;
  859.         u32 savePP_CONTROL;
  860.         u32 savePP_DIVISOR;
  861.         u32 savePFIT_CONTROL;
  862.         u32 save_palette_a[256];
  863.         u32 save_palette_b[256];
  864.         u32 saveFBC_CONTROL;
  865.         u32 saveIER;
  866.         u32 saveIIR;
  867.         u32 saveIMR;
  868.         u32 saveDEIER;
  869.         u32 saveDEIMR;
  870.         u32 saveGTIER;
  871.         u32 saveGTIMR;
  872.         u32 saveFDI_RXA_IMR;
  873.         u32 saveFDI_RXB_IMR;
  874.         u32 saveCACHE_MODE_0;
  875.         u32 saveMI_ARB_STATE;
  876.         u32 saveSWF0[16];
  877.         u32 saveSWF1[16];
  878.         u32 saveSWF2[3];
  879.         u8 saveMSR;
  880.         u8 saveSR[8];
  881.         u8 saveGR[25];
  882.         u8 saveAR_INDEX;
  883.         u8 saveAR[21];
  884.         u8 saveDACMASK;
  885.         u8 saveCR[37];
  886.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  887.         u32 saveCURACNTR;
  888.         u32 saveCURAPOS;
  889.         u32 saveCURABASE;
  890.         u32 saveCURBCNTR;
  891.         u32 saveCURBPOS;
  892.         u32 saveCURBBASE;
  893.         u32 saveCURSIZE;
  894.         u32 saveDP_B;
  895.         u32 saveDP_C;
  896.         u32 saveDP_D;
  897.         u32 savePIPEA_GMCH_DATA_M;
  898.         u32 savePIPEB_GMCH_DATA_M;
  899.         u32 savePIPEA_GMCH_DATA_N;
  900.         u32 savePIPEB_GMCH_DATA_N;
  901.         u32 savePIPEA_DP_LINK_M;
  902.         u32 savePIPEB_DP_LINK_M;
  903.         u32 savePIPEA_DP_LINK_N;
  904.         u32 savePIPEB_DP_LINK_N;
  905.         u32 saveFDI_RXA_CTL;
  906.         u32 saveFDI_TXA_CTL;
  907.         u32 saveFDI_RXB_CTL;
  908.         u32 saveFDI_TXB_CTL;
  909.         u32 savePFA_CTL_1;
  910.         u32 savePFB_CTL_1;
  911.         u32 savePFA_WIN_SZ;
  912.         u32 savePFB_WIN_SZ;
  913.         u32 savePFA_WIN_POS;
  914.         u32 savePFB_WIN_POS;
  915.         u32 savePCH_DREF_CONTROL;
  916.         u32 saveDISP_ARB_CTL;
  917.         u32 savePIPEA_DATA_M1;
  918.         u32 savePIPEA_DATA_N1;
  919.         u32 savePIPEA_LINK_M1;
  920.         u32 savePIPEA_LINK_N1;
  921.         u32 savePIPEB_DATA_M1;
  922.         u32 savePIPEB_DATA_N1;
  923.         u32 savePIPEB_LINK_M1;
  924.         u32 savePIPEB_LINK_N1;
  925.         u32 saveMCHBAR_RENDER_STANDBY;
  926.         u32 savePCH_PORT_HOTPLUG;
  927.         u16 saveGCDGMBUS;
  928. };
  929.  
  930. struct vlv_s0ix_state {
  931.         /* GAM */
  932.         u32 wr_watermark;
  933.         u32 gfx_prio_ctrl;
  934.         u32 arb_mode;
  935.         u32 gfx_pend_tlb0;
  936.         u32 gfx_pend_tlb1;
  937.         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  938.         u32 media_max_req_count;
  939.         u32 gfx_max_req_count;
  940.         u32 render_hwsp;
  941.         u32 ecochk;
  942.         u32 bsd_hwsp;
  943.         u32 blt_hwsp;
  944.         u32 tlb_rd_addr;
  945.  
  946.         /* MBC */
  947.         u32 g3dctl;
  948.         u32 gsckgctl;
  949.         u32 mbctl;
  950.  
  951.         /* GCP */
  952.         u32 ucgctl1;
  953.         u32 ucgctl3;
  954.         u32 rcgctl1;
  955.         u32 rcgctl2;
  956.         u32 rstctl;
  957.         u32 misccpctl;
  958.  
  959.         /* GPM */
  960.         u32 gfxpause;
  961.         u32 rpdeuhwtc;
  962.         u32 rpdeuc;
  963.         u32 ecobus;
  964.         u32 pwrdwnupctl;
  965.         u32 rp_down_timeout;
  966.         u32 rp_deucsw;
  967.         u32 rcubmabdtmr;
  968.         u32 rcedata;
  969.         u32 spare2gh;
  970.  
  971.         /* Display 1 CZ domain */
  972.         u32 gt_imr;
  973.         u32 gt_ier;
  974.         u32 pm_imr;
  975.         u32 pm_ier;
  976.         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
  977.  
  978.         /* GT SA CZ domain */
  979.         u32 tilectl;
  980.         u32 gt_fifoctl;
  981.         u32 gtlc_wake_ctrl;
  982.         u32 gtlc_survive;
  983.         u32 pmwgicz;
  984.  
  985.         /* Display 2 CZ domain */
  986.         u32 gu_ctl0;
  987.         u32 gu_ctl1;
  988.         u32 clock_gate_dis2;
  989. };
  990.  
  991. struct intel_rps_ei {
  992.         u32 cz_clock;
  993.         u32 render_c0;
  994.         u32 media_c0;
  995. };
  996.  
  997. struct intel_gen6_power_mgmt {
  998.         /*
  999.          * work, interrupts_enabled and pm_iir are protected by
  1000.          * dev_priv->irq_lock
  1001.          */
  1002.         struct work_struct work;
  1003.         bool interrupts_enabled;
  1004.         u32 pm_iir;
  1005.  
  1006.         /* Frequencies are stored in potentially platform dependent multiples.
  1007.          * In other words, *_freq needs to be multiplied by X to be interesting.
  1008.          * Soft limits are those which are used for the dynamic reclocking done
  1009.          * by the driver (raise frequencies under heavy loads, and lower for
  1010.          * lighter loads). Hard limits are those imposed by the hardware.
  1011.          *
  1012.          * A distinction is made for overclocking, which is never enabled by
  1013.          * default, and is considered to be above the hard limit if it's
  1014.          * possible at all.
  1015.          */
  1016.         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
  1017.         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
  1018.         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
  1019.         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
  1020.         u8 min_freq;            /* AKA RPn. Minimum frequency */
  1021.         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
  1022.         u8 rp1_freq;            /* "less than" RP0 power/freqency */
  1023.         u8 rp0_freq;            /* Non-overclocked max frequency. */
  1024.         u32 cz_freq;
  1025.  
  1026.         u32 ei_interrupt_count;
  1027.  
  1028.         int last_adj;
  1029.         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
  1030.  
  1031.         bool enabled;
  1032.         struct delayed_work delayed_resume_work;
  1033.  
  1034.         /* manual wa residency calculations */
  1035.         struct intel_rps_ei up_ei, down_ei;
  1036.  
  1037.         /*
  1038.          * Protects RPS/RC6 register access and PCU communication.
  1039.          * Must be taken after struct_mutex if nested.
  1040.          */
  1041.         struct mutex hw_lock;
  1042. };
  1043.  
  1044. /* defined intel_pm.c */
  1045. extern spinlock_t mchdev_lock;
  1046.  
  1047. struct intel_ilk_power_mgmt {
  1048.         u8 cur_delay;
  1049.         u8 min_delay;
  1050.         u8 max_delay;
  1051.         u8 fmax;
  1052.         u8 fstart;
  1053.  
  1054.         u64 last_count1;
  1055.         unsigned long last_time1;
  1056.         unsigned long chipset_power;
  1057.         u64 last_count2;
  1058.         u64 last_time2;
  1059.         unsigned long gfx_power;
  1060.         u8 corr;
  1061.  
  1062.         int c_m;
  1063.         int r_t;
  1064.  
  1065.         struct drm_i915_gem_object *pwrctx;
  1066.         struct drm_i915_gem_object *renderctx;
  1067. };
  1068.  
  1069. struct drm_i915_private;
  1070. struct i915_power_well;
  1071.  
  1072. struct i915_power_well_ops {
  1073.         /*
  1074.          * Synchronize the well's hw state to match the current sw state, for
  1075.          * example enable/disable it based on the current refcount. Called
  1076.          * during driver init and resume time, possibly after first calling
  1077.          * the enable/disable handlers.
  1078.          */
  1079.         void (*sync_hw)(struct drm_i915_private *dev_priv,
  1080.                         struct i915_power_well *power_well);
  1081.         /*
  1082.          * Enable the well and resources that depend on it (for example
  1083.          * interrupts located on the well). Called after the 0->1 refcount
  1084.          * transition.
  1085.          */
  1086.         void (*enable)(struct drm_i915_private *dev_priv,
  1087.                        struct i915_power_well *power_well);
  1088.         /*
  1089.          * Disable the well and resources that depend on it. Called after
  1090.          * the 1->0 refcount transition.
  1091.          */
  1092.         void (*disable)(struct drm_i915_private *dev_priv,
  1093.                         struct i915_power_well *power_well);
  1094.         /* Returns the hw enabled state. */
  1095.         bool (*is_enabled)(struct drm_i915_private *dev_priv,
  1096.                            struct i915_power_well *power_well);
  1097. };
  1098.  
  1099. /* Power well structure for haswell */
  1100. struct i915_power_well {
  1101.         const char *name;
  1102.         bool always_on;
  1103.         /* power well enable/disable usage count */
  1104.         int count;
  1105.         /* cached hw enabled state */
  1106.         bool hw_enabled;
  1107.         unsigned long domains;
  1108.         unsigned long data;
  1109.         const struct i915_power_well_ops *ops;
  1110. };
  1111.  
  1112. struct i915_power_domains {
  1113.         /*
  1114.          * Power wells needed for initialization at driver init and suspend
  1115.          * time are on. They are kept on until after the first modeset.
  1116.          */
  1117.         bool init_power_on;
  1118.         bool initializing;
  1119.         int power_well_count;
  1120.  
  1121.         struct mutex lock;
  1122.         int domain_use_count[POWER_DOMAIN_NUM];
  1123.         struct i915_power_well *power_wells;
  1124. };
  1125.  
  1126. #define MAX_L3_SLICES 2
  1127. struct intel_l3_parity {
  1128.         u32 *remap_info[MAX_L3_SLICES];
  1129.         struct work_struct error_work;
  1130.         int which_slice;
  1131. };
  1132.  
  1133. struct i915_gem_mm {
  1134.         /** Memory allocator for GTT stolen memory */
  1135.         struct drm_mm stolen;
  1136.         /** List of all objects in gtt_space. Used to restore gtt
  1137.          * mappings on resume */
  1138.         struct list_head bound_list;
  1139.         /**
  1140.          * List of objects which are not bound to the GTT (thus
  1141.          * are idle and not used by the GPU) but still have
  1142.          * (presumably uncached) pages still attached.
  1143.          */
  1144.         struct list_head unbound_list;
  1145.  
  1146.         /** Usable portion of the GTT for GEM */
  1147.         unsigned long stolen_base; /* limited to low memory (32-bit) */
  1148.  
  1149.         /** PPGTT used for aliasing the PPGTT with the GTT */
  1150.         struct i915_hw_ppgtt *aliasing_ppgtt;
  1151.  
  1152.         /** LRU list of objects with fence regs on them. */
  1153.         struct list_head fence_list;
  1154.  
  1155.         /**
  1156.          * We leave the user IRQ off as much as possible,
  1157.          * but this means that requests will finish and never
  1158.          * be retired once the system goes idle. Set a timer to
  1159.          * fire periodically while the ring is running. When it
  1160.          * fires, go retire requests.
  1161.          */
  1162.         struct delayed_work retire_work;
  1163.  
  1164.         /**
  1165.          * When we detect an idle GPU, we want to turn on
  1166.          * powersaving features. So once we see that there
  1167.          * are no more requests outstanding and no more
  1168.          * arrive within a small period of time, we fire
  1169.          * off the idle_work.
  1170.          */
  1171.         struct delayed_work idle_work;
  1172.  
  1173.         /**
  1174.          * Are we in a non-interruptible section of code like
  1175.          * modesetting?
  1176.          */
  1177.         bool interruptible;
  1178.  
  1179.         /**
  1180.          * Is the GPU currently considered idle, or busy executing userspace
  1181.          * requests?  Whilst idle, we attempt to power down the hardware and
  1182.          * display clocks. In order to reduce the effect on performance, there
  1183.          * is a slight delay before we do so.
  1184.          */
  1185.         bool busy;
  1186.  
  1187.         /* the indicator for dispatch video commands on two BSD rings */
  1188.         int bsd_ring_dispatch_index;
  1189.  
  1190.         /** Bit 6 swizzling required for X tiling */
  1191.         uint32_t bit_6_swizzle_x;
  1192.         /** Bit 6 swizzling required for Y tiling */
  1193.         uint32_t bit_6_swizzle_y;
  1194.  
  1195.         /* accounting, useful for userland debugging */
  1196.         spinlock_t object_stat_lock;
  1197.         size_t object_memory;
  1198.         u32 object_count;
  1199. };
  1200.  
  1201. struct drm_i915_error_state_buf {
  1202.         struct drm_i915_private *i915;
  1203.         unsigned bytes;
  1204.         unsigned size;
  1205.         int err;
  1206.         u8 *buf;
  1207.         loff_t start;
  1208.         loff_t pos;
  1209. };
  1210.  
  1211. struct i915_error_state_file_priv {
  1212.         struct drm_device *dev;
  1213.         struct drm_i915_error_state *error;
  1214. };
  1215.  
  1216. struct i915_gpu_error {
  1217.         /* For hangcheck timer */
  1218. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  1219. #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  1220.         /* Hang gpu twice in this window and your context gets banned */
  1221. #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
  1222.  
  1223.         struct timer_list hangcheck_timer;
  1224.  
  1225.         /* For reset and error_state handling. */
  1226.         spinlock_t lock;
  1227.         /* Protected by the above dev->gpu_error.lock. */
  1228.         struct drm_i915_error_state *first_error;
  1229.         struct work_struct work;
  1230.  
  1231.  
  1232.         unsigned long missed_irq_rings;
  1233.  
  1234.         /**
  1235.          * State variable controlling the reset flow and count
  1236.          *
  1237.          * This is a counter which gets incremented when reset is triggered,
  1238.          * and again when reset has been handled. So odd values (lowest bit set)
  1239.          * means that reset is in progress and even values that
  1240.          * (reset_counter >> 1):th reset was successfully completed.
  1241.          *
  1242.          * If reset is not completed succesfully, the I915_WEDGE bit is
  1243.          * set meaning that hardware is terminally sour and there is no
  1244.          * recovery. All waiters on the reset_queue will be woken when
  1245.          * that happens.
  1246.          *
  1247.          * This counter is used by the wait_seqno code to notice that reset
  1248.          * event happened and it needs to restart the entire ioctl (since most
  1249.          * likely the seqno it waited for won't ever signal anytime soon).
  1250.          *
  1251.          * This is important for lock-free wait paths, where no contended lock
  1252.          * naturally enforces the correct ordering between the bail-out of the
  1253.          * waiter and the gpu reset work code.
  1254.          */
  1255.         atomic_t reset_counter;
  1256.  
  1257. #define I915_RESET_IN_PROGRESS_FLAG     1
  1258. #define I915_WEDGED                     (1 << 31)
  1259.  
  1260.         /**
  1261.          * Waitqueue to signal when the reset has completed. Used by clients
  1262.          * that wait for dev_priv->mm.wedged to settle.
  1263.          */
  1264.         wait_queue_head_t reset_queue;
  1265.  
  1266.         /* Userspace knobs for gpu hang simulation;
  1267.          * combines both a ring mask, and extra flags
  1268.          */
  1269.         u32 stop_rings;
  1270. #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
  1271. #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
  1272.  
  1273.         /* For missed irq/seqno simulation. */
  1274.         unsigned int test_irq_rings;
  1275.  
  1276.         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
  1277.         bool reload_in_reset;
  1278. };
  1279.  
  1280. enum modeset_restore {
  1281.         MODESET_ON_LID_OPEN,
  1282.         MODESET_DONE,
  1283.         MODESET_SUSPENDED,
  1284. };
  1285.  
  1286. struct ddi_vbt_port_info {
  1287.         /*
  1288.          * This is an index in the HDMI/DVI DDI buffer translation table.
  1289.          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
  1290.          * populate this field.
  1291.          */
  1292. #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
  1293.         uint8_t hdmi_level_shift;
  1294.  
  1295.         uint8_t supports_dvi:1;
  1296.         uint8_t supports_hdmi:1;
  1297.         uint8_t supports_dp:1;
  1298. };
  1299.  
  1300. enum drrs_support_type {
  1301.         DRRS_NOT_SUPPORTED = 0,
  1302.         STATIC_DRRS_SUPPORT = 1,
  1303.         SEAMLESS_DRRS_SUPPORT = 2
  1304. };
  1305.  
  1306. struct intel_vbt_data {
  1307.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  1308.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  1309.  
  1310.         /* Feature bits */
  1311.         unsigned int int_tv_support:1;
  1312.         unsigned int lvds_dither:1;
  1313.         unsigned int lvds_vbt:1;
  1314.         unsigned int int_crt_support:1;
  1315.         unsigned int lvds_use_ssc:1;
  1316.         unsigned int display_clock_mode:1;
  1317.         unsigned int fdi_rx_polarity_inverted:1;
  1318.         unsigned int has_mipi:1;
  1319.         int lvds_ssc_freq;
  1320.         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  1321.  
  1322.         enum drrs_support_type drrs_type;
  1323.  
  1324.         /* eDP */
  1325.         int edp_rate;
  1326.         int edp_lanes;
  1327.         int edp_preemphasis;
  1328.         int edp_vswing;
  1329.         bool edp_initialized;
  1330.         bool edp_support;
  1331.         int edp_bpp;
  1332.         struct edp_power_seq edp_pps;
  1333.  
  1334.         struct {
  1335.                 u16 pwm_freq_hz;
  1336.                 bool present;
  1337.                 bool active_low_pwm;
  1338.                 u8 min_brightness;      /* min_brightness/255 of max */
  1339.         } backlight;
  1340.  
  1341.         /* MIPI DSI */
  1342.         struct {
  1343.                 u16 port;
  1344.                 u16 panel_id;
  1345.                 struct mipi_config *config;
  1346.                 struct mipi_pps_data *pps;
  1347.                 u8 seq_version;
  1348.                 u32 size;
  1349.                 u8 *data;
  1350.                 u8 *sequence[MIPI_SEQ_MAX];
  1351.         } dsi;
  1352.  
  1353.         int crt_ddc_pin;
  1354.  
  1355.         int child_dev_num;
  1356.         union child_device_config *child_dev;
  1357.  
  1358.         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
  1359. };
  1360.  
  1361. enum intel_ddb_partitioning {
  1362.         INTEL_DDB_PART_1_2,
  1363.         INTEL_DDB_PART_5_6, /* IVB+ */
  1364. };
  1365.  
  1366. struct intel_wm_level {
  1367.         bool enable;
  1368.         uint32_t pri_val;
  1369.         uint32_t spr_val;
  1370.         uint32_t cur_val;
  1371.         uint32_t fbc_val;
  1372. };
  1373.  
  1374. struct ilk_wm_values {
  1375.         uint32_t wm_pipe[3];
  1376.         uint32_t wm_lp[3];
  1377.         uint32_t wm_lp_spr[3];
  1378.         uint32_t wm_linetime[3];
  1379.         bool enable_fbc_wm;
  1380.         enum intel_ddb_partitioning partitioning;
  1381. };
  1382.  
  1383. struct skl_ddb_entry {
  1384.         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
  1385. };
  1386.  
  1387. static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
  1388. {
  1389.         return entry->end - entry->start;
  1390. }
  1391.  
  1392. static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
  1393.                                        const struct skl_ddb_entry *e2)
  1394. {
  1395.         if (e1->start == e2->start && e1->end == e2->end)
  1396.                 return true;
  1397.  
  1398.         return false;
  1399. }
  1400.  
  1401. struct skl_ddb_allocation {
  1402.         struct skl_ddb_entry pipe[I915_MAX_PIPES];
  1403.         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
  1404.         struct skl_ddb_entry cursor[I915_MAX_PIPES];
  1405. };
  1406.  
  1407. struct skl_wm_values {
  1408.         bool dirty[I915_MAX_PIPES];
  1409.         struct skl_ddb_allocation ddb;
  1410.         uint32_t wm_linetime[I915_MAX_PIPES];
  1411.         uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
  1412.         uint32_t cursor[I915_MAX_PIPES][8];
  1413.         uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
  1414.         uint32_t cursor_trans[I915_MAX_PIPES];
  1415. };
  1416.  
  1417. struct skl_wm_level {
  1418.         bool plane_en[I915_MAX_PLANES];
  1419.         bool cursor_en;
  1420.         uint16_t plane_res_b[I915_MAX_PLANES];
  1421.         uint8_t plane_res_l[I915_MAX_PLANES];
  1422.         uint16_t cursor_res_b;
  1423.         uint8_t cursor_res_l;
  1424. };
  1425.  
  1426. /*
  1427.  * This struct helps tracking the state needed for runtime PM, which puts the
  1428.  * device in PCI D3 state. Notice that when this happens, nothing on the
  1429.  * graphics device works, even register access, so we don't get interrupts nor
  1430.  * anything else.
  1431.  *
  1432.  * Every piece of our code that needs to actually touch the hardware needs to
  1433.  * either call intel_runtime_pm_get or call intel_display_power_get with the
  1434.  * appropriate power domain.
  1435.  *
  1436.  * Our driver uses the autosuspend delay feature, which means we'll only really
  1437.  * suspend if we stay with zero refcount for a certain amount of time. The
  1438.  * default value is currently very conservative (see intel_runtime_pm_enable), but
  1439.  * it can be changed with the standard runtime PM files from sysfs.
  1440.  *
  1441.  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
  1442.  * goes back to false exactly before we reenable the IRQs. We use this variable
  1443.  * to check if someone is trying to enable/disable IRQs while they're supposed
  1444.  * to be disabled. This shouldn't happen and we'll print some error messages in
  1445.  * case it happens.
  1446.  *
  1447.  * For more, read the Documentation/power/runtime_pm.txt.
  1448.  */
  1449. struct i915_runtime_pm {
  1450.         bool suspended;
  1451.         bool irqs_enabled;
  1452. };
  1453.  
  1454. enum intel_pipe_crc_source {
  1455.         INTEL_PIPE_CRC_SOURCE_NONE,
  1456.         INTEL_PIPE_CRC_SOURCE_PLANE1,
  1457.         INTEL_PIPE_CRC_SOURCE_PLANE2,
  1458.         INTEL_PIPE_CRC_SOURCE_PF,
  1459.         INTEL_PIPE_CRC_SOURCE_PIPE,
  1460.         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
  1461.         INTEL_PIPE_CRC_SOURCE_TV,
  1462.         INTEL_PIPE_CRC_SOURCE_DP_B,
  1463.         INTEL_PIPE_CRC_SOURCE_DP_C,
  1464.         INTEL_PIPE_CRC_SOURCE_DP_D,
  1465.         INTEL_PIPE_CRC_SOURCE_AUTO,
  1466.         INTEL_PIPE_CRC_SOURCE_MAX,
  1467. };
  1468.  
  1469. struct intel_pipe_crc_entry {
  1470.         uint32_t frame;
  1471.         uint32_t crc[5];
  1472. };
  1473.  
  1474. #define INTEL_PIPE_CRC_ENTRIES_NR       128
  1475. struct intel_pipe_crc {
  1476.         spinlock_t lock;
  1477.         bool opened;            /* exclusive access to the result file */
  1478.         struct intel_pipe_crc_entry *entries;
  1479.         enum intel_pipe_crc_source source;
  1480.         int head, tail;
  1481.         wait_queue_head_t wq;
  1482. };
  1483.  
  1484. struct i915_frontbuffer_tracking {
  1485.         struct mutex lock;
  1486.  
  1487.         /*
  1488.          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
  1489.          * scheduled flips.
  1490.          */
  1491.         unsigned busy_bits;
  1492.         unsigned flip_bits;
  1493. };
  1494.  
  1495. struct i915_wa_reg {
  1496.         u32 addr;
  1497.         u32 value;
  1498.         /* bitmask representing WA bits */
  1499.         u32 mask;
  1500. };
  1501.  
  1502. #define I915_MAX_WA_REGS 16
  1503.  
  1504. struct i915_workarounds {
  1505.         struct i915_wa_reg reg[I915_MAX_WA_REGS];
  1506.         u32 count;
  1507. };
  1508.  
  1509. struct drm_i915_private {
  1510.         struct drm_device *dev;
  1511.  
  1512.         const struct intel_device_info info;
  1513.  
  1514.         int relative_constants_mode;
  1515.  
  1516.         void __iomem *regs;
  1517.  
  1518.         struct intel_uncore uncore;
  1519.  
  1520.         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  1521.  
  1522.  
  1523.         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  1524.          * controller on different i2c buses. */
  1525.         struct mutex gmbus_mutex;
  1526.  
  1527.         /**
  1528.          * Base address of the gmbus and gpio block.
  1529.          */
  1530.         uint32_t gpio_mmio_base;
  1531.  
  1532.         /* MMIO base address for MIPI regs */
  1533.         uint32_t mipi_mmio_base;
  1534.  
  1535.         wait_queue_head_t gmbus_wait_queue;
  1536.  
  1537.         struct pci_dev *bridge_dev;
  1538.         struct intel_engine_cs ring[I915_NUM_RINGS];
  1539.         struct drm_i915_gem_object *semaphore_obj;
  1540.         uint32_t last_seqno, next_seqno;
  1541.  
  1542.         struct drm_dma_handle *status_page_dmah;
  1543.         struct resource mch_res;
  1544.  
  1545.         /* protects the irq masks */
  1546.         spinlock_t irq_lock;
  1547.  
  1548.         /* protects the mmio flip data */
  1549.         spinlock_t mmio_flip_lock;
  1550.  
  1551.         bool display_irqs_enabled;
  1552.  
  1553.         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
  1554. //      struct pm_qos_request pm_qos;
  1555.  
  1556.         /* DPIO indirect register protection */
  1557.         struct mutex dpio_lock;
  1558.  
  1559.         /** Cached value of IMR to avoid reads in updating the bitfield */
  1560.         union {
  1561.         u32 irq_mask;
  1562.                 u32 de_irq_mask[I915_MAX_PIPES];
  1563.         };
  1564.         u32 gt_irq_mask;
  1565.         u32 pm_irq_mask;
  1566.         u32 pm_rps_events;
  1567.         u32 pipestat_irq_mask[I915_MAX_PIPES];
  1568.  
  1569.         struct work_struct hotplug_work;
  1570.         struct {
  1571.                 unsigned long hpd_last_jiffies;
  1572.                 int hpd_cnt;
  1573.                 enum {
  1574.                         HPD_ENABLED = 0,
  1575.                         HPD_DISABLED = 1,
  1576.                         HPD_MARK_DISABLED = 2
  1577.                 } hpd_mark;
  1578.         } hpd_stats[HPD_NUM_PINS];
  1579.         u32 hpd_event_bits;
  1580.         struct delayed_work hotplug_reenable_work;
  1581.  
  1582.         struct i915_fbc fbc;
  1583.         struct i915_drrs drrs;
  1584.         struct intel_opregion opregion;
  1585.         struct intel_vbt_data vbt;
  1586.  
  1587.         bool preserve_bios_swizzle;
  1588.  
  1589.         /* overlay */
  1590.         struct intel_overlay *overlay;
  1591.  
  1592.         /* backlight registers and fields in struct intel_panel */
  1593.         struct mutex backlight_lock;
  1594.  
  1595.         /* LVDS info */
  1596.         bool no_aux_handshake;
  1597.  
  1598.         /* protects panel power sequencer state */
  1599.         struct mutex pps_mutex;
  1600.  
  1601.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  1602.         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  1603.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  1604.  
  1605.         unsigned int fsb_freq, mem_freq, is_ddr3;
  1606.         unsigned int vlv_cdclk_freq;
  1607.         unsigned int hpll_freq;
  1608.  
  1609.         /**
  1610.          * wq - Driver workqueue for GEM.
  1611.          *
  1612.          * NOTE: Work items scheduled here are not allowed to grab any modeset
  1613.          * locks, for otherwise the flushing done in the pageflip code will
  1614.          * result in deadlocks.
  1615.          */
  1616.         struct workqueue_struct *wq;
  1617.  
  1618.         /* Display functions */
  1619.         struct drm_i915_display_funcs display;
  1620.  
  1621.         /* PCH chipset type */
  1622.         enum intel_pch pch_type;
  1623.         unsigned short pch_id;
  1624.  
  1625.         unsigned long quirks;
  1626.  
  1627.         enum modeset_restore modeset_restore;
  1628.         struct mutex modeset_restore_lock;
  1629.  
  1630.         struct list_head vm_list; /* Global list of all address spaces */
  1631.         struct i915_gtt gtt; /* VM representing the global address space */
  1632.  
  1633.         struct i915_gem_mm mm;
  1634.         DECLARE_HASHTABLE(mm_structs, 7);
  1635.         struct mutex mm_lock;
  1636.  
  1637.         /* Kernel Modesetting */
  1638.  
  1639.     struct sdvo_device_mapping sdvo_mappings[2];
  1640.  
  1641.         struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
  1642.         struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
  1643.         wait_queue_head_t pending_flip_queue;
  1644.  
  1645. #ifdef CONFIG_DEBUG_FS
  1646.         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
  1647. #endif
  1648.  
  1649.         int num_shared_dpll;
  1650.         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
  1651.         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
  1652.  
  1653.         struct i915_workarounds workarounds;
  1654.  
  1655.         /* Reclocking support */
  1656.         bool render_reclock_avail;
  1657.         bool lvds_downclock_avail;
  1658.         /* indicates the reduced downclock for LVDS*/
  1659.         int lvds_downclock;
  1660.  
  1661.         struct i915_frontbuffer_tracking fb_tracking;
  1662.  
  1663.         u16 orig_clock;
  1664.  
  1665.         bool mchbar_need_disable;
  1666.  
  1667.         struct intel_l3_parity l3_parity;
  1668.  
  1669.         /* Cannot be determined by PCIID. You must always read a register. */
  1670.         size_t ellc_size;
  1671.  
  1672.         /* gen6+ rps state */
  1673.         struct intel_gen6_power_mgmt rps;
  1674.  
  1675.         /* ilk-only ips/rps state. Everything in here is protected by the global
  1676.          * mchdev_lock in intel_pm.c */
  1677.         struct intel_ilk_power_mgmt ips;
  1678.  
  1679.         struct i915_power_domains power_domains;
  1680.  
  1681.         struct i915_psr psr;
  1682.  
  1683.         struct i915_gpu_error gpu_error;
  1684.  
  1685.         struct drm_i915_gem_object *vlv_pctx;
  1686.  
  1687. #ifdef CONFIG_DRM_I915_FBDEV
  1688.         /* list of fbdev register on this device */
  1689.     struct intel_fbdev *fbdev;
  1690.         struct work_struct fbdev_suspend_work;
  1691. #endif
  1692.  
  1693.         struct drm_property *broadcast_rgb_property;
  1694.         struct drm_property *force_audio_property;
  1695.  
  1696.         uint32_t hw_context_size;
  1697.         struct list_head context_list;
  1698.  
  1699.         u32 fdi_rx_config;
  1700.  
  1701.         u32 suspend_count;
  1702.         struct i915_suspend_saved_registers regfile;
  1703.         struct vlv_s0ix_state vlv_s0ix_state;
  1704.  
  1705.         struct {
  1706.                 /*
  1707.                  * Raw watermark latency values:
  1708.                  * in 0.1us units for WM0,
  1709.                  * in 0.5us units for WM1+.
  1710.                  */
  1711.                 /* primary */
  1712.                 uint16_t pri_latency[5];
  1713.                 /* sprite */
  1714.                 uint16_t spr_latency[5];
  1715.                 /* cursor */
  1716.                 uint16_t cur_latency[5];
  1717.                 /*
  1718.                  * Raw watermark memory latency values
  1719.                  * for SKL for all 8 levels
  1720.                  * in 1us units.
  1721.                  */
  1722.                 uint16_t skl_latency[8];
  1723.  
  1724.                 /*
  1725.                  * The skl_wm_values structure is a bit too big for stack
  1726.                  * allocation, so we keep the staging struct where we store
  1727.                  * intermediate results here instead.
  1728.                  */
  1729.                 struct skl_wm_values skl_results;
  1730.  
  1731.                 /* current hardware state */
  1732.                 union {
  1733.                 struct ilk_wm_values hw;
  1734.                         struct skl_wm_values skl_hw;
  1735.                 };
  1736.         } wm;
  1737.  
  1738.         struct i915_runtime_pm pm;
  1739.  
  1740.         struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
  1741.         u32 long_hpd_port_mask;
  1742.         u32 short_hpd_port_mask;
  1743.         struct work_struct dig_port_work;
  1744.  
  1745.         /*
  1746.          * if we get a HPD irq from DP and a HPD irq from non-DP
  1747.          * the non-DP HPD could block the workqueue on a mode config
  1748.          * mutex getting, that userspace may have taken. However
  1749.          * userspace is waiting on the DP workqueue to run which is
  1750.          * blocked behind the non-DP one.
  1751.          */
  1752.         struct workqueue_struct *dp_wq;
  1753.  
  1754.         uint32_t bios_vgacntr;
  1755.  
  1756.         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
  1757.         struct {
  1758.                 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
  1759.                                   struct intel_engine_cs *ring,
  1760.                                   struct intel_context *ctx,
  1761.                                   struct drm_i915_gem_execbuffer2 *args,
  1762.                                   struct list_head *vmas,
  1763.                                   struct drm_i915_gem_object *batch_obj,
  1764.                                   u64 exec_start, u32 flags);
  1765.                 int (*init_rings)(struct drm_device *dev);
  1766.                 void (*cleanup_ring)(struct intel_engine_cs *ring);
  1767.                 void (*stop_ring)(struct intel_engine_cs *ring);
  1768.         } gt;
  1769.  
  1770.         /*
  1771.          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
  1772.          * will be rejected. Instead look for a better place.
  1773.          */
  1774. };
  1775.  
  1776. static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
  1777. {
  1778.         return dev->dev_private;
  1779. }
  1780.  
  1781. /* Iterate over initialised rings */
  1782. #define for_each_ring(ring__, dev_priv__, i__) \
  1783.         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  1784.                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  1785.  
  1786. enum hdmi_force_audio {
  1787.         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
  1788.         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
  1789.         HDMI_AUDIO_AUTO,                /* trust EDID */
  1790.         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
  1791. };
  1792.  
  1793. #define I915_GTT_OFFSET_NONE ((u32)-1)
  1794.  
  1795. struct drm_i915_gem_object_ops {
  1796.         /* Interface between the GEM object and its backing storage.
  1797.          * get_pages() is called once prior to the use of the associated set
  1798.          * of pages before to binding them into the GTT, and put_pages() is
  1799.          * called after we no longer need them. As we expect there to be
  1800.          * associated cost with migrating pages between the backing storage
  1801.          * and making them available for the GPU (e.g. clflush), we may hold
  1802.          * onto the pages after they are no longer referenced by the GPU
  1803.          * in case they may be used again shortly (for example migrating the
  1804.          * pages to a different memory domain within the GTT). put_pages()
  1805.          * will therefore most likely be called when the object itself is
  1806.          * being released or under memory pressure (where we attempt to
  1807.          * reap pages for the shrinker).
  1808.          */
  1809.         int (*get_pages)(struct drm_i915_gem_object *);
  1810.         void (*put_pages)(struct drm_i915_gem_object *);
  1811.         int (*dmabuf_export)(struct drm_i915_gem_object *);
  1812.         void (*release)(struct drm_i915_gem_object *);
  1813. };
  1814.  
  1815. /*
  1816.  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
  1817.  * considered to be the frontbuffer for the given plane interface-vise. This
  1818.  * doesn't mean that the hw necessarily already scans it out, but that any
  1819.  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
  1820.  *
  1821.  * We have one bit per pipe and per scanout plane type.
  1822.  */
  1823. #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
  1824. #define INTEL_FRONTBUFFER_BITS \
  1825.         (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
  1826. #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
  1827.         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
  1828. #define INTEL_FRONTBUFFER_CURSOR(pipe) \
  1829.         (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
  1830. #define INTEL_FRONTBUFFER_SPRITE(pipe) \
  1831.         (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
  1832. #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
  1833.         (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
  1834. #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
  1835.         (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
  1836.  
  1837. struct drm_i915_gem_object {
  1838.     struct drm_gem_object base;
  1839.  
  1840.         const struct drm_i915_gem_object_ops *ops;
  1841.  
  1842.         /** List of VMAs backed by this object */
  1843.         struct list_head vma_list;
  1844.  
  1845.         /** Stolen memory for this object, instead of being backed by shmem. */
  1846.         struct drm_mm_node *stolen;
  1847.         struct list_head global_list;
  1848.  
  1849.     struct list_head ring_list;
  1850.         /** Used in execbuf to temporarily hold a ref */
  1851.         struct list_head obj_exec_link;
  1852.  
  1853.     /**
  1854.          * This is set if the object is on the active lists (has pending
  1855.          * rendering and so a non-zero seqno), and is not set if it i s on
  1856.          * inactive (ready to be unbound) list.
  1857.      */
  1858.         unsigned int active:1;
  1859.  
  1860.     /**
  1861.      * This is set if the object has been written to since last bound
  1862.      * to the GTT
  1863.      */
  1864.         unsigned int dirty:1;
  1865.  
  1866.     /**
  1867.      * Fence register bits (if any) for this object.  Will be set
  1868.      * as needed when mapped into the GTT.
  1869.      * Protected by dev->struct_mutex.
  1870.      */
  1871.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  1872.  
  1873.     /**
  1874.      * Advice: are the backing pages purgeable?
  1875.      */
  1876.         unsigned int madv:2;
  1877.  
  1878.     /**
  1879.      * Current tiling mode for the object.
  1880.      */
  1881.         unsigned int tiling_mode:2;
  1882.         /**
  1883.          * Whether the tiling parameters for the currently associated fence
  1884.          * register have changed. Note that for the purposes of tracking
  1885.          * tiling changes we also treat the unfenced register, the register
  1886.          * slot that the object occupies whilst it executes a fenced
  1887.          * command (such as BLT on gen2/3), as a "fence".
  1888.          */
  1889.         unsigned int fence_dirty:1;
  1890.  
  1891.     /**
  1892.      * Is the object at the current location in the gtt mappable and
  1893.      * fenceable? Used to avoid costly recalculations.
  1894.      */
  1895.         unsigned int map_and_fenceable:1;
  1896.  
  1897.     /**
  1898.      * Whether the current gtt mapping needs to be mappable (and isn't just
  1899.      * mappable by accident). Track pin and fault separate for a more
  1900.      * accurate mappable working set.
  1901.      */
  1902.         unsigned int fault_mappable:1;
  1903.         unsigned int pin_mappable:1;
  1904.         unsigned int pin_display:1;
  1905.  
  1906.     /*
  1907.          * Is the object to be mapped as read-only to the GPU
  1908.          * Only honoured if hardware has relevant pte bit
  1909.          */
  1910.         unsigned long gt_ro:1;
  1911.         unsigned int cache_level:3;
  1912.  
  1913.         unsigned int has_dma_mapping:1;
  1914.  
  1915.         unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
  1916.  
  1917.         struct sg_table *pages;
  1918.         int pages_pin_count;
  1919.  
  1920.         /* prime dma-buf support */
  1921.         void *dma_buf_vmapping;
  1922.         int vmapping_count;
  1923.  
  1924.         struct intel_engine_cs *ring;
  1925.  
  1926.     /** Breadcrumb of last rendering to the buffer. */
  1927.         uint32_t last_read_seqno;
  1928.         uint32_t last_write_seqno;
  1929.     /** Breadcrumb of last fenced GPU access to the buffer. */
  1930.     uint32_t last_fenced_seqno;
  1931.  
  1932.     /** Current tiling stride for the object, if it's tiled. */
  1933.     uint32_t stride;
  1934.  
  1935.         /** References from framebuffers, locks out tiling changes. */
  1936.         unsigned long framebuffer_references;
  1937.  
  1938.     /** Record of address bit 17 of each page at last unbind. */
  1939.     unsigned long *bit_17;
  1940.  
  1941.     /** User space pin count and filp owning the pin */
  1942.         unsigned long user_pin_count;
  1943.     struct drm_file *pin_filp;
  1944.  
  1945.         union {
  1946.     /** for phy allocated objects */
  1947.                 struct drm_dma_handle *phys_handle;
  1948.  
  1949.                 struct i915_gem_userptr {
  1950.                         uintptr_t ptr;
  1951.                         unsigned read_only :1;
  1952.                         unsigned workers :4;
  1953. #define I915_GEM_USERPTR_MAX_WORKERS 15
  1954.  
  1955.                         struct i915_mm_struct *mm;
  1956.                         struct i915_mmu_object *mmu_object;
  1957.                         struct work_struct *work;
  1958.                 } userptr;
  1959.         };
  1960. };
  1961. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  1962.  
  1963. void i915_gem_track_fb(struct drm_i915_gem_object *old,
  1964.                        struct drm_i915_gem_object *new,
  1965.                        unsigned frontbuffer_bits);
  1966.  
  1967. /**
  1968.  * Request queue structure.
  1969.  *
  1970.  * The request queue allows us to note sequence numbers that have been emitted
  1971.  * and may be associated with active buffers to be retired.
  1972.  *
  1973.  * By keeping this list, we can avoid having to do questionable
  1974.  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  1975.  * an emission time with seqnos for tracking how far ahead of the GPU we are.
  1976.  */
  1977. struct drm_i915_gem_request {
  1978.         /** On Which ring this request was generated */
  1979.         struct intel_engine_cs *ring;
  1980.  
  1981.         /** GEM sequence number associated with this request. */
  1982.         uint32_t seqno;
  1983.  
  1984.         /** Position in the ringbuffer of the start of the request */
  1985.         u32 head;
  1986.  
  1987.         /** Position in the ringbuffer of the end of the request */
  1988.         u32 tail;
  1989.  
  1990.         /** Context related to this request */
  1991.         struct intel_context *ctx;
  1992.  
  1993.         /** Batch buffer related to this request if any */
  1994.         struct drm_i915_gem_object *batch_obj;
  1995.  
  1996.         /** Time at which this request was emitted, in jiffies. */
  1997.         unsigned long emitted_jiffies;
  1998.  
  1999.         /** global list entry for this request */
  2000.         struct list_head list;
  2001.  
  2002.         struct drm_i915_file_private *file_priv;
  2003.         /** file_priv list entry for this request */
  2004.         struct list_head client_list;
  2005. };
  2006.  
  2007. struct drm_i915_file_private {
  2008.         struct drm_i915_private *dev_priv;
  2009.         struct drm_file *file;
  2010.  
  2011.         struct {
  2012.                 spinlock_t lock;
  2013.                 struct list_head request_list;
  2014.                 struct delayed_work idle_work;
  2015.         } mm;
  2016.         struct idr context_idr;
  2017.  
  2018.         atomic_t rps_wait_boost;
  2019.         struct  intel_engine_cs *bsd_ring;
  2020. };
  2021.  
  2022. /*
  2023.  * A command that requires special handling by the command parser.
  2024.  */
  2025. struct drm_i915_cmd_descriptor {
  2026.         /*
  2027.          * Flags describing how the command parser processes the command.
  2028.          *
  2029.          * CMD_DESC_FIXED: The command has a fixed length if this is set,
  2030.          *                 a length mask if not set
  2031.          * CMD_DESC_SKIP: The command is allowed but does not follow the
  2032.          *                standard length encoding for the opcode range in
  2033.          *                which it falls
  2034.          * CMD_DESC_REJECT: The command is never allowed
  2035.          * CMD_DESC_REGISTER: The command should be checked against the
  2036.          *                    register whitelist for the appropriate ring
  2037.          * CMD_DESC_MASTER: The command is allowed if the submitting process
  2038.          *                  is the DRM master
  2039.          */
  2040.         u32 flags;
  2041. #define CMD_DESC_FIXED    (1<<0)
  2042. #define CMD_DESC_SKIP     (1<<1)
  2043. #define CMD_DESC_REJECT   (1<<2)
  2044. #define CMD_DESC_REGISTER (1<<3)
  2045. #define CMD_DESC_BITMASK  (1<<4)
  2046. #define CMD_DESC_MASTER   (1<<5)
  2047.  
  2048.         /*
  2049.          * The command's unique identification bits and the bitmask to get them.
  2050.          * This isn't strictly the opcode field as defined in the spec and may
  2051.          * also include type, subtype, and/or subop fields.
  2052.          */
  2053.         struct {
  2054.                 u32 value;
  2055.                 u32 mask;
  2056.         } cmd;
  2057.  
  2058.         /*
  2059.          * The command's length. The command is either fixed length (i.e. does
  2060.          * not include a length field) or has a length field mask. The flag
  2061.          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
  2062.          * a length mask. All command entries in a command table must include
  2063.          * length information.
  2064.          */
  2065.         union {
  2066.                 u32 fixed;
  2067.                 u32 mask;
  2068.         } length;
  2069.  
  2070.         /*
  2071.          * Describes where to find a register address in the command to check
  2072.          * against the ring's register whitelist. Only valid if flags has the
  2073.          * CMD_DESC_REGISTER bit set.
  2074.          */
  2075.         struct {
  2076.                 u32 offset;
  2077.                 u32 mask;
  2078.         } reg;
  2079.  
  2080. #define MAX_CMD_DESC_BITMASKS 3
  2081.         /*
  2082.          * Describes command checks where a particular dword is masked and
  2083.          * compared against an expected value. If the command does not match
  2084.          * the expected value, the parser rejects it. Only valid if flags has
  2085.          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
  2086.          * are valid.
  2087.          *
  2088.          * If the check specifies a non-zero condition_mask then the parser
  2089.          * only performs the check when the bits specified by condition_mask
  2090.          * are non-zero.
  2091.          */
  2092.         struct {
  2093.                 u32 offset;
  2094.                 u32 mask;
  2095.                 u32 expected;
  2096.                 u32 condition_offset;
  2097.                 u32 condition_mask;
  2098.         } bits[MAX_CMD_DESC_BITMASKS];
  2099. };
  2100.  
  2101. /*
  2102.  * A table of commands requiring special handling by the command parser.
  2103.  *
  2104.  * Each ring has an array of tables. Each table consists of an array of command
  2105.  * descriptors, which must be sorted with command opcodes in ascending order.
  2106.  */
  2107. struct drm_i915_cmd_table {
  2108.         const struct drm_i915_cmd_descriptor *table;
  2109.         int count;
  2110. };
  2111.  
  2112. /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
  2113. #define __I915__(p) ({ \
  2114.         struct drm_i915_private *__p; \
  2115.         if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
  2116.                 __p = (struct drm_i915_private *)p; \
  2117.         else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
  2118.                 __p = to_i915((struct drm_device *)p); \
  2119.         else \
  2120.                 BUILD_BUG(); \
  2121.         __p; \
  2122. })
  2123. #define INTEL_INFO(p)   (&__I915__(p)->info)
  2124. #define INTEL_DEVID(p)  (INTEL_INFO(p)->device_id)
  2125.  
  2126. #define IS_I830(dev)            (INTEL_DEVID(dev) == 0x3577)
  2127. #define IS_845G(dev)            (INTEL_DEVID(dev) == 0x2562)
  2128. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  2129. #define IS_I865G(dev)           (INTEL_DEVID(dev) == 0x2572)
  2130. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  2131. #define IS_I915GM(dev)          (INTEL_DEVID(dev) == 0x2592)
  2132. #define IS_I945G(dev)           (INTEL_DEVID(dev) == 0x2772)
  2133. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  2134. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  2135. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  2136. #define IS_GM45(dev)            (INTEL_DEVID(dev) == 0x2A42)
  2137. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  2138. #define IS_PINEVIEW_G(dev)      (INTEL_DEVID(dev) == 0xa001)
  2139. #define IS_PINEVIEW_M(dev)      (INTEL_DEVID(dev) == 0xa011)
  2140. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  2141. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  2142. #define IS_IRONLAKE_M(dev)      (INTEL_DEVID(dev) == 0x0046)
  2143. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  2144. #define IS_IVB_GT1(dev)         (INTEL_DEVID(dev) == 0x0156 || \
  2145.                                  INTEL_DEVID(dev) == 0x0152 || \
  2146.                                  INTEL_DEVID(dev) == 0x015a)
  2147. #define IS_SNB_GT1(dev)         (INTEL_DEVID(dev) == 0x0102 || \
  2148.                                  INTEL_DEVID(dev) == 0x0106 || \
  2149.                                  INTEL_DEVID(dev) == 0x010A)
  2150. #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
  2151. #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
  2152. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  2153. #define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
  2154. #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
  2155. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  2156. #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
  2157.                                  (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
  2158. #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
  2159.                                  ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
  2160.                                  (INTEL_DEVID(dev) & 0xf) == 0x6 || \
  2161.                                  (INTEL_DEVID(dev) & 0xf) == 0xe))
  2162. #define IS_BDW_GT3(dev)         (IS_BROADWELL(dev) && \
  2163.                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
  2164. #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
  2165.                                  (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
  2166. #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
  2167.                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
  2168. /* ULX machines are also considered ULT. */
  2169. #define IS_HSW_ULX(dev)         (INTEL_DEVID(dev) == 0x0A0E || \
  2170.                                  INTEL_DEVID(dev) == 0x0A1E)
  2171. #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
  2172.  
  2173. /*
  2174.  * The genX designation typically refers to the render engine, so render
  2175.  * capability related checks should use IS_GEN, while display and other checks
  2176.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  2177.  * chips, etc.).
  2178.  */
  2179. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  2180. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  2181. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  2182. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  2183. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  2184. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  2185. #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
  2186. #define IS_GEN9(dev)    (INTEL_INFO(dev)->gen == 9)
  2187.  
  2188. #define RENDER_RING             (1<<RCS)
  2189. #define BSD_RING                (1<<VCS)
  2190. #define BLT_RING                (1<<BCS)
  2191. #define VEBOX_RING              (1<<VECS)
  2192. #define BSD2_RING               (1<<VCS2)
  2193. #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
  2194. #define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
  2195. #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
  2196. #define HAS_VEBOX(dev)            (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
  2197. #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
  2198. #define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
  2199.                                  __I915__(dev)->ellc_size)
  2200. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  2201.  
  2202. #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
  2203. #define HAS_LOGICAL_RING_CONTEXTS(dev)  (INTEL_INFO(dev)->gen >= 8)
  2204. #define USES_PPGTT(dev)         (i915.enable_ppgtt)
  2205. #define USES_FULL_PPGTT(dev)    (i915.enable_ppgtt == 2)
  2206.  
  2207. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  2208. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  2209.  
  2210. /* Early gen2 have a totally busted CS tlb and require pinned batches. */
  2211. #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
  2212. /*
  2213.  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  2214.  * even when in MSI mode. This results in spurious interrupt warnings if the
  2215.  * legacy irq no. is shared with another device. The kernel then disables that
  2216.  * interrupt source and so prevents the other device from working properly.
  2217.  */
  2218. #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
  2219. #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
  2220.  
  2221. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  2222.  * rows, which changed the alignment requirements and fence programming.
  2223.  */
  2224. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  2225.                                                       IS_I915GM(dev)))
  2226. #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  2227. #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
  2228. #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
  2229. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  2230. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  2231.  
  2232. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  2233. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  2234. #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  2235.  
  2236. #define HAS_IPS(dev)            (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
  2237.  
  2238. #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
  2239. #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
  2240. #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
  2241. #define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
  2242.                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
  2243. #define HAS_RC6(dev)            (INTEL_INFO(dev)->gen >= 6)
  2244. #define HAS_RC6p(dev)           (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
  2245.  
  2246. #define INTEL_PCH_DEVICE_ID_MASK                0xff00
  2247. #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
  2248. #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
  2249. #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
  2250. #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
  2251. #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
  2252. #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
  2253. #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
  2254.  
  2255. #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
  2256. #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
  2257. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  2258. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  2259. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  2260. #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
  2261. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  2262.  
  2263. #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
  2264.  
  2265. /* DPF == dynamic parity feature */
  2266. #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  2267. #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
  2268.  
  2269. #define GT_FREQUENCY_MULTIPLIER 50
  2270.  
  2271. #include "i915_trace.h"
  2272.  
  2273.  
  2274. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  2275. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  2276.  
  2277. /* i915_params.c */
  2278. struct i915_params {
  2279.         int modeset;
  2280.         int panel_ignore_lid;
  2281.         unsigned int powersave;
  2282.         int semaphores;
  2283.         unsigned int lvds_downclock;
  2284.         int lvds_channel_mode;
  2285.         int panel_use_ssc;
  2286.         int vbt_sdvo_panel_type;
  2287.         int enable_rc6;
  2288.         int enable_fbc;
  2289.         int enable_ppgtt;
  2290.         int enable_execlists;
  2291.         int enable_psr;
  2292.         unsigned int preliminary_hw_support;
  2293.         int disable_power_well;
  2294.         int enable_ips;
  2295.         int invert_brightness;
  2296.         int enable_cmd_parser;
  2297.         /* leave bools at the end to not create holes */
  2298.         bool enable_hangcheck;
  2299.         bool fastboot;
  2300.         bool prefault_disable;
  2301.         bool reset;
  2302.         bool disable_display;
  2303.         bool disable_vtd_wa;
  2304.         int use_mmio_flip;
  2305.         bool mmio_debug;
  2306. };
  2307. extern struct i915_params i915 __read_mostly;
  2308.  
  2309.                                 /* i915_dma.c */
  2310. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  2311. extern int i915_driver_unload(struct drm_device *);
  2312. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
  2313. extern void i915_driver_lastclose(struct drm_device * dev);
  2314. extern void i915_driver_preclose(struct drm_device *dev,
  2315.                                  struct drm_file *file);
  2316. extern void i915_driver_postclose(struct drm_device *dev,
  2317.                                   struct drm_file *file);
  2318. extern int i915_driver_device_is_agp(struct drm_device * dev);
  2319. #ifdef CONFIG_COMPAT
  2320. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  2321.                               unsigned long arg);
  2322. #endif
  2323. extern int intel_gpu_reset(struct drm_device *dev);
  2324. extern int i915_reset(struct drm_device *dev);
  2325. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  2326. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  2327. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  2328. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  2329. int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
  2330. void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
  2331.  
  2332. /* i915_irq.c */
  2333. void i915_queue_hangcheck(struct drm_device *dev);
  2334. __printf(3, 4)
  2335. void i915_handle_error(struct drm_device *dev, bool wedged,
  2336.                        const char *fmt, ...);
  2337.  
  2338. extern void intel_irq_init(struct drm_i915_private *dev_priv);
  2339. extern void intel_hpd_init(struct drm_i915_private *dev_priv);
  2340. int intel_irq_install(struct drm_i915_private *dev_priv);
  2341. void intel_irq_uninstall(struct drm_i915_private *dev_priv);
  2342.  
  2343. extern void intel_uncore_sanitize(struct drm_device *dev);
  2344. extern void intel_uncore_early_sanitize(struct drm_device *dev,
  2345.                                         bool restore_forcewake);
  2346. extern void intel_uncore_init(struct drm_device *dev);
  2347. extern void intel_uncore_check_errors(struct drm_device *dev);
  2348. extern void intel_uncore_fini(struct drm_device *dev);
  2349. extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
  2350.  
  2351. void
  2352. i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  2353.                      u32 status_mask);
  2354.  
  2355. void
  2356. i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  2357.                       u32 status_mask);
  2358.  
  2359. void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
  2360. void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
  2361. void
  2362. ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
  2363. void
  2364. ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
  2365. void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
  2366.                                   uint32_t interrupt_mask,
  2367.                                   uint32_t enabled_irq_mask);
  2368. #define ibx_enable_display_interrupt(dev_priv, bits) \
  2369.         ibx_display_interrupt_update((dev_priv), (bits), (bits))
  2370. #define ibx_disable_display_interrupt(dev_priv, bits) \
  2371.         ibx_display_interrupt_update((dev_priv), (bits), 0)
  2372.  
  2373. /* i915_gem.c */
  2374. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  2375.                           struct drm_file *file_priv);
  2376. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  2377.                          struct drm_file *file_priv);
  2378. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  2379.                           struct drm_file *file_priv);
  2380. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  2381.                         struct drm_file *file_priv);
  2382. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  2383.                         struct drm_file *file_priv);
  2384. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  2385.                               struct drm_file *file_priv);
  2386. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  2387.                              struct drm_file *file_priv);
  2388. void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
  2389.                                         struct intel_engine_cs *ring);
  2390. void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
  2391.                                          struct drm_file *file,
  2392.                                          struct intel_engine_cs *ring,
  2393.                                          struct drm_i915_gem_object *obj);
  2394. int i915_gem_ringbuffer_submission(struct drm_device *dev,
  2395.                                    struct drm_file *file,
  2396.                                    struct intel_engine_cs *ring,
  2397.                                    struct intel_context *ctx,
  2398.                                    struct drm_i915_gem_execbuffer2 *args,
  2399.                                    struct list_head *vmas,
  2400.                                    struct drm_i915_gem_object *batch_obj,
  2401.                                    u64 exec_start, u32 flags);
  2402. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  2403.                         struct drm_file *file_priv);
  2404. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  2405.                          struct drm_file *file_priv);
  2406. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  2407.                        struct drm_file *file_priv);
  2408. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  2409.                          struct drm_file *file_priv);
  2410. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  2411.                         struct drm_file *file_priv);
  2412. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  2413.                                struct drm_file *file);
  2414. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  2415.                                struct drm_file *file);
  2416. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  2417.                             struct drm_file *file_priv);
  2418. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  2419.                            struct drm_file *file_priv);
  2420. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  2421.                         struct drm_file *file_priv);
  2422. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  2423.                         struct drm_file *file_priv);
  2424. int i915_gem_init_userptr(struct drm_device *dev);
  2425. int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
  2426.                            struct drm_file *file);
  2427. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  2428.                                 struct drm_file *file_priv);
  2429. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  2430.                         struct drm_file *file_priv);
  2431. void i915_gem_load(struct drm_device *dev);
  2432. unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
  2433.                               long target,
  2434.                               unsigned flags);
  2435. #define I915_SHRINK_PURGEABLE 0x1
  2436. #define I915_SHRINK_UNBOUND 0x2
  2437. #define I915_SHRINK_BOUND 0x4
  2438. void *i915_gem_object_alloc(struct drm_device *dev);
  2439. void i915_gem_object_free(struct drm_i915_gem_object *obj);
  2440. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  2441.                          const struct drm_i915_gem_object_ops *ops);
  2442. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  2443.                                                   size_t size);
  2444. void i915_init_vm(struct drm_i915_private *dev_priv,
  2445.                   struct i915_address_space *vm);
  2446. void i915_gem_free_object(struct drm_gem_object *obj);
  2447. void i915_gem_vma_destroy(struct i915_vma *vma);
  2448.  
  2449. #define PIN_MAPPABLE 0x1
  2450. #define PIN_NONBLOCK 0x2
  2451. #define PIN_GLOBAL 0x4
  2452. #define PIN_OFFSET_BIAS 0x8
  2453. #define PIN_OFFSET_MASK (~4095)
  2454. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  2455.                                      struct i915_address_space *vm,
  2456.                                      uint32_t alignment,
  2457.                                      uint64_t flags);
  2458. int __must_check i915_vma_unbind(struct i915_vma *vma);
  2459. int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
  2460. void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
  2461. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  2462.  
  2463. int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
  2464.                                     int *needs_clflush);
  2465.  
  2466. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  2467. static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  2468. {
  2469.         struct sg_page_iter sg_iter;
  2470.  
  2471.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
  2472.                 return sg_page_iter_page(&sg_iter);
  2473.  
  2474.         return NULL;
  2475. }
  2476. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  2477. {
  2478.         BUG_ON(obj->pages == NULL);
  2479.         obj->pages_pin_count++;
  2480. }
  2481. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  2482. {
  2483.         BUG_ON(obj->pages_pin_count == 0);
  2484.         obj->pages_pin_count--;
  2485. }
  2486.  
  2487. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  2488. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  2489.                          struct intel_engine_cs *to);
  2490. void i915_vma_move_to_active(struct i915_vma *vma,
  2491.                              struct intel_engine_cs *ring);
  2492. int i915_gem_dumb_create(struct drm_file *file_priv,
  2493.                          struct drm_device *dev,
  2494.                          struct drm_mode_create_dumb *args);
  2495. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  2496.                       uint32_t handle, uint64_t *offset);
  2497. /**
  2498.  * Returns true if seq1 is later than seq2.
  2499.  */
  2500. static inline bool
  2501. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  2502. {
  2503.         return (int32_t)(seq1 - seq2) >= 0;
  2504. }
  2505.  
  2506. int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
  2507. int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
  2508. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  2509. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  2510.  
  2511. bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
  2512. void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
  2513.  
  2514. struct drm_i915_gem_request *
  2515. i915_gem_find_active_request(struct intel_engine_cs *ring);
  2516.  
  2517. bool i915_gem_retire_requests(struct drm_device *dev);
  2518. void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
  2519. int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
  2520.                                       bool interruptible);
  2521. int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
  2522.  
  2523. static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
  2524. {
  2525.         return unlikely(atomic_read(&error->reset_counter)
  2526.                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
  2527. }
  2528.  
  2529. static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
  2530. {
  2531.         return atomic_read(&error->reset_counter) & I915_WEDGED;
  2532. }
  2533.  
  2534. static inline u32 i915_reset_count(struct i915_gpu_error *error)
  2535. {
  2536.         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
  2537. }
  2538.  
  2539. static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
  2540. {
  2541.         return dev_priv->gpu_error.stop_rings == 0 ||
  2542.                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
  2543. }
  2544.  
  2545. static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
  2546. {
  2547.         return dev_priv->gpu_error.stop_rings == 0 ||
  2548.                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
  2549. }
  2550.  
  2551. void i915_gem_reset(struct drm_device *dev);
  2552. bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
  2553. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  2554. int __must_check i915_gem_init(struct drm_device *dev);
  2555. int i915_gem_init_rings(struct drm_device *dev);
  2556. int __must_check i915_gem_init_hw(struct drm_device *dev);
  2557. int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
  2558. void i915_gem_init_swizzling(struct drm_device *dev);
  2559. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  2560. int __must_check i915_gpu_idle(struct drm_device *dev);
  2561. int __must_check i915_gem_suspend(struct drm_device *dev);
  2562. int __i915_add_request(struct intel_engine_cs *ring,
  2563.                                   struct drm_file *file,
  2564.                        struct drm_i915_gem_object *batch_obj,
  2565.                      u32 *seqno);
  2566. #define i915_add_request(ring, seqno) \
  2567.         __i915_add_request(ring, NULL, NULL, seqno)
  2568. int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
  2569.                         unsigned reset_counter,
  2570.                         bool interruptible,
  2571.                         s64 *timeout,
  2572.                         struct drm_i915_file_private *file_priv);
  2573. int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
  2574.                                    uint32_t seqno);
  2575. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  2576. int __must_check
  2577. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  2578.                                   bool write);
  2579. int __must_check
  2580. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  2581. int __must_check
  2582. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  2583.                                      u32 alignment,
  2584.                                      struct intel_engine_cs *pipelined);
  2585. void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
  2586. int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
  2587.                                 int align);
  2588. int i915_gem_open(struct drm_device *dev, struct drm_file *file);
  2589. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  2590.  
  2591. uint32_t
  2592. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
  2593. uint32_t
  2594. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  2595.                             int tiling_mode, bool fenced);
  2596.  
  2597. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  2598.                                     enum i915_cache_level cache_level);
  2599.  
  2600. struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
  2601.                                 struct dma_buf *dma_buf);
  2602.  
  2603. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  2604.                                 struct drm_gem_object *gem_obj, int flags);
  2605.  
  2606. void i915_gem_restore_fences(struct drm_device *dev);
  2607.  
  2608. unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
  2609.                                   struct i915_address_space *vm);
  2610. bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
  2611. bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
  2612.                         struct i915_address_space *vm);
  2613. unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
  2614.                                 struct i915_address_space *vm);
  2615. struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
  2616.                                      struct i915_address_space *vm);
  2617. struct i915_vma *
  2618. i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
  2619.                                   struct i915_address_space *vm);
  2620.  
  2621. struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
  2622. static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
  2623.         struct i915_vma *vma;
  2624.         list_for_each_entry(vma, &obj->vma_list, vma_link)
  2625.                 if (vma->pin_count > 0)
  2626.                         return true;
  2627.         return false;
  2628. }
  2629.  
  2630. /* Some GGTT VM helpers */
  2631. #define i915_obj_to_ggtt(obj) \
  2632.         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
  2633. static inline bool i915_is_ggtt(struct i915_address_space *vm)
  2634. {
  2635.         struct i915_address_space *ggtt =
  2636.                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
  2637.         return vm == ggtt;
  2638. }
  2639.  
  2640. static inline struct i915_hw_ppgtt *
  2641. i915_vm_to_ppgtt(struct i915_address_space *vm)
  2642. {
  2643.         WARN_ON(i915_is_ggtt(vm));
  2644.  
  2645.         return container_of(vm, struct i915_hw_ppgtt, base);
  2646. }
  2647.  
  2648.  
  2649. static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
  2650. {
  2651.         return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
  2652. }
  2653.  
  2654. static inline unsigned long
  2655. i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
  2656. {
  2657.         return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
  2658. }
  2659.  
  2660. static inline unsigned long
  2661. i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
  2662. {
  2663.         return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
  2664. }
  2665.  
  2666. static inline int __must_check
  2667. i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
  2668.                       uint32_t alignment,
  2669.                       unsigned flags)
  2670. {
  2671.         return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
  2672.                                    alignment, flags | PIN_GLOBAL);
  2673. }
  2674.  
  2675. static inline int
  2676. i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
  2677. {
  2678.         return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
  2679. }
  2680.  
  2681. void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
  2682.  
  2683. /* i915_gem_context.c */
  2684. int __must_check i915_gem_context_init(struct drm_device *dev);
  2685. void i915_gem_context_fini(struct drm_device *dev);
  2686. void i915_gem_context_reset(struct drm_device *dev);
  2687. int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
  2688. int i915_gem_context_enable(struct drm_i915_private *dev_priv);
  2689. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  2690. int i915_switch_context(struct intel_engine_cs *ring,
  2691.                         struct intel_context *to);
  2692. struct intel_context *
  2693. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
  2694. void i915_gem_context_free(struct kref *ctx_ref);
  2695. struct drm_i915_gem_object *
  2696. i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
  2697. static inline void i915_gem_context_reference(struct intel_context *ctx)
  2698. {
  2699.         kref_get(&ctx->ref);
  2700. }
  2701.  
  2702. static inline void i915_gem_context_unreference(struct intel_context *ctx)
  2703. {
  2704.         kref_put(&ctx->ref, i915_gem_context_free);
  2705. }
  2706.  
  2707. static inline bool i915_gem_context_is_default(const struct intel_context *c)
  2708. {
  2709.         return c->user_handle == DEFAULT_CONTEXT_HANDLE;
  2710. }
  2711.  
  2712. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  2713.                                   struct drm_file *file);
  2714. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  2715.                                    struct drm_file *file);
  2716.  
  2717. /* i915_gem_evict.c */
  2718. int __must_check i915_gem_evict_something(struct drm_device *dev,
  2719.                                           struct i915_address_space *vm,
  2720.                                           int min_size,
  2721.                                           unsigned alignment,
  2722.                                           unsigned cache_level,
  2723.                                           unsigned long start,
  2724.                                           unsigned long end,
  2725.                                           unsigned flags);
  2726. int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
  2727. int i915_gem_evict_everything(struct drm_device *dev);
  2728.  
  2729. /* belongs in i915_gem_gtt.h */
  2730. static inline void i915_gem_chipset_flush(struct drm_device *dev)
  2731. {
  2732.         if (INTEL_INFO(dev)->gen < 6)
  2733.                 intel_gtt_chipset_flush();
  2734. }
  2735.  
  2736. /* i915_gem_stolen.c */
  2737. int i915_gem_init_stolen(struct drm_device *dev);
  2738. int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
  2739. void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
  2740. void i915_gem_cleanup_stolen(struct drm_device *dev);
  2741. struct drm_i915_gem_object *
  2742. i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
  2743. struct drm_i915_gem_object *
  2744. i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
  2745.                                                u32 stolen_offset,
  2746.                                                u32 gtt_offset,
  2747.                                                u32 size);
  2748.  
  2749. /* i915_gem_tiling.c */
  2750. static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
  2751. {
  2752.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2753.  
  2754.         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
  2755.                 obj->tiling_mode != I915_TILING_NONE;
  2756. }
  2757.  
  2758. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  2759. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  2760. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  2761.  
  2762. /* i915_gem_debug.c */
  2763. #if WATCH_LISTS
  2764. int i915_verify_lists(struct drm_device *dev);
  2765. #else
  2766. #define i915_verify_lists(dev) 0
  2767. #endif
  2768.  
  2769. /* i915_debugfs.c */
  2770. int i915_debugfs_init(struct drm_minor *minor);
  2771. void i915_debugfs_cleanup(struct drm_minor *minor);
  2772. #ifdef CONFIG_DEBUG_FS
  2773. void intel_display_crc_init(struct drm_device *dev);
  2774. #else
  2775. static inline void intel_display_crc_init(struct drm_device *dev) {}
  2776. #endif
  2777.  
  2778. /* i915_gpu_error.c */
  2779. __printf(2, 3)
  2780. void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
  2781. int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
  2782.                             const struct i915_error_state_file_priv *error);
  2783. int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
  2784.                               struct drm_i915_private *i915,
  2785.                               size_t count, loff_t pos);
  2786. static inline void i915_error_state_buf_release(
  2787.         struct drm_i915_error_state_buf *eb)
  2788. {
  2789.         kfree(eb->buf);
  2790. }
  2791. void i915_capture_error_state(struct drm_device *dev, bool wedge,
  2792.                               const char *error_msg);
  2793. void i915_error_state_get(struct drm_device *dev,
  2794.                           struct i915_error_state_file_priv *error_priv);
  2795. void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
  2796. void i915_destroy_error_state(struct drm_device *dev);
  2797.  
  2798. void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
  2799. const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
  2800.  
  2801. /* i915_cmd_parser.c */
  2802. int i915_cmd_parser_get_version(void);
  2803. int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
  2804. void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
  2805. bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
  2806. int i915_parse_cmds(struct intel_engine_cs *ring,
  2807.                     struct drm_i915_gem_object *batch_obj,
  2808.                     u32 batch_start_offset,
  2809.                     bool is_master);
  2810.  
  2811. /* i915_suspend.c */
  2812. extern int i915_save_state(struct drm_device *dev);
  2813. extern int i915_restore_state(struct drm_device *dev);
  2814.  
  2815. /* i915_ums.c */
  2816. void i915_save_display_reg(struct drm_device *dev);
  2817. void i915_restore_display_reg(struct drm_device *dev);
  2818.  
  2819. /* i915_sysfs.c */
  2820. void i915_setup_sysfs(struct drm_device *dev_priv);
  2821. void i915_teardown_sysfs(struct drm_device *dev_priv);
  2822.  
  2823. /* intel_i2c.c */
  2824. extern int intel_setup_gmbus(struct drm_device *dev);
  2825. extern void intel_teardown_gmbus(struct drm_device *dev);
  2826. static inline bool intel_gmbus_is_port_valid(unsigned port)
  2827. {
  2828.         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  2829. }
  2830.  
  2831. extern struct i2c_adapter *intel_gmbus_get_adapter(
  2832.                 struct drm_i915_private *dev_priv, unsigned port);
  2833. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  2834. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  2835. static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  2836. {
  2837.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  2838. }
  2839. extern void intel_i2c_reset(struct drm_device *dev);
  2840.  
  2841. /* intel_opregion.c */
  2842. #ifdef CONFIG_ACPI
  2843. extern int intel_opregion_setup(struct drm_device *dev);
  2844. extern void intel_opregion_init(struct drm_device *dev);
  2845. extern void intel_opregion_fini(struct drm_device *dev);
  2846. extern void intel_opregion_asle_intr(struct drm_device *dev);
  2847. extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
  2848.                                          bool enable);
  2849. extern int intel_opregion_notify_adapter(struct drm_device *dev,
  2850.                                          pci_power_t state);
  2851. #else
  2852. static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
  2853. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  2854. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  2855. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  2856. static inline int
  2857. intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
  2858. {
  2859.         return 0;
  2860. }
  2861. static inline int
  2862. intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
  2863. {
  2864.         return 0;
  2865. }
  2866. #endif
  2867.  
  2868. /* intel_acpi.c */
  2869. #ifdef CONFIG_ACPI
  2870. extern void intel_register_dsm_handler(void);
  2871. extern void intel_unregister_dsm_handler(void);
  2872. #else
  2873. static inline void intel_register_dsm_handler(void) { return; }
  2874. static inline void intel_unregister_dsm_handler(void) { return; }
  2875. #endif /* CONFIG_ACPI */
  2876.  
  2877. /* modesetting */
  2878. extern void intel_modeset_init_hw(struct drm_device *dev);
  2879. extern void intel_modeset_init(struct drm_device *dev);
  2880. extern void intel_modeset_gem_init(struct drm_device *dev);
  2881. extern void intel_modeset_cleanup(struct drm_device *dev);
  2882. extern void intel_connector_unregister(struct intel_connector *);
  2883. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  2884. extern void intel_modeset_setup_hw_state(struct drm_device *dev,
  2885.                                          bool force_restore);
  2886. extern void i915_redisable_vga(struct drm_device *dev);
  2887. extern void i915_redisable_vga_power_on(struct drm_device *dev);
  2888. extern bool intel_fbc_enabled(struct drm_device *dev);
  2889. extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
  2890. extern void intel_disable_fbc(struct drm_device *dev);
  2891. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  2892. extern void intel_init_pch_refclk(struct drm_device *dev);
  2893. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  2894. extern void valleyview_set_rps(struct drm_device *dev, u8 val);
  2895. extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
  2896.                                   bool enable);
  2897. extern void intel_detect_pch(struct drm_device *dev);
  2898. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  2899. extern int intel_enable_rc6(const struct drm_device *dev);
  2900.  
  2901. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  2902. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  2903.                         struct drm_file *file);
  2904. int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
  2905.                                struct drm_file *file);
  2906.  
  2907. void intel_notify_mmio_flip(struct intel_engine_cs *ring);
  2908.  
  2909. /* overlay */
  2910. #ifdef CONFIG_DEBUG_FS
  2911. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  2912. extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
  2913.                                             struct intel_overlay_error_state *error);
  2914.  
  2915. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  2916. extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
  2917.                                             struct drm_device *dev,
  2918.                                             struct intel_display_error_state *error);
  2919. #endif
  2920.  
  2921. /* On SNB platform, before reading ring registers forcewake bit
  2922.  * must be set to prevent GT core from power down and stale values being
  2923.  * returned.
  2924.  */
  2925. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
  2926. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
  2927. void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
  2928.  
  2929. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
  2930. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
  2931.  
  2932. /* intel_sideband.c */
  2933. u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
  2934. void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
  2935. u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  2936. u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
  2937. void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2938. u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
  2939. void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2940. u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
  2941. void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2942. u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
  2943. void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2944. u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
  2945. void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2946. u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
  2947. void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
  2948. u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  2949.                    enum intel_sbi_destination destination);
  2950. void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  2951.                      enum intel_sbi_destination destination);
  2952. u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
  2953. void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2954.  
  2955. int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
  2956. int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
  2957.  
  2958. #define FORCEWAKE_RENDER        (1 << 0)
  2959. #define FORCEWAKE_MEDIA         (1 << 1)
  2960. #define FORCEWAKE_BLITTER       (1 << 2)
  2961. #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
  2962.                                         FORCEWAKE_BLITTER)
  2963.  
  2964.  
  2965. #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
  2966. #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
  2967.  
  2968. #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
  2969. #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
  2970. #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
  2971. #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
  2972.  
  2973. #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
  2974. #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
  2975. #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
  2976. #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
  2977.  
  2978. /* Be very careful with read/write 64-bit values. On 32-bit machines, they
  2979.  * will be implemented using 2 32-bit writes in an arbitrary order with
  2980.  * an arbitrary delay between them. This can cause the hardware to
  2981.  * act upon the intermediate value, possibly leading to corruption and
  2982.  * machine death. You have been warned.
  2983.  */
  2984. #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
  2985. #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
  2986.  
  2987. #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
  2988.                 u32 upper = I915_READ(upper_reg);                       \
  2989.                 u32 lower = I915_READ(lower_reg);                       \
  2990.                 u32 tmp = I915_READ(upper_reg);                         \
  2991.                 if (upper != tmp) {                                     \
  2992.                         upper = tmp;                                    \
  2993.                         lower = I915_READ(lower_reg);                   \
  2994.                         WARN_ON(I915_READ(upper_reg) != upper);         \
  2995.                 }                                                       \
  2996.                 (u64)upper << 32 | lower; })
  2997.  
  2998. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  2999. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  3000.  
  3001. /* "Broadcast RGB" property */
  3002. #define INTEL_BROADCAST_RGB_AUTO 0
  3003. #define INTEL_BROADCAST_RGB_FULL 1
  3004. #define INTEL_BROADCAST_RGB_LIMITED 2
  3005.  
  3006. static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
  3007. {
  3008.         if (IS_VALLEYVIEW(dev))
  3009.                 return VLV_VGACNTRL;
  3010.         else if (INTEL_INFO(dev)->gen >= 5)
  3011.                 return CPU_VGACNTRL;
  3012.         else
  3013.                 return VGACNTRL;
  3014. }
  3015.  
  3016. static inline void __user *to_user_ptr(u64 address)
  3017. {
  3018.         return (void __user *)(uintptr_t)address;
  3019. }
  3020.  
  3021. static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
  3022. {
  3023.         unsigned long j = msecs_to_jiffies(m);
  3024.  
  3025.         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  3026. }
  3027.  
  3028. static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
  3029. {
  3030.         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
  3031. }
  3032.  
  3033. static inline unsigned long
  3034. timespec_to_jiffies_timeout(const struct timespec *value)
  3035. {
  3036.         unsigned long j = timespec_to_jiffies(value);
  3037.  
  3038.         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  3039. }
  3040.  
  3041. /*
  3042.  * If you need to wait X milliseconds between events A and B, but event B
  3043.  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
  3044.  * when event A happened, then just before event B you call this function and
  3045.  * pass the timestamp as the first argument, and X as the second argument.
  3046.  */
  3047. static inline void
  3048. wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
  3049. {
  3050.         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
  3051.  
  3052.         /*
  3053.          * Don't re-read the value of "jiffies" every time since it may change
  3054.          * behind our back and break the math.
  3055.          */
  3056.         tmp_jiffies = jiffies;
  3057.         target_jiffies = timestamp_jiffies +
  3058.                          msecs_to_jiffies_timeout(to_wait_ms);
  3059.  
  3060.         if (time_after(target_jiffies, tmp_jiffies)) {
  3061.                 remaining_jiffies = target_jiffies - tmp_jiffies;
  3062.                 while ((int)remaining_jiffies > 0) {
  3063.                         delay(remaining_jiffies);
  3064.                         remaining_jiffies = target_jiffies - jiffies;
  3065.                 }
  3066.         }
  3067. }
  3068.  
  3069. typedef struct
  3070. {
  3071.   int width;
  3072.   int height;
  3073.   int bpp;
  3074.   int freq;
  3075. }videomode_t;
  3076.  
  3077. struct cmdtable
  3078. {
  3079.     char *key;
  3080.     int   size;
  3081.     int  *val;
  3082. };
  3083.  
  3084. #define CMDENTRY(key, val) {(key), (sizeof(key)-1), &val}
  3085.  
  3086. void parse_cmdline(char *cmdline, struct cmdtable *table, char *log, videomode_t *mode);
  3087. struct drm_i915_gem_object
  3088. *kos_gem_fb_object_create(struct drm_device *dev, u32 gtt_offset, u32 size);
  3089.  
  3090. extern struct drm_i915_gem_object *main_fb_obj;
  3091.  
  3092. static struct drm_i915_gem_object *get_fb_obj()
  3093. {
  3094.     return main_fb_obj;
  3095. };
  3096.  
  3097. #define ioread32(addr)          readl(addr)
  3098.  
  3099.  
  3100. static inline int pm_runtime_get_sync(struct device *dev)
  3101. {
  3102.     return 0;
  3103. }
  3104.  
  3105. static inline int pm_runtime_set_active(struct device *dev)
  3106. {
  3107.     return 0;
  3108. }
  3109.  
  3110. static inline void pm_runtime_disable(struct device *dev)
  3111. {
  3112.  
  3113. }
  3114.  
  3115. static inline int pm_runtime_put_autosuspend(struct device *dev)
  3116. {
  3117.     return 0;
  3118. }
  3119.  
  3120. static inline u8 inb(u16 port)
  3121. {
  3122.         u8 v;
  3123.         asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
  3124.         return v;
  3125. }
  3126.  
  3127. static inline void outb(u8 v, u16 port)
  3128. {
  3129.         asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
  3130. }
  3131.  
  3132. #endif
  3133.