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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include <uapi/drm/i915_drm.h>
  34.  
  35. #include "i915_reg.h"
  36. #include "intel_bios.h"
  37. #include "intel_ringbuffer.h"
  38. #include <linux/scatterlist.h>
  39. //#include <linux/io-mapping.h>
  40. #include <linux/i2c.h>
  41. #include <linux/i2c-algo-bit.h>
  42. #include <drm/intel-gtt.h>
  43. //#include <linux/backlight.h>
  44.  
  45. #include <linux/spinlock.h>
  46. #include <linux/err.h>
  47.  
  48.  
  49. /* General customization:
  50.  */
  51.  
  52. #define I915_TILING_NONE          0
  53.  
  54. #define VGA_RSRC_NONE          0x00
  55. #define VGA_RSRC_LEGACY_IO     0x01
  56. #define VGA_RSRC_LEGACY_MEM    0x02
  57. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  58. /* Non-legacy access */
  59. #define VGA_RSRC_NORMAL_IO     0x04
  60. #define VGA_RSRC_NORMAL_MEM    0x08
  61.  
  62. #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  63.  
  64. #define DRIVER_NAME             "i915"
  65. #define DRIVER_DESC             "Intel Graphics"
  66. #define DRIVER_DATE             "20080730"
  67.  
  68. enum pipe {
  69.         PIPE_A = 0,
  70.         PIPE_B,
  71.         PIPE_C,
  72.         I915_MAX_PIPES
  73. };
  74. #define pipe_name(p) ((p) + 'A')
  75.  
  76. enum transcoder {
  77.         TRANSCODER_A = 0,
  78.         TRANSCODER_B,
  79.         TRANSCODER_C,
  80.         TRANSCODER_EDP = 0xF,
  81. };
  82. #define transcoder_name(t) ((t) + 'A')
  83.  
  84. enum plane {
  85.         PLANE_A = 0,
  86.         PLANE_B,
  87.         PLANE_C,
  88. };
  89. #define plane_name(p) ((p) + 'A')
  90.  
  91. #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
  92.  
  93. enum port {
  94.         PORT_A = 0,
  95.         PORT_B,
  96.         PORT_C,
  97.         PORT_D,
  98.         PORT_E,
  99.         I915_MAX_PORTS
  100. };
  101. #define port_name(p) ((p) + 'A')
  102.  
  103. enum intel_display_power_domain {
  104.         POWER_DOMAIN_PIPE_A,
  105.         POWER_DOMAIN_PIPE_B,
  106.         POWER_DOMAIN_PIPE_C,
  107.         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  108.         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  109.         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  110.         POWER_DOMAIN_TRANSCODER_A,
  111.         POWER_DOMAIN_TRANSCODER_B,
  112.         POWER_DOMAIN_TRANSCODER_C,
  113.         POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
  114. };
  115.  
  116. #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
  117. #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
  118.                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
  119. #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
  120.  
  121. enum hpd_pin {
  122.         HPD_NONE = 0,
  123.         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
  124.         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
  125.         HPD_CRT,
  126.         HPD_SDVO_B,
  127.         HPD_SDVO_C,
  128.         HPD_PORT_B,
  129.         HPD_PORT_C,
  130.         HPD_PORT_D,
  131.         HPD_NUM_PINS
  132. };
  133.  
  134. #define I915_GEM_GPU_DOMAINS \
  135.         (I915_GEM_DOMAIN_RENDER | \
  136.          I915_GEM_DOMAIN_SAMPLER | \
  137.          I915_GEM_DOMAIN_COMMAND | \
  138.          I915_GEM_DOMAIN_INSTRUCTION | \
  139.          I915_GEM_DOMAIN_VERTEX)
  140.  
  141. #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
  142.  
  143. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  144.         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  145.                 if ((intel_encoder)->base.crtc == (__crtc))
  146.  
  147. struct drm_i915_private;
  148.  
  149. enum intel_dpll_id {
  150.         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
  151.         /* real shared dpll ids must be >= 0 */
  152.         DPLL_ID_PCH_PLL_A,
  153.         DPLL_ID_PCH_PLL_B,
  154. };
  155. #define I915_NUM_PLLS 2
  156.  
  157. struct intel_dpll_hw_state {
  158.         uint32_t dpll;
  159.         uint32_t dpll_md;
  160.         uint32_t fp0;
  161.         uint32_t fp1;
  162. };
  163.  
  164. struct intel_shared_dpll {
  165.         int refcount; /* count of number of CRTCs sharing this PLL */
  166.         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  167.         bool on; /* is the PLL actually active? Disabled during modeset */
  168.         const char *name;
  169.         /* should match the index in the dev_priv->shared_dplls array */
  170.         enum intel_dpll_id id;
  171.         struct intel_dpll_hw_state hw_state;
  172.         void (*mode_set)(struct drm_i915_private *dev_priv,
  173.                          struct intel_shared_dpll *pll);
  174.         void (*enable)(struct drm_i915_private *dev_priv,
  175.                        struct intel_shared_dpll *pll);
  176.         void (*disable)(struct drm_i915_private *dev_priv,
  177.                         struct intel_shared_dpll *pll);
  178.         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
  179.                              struct intel_shared_dpll *pll,
  180.                              struct intel_dpll_hw_state *hw_state);
  181. };
  182.  
  183. /* Used by dp and fdi links */
  184. struct intel_link_m_n {
  185.         uint32_t        tu;
  186.         uint32_t        gmch_m;
  187.         uint32_t        gmch_n;
  188.         uint32_t        link_m;
  189.         uint32_t        link_n;
  190. };
  191.  
  192. void intel_link_compute_m_n(int bpp, int nlanes,
  193.                             int pixel_clock, int link_clock,
  194.                             struct intel_link_m_n *m_n);
  195.  
  196. struct intel_ddi_plls {
  197.         int spll_refcount;
  198.         int wrpll1_refcount;
  199.         int wrpll2_refcount;
  200. };
  201.  
  202. /* Interface history:
  203.  *
  204.  * 1.1: Original.
  205.  * 1.2: Add Power Management
  206.  * 1.3: Add vblank support
  207.  * 1.4: Fix cmdbuffer path, add heap destroy
  208.  * 1.5: Add vblank pipe configuration
  209.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  210.  *      - Support vertical blank on secondary display pipe
  211.  */
  212. #define DRIVER_MAJOR            1
  213. #define DRIVER_MINOR            6
  214. #define DRIVER_PATCHLEVEL       0
  215.  
  216. #define WATCH_LISTS     0
  217. #define WATCH_GTT       0
  218.  
  219. #define I915_GEM_PHYS_CURSOR_0 1
  220. #define I915_GEM_PHYS_CURSOR_1 2
  221. #define I915_GEM_PHYS_OVERLAY_REGS 3
  222. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  223.  
  224. struct drm_i915_gem_phys_object {
  225.         int id;
  226.         struct page **page_list;
  227.         drm_dma_handle_t *handle;
  228.         struct drm_i915_gem_object *cur_obj;
  229. };
  230.  
  231. struct opregion_header;
  232. struct opregion_acpi;
  233. struct opregion_swsci;
  234. struct opregion_asle;
  235.  
  236. struct intel_opregion {
  237.         struct opregion_header __iomem *header;
  238.         struct opregion_acpi __iomem *acpi;
  239.         struct opregion_swsci __iomem *swsci;
  240.         struct opregion_asle __iomem *asle;
  241.         void __iomem *vbt;
  242.         u32 __iomem *lid_state;
  243. };
  244. #define OPREGION_SIZE            (8*1024)
  245.  
  246. struct intel_overlay;
  247. struct intel_overlay_error_state;
  248.  
  249. struct drm_i915_master_private {
  250.         drm_local_map_t *sarea;
  251.         struct _drm_i915_sarea *sarea_priv;
  252. };
  253. #define I915_FENCE_REG_NONE -1
  254. #define I915_MAX_NUM_FENCES 32
  255. /* 32 fences + sign bit for FENCE_REG_NONE */
  256. #define I915_MAX_NUM_FENCE_BITS 6
  257.  
  258. struct drm_i915_fence_reg {
  259.         struct list_head lru_list;
  260.         struct drm_i915_gem_object *obj;
  261.         int pin_count;
  262. };
  263.  
  264. struct sdvo_device_mapping {
  265.         u8 initialized;
  266.         u8 dvo_port;
  267.         u8 slave_addr;
  268.         u8 dvo_wiring;
  269.         u8 i2c_pin;
  270.         u8 ddc_pin;
  271. };
  272.  
  273. struct intel_display_error_state;
  274.  
  275. struct drm_i915_error_state {
  276.         struct kref ref;
  277.         u32 eir;
  278.         u32 pgtbl_er;
  279.         u32 ier;
  280.         u32 ccid;
  281.         u32 derrmr;
  282.         u32 forcewake;
  283.         bool waiting[I915_NUM_RINGS];
  284.         u32 pipestat[I915_MAX_PIPES];
  285.         u32 tail[I915_NUM_RINGS];
  286.         u32 head[I915_NUM_RINGS];
  287.         u32 ctl[I915_NUM_RINGS];
  288.         u32 ipeir[I915_NUM_RINGS];
  289.         u32 ipehr[I915_NUM_RINGS];
  290.         u32 instdone[I915_NUM_RINGS];
  291.         u32 acthd[I915_NUM_RINGS];
  292.         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  293.         u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  294.         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
  295.         /* our own tracking of ring head and tail */
  296.         u32 cpu_ring_head[I915_NUM_RINGS];
  297.         u32 cpu_ring_tail[I915_NUM_RINGS];
  298.         u32 error; /* gen6+ */
  299.         u32 err_int; /* gen7 */
  300.         u32 instpm[I915_NUM_RINGS];
  301.         u32 instps[I915_NUM_RINGS];
  302.         u32 extra_instdone[I915_NUM_INSTDONE_REG];
  303.         u32 seqno[I915_NUM_RINGS];
  304.         u64 bbaddr;
  305.         u32 fault_reg[I915_NUM_RINGS];
  306.         u32 done_reg;
  307.         u32 faddr[I915_NUM_RINGS];
  308.         u64 fence[I915_MAX_NUM_FENCES];
  309.         struct timeval time;
  310.         struct drm_i915_error_ring {
  311.         struct drm_i915_error_object {
  312.                 int page_count;
  313.                 u32 gtt_offset;
  314.                 u32 *pages[0];
  315.                 } *ringbuffer, *batchbuffer, *ctx;
  316.                 struct drm_i915_error_request {
  317.                         long jiffies;
  318.                         u32 seqno;
  319.                         u32 tail;
  320.                 } *requests;
  321.                 int num_requests;
  322.         } ring[I915_NUM_RINGS];
  323.         struct drm_i915_error_buffer {
  324.                 u32 size;
  325.                 u32 name;
  326.                 u32 rseqno, wseqno;
  327.                 u32 gtt_offset;
  328.                 u32 read_domains;
  329.                 u32 write_domain;
  330.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  331.                 s32 pinned:2;
  332.                 u32 tiling:2;
  333.                 u32 dirty:1;
  334.                 u32 purgeable:1;
  335.                 s32 ring:4;
  336.                 u32 cache_level:2;
  337.         } **active_bo, **pinned_bo;
  338.         u32 *active_bo_count, *pinned_bo_count;
  339.         struct intel_overlay_error_state *overlay;
  340.         struct intel_display_error_state *display;
  341. };
  342.  
  343. struct intel_crtc_config;
  344. struct intel_crtc;
  345. struct intel_limit;
  346. struct dpll;
  347.  
  348. struct drm_i915_display_funcs {
  349.         bool (*fbc_enabled)(struct drm_device *dev);
  350.         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  351.         void (*disable_fbc)(struct drm_device *dev);
  352.         int (*get_display_clock_speed)(struct drm_device *dev);
  353.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  354.         /**
  355.          * find_dpll() - Find the best values for the PLL
  356.          * @limit: limits for the PLL
  357.          * @crtc: current CRTC
  358.          * @target: target frequency in kHz
  359.          * @refclk: reference clock frequency in kHz
  360.          * @match_clock: if provided, @best_clock P divider must
  361.          *               match the P divider from @match_clock
  362.          *               used for LVDS downclocking
  363.          * @best_clock: best PLL values found
  364.          *
  365.          * Returns true on success, false on failure.
  366.          */
  367.         bool (*find_dpll)(const struct intel_limit *limit,
  368.                           struct drm_crtc *crtc,
  369.                           int target, int refclk,
  370.                           struct dpll *match_clock,
  371.                           struct dpll *best_clock);
  372.         void (*update_wm)(struct drm_device *dev);
  373.         void (*update_sprite_wm)(struct drm_plane *plane,
  374.                                  struct drm_crtc *crtc,
  375.                                  uint32_t sprite_width, int pixel_size,
  376.                                  bool enable, bool scaled);
  377.         void (*modeset_global_resources)(struct drm_device *dev);
  378.         /* Returns the active state of the crtc, and if the crtc is active,
  379.          * fills out the pipe-config with the hw state. */
  380.         bool (*get_pipe_config)(struct intel_crtc *,
  381.                                 struct intel_crtc_config *);
  382.         void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
  383.         int (*crtc_mode_set)(struct drm_crtc *crtc,
  384.                              int x, int y,
  385.                              struct drm_framebuffer *old_fb);
  386.         void (*crtc_enable)(struct drm_crtc *crtc);
  387.         void (*crtc_disable)(struct drm_crtc *crtc);
  388.         void (*off)(struct drm_crtc *crtc);
  389.         void (*write_eld)(struct drm_connector *connector,
  390.                           struct drm_crtc *crtc);
  391.         void (*fdi_link_train)(struct drm_crtc *crtc);
  392.         void (*init_clock_gating)(struct drm_device *dev);
  393.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  394.                           struct drm_framebuffer *fb,
  395.                           struct drm_i915_gem_object *obj,
  396.                           uint32_t flags);
  397.         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  398.                             int x, int y);
  399.         void (*hpd_irq_setup)(struct drm_device *dev);
  400.         /* clock updates for mode set */
  401.         /* cursor updates */
  402.         /* render clock increase/decrease */
  403.         /* display clock increase/decrease */
  404.         /* pll clock increase/decrease */
  405. };
  406.  
  407. struct intel_uncore_funcs {
  408.         void (*force_wake_get)(struct drm_i915_private *dev_priv);
  409.         void (*force_wake_put)(struct drm_i915_private *dev_priv);
  410. };
  411.  
  412. struct intel_uncore {
  413.         spinlock_t lock; /** lock is also taken in irq contexts. */
  414.  
  415.         struct intel_uncore_funcs funcs;
  416.  
  417.         unsigned fifo_count;
  418.         unsigned forcewake_count;
  419. };
  420.  
  421. #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
  422.         func(is_mobile) sep \
  423.         func(is_i85x) sep \
  424.         func(is_i915g) sep \
  425.         func(is_i945gm) sep \
  426.         func(is_g33) sep \
  427.         func(need_gfx_hws) sep \
  428.         func(is_g4x) sep \
  429.         func(is_pineview) sep \
  430.         func(is_broadwater) sep \
  431.         func(is_crestline) sep \
  432.         func(is_ivybridge) sep \
  433.         func(is_valleyview) sep \
  434.         func(is_haswell) sep \
  435.         func(has_force_wake) sep \
  436.         func(has_fbc) sep \
  437.         func(has_pipe_cxsr) sep \
  438.         func(has_hotplug) sep \
  439.         func(cursor_needs_physical) sep \
  440.         func(has_overlay) sep \
  441.         func(overlay_needs_physical) sep \
  442.         func(supports_tv) sep \
  443.         func(has_bsd_ring) sep \
  444.         func(has_blt_ring) sep \
  445.         func(has_vebox_ring) sep \
  446.         func(has_llc) sep \
  447.         func(has_ddi) sep \
  448.         func(has_fpga_dbg)
  449.  
  450. #define DEFINE_FLAG(name) u8 name:1
  451. #define SEP_SEMICOLON ;
  452.  
  453. struct intel_device_info {
  454.         u32 display_mmio_offset;
  455.         u8 num_pipes:3;
  456.         u8 gen;
  457.         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
  458. };
  459.  
  460. #undef DEFINE_FLAG
  461. #undef SEP_SEMICOLON
  462.  
  463. enum i915_cache_level {
  464.         I915_CACHE_NONE = 0,
  465.         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
  466.         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
  467.                               caches, eg sampler/render caches, and the
  468.                               large Last-Level-Cache. LLC is coherent with
  469.                               the CPU, but L3 is only visible to the GPU. */
  470.         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
  471. };
  472.  
  473. typedef uint32_t gen6_gtt_pte_t;
  474.  
  475. struct i915_address_space {
  476.         struct drm_mm mm;
  477.         struct drm_device *dev;
  478.         struct list_head global_link;
  479.         unsigned long start;            /* Start offset always 0 for dri2 */
  480.         size_t total;           /* size addr space maps (ex. 2GB for ggtt) */
  481.  
  482.         struct {
  483.                 dma_addr_t addr;
  484.                 struct page *page;
  485.         } scratch;
  486.  
  487.         /**
  488.          * List of objects currently involved in rendering.
  489.          *
  490.          * Includes buffers having the contents of their GPU caches
  491.          * flushed, not necessarily primitives.  last_rendering_seqno
  492.          * represents when the rendering involved will be completed.
  493.          *
  494.          * A reference is held on the buffer while on this list.
  495.          */
  496.         struct list_head active_list;
  497.  
  498.         /**
  499.          * LRU list of objects which are not in the ringbuffer and
  500.          * are ready to unbind, but are still in the GTT.
  501.          *
  502.          * last_rendering_seqno is 0 while an object is in this list.
  503.          *
  504.          * A reference is not held on the buffer while on this list,
  505.          * as merely being GTT-bound shouldn't prevent its being
  506.          * freed, and we'll pull it off the list in the free path.
  507.          */
  508.         struct list_head inactive_list;
  509.  
  510.         /* FIXME: Need a more generic return type */
  511.         gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
  512.                                      enum i915_cache_level level,
  513.                                      bool valid); /* Create a valid PTE */
  514.         void (*clear_range)(struct i915_address_space *vm,
  515.                             unsigned int first_entry,
  516.                             unsigned int num_entries,
  517.                             bool use_scratch);
  518.         void (*insert_entries)(struct i915_address_space *vm,
  519.                                struct sg_table *st,
  520.                                unsigned int first_entry,
  521.                                enum i915_cache_level cache_level);
  522.         void (*cleanup)(struct i915_address_space *vm);
  523. };
  524.  
  525. /* The Graphics Translation Table is the way in which GEN hardware translates a
  526.  * Graphics Virtual Address into a Physical Address. In addition to the normal
  527.  * collateral associated with any va->pa translations GEN hardware also has a
  528.  * portion of the GTT which can be mapped by the CPU and remain both coherent
  529.  * and correct (in cases like swizzling). That region is referred to as GMADR in
  530.  * the spec.
  531.  */
  532. struct i915_gtt {
  533.         struct i915_address_space base;
  534.         size_t stolen_size;             /* Total size of stolen memory */
  535.  
  536.         unsigned long mappable_end;     /* End offset that we can CPU map */
  537.         struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
  538.         phys_addr_t mappable_base;      /* PA of our GMADR */
  539.  
  540.         /** "Graphics Stolen Memory" holds the global PTEs */
  541.         void __iomem *gsm;
  542.  
  543.         bool do_idle_maps;
  544.  
  545.         int mtrr;
  546.  
  547.         /* global gtt ops */
  548.         int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
  549.                           size_t *stolen, phys_addr_t *mappable_base,
  550.                           unsigned long *mappable_end);
  551. };
  552. #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
  553.  
  554. struct i915_hw_ppgtt {
  555.         struct i915_address_space base;
  556.         unsigned num_pd_entries;
  557.         struct page **pt_pages;
  558.         uint32_t pd_offset;
  559.         dma_addr_t *pt_dma_addr;
  560.  
  561.         int (*enable)(struct drm_device *dev);
  562. };
  563.  
  564. /**
  565.  * A VMA represents a GEM BO that is bound into an address space. Therefore, a
  566.  * VMA's presence cannot be guaranteed before binding, or after unbinding the
  567.  * object into/from the address space.
  568.  *
  569.  * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
  570.  * will always be <= an objects lifetime. So object refcounting should cover us.
  571.  */
  572. struct i915_vma {
  573.         struct drm_mm_node node;
  574.         struct drm_i915_gem_object *obj;
  575.         struct i915_address_space *vm;
  576.  
  577.         /** This object's place on the active/inactive lists */
  578.         struct list_head mm_list;
  579.  
  580.         struct list_head vma_link; /* Link in the object's VMA list */
  581.  
  582.         /** This vma's place in the batchbuffer or on the eviction list */
  583.         struct list_head exec_list;
  584.  
  585. };
  586.  
  587. struct i915_ctx_hang_stats {
  588.         /* This context had batch pending when hang was declared */
  589.         unsigned batch_pending;
  590.  
  591.         /* This context had batch active when hang was declared */
  592.         unsigned batch_active;
  593. };
  594.  
  595. /* This must match up with the value previously used for execbuf2.rsvd1. */
  596. #define DEFAULT_CONTEXT_ID 0
  597. struct i915_hw_context {
  598.         struct kref ref;
  599.         int id;
  600.         bool is_initialized;
  601.         struct drm_i915_file_private *file_priv;
  602.         struct intel_ring_buffer *ring;
  603.         struct drm_i915_gem_object *obj;
  604.         struct i915_ctx_hang_stats hang_stats;
  605. };
  606.  
  607. struct i915_fbc {
  608.         unsigned long size;
  609.         unsigned int fb_id;
  610.         enum plane plane;
  611.         int y;
  612.  
  613.         struct drm_mm_node *compressed_fb;
  614.         struct drm_mm_node *compressed_llb;
  615.  
  616.         struct intel_fbc_work {
  617.                 struct delayed_work work;
  618.                 struct drm_crtc *crtc;
  619.                 struct drm_framebuffer *fb;
  620.                 int interval;
  621.         } *fbc_work;
  622.  
  623. enum no_fbc_reason {
  624.                 FBC_OK, /* FBC is enabled */
  625.                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
  626.         FBC_NO_OUTPUT, /* no outputs enabled to compress */
  627.                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
  628.         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  629.         FBC_MODE_TOO_LARGE, /* mode too large for compression */
  630.         FBC_BAD_PLANE, /* fbc not supported on plane */
  631.         FBC_NOT_TILED, /* buffer not tiled */
  632.         FBC_MULTIPLE_PIPES, /* more than one pipe active */
  633.         FBC_MODULE_PARAM,
  634.                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
  635.         } no_fbc_reason;
  636. };
  637.  
  638. enum no_psr_reason {
  639.         PSR_NO_SOURCE, /* Not supported on platform */
  640.         PSR_NO_SINK, /* Not supported by panel */
  641.         PSR_MODULE_PARAM,
  642.         PSR_CRTC_NOT_ACTIVE,
  643.         PSR_PWR_WELL_ENABLED,
  644.         PSR_NOT_TILED,
  645.         PSR_SPRITE_ENABLED,
  646.         PSR_S3D_ENABLED,
  647.         PSR_INTERLACED_ENABLED,
  648.         PSR_HSW_NOT_DDIA,
  649. };
  650.  
  651. enum intel_pch {
  652.         PCH_NONE = 0,   /* No PCH present */
  653.         PCH_IBX,        /* Ibexpeak PCH */
  654.         PCH_CPT,        /* Cougarpoint PCH */
  655.         PCH_LPT,        /* Lynxpoint PCH */
  656.         PCH_NOP,
  657. };
  658.  
  659. enum intel_sbi_destination {
  660.         SBI_ICLK,
  661.         SBI_MPHY,
  662. };
  663.  
  664. #define QUIRK_PIPEA_FORCE (1<<0)
  665. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  666. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  667. #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
  668.  
  669. struct intel_fbdev;
  670. struct intel_fbc_work;
  671.  
  672. struct intel_gmbus {
  673.         struct i2c_adapter adapter;
  674.         u32 force_bit;
  675.         u32 reg0;
  676.         u32 gpio_reg;
  677.         struct i2c_algo_bit_data bit_algo;
  678.         struct drm_i915_private *dev_priv;
  679. };
  680.  
  681. struct i915_suspend_saved_registers {
  682.         u8 saveLBB;
  683.         u32 saveDSPACNTR;
  684.         u32 saveDSPBCNTR;
  685.         u32 saveDSPARB;
  686.         u32 savePIPEACONF;
  687.         u32 savePIPEBCONF;
  688.         u32 savePIPEASRC;
  689.         u32 savePIPEBSRC;
  690.         u32 saveFPA0;
  691.         u32 saveFPA1;
  692.         u32 saveDPLL_A;
  693.         u32 saveDPLL_A_MD;
  694.         u32 saveHTOTAL_A;
  695.         u32 saveHBLANK_A;
  696.         u32 saveHSYNC_A;
  697.         u32 saveVTOTAL_A;
  698.         u32 saveVBLANK_A;
  699.         u32 saveVSYNC_A;
  700.         u32 saveBCLRPAT_A;
  701.         u32 saveTRANSACONF;
  702.         u32 saveTRANS_HTOTAL_A;
  703.         u32 saveTRANS_HBLANK_A;
  704.         u32 saveTRANS_HSYNC_A;
  705.         u32 saveTRANS_VTOTAL_A;
  706.         u32 saveTRANS_VBLANK_A;
  707.         u32 saveTRANS_VSYNC_A;
  708.         u32 savePIPEASTAT;
  709.         u32 saveDSPASTRIDE;
  710.         u32 saveDSPASIZE;
  711.         u32 saveDSPAPOS;
  712.         u32 saveDSPAADDR;
  713.         u32 saveDSPASURF;
  714.         u32 saveDSPATILEOFF;
  715.         u32 savePFIT_PGM_RATIOS;
  716.         u32 saveBLC_HIST_CTL;
  717.         u32 saveBLC_PWM_CTL;
  718.         u32 saveBLC_PWM_CTL2;
  719.         u32 saveBLC_CPU_PWM_CTL;
  720.         u32 saveBLC_CPU_PWM_CTL2;
  721.         u32 saveFPB0;
  722.         u32 saveFPB1;
  723.         u32 saveDPLL_B;
  724.         u32 saveDPLL_B_MD;
  725.         u32 saveHTOTAL_B;
  726.         u32 saveHBLANK_B;
  727.         u32 saveHSYNC_B;
  728.         u32 saveVTOTAL_B;
  729.         u32 saveVBLANK_B;
  730.         u32 saveVSYNC_B;
  731.         u32 saveBCLRPAT_B;
  732.         u32 saveTRANSBCONF;
  733.         u32 saveTRANS_HTOTAL_B;
  734.         u32 saveTRANS_HBLANK_B;
  735.         u32 saveTRANS_HSYNC_B;
  736.         u32 saveTRANS_VTOTAL_B;
  737.         u32 saveTRANS_VBLANK_B;
  738.         u32 saveTRANS_VSYNC_B;
  739.         u32 savePIPEBSTAT;
  740.         u32 saveDSPBSTRIDE;
  741.         u32 saveDSPBSIZE;
  742.         u32 saveDSPBPOS;
  743.         u32 saveDSPBADDR;
  744.         u32 saveDSPBSURF;
  745.         u32 saveDSPBTILEOFF;
  746.         u32 saveVGA0;
  747.         u32 saveVGA1;
  748.         u32 saveVGA_PD;
  749.         u32 saveVGACNTRL;
  750.         u32 saveADPA;
  751.         u32 saveLVDS;
  752.         u32 savePP_ON_DELAYS;
  753.         u32 savePP_OFF_DELAYS;
  754.         u32 saveDVOA;
  755.         u32 saveDVOB;
  756.         u32 saveDVOC;
  757.         u32 savePP_ON;
  758.         u32 savePP_OFF;
  759.         u32 savePP_CONTROL;
  760.         u32 savePP_DIVISOR;
  761.         u32 savePFIT_CONTROL;
  762.         u32 save_palette_a[256];
  763.         u32 save_palette_b[256];
  764.         u32 saveDPFC_CB_BASE;
  765.         u32 saveFBC_CFB_BASE;
  766.         u32 saveFBC_LL_BASE;
  767.         u32 saveFBC_CONTROL;
  768.         u32 saveFBC_CONTROL2;
  769.         u32 saveIER;
  770.         u32 saveIIR;
  771.         u32 saveIMR;
  772.         u32 saveDEIER;
  773.         u32 saveDEIMR;
  774.         u32 saveGTIER;
  775.         u32 saveGTIMR;
  776.         u32 saveFDI_RXA_IMR;
  777.         u32 saveFDI_RXB_IMR;
  778.         u32 saveCACHE_MODE_0;
  779.         u32 saveMI_ARB_STATE;
  780.         u32 saveSWF0[16];
  781.         u32 saveSWF1[16];
  782.         u32 saveSWF2[3];
  783.         u8 saveMSR;
  784.         u8 saveSR[8];
  785.         u8 saveGR[25];
  786.         u8 saveAR_INDEX;
  787.         u8 saveAR[21];
  788.         u8 saveDACMASK;
  789.         u8 saveCR[37];
  790.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  791.         u32 saveCURACNTR;
  792.         u32 saveCURAPOS;
  793.         u32 saveCURABASE;
  794.         u32 saveCURBCNTR;
  795.         u32 saveCURBPOS;
  796.         u32 saveCURBBASE;
  797.         u32 saveCURSIZE;
  798.         u32 saveDP_B;
  799.         u32 saveDP_C;
  800.         u32 saveDP_D;
  801.         u32 savePIPEA_GMCH_DATA_M;
  802.         u32 savePIPEB_GMCH_DATA_M;
  803.         u32 savePIPEA_GMCH_DATA_N;
  804.         u32 savePIPEB_GMCH_DATA_N;
  805.         u32 savePIPEA_DP_LINK_M;
  806.         u32 savePIPEB_DP_LINK_M;
  807.         u32 savePIPEA_DP_LINK_N;
  808.         u32 savePIPEB_DP_LINK_N;
  809.         u32 saveFDI_RXA_CTL;
  810.         u32 saveFDI_TXA_CTL;
  811.         u32 saveFDI_RXB_CTL;
  812.         u32 saveFDI_TXB_CTL;
  813.         u32 savePFA_CTL_1;
  814.         u32 savePFB_CTL_1;
  815.         u32 savePFA_WIN_SZ;
  816.         u32 savePFB_WIN_SZ;
  817.         u32 savePFA_WIN_POS;
  818.         u32 savePFB_WIN_POS;
  819.         u32 savePCH_DREF_CONTROL;
  820.         u32 saveDISP_ARB_CTL;
  821.         u32 savePIPEA_DATA_M1;
  822.         u32 savePIPEA_DATA_N1;
  823.         u32 savePIPEA_LINK_M1;
  824.         u32 savePIPEA_LINK_N1;
  825.         u32 savePIPEB_DATA_M1;
  826.         u32 savePIPEB_DATA_N1;
  827.         u32 savePIPEB_LINK_M1;
  828.         u32 savePIPEB_LINK_N1;
  829.         u32 saveMCHBAR_RENDER_STANDBY;
  830.         u32 savePCH_PORT_HOTPLUG;
  831. };
  832.  
  833. struct intel_gen6_power_mgmt {
  834.         /* work and pm_iir are protected by dev_priv->irq_lock */
  835.         struct work_struct work;
  836.         u32 pm_iir;
  837.  
  838.         /* On vlv we need to manually drop to Vmin with a delayed work. */
  839.         struct delayed_work vlv_work;
  840.  
  841.         /* The below variables an all the rps hw state are protected by
  842.          * dev->struct mutext. */
  843.         u8 cur_delay;
  844.         u8 min_delay;
  845.         u8 max_delay;
  846.         u8 rpe_delay;
  847.         u8 hw_max;
  848.  
  849.         struct delayed_work delayed_resume_work;
  850.  
  851.         /*
  852.          * Protects RPS/RC6 register access and PCU communication.
  853.          * Must be taken after struct_mutex if nested.
  854.          */
  855.         struct mutex hw_lock;
  856. };
  857.  
  858. /* defined intel_pm.c */
  859. extern spinlock_t mchdev_lock;
  860.  
  861. struct intel_ilk_power_mgmt {
  862.         u8 cur_delay;
  863.         u8 min_delay;
  864.         u8 max_delay;
  865.         u8 fmax;
  866.         u8 fstart;
  867.  
  868.         u64 last_count1;
  869.         unsigned long last_time1;
  870.         unsigned long chipset_power;
  871.         u64 last_count2;
  872.         struct timespec last_time2;
  873.         unsigned long gfx_power;
  874.         u8 corr;
  875.  
  876.         int c_m;
  877.         int r_t;
  878.  
  879.         struct drm_i915_gem_object *pwrctx;
  880.         struct drm_i915_gem_object *renderctx;
  881. };
  882.  
  883. /* Power well structure for haswell */
  884. struct i915_power_well {
  885.         struct drm_device *device;
  886.         spinlock_t lock;
  887.         /* power well enable/disable usage count */
  888.         int count;
  889.         int i915_request;
  890. };
  891.  
  892. struct i915_dri1_state {
  893.         unsigned allow_batchbuffer : 1;
  894.         u32 __iomem *gfx_hws_cpu_addr;
  895.  
  896.         unsigned int cpp;
  897.         int back_offset;
  898.         int front_offset;
  899.         int current_page;
  900.         int page_flipping;
  901.  
  902.         uint32_t counter;
  903. };
  904.  
  905. struct i915_ums_state {
  906.         /**
  907.          * Flag if the X Server, and thus DRM, is not currently in
  908.          * control of the device.
  909.          *
  910.          * This is set between LeaveVT and EnterVT.  It needs to be
  911.          * replaced with a semaphore.  It also needs to be
  912.          * transitioned away from for kernel modesetting.
  913.          */
  914.         int mm_suspended;
  915. };
  916.  
  917. struct intel_l3_parity {
  918.         u32 *remap_info;
  919.         struct work_struct error_work;
  920. };
  921.  
  922. struct i915_gem_mm {
  923.         /** Memory allocator for GTT stolen memory */
  924.         struct drm_mm stolen;
  925.         /** List of all objects in gtt_space. Used to restore gtt
  926.          * mappings on resume */
  927.         struct list_head bound_list;
  928.         /**
  929.          * List of objects which are not bound to the GTT (thus
  930.          * are idle and not used by the GPU) but still have
  931.          * (presumably uncached) pages still attached.
  932.          */
  933.         struct list_head unbound_list;
  934.  
  935.         /** Usable portion of the GTT for GEM */
  936.         unsigned long stolen_base; /* limited to low memory (32-bit) */
  937.  
  938.         /** PPGTT used for aliasing the PPGTT with the GTT */
  939.         struct i915_hw_ppgtt *aliasing_ppgtt;
  940.  
  941.         bool shrinker_no_lock_stealing;
  942.  
  943.         /** LRU list of objects with fence regs on them. */
  944.         struct list_head fence_list;
  945.  
  946.         /**
  947.          * We leave the user IRQ off as much as possible,
  948.          * but this means that requests will finish and never
  949.          * be retired once the system goes idle. Set a timer to
  950.          * fire periodically while the ring is running. When it
  951.          * fires, go retire requests.
  952.          */
  953.         struct delayed_work retire_work;
  954.  
  955.         /**
  956.          * Are we in a non-interruptible section of code like
  957.          * modesetting?
  958.          */
  959.         bool interruptible;
  960.  
  961.         /** Bit 6 swizzling required for X tiling */
  962.         uint32_t bit_6_swizzle_x;
  963.         /** Bit 6 swizzling required for Y tiling */
  964.         uint32_t bit_6_swizzle_y;
  965.  
  966.         /* storage for physical objects */
  967.         struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  968.  
  969.         /* accounting, useful for userland debugging */
  970.         spinlock_t object_stat_lock;
  971.         size_t object_memory;
  972.         u32 object_count;
  973. };
  974.  
  975. struct drm_i915_error_state_buf {
  976.         unsigned bytes;
  977.         unsigned size;
  978.         int err;
  979.         u8 *buf;
  980.         loff_t start;
  981.         loff_t pos;
  982. };
  983.  
  984. struct i915_error_state_file_priv {
  985.         struct drm_device *dev;
  986.         struct drm_i915_error_state *error;
  987. };
  988.  
  989. struct i915_gpu_error {
  990.         /* For hangcheck timer */
  991. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  992. #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  993.         struct timer_list hangcheck_timer;
  994.  
  995.         /* For reset and error_state handling. */
  996.         spinlock_t lock;
  997.         /* Protected by the above dev->gpu_error.lock. */
  998.         struct drm_i915_error_state *first_error;
  999.         struct work_struct work;
  1000.  
  1001.         unsigned long last_reset;
  1002.  
  1003.         /**
  1004.          * State variable and reset counter controlling the reset flow
  1005.          *
  1006.          * Upper bits are for the reset counter.  This counter is used by the
  1007.          * wait_seqno code to race-free noticed that a reset event happened and
  1008.          * that it needs to restart the entire ioctl (since most likely the
  1009.          * seqno it waited for won't ever signal anytime soon).
  1010.          *
  1011.          * This is important for lock-free wait paths, where no contended lock
  1012.          * naturally enforces the correct ordering between the bail-out of the
  1013.          * waiter and the gpu reset work code.
  1014.          *
  1015.          * Lowest bit controls the reset state machine: Set means a reset is in
  1016.          * progress. This state will (presuming we don't have any bugs) decay
  1017.          * into either unset (successful reset) or the special WEDGED value (hw
  1018.          * terminally sour). All waiters on the reset_queue will be woken when
  1019.          * that happens.
  1020.          */
  1021.         atomic_t reset_counter;
  1022.  
  1023.         /**
  1024.          * Special values/flags for reset_counter
  1025.          *
  1026.          * Note that the code relies on
  1027.          *      I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
  1028.          * being true.
  1029.          */
  1030. #define I915_RESET_IN_PROGRESS_FLAG     1
  1031. #define I915_WEDGED                     0xffffffff
  1032.  
  1033.         /**
  1034.          * Waitqueue to signal when the reset has completed. Used by clients
  1035.          * that wait for dev_priv->mm.wedged to settle.
  1036.          */
  1037.         wait_queue_head_t reset_queue;
  1038.  
  1039.         /* For gpu hang simulation. */
  1040.         unsigned int stop_rings;
  1041. };
  1042.  
  1043. enum modeset_restore {
  1044.         MODESET_ON_LID_OPEN,
  1045.         MODESET_DONE,
  1046.         MODESET_SUSPENDED,
  1047. };
  1048.  
  1049. struct intel_vbt_data {
  1050.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  1051.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  1052.  
  1053.         /* Feature bits */
  1054.         unsigned int int_tv_support:1;
  1055.         unsigned int lvds_dither:1;
  1056.         unsigned int lvds_vbt:1;
  1057.         unsigned int int_crt_support:1;
  1058.         unsigned int lvds_use_ssc:1;
  1059.         unsigned int display_clock_mode:1;
  1060.         unsigned int fdi_rx_polarity_inverted:1;
  1061.         int lvds_ssc_freq;
  1062.         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  1063.  
  1064.         /* eDP */
  1065.         int edp_rate;
  1066.         int edp_lanes;
  1067.         int edp_preemphasis;
  1068.         int edp_vswing;
  1069.         bool edp_initialized;
  1070.         bool edp_support;
  1071.         int edp_bpp;
  1072.         struct edp_power_seq edp_pps;
  1073.  
  1074.         int crt_ddc_pin;
  1075.  
  1076.         int child_dev_num;
  1077.         struct child_device_config *child_dev;
  1078. };
  1079.  
  1080. enum intel_ddb_partitioning {
  1081.         INTEL_DDB_PART_1_2,
  1082.         INTEL_DDB_PART_5_6, /* IVB+ */
  1083. };
  1084.  
  1085. struct intel_wm_level {
  1086.         bool enable;
  1087.         uint32_t pri_val;
  1088.         uint32_t spr_val;
  1089.         uint32_t cur_val;
  1090.         uint32_t fbc_val;
  1091. };
  1092.  
  1093. /*
  1094.  * This struct tracks the state needed for the Package C8+ feature.
  1095.  *
  1096.  * Package states C8 and deeper are really deep PC states that can only be
  1097.  * reached when all the devices on the system allow it, so even if the graphics
  1098.  * device allows PC8+, it doesn't mean the system will actually get to these
  1099.  * states.
  1100.  *
  1101.  * Our driver only allows PC8+ when all the outputs are disabled, the power well
  1102.  * is disabled and the GPU is idle. When these conditions are met, we manually
  1103.  * do the other conditions: disable the interrupts, clocks and switch LCPLL
  1104.  * refclk to Fclk.
  1105.  *
  1106.  * When we really reach PC8 or deeper states (not just when we allow it) we lose
  1107.  * the state of some registers, so when we come back from PC8+ we need to
  1108.  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
  1109.  * need to take care of the registers kept by RC6.
  1110.  *
  1111.  * The interrupt disabling is part of the requirements. We can only leave the
  1112.  * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
  1113.  * can lock the machine.
  1114.  *
  1115.  * Ideally every piece of our code that needs PC8+ disabled would call
  1116.  * hsw_disable_package_c8, which would increment disable_count and prevent the
  1117.  * system from reaching PC8+. But we don't have a symmetric way to do this for
  1118.  * everything, so we have the requirements_met and gpu_idle variables. When we
  1119.  * switch requirements_met or gpu_idle to true we decrease disable_count, and
  1120.  * increase it in the opposite case. The requirements_met variable is true when
  1121.  * all the CRTCs, encoders and the power well are disabled. The gpu_idle
  1122.  * variable is true when the GPU is idle.
  1123.  *
  1124.  * In addition to everything, we only actually enable PC8+ if disable_count
  1125.  * stays at zero for at least some seconds. This is implemented with the
  1126.  * enable_work variable. We do this so we don't enable/disable PC8 dozens of
  1127.  * consecutive times when all screens are disabled and some background app
  1128.  * queries the state of our connectors, or we have some application constantly
  1129.  * waking up to use the GPU. Only after the enable_work function actually
  1130.  * enables PC8+ the "enable" variable will become true, which means that it can
  1131.  * be false even if disable_count is 0.
  1132.  *
  1133.  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
  1134.  * goes back to false exactly before we reenable the IRQs. We use this variable
  1135.  * to check if someone is trying to enable/disable IRQs while they're supposed
  1136.  * to be disabled. This shouldn't happen and we'll print some error messages in
  1137.  * case it happens, but if it actually happens we'll also update the variables
  1138.  * inside struct regsave so when we restore the IRQs they will contain the
  1139.  * latest expected values.
  1140.  *
  1141.  * For more, read "Display Sequences for Package C8" on our documentation.
  1142.  */
  1143. struct i915_package_c8 {
  1144.         bool requirements_met;
  1145.         bool gpu_idle;
  1146.         bool irqs_disabled;
  1147.         /* Only true after the delayed work task actually enables it. */
  1148.         bool enabled;
  1149.         int disable_count;
  1150.         struct mutex lock;
  1151.         struct delayed_work enable_work;
  1152.  
  1153.         struct {
  1154.                 uint32_t deimr;
  1155.                 uint32_t sdeimr;
  1156.                 uint32_t gtimr;
  1157.                 uint32_t gtier;
  1158.                 uint32_t gen6_pmimr;
  1159.         } regsave;
  1160. };
  1161.  
  1162. typedef struct drm_i915_private {
  1163.         struct drm_device *dev;
  1164.  
  1165.         const struct intel_device_info *info;
  1166.  
  1167.         int relative_constants_mode;
  1168.  
  1169.         void __iomem *regs;
  1170.  
  1171.         struct intel_uncore uncore;
  1172.  
  1173.         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  1174.  
  1175.  
  1176.         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  1177.          * controller on different i2c buses. */
  1178.         struct mutex gmbus_mutex;
  1179.  
  1180.         /**
  1181.          * Base address of the gmbus and gpio block.
  1182.          */
  1183.         uint32_t gpio_mmio_base;
  1184.  
  1185.         wait_queue_head_t gmbus_wait_queue;
  1186.  
  1187.         struct pci_dev *bridge_dev;
  1188.         struct intel_ring_buffer ring[I915_NUM_RINGS];
  1189.         uint32_t last_seqno, next_seqno;
  1190.  
  1191.         drm_dma_handle_t *status_page_dmah;
  1192.         struct resource mch_res;
  1193.  
  1194.         atomic_t irq_received;
  1195.  
  1196.         /* protects the irq masks */
  1197.         spinlock_t irq_lock;
  1198.  
  1199.         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
  1200. //      struct pm_qos_request pm_qos;
  1201.  
  1202.         /* DPIO indirect register protection */
  1203.         struct mutex dpio_lock;
  1204.  
  1205.         /** Cached value of IMR to avoid reads in updating the bitfield */
  1206.         u32 irq_mask;
  1207.         u32 gt_irq_mask;
  1208.         u32 pm_irq_mask;
  1209.  
  1210.         struct work_struct hotplug_work;
  1211.         bool enable_hotplug_processing;
  1212.         struct {
  1213.                 unsigned long hpd_last_jiffies;
  1214.                 int hpd_cnt;
  1215.                 enum {
  1216.                         HPD_ENABLED = 0,
  1217.                         HPD_DISABLED = 1,
  1218.                         HPD_MARK_DISABLED = 2
  1219.                 } hpd_mark;
  1220.         } hpd_stats[HPD_NUM_PINS];
  1221.         u32 hpd_event_bits;
  1222.         struct timer_list hotplug_reenable_timer;
  1223.  
  1224.         int num_plane;
  1225.  
  1226.         struct i915_fbc fbc;
  1227.         struct intel_opregion opregion;
  1228.         struct intel_vbt_data vbt;
  1229.  
  1230.         /* overlay */
  1231.         struct intel_overlay *overlay;
  1232.         unsigned int sprite_scaling_enabled;
  1233.  
  1234.         /* backlight */
  1235.         struct {
  1236.                 int level;
  1237.                 bool enabled;
  1238.                 spinlock_t lock; /* bl registers and the above bl fields */
  1239.                 struct backlight_device *device;
  1240.         } backlight;
  1241.  
  1242.         /* LVDS info */
  1243.         bool no_aux_handshake;
  1244.  
  1245.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  1246.         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  1247.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  1248.  
  1249.         unsigned int fsb_freq, mem_freq, is_ddr3;
  1250.  
  1251.         /**
  1252.          * wq - Driver workqueue for GEM.
  1253.          *
  1254.          * NOTE: Work items scheduled here are not allowed to grab any modeset
  1255.          * locks, for otherwise the flushing done in the pageflip code will
  1256.          * result in deadlocks.
  1257.          */
  1258.         struct workqueue_struct *wq;
  1259.  
  1260.         /* Display functions */
  1261.         struct drm_i915_display_funcs display;
  1262.  
  1263.         /* PCH chipset type */
  1264.         enum intel_pch pch_type;
  1265.         unsigned short pch_id;
  1266.  
  1267.         unsigned long quirks;
  1268.  
  1269.         enum modeset_restore modeset_restore;
  1270.         struct mutex modeset_restore_lock;
  1271.  
  1272.         struct list_head vm_list; /* Global list of all address spaces */
  1273.         struct i915_gtt gtt; /* VMA representing the global address space */
  1274.  
  1275.         struct i915_gem_mm mm;
  1276.  
  1277.         /* Kernel Modesetting */
  1278.  
  1279.     struct sdvo_device_mapping sdvo_mappings[2];
  1280.  
  1281.     struct drm_crtc *plane_to_crtc_mapping[3];
  1282.     struct drm_crtc *pipe_to_crtc_mapping[3];
  1283.         wait_queue_head_t pending_flip_queue;
  1284.  
  1285.         int num_shared_dpll;
  1286.         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
  1287.         struct intel_ddi_plls ddi_plls;
  1288.  
  1289.         /* Reclocking support */
  1290.         bool render_reclock_avail;
  1291.         bool lvds_downclock_avail;
  1292.         /* indicates the reduced downclock for LVDS*/
  1293.         int lvds_downclock;
  1294.         u16 orig_clock;
  1295.  
  1296.         bool mchbar_need_disable;
  1297.  
  1298.         struct intel_l3_parity l3_parity;
  1299.  
  1300.         /* Cannot be determined by PCIID. You must always read a register. */
  1301.         size_t ellc_size;
  1302.  
  1303.         /* gen6+ rps state */
  1304.         struct intel_gen6_power_mgmt rps;
  1305.  
  1306.         /* ilk-only ips/rps state. Everything in here is protected by the global
  1307.          * mchdev_lock in intel_pm.c */
  1308.         struct intel_ilk_power_mgmt ips;
  1309.  
  1310.         /* Haswell power well */
  1311.         struct i915_power_well power_well;
  1312.  
  1313.         enum no_psr_reason no_psr_reason;
  1314.  
  1315.         struct i915_gpu_error gpu_error;
  1316.  
  1317.         struct drm_i915_gem_object *vlv_pctx;
  1318.  
  1319.         /* list of fbdev register on this device */
  1320.     struct intel_fbdev *fbdev;
  1321.  
  1322.         /*
  1323.          * The console may be contended at resume, but we don't
  1324.          * want it to block on it.
  1325.          */
  1326.         struct work_struct console_resume_work;
  1327.  
  1328.         struct drm_property *broadcast_rgb_property;
  1329.         struct drm_property *force_audio_property;
  1330.  
  1331.         bool hw_contexts_disabled;
  1332.         uint32_t hw_context_size;
  1333.  
  1334.         u32 fdi_rx_config;
  1335.  
  1336.         struct i915_suspend_saved_registers regfile;
  1337.  
  1338.         struct {
  1339.                 /*
  1340.                  * Raw watermark latency values:
  1341.                  * in 0.1us units for WM0,
  1342.                  * in 0.5us units for WM1+.
  1343.                  */
  1344.                 /* primary */
  1345.                 uint16_t pri_latency[5];
  1346.                 /* sprite */
  1347.                 uint16_t spr_latency[5];
  1348.                 /* cursor */
  1349.                 uint16_t cur_latency[5];
  1350.         } wm;
  1351.  
  1352.         struct i915_package_c8 pc8;
  1353.  
  1354.         /* Old dri1 support infrastructure, beware the dragons ya fools entering
  1355.          * here! */
  1356.         struct i915_dri1_state dri1;
  1357.         /* Old ums support infrastructure, same warning applies. */
  1358.         struct i915_ums_state ums;
  1359. } drm_i915_private_t;
  1360.  
  1361. static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
  1362. {
  1363.         return dev->dev_private;
  1364. }
  1365.  
  1366. /* Iterate over initialised rings */
  1367. #define for_each_ring(ring__, dev_priv__, i__) \
  1368.         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  1369.                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  1370.  
  1371. enum hdmi_force_audio {
  1372.         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
  1373.         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
  1374.         HDMI_AUDIO_AUTO,                /* trust EDID */
  1375.         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
  1376. };
  1377.  
  1378. #define I915_GTT_OFFSET_NONE ((u32)-1)
  1379.  
  1380. struct drm_i915_gem_object_ops {
  1381.         /* Interface between the GEM object and its backing storage.
  1382.          * get_pages() is called once prior to the use of the associated set
  1383.          * of pages before to binding them into the GTT, and put_pages() is
  1384.          * called after we no longer need them. As we expect there to be
  1385.          * associated cost with migrating pages between the backing storage
  1386.          * and making them available for the GPU (e.g. clflush), we may hold
  1387.          * onto the pages after they are no longer referenced by the GPU
  1388.          * in case they may be used again shortly (for example migrating the
  1389.          * pages to a different memory domain within the GTT). put_pages()
  1390.          * will therefore most likely be called when the object itself is
  1391.          * being released or under memory pressure (where we attempt to
  1392.          * reap pages for the shrinker).
  1393.          */
  1394.         int (*get_pages)(struct drm_i915_gem_object *);
  1395.         void (*put_pages)(struct drm_i915_gem_object *);
  1396. };
  1397.  
  1398. struct drm_i915_gem_object {
  1399.     struct drm_gem_object base;
  1400.  
  1401.         const struct drm_i915_gem_object_ops *ops;
  1402.  
  1403.         /** List of VMAs backed by this object */
  1404.         struct list_head vma_list;
  1405.  
  1406.         /** Stolen memory for this object, instead of being backed by shmem. */
  1407.         struct drm_mm_node *stolen;
  1408.         struct list_head global_list;
  1409.  
  1410.     struct list_head ring_list;
  1411.         /** Used in execbuf to temporarily hold a ref */
  1412.         struct list_head obj_exec_link;
  1413.     /** This object's place in the batchbuffer or on the eviction list */
  1414.     struct list_head exec_list;
  1415.  
  1416.     /**
  1417.          * This is set if the object is on the active lists (has pending
  1418.          * rendering and so a non-zero seqno), and is not set if it i s on
  1419.          * inactive (ready to be unbound) list.
  1420.      */
  1421.         unsigned int active:1;
  1422.  
  1423.     /**
  1424.      * This is set if the object has been written to since last bound
  1425.      * to the GTT
  1426.      */
  1427.         unsigned int dirty:1;
  1428.  
  1429.     /**
  1430.      * Fence register bits (if any) for this object.  Will be set
  1431.      * as needed when mapped into the GTT.
  1432.      * Protected by dev->struct_mutex.
  1433.      */
  1434.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  1435.  
  1436.     /**
  1437.      * Advice: are the backing pages purgeable?
  1438.      */
  1439.         unsigned int madv:2;
  1440.  
  1441.     /**
  1442.      * Current tiling mode for the object.
  1443.      */
  1444.         unsigned int tiling_mode:2;
  1445.         /**
  1446.          * Whether the tiling parameters for the currently associated fence
  1447.          * register have changed. Note that for the purposes of tracking
  1448.          * tiling changes we also treat the unfenced register, the register
  1449.          * slot that the object occupies whilst it executes a fenced
  1450.          * command (such as BLT on gen2/3), as a "fence".
  1451.          */
  1452.         unsigned int fence_dirty:1;
  1453.  
  1454.     /** How many users have pinned this object in GTT space. The following
  1455.      * users can each hold at most one reference: pwrite/pread, pin_ioctl
  1456.      * (via user_pin_count), execbuffer (objects are not allowed multiple
  1457.      * times for the same batchbuffer), and the framebuffer code. When
  1458.      * switching/pageflipping, the framebuffer code has at most two buffers
  1459.      * pinned per crtc.
  1460.      *
  1461.      * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  1462.      * bits with absolutely no headroom. So use 4 bits. */
  1463.         unsigned int pin_count:4;
  1464. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  1465.  
  1466.     /**
  1467.      * Is the object at the current location in the gtt mappable and
  1468.      * fenceable? Used to avoid costly recalculations.
  1469.      */
  1470.         unsigned int map_and_fenceable:1;
  1471.  
  1472.     /**
  1473.      * Whether the current gtt mapping needs to be mappable (and isn't just
  1474.      * mappable by accident). Track pin and fault separate for a more
  1475.      * accurate mappable working set.
  1476.      */
  1477.         unsigned int fault_mappable:1;
  1478.         unsigned int pin_mappable:1;
  1479.         unsigned int pin_display:1;
  1480.  
  1481.     /*
  1482.      * Is the GPU currently using a fence to access this buffer,
  1483.      */
  1484.     unsigned int pending_fenced_gpu_access:1;
  1485.     unsigned int fenced_gpu_access:1;
  1486.  
  1487.         unsigned int cache_level:3;
  1488.  
  1489.         unsigned int has_aliasing_ppgtt_mapping:1;
  1490.         unsigned int has_global_gtt_mapping:1;
  1491.         unsigned int has_dma_mapping:1;
  1492.  
  1493.         struct sg_table *pages;
  1494.         int pages_pin_count;
  1495.  
  1496.         /* prime dma-buf support */
  1497.         void *dma_buf_vmapping;
  1498.         int vmapping_count;
  1499.  
  1500.     /**
  1501.      * Used for performing relocations during execbuffer insertion.
  1502.      */
  1503.     struct hlist_node exec_node;
  1504.     unsigned long exec_handle;
  1505.     struct drm_i915_gem_exec_object2 *exec_entry;
  1506.  
  1507.         struct intel_ring_buffer *ring;
  1508.  
  1509.     /** Breadcrumb of last rendering to the buffer. */
  1510.         uint32_t last_read_seqno;
  1511.         uint32_t last_write_seqno;
  1512.     /** Breadcrumb of last fenced GPU access to the buffer. */
  1513.     uint32_t last_fenced_seqno;
  1514.  
  1515.     /** Current tiling stride for the object, if it's tiled. */
  1516.     uint32_t stride;
  1517.  
  1518.     /** Record of address bit 17 of each page at last unbind. */
  1519.     unsigned long *bit_17;
  1520.  
  1521.     /** User space pin count and filp owning the pin */
  1522.     uint32_t user_pin_count;
  1523.     struct drm_file *pin_filp;
  1524.  
  1525.     /** for phy allocated objects */
  1526.     struct drm_i915_gem_phys_object *phys_obj;
  1527. };
  1528. #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
  1529.  
  1530. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  1531.  
  1532. /**
  1533.  * Request queue structure.
  1534.  *
  1535.  * The request queue allows us to note sequence numbers that have been emitted
  1536.  * and may be associated with active buffers to be retired.
  1537.  *
  1538.  * By keeping this list, we can avoid having to do questionable
  1539.  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  1540.  * an emission time with seqnos for tracking how far ahead of the GPU we are.
  1541.  */
  1542. struct drm_i915_gem_request {
  1543.         /** On Which ring this request was generated */
  1544.         struct intel_ring_buffer *ring;
  1545.  
  1546.         /** GEM sequence number associated with this request. */
  1547.         uint32_t seqno;
  1548.  
  1549.         /** Position in the ringbuffer of the start of the request */
  1550.         u32 head;
  1551.  
  1552.         /** Position in the ringbuffer of the end of the request */
  1553.         u32 tail;
  1554.  
  1555.         /** Context related to this request */
  1556.         struct i915_hw_context *ctx;
  1557.  
  1558.         /** Batch buffer related to this request if any */
  1559.         struct drm_i915_gem_object *batch_obj;
  1560.  
  1561.         /** Time at which this request was emitted, in jiffies. */
  1562.         unsigned long emitted_jiffies;
  1563.  
  1564.         /** global list entry for this request */
  1565.         struct list_head list;
  1566.  
  1567.         struct drm_i915_file_private *file_priv;
  1568.         /** file_priv list entry for this request */
  1569.         struct list_head client_list;
  1570. };
  1571.  
  1572. struct drm_i915_file_private {
  1573.         struct {
  1574.                 spinlock_t lock;
  1575.                 struct list_head request_list;
  1576.         } mm;
  1577.         struct idr context_idr;
  1578.  
  1579.         struct i915_ctx_hang_stats hang_stats;
  1580. };
  1581.  
  1582. #define INTEL_INFO(dev) (to_i915(dev)->info)
  1583.  
  1584. #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
  1585. #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
  1586. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  1587. #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
  1588. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  1589. #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
  1590. #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
  1591. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  1592. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  1593. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  1594. #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
  1595. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  1596. #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
  1597. #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
  1598. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  1599. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  1600. #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
  1601. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  1602. #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
  1603.                                  (dev)->pci_device == 0x0152 || \
  1604.                                  (dev)->pci_device == 0x015a)
  1605. #define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
  1606.                                  (dev)->pci_device == 0x0106 || \
  1607.                                  (dev)->pci_device == 0x010A)
  1608. #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
  1609. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  1610. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  1611. #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
  1612.                                  ((dev)->pci_device & 0xFF00) == 0x0C00)
  1613. #define IS_ULT(dev)             (IS_HASWELL(dev) && \
  1614.                                  ((dev)->pci_device & 0xFF00) == 0x0A00)
  1615.  
  1616. /*
  1617.  * The genX designation typically refers to the render engine, so render
  1618.  * capability related checks should use IS_GEN, while display and other checks
  1619.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  1620.  * chips, etc.).
  1621.  */
  1622. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  1623. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  1624. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  1625. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  1626. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  1627. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  1628.  
  1629. #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
  1630. #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
  1631. #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->has_vebox_ring)
  1632. #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
  1633. #define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
  1634. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  1635.  
  1636. #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
  1637. #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
  1638.  
  1639. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  1640. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  1641.  
  1642. /* Early gen2 have a totally busted CS tlb and require pinned batches. */
  1643. #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
  1644.  
  1645. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1646.  * rows, which changed the alignment requirements and fence programming.
  1647.  */
  1648. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1649.                                                       IS_I915GM(dev)))
  1650. #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1651. #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
  1652. #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
  1653. #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
  1654. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  1655. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  1656.  
  1657. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1658. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1659. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1660.  
  1661. #define HAS_IPS(dev)            (IS_ULT(dev))
  1662.  
  1663. #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
  1664. #define HAS_POWER_WELL(dev)     (IS_HASWELL(dev))
  1665. #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
  1666.  
  1667. #define INTEL_PCH_DEVICE_ID_MASK                0xff00
  1668. #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
  1669. #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
  1670. #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
  1671. #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
  1672. #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
  1673.  
  1674. #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
  1675. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  1676. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1677. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1678. #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
  1679. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  1680.  
  1681. #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
  1682.  
  1683. #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  1684.  
  1685. #define GT_FREQUENCY_MULTIPLIER 50
  1686.  
  1687. #include "i915_trace.h"
  1688.  
  1689. /**
  1690.  * RC6 is a special power stage which allows the GPU to enter an very
  1691.  * low-voltage mode when idle, using down to 0V while at this stage.  This
  1692.  * stage is entered automatically when the GPU is idle when RC6 support is
  1693.  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  1694.  *
  1695.  * There are different RC6 modes available in Intel GPU, which differentiate
  1696.  * among each other with the latency required to enter and leave RC6 and
  1697.  * voltage consumed by the GPU in different states.
  1698.  *
  1699.  * The combination of the following flags define which states GPU is allowed
  1700.  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  1701.  * RC6pp is deepest RC6. Their support by hardware varies according to the
  1702.  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  1703.  * which brings the most power savings; deeper states save more power, but
  1704.  * require higher latency to switch to and wake up.
  1705.  */
  1706. #define INTEL_RC6_ENABLE                        (1<<0)
  1707. #define INTEL_RC6p_ENABLE                       (1<<1)
  1708. #define INTEL_RC6pp_ENABLE                      (1<<2)
  1709.  
  1710. extern unsigned int i915_fbpercrtc      __always_unused;
  1711. extern int i915_panel_ignore_lid        __read_mostly;
  1712. extern unsigned int i915_powersave      __read_mostly;
  1713. extern int i915_semaphores              __read_mostly;
  1714. extern unsigned int i915_lvds_downclock __read_mostly;
  1715. extern int i915_lvds_channel_mode       __read_mostly;
  1716. extern int i915_panel_use_ssc           __read_mostly;
  1717. extern int i915_vbt_sdvo_panel_type     __read_mostly;
  1718. extern int i915_enable_rc6              __read_mostly;
  1719. extern int i915_enable_fbc              __read_mostly;
  1720. extern bool i915_enable_hangcheck       __read_mostly;
  1721. extern int i915_enable_ppgtt            __read_mostly;
  1722. extern int i915_enable_psr __read_mostly;
  1723. extern unsigned int i915_preliminary_hw_support __read_mostly;
  1724. extern int i915_disable_power_well __read_mostly;
  1725. extern int i915_enable_ips __read_mostly;
  1726. extern bool i915_fastboot __read_mostly;
  1727. extern int i915_enable_pc8 __read_mostly;
  1728. extern int i915_pc8_timeout __read_mostly;
  1729. extern bool i915_prefault_disable __read_mostly;
  1730.  
  1731. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1732. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1733.  
  1734.                                 /* i915_dma.c */
  1735. void i915_update_dri1_breadcrumb(struct drm_device *dev);
  1736. extern void i915_kernel_lost_context(struct drm_device * dev);
  1737. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1738. extern int i915_driver_unload(struct drm_device *);
  1739. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1740. extern void i915_driver_lastclose(struct drm_device * dev);
  1741. extern void i915_driver_preclose(struct drm_device *dev,
  1742.                                  struct drm_file *file_priv);
  1743. extern void i915_driver_postclose(struct drm_device *dev,
  1744.                                   struct drm_file *file_priv);
  1745. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1746. #ifdef CONFIG_COMPAT
  1747. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1748.                               unsigned long arg);
  1749. #endif
  1750. extern int i915_emit_box(struct drm_device *dev,
  1751.                          struct drm_clip_rect *box,
  1752.                          int DR1, int DR4);
  1753. extern int intel_gpu_reset(struct drm_device *dev);
  1754. extern int i915_reset(struct drm_device *dev);
  1755. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1756. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1757. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1758. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1759.  
  1760. extern void intel_console_resume(struct work_struct *work);
  1761.  
  1762. /* i915_irq.c */
  1763. void i915_queue_hangcheck(struct drm_device *dev);
  1764. void i915_handle_error(struct drm_device *dev, bool wedged);
  1765.  
  1766. extern void intel_irq_init(struct drm_device *dev);
  1767. extern void intel_pm_init(struct drm_device *dev);
  1768. extern void intel_hpd_init(struct drm_device *dev);
  1769. extern void intel_pm_init(struct drm_device *dev);
  1770.  
  1771. extern void intel_uncore_sanitize(struct drm_device *dev);
  1772. extern void intel_uncore_early_sanitize(struct drm_device *dev);
  1773. extern void intel_uncore_init(struct drm_device *dev);
  1774. extern void intel_uncore_clear_errors(struct drm_device *dev);
  1775. extern void intel_uncore_check_errors(struct drm_device *dev);
  1776.  
  1777. void
  1778. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1779.  
  1780. void
  1781. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1782.  
  1783. /* i915_gem.c */
  1784. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1785.                         struct drm_file *file_priv);
  1786. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1787.                           struct drm_file *file_priv);
  1788. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1789.                          struct drm_file *file_priv);
  1790. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1791.                           struct drm_file *file_priv);
  1792. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1793.                         struct drm_file *file_priv);
  1794. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1795.                         struct drm_file *file_priv);
  1796. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1797.                               struct drm_file *file_priv);
  1798. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1799.                              struct drm_file *file_priv);
  1800. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1801.                         struct drm_file *file_priv);
  1802. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1803.                          struct drm_file *file_priv);
  1804. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1805.                        struct drm_file *file_priv);
  1806. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1807.                          struct drm_file *file_priv);
  1808. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1809.                         struct drm_file *file_priv);
  1810. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  1811.                                struct drm_file *file);
  1812. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  1813.                                struct drm_file *file);
  1814. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1815.                             struct drm_file *file_priv);
  1816. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1817.                            struct drm_file *file_priv);
  1818. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1819.                            struct drm_file *file_priv);
  1820. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1821.                            struct drm_file *file_priv);
  1822. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1823.                         struct drm_file *file_priv);
  1824. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1825.                         struct drm_file *file_priv);
  1826. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1827.                                 struct drm_file *file_priv);
  1828. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  1829.                         struct drm_file *file_priv);
  1830. void i915_gem_load(struct drm_device *dev);
  1831. void *i915_gem_object_alloc(struct drm_device *dev);
  1832. void i915_gem_object_free(struct drm_i915_gem_object *obj);
  1833. int i915_gem_init_object(struct drm_gem_object *obj);
  1834. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  1835.                          const struct drm_i915_gem_object_ops *ops);
  1836. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1837.                                                   size_t size);
  1838. void i915_gem_free_object(struct drm_gem_object *obj);
  1839. struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
  1840.                                      struct i915_address_space *vm);
  1841. void i915_gem_vma_destroy(struct i915_vma *vma);
  1842.  
  1843. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1844.                                      struct i915_address_space *vm,
  1845.                                      uint32_t alignment,
  1846.                                      bool map_and_fenceable,
  1847.                                      bool nonblocking);
  1848. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1849. int __must_check i915_vma_unbind(struct i915_vma *vma);
  1850. int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
  1851. int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
  1852. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1853. void i915_gem_lastclose(struct drm_device *dev);
  1854.  
  1855. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  1856. static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  1857. {
  1858.         struct sg_page_iter sg_iter;
  1859.  
  1860.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
  1861.                 return sg_page_iter_page(&sg_iter);
  1862.  
  1863.         return NULL;
  1864. }
  1865. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  1866. {
  1867.         BUG_ON(obj->pages == NULL);
  1868.         obj->pages_pin_count++;
  1869. }
  1870. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  1871. {
  1872.         BUG_ON(obj->pages_pin_count == 0);
  1873.         obj->pages_pin_count--;
  1874. }
  1875.  
  1876. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1877. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  1878.                          struct intel_ring_buffer *to);
  1879. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1880.                                     struct intel_ring_buffer *ring);
  1881.  
  1882. int i915_gem_dumb_create(struct drm_file *file_priv,
  1883.                          struct drm_device *dev,
  1884.                          struct drm_mode_create_dumb *args);
  1885. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1886.                       uint32_t handle, uint64_t *offset);
  1887. /**
  1888.  * Returns true if seq1 is later than seq2.
  1889.  */
  1890. static inline bool
  1891. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1892. {
  1893.         return (int32_t)(seq1 - seq2) >= 0;
  1894. }
  1895.  
  1896. int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
  1897. int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
  1898. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  1899. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1900.  
  1901. static inline bool
  1902. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  1903. {
  1904.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1905.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1906.                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
  1907.                 return true;
  1908.         } else
  1909.                 return false;
  1910. }
  1911.  
  1912. static inline void
  1913. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  1914. {
  1915.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1916.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1917.                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
  1918.                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
  1919.         }
  1920. }
  1921.  
  1922. void i915_gem_retire_requests(struct drm_device *dev);
  1923. void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
  1924. int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
  1925.                                       bool interruptible);
  1926. static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
  1927. {
  1928.         return unlikely(atomic_read(&error->reset_counter)
  1929.                         & I915_RESET_IN_PROGRESS_FLAG);
  1930. }
  1931.  
  1932. static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
  1933. {
  1934.         return atomic_read(&error->reset_counter) == I915_WEDGED;
  1935. }
  1936.  
  1937. void i915_gem_reset(struct drm_device *dev);
  1938. bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
  1939. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1940. int __must_check i915_gem_init(struct drm_device *dev);
  1941. int __must_check i915_gem_init_hw(struct drm_device *dev);
  1942. void i915_gem_l3_remap(struct drm_device *dev);
  1943. void i915_gem_init_swizzling(struct drm_device *dev);
  1944. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1945. int __must_check i915_gpu_idle(struct drm_device *dev);
  1946. int __must_check i915_gem_idle(struct drm_device *dev);
  1947. int __i915_add_request(struct intel_ring_buffer *ring,
  1948.                                   struct drm_file *file,
  1949.                        struct drm_i915_gem_object *batch_obj,
  1950.                      u32 *seqno);
  1951. #define i915_add_request(ring, seqno) \
  1952.         __i915_add_request(ring, NULL, NULL, seqno)
  1953. int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
  1954.                                    uint32_t seqno);
  1955. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1956. int __must_check
  1957. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1958.                                   bool write);
  1959. int __must_check
  1960. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  1961. int __must_check
  1962. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1963.                                      u32 alignment,
  1964.                                      struct intel_ring_buffer *pipelined);
  1965. void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
  1966. int i915_gem_attach_phys_object(struct drm_device *dev,
  1967.                                 struct drm_i915_gem_object *obj,
  1968.                                 int id,
  1969.                                 int align);
  1970. void i915_gem_detach_phys_object(struct drm_device *dev,
  1971.                                  struct drm_i915_gem_object *obj);
  1972. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1973. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1974.  
  1975. uint32_t
  1976. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
  1977. uint32_t
  1978. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  1979.                             int tiling_mode, bool fenced);
  1980.  
  1981. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1982.                                     enum i915_cache_level cache_level);
  1983.  
  1984. struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
  1985.                                 struct dma_buf *dma_buf);
  1986.  
  1987. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  1988.                                 struct drm_gem_object *gem_obj, int flags);
  1989.  
  1990. void i915_gem_restore_fences(struct drm_device *dev);
  1991.  
  1992. unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
  1993.                                   struct i915_address_space *vm);
  1994. bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
  1995. bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
  1996.                         struct i915_address_space *vm);
  1997. unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
  1998.                                 struct i915_address_space *vm);
  1999. struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
  2000.                                      struct i915_address_space *vm);
  2001. struct i915_vma *
  2002. i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
  2003.                                   struct i915_address_space *vm);
  2004. /* Some GGTT VM helpers */
  2005. #define obj_to_ggtt(obj) \
  2006.         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
  2007. static inline bool i915_is_ggtt(struct i915_address_space *vm)
  2008. {
  2009.         struct i915_address_space *ggtt =
  2010.                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
  2011.         return vm == ggtt;
  2012. }
  2013.  
  2014. static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
  2015. {
  2016.         return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
  2017. }
  2018.  
  2019. static inline unsigned long
  2020. i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
  2021. {
  2022.         return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
  2023. }
  2024.  
  2025. static inline unsigned long
  2026. i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
  2027. {
  2028.         return i915_gem_obj_size(obj, obj_to_ggtt(obj));
  2029. }
  2030.  
  2031. static inline int __must_check
  2032. i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
  2033.                       uint32_t alignment,
  2034.                       bool map_and_fenceable,
  2035.                       bool nonblocking)
  2036. {
  2037.         return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
  2038.                                    map_and_fenceable, nonblocking);
  2039. }
  2040. #undef obj_to_ggtt
  2041.  
  2042. /* i915_gem_context.c */
  2043. void i915_gem_context_init(struct drm_device *dev);
  2044. void i915_gem_context_fini(struct drm_device *dev);
  2045. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  2046. int i915_switch_context(struct intel_ring_buffer *ring,
  2047.                         struct drm_file *file, int to_id);
  2048. void i915_gem_context_free(struct kref *ctx_ref);
  2049. static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
  2050. {
  2051.         kref_get(&ctx->ref);
  2052. }
  2053.  
  2054. static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
  2055. {
  2056.         kref_put(&ctx->ref, i915_gem_context_free);
  2057. }
  2058.  
  2059. struct i915_ctx_hang_stats * __must_check
  2060. i915_gem_context_get_hang_stats(struct drm_device *dev,
  2061.                                 struct drm_file *file,
  2062.                                 u32 id);
  2063. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  2064.                                   struct drm_file *file);
  2065. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  2066.                                    struct drm_file *file);
  2067.  
  2068. /* i915_gem_gtt.c */
  2069. void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
  2070. void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
  2071.                             struct drm_i915_gem_object *obj,
  2072.                             enum i915_cache_level cache_level);
  2073. void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  2074.                               struct drm_i915_gem_object *obj);
  2075.  
  2076. void i915_check_and_clear_faults(struct drm_device *dev);
  2077. void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
  2078. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  2079. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  2080. void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
  2081.                                 enum i915_cache_level cache_level);
  2082. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  2083. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  2084. void i915_gem_init_global_gtt(struct drm_device *dev);
  2085. void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
  2086.                                unsigned long mappable_end, unsigned long end);
  2087. int i915_gem_gtt_init(struct drm_device *dev);
  2088. static inline void i915_gem_chipset_flush(struct drm_device *dev)
  2089. {
  2090.         if (INTEL_INFO(dev)->gen < 6)
  2091.                 intel_gtt_chipset_flush();
  2092. }
  2093.  
  2094.  
  2095. /* i915_gem_evict.c */
  2096. int __must_check i915_gem_evict_something(struct drm_device *dev,
  2097.                                           struct i915_address_space *vm,
  2098.                                           int min_size,
  2099.                                           unsigned alignment,
  2100.                                           unsigned cache_level,
  2101.                                           bool mappable,
  2102.                                           bool nonblock);
  2103. int i915_gem_evict_everything(struct drm_device *dev);
  2104.  
  2105. /* i915_gem_stolen.c */
  2106. int i915_gem_init_stolen(struct drm_device *dev);
  2107. int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
  2108. void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
  2109. void i915_gem_cleanup_stolen(struct drm_device *dev);
  2110. struct drm_i915_gem_object *
  2111. i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
  2112. struct drm_i915_gem_object *
  2113. i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
  2114.                                                u32 stolen_offset,
  2115.                                                u32 gtt_offset,
  2116.                                                u32 size);
  2117. void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
  2118.  
  2119. /* i915_gem_tiling.c */
  2120. static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
  2121. {
  2122.         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
  2123.  
  2124.         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
  2125.                 obj->tiling_mode != I915_TILING_NONE;
  2126. }
  2127.  
  2128. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  2129. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  2130. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  2131.  
  2132. /* i915_gem_debug.c */
  2133. #if WATCH_LISTS
  2134. int i915_verify_lists(struct drm_device *dev);
  2135. #else
  2136. #define i915_verify_lists(dev) 0
  2137. #endif
  2138.  
  2139. /* i915_debugfs.c */
  2140. int i915_debugfs_init(struct drm_minor *minor);
  2141. void i915_debugfs_cleanup(struct drm_minor *minor);
  2142.  
  2143. /* i915_gpu_error.c */
  2144. __printf(2, 3)
  2145. void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
  2146. int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
  2147.                             const struct i915_error_state_file_priv *error);
  2148. int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
  2149.                               size_t count, loff_t pos);
  2150. static inline void i915_error_state_buf_release(
  2151.         struct drm_i915_error_state_buf *eb)
  2152. {
  2153.         kfree(eb->buf);
  2154. }
  2155. void i915_capture_error_state(struct drm_device *dev);
  2156. void i915_error_state_get(struct drm_device *dev,
  2157.                           struct i915_error_state_file_priv *error_priv);
  2158. void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
  2159. void i915_destroy_error_state(struct drm_device *dev);
  2160.  
  2161. void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
  2162. const char *i915_cache_level_str(int type);
  2163.  
  2164. /* i915_suspend.c */
  2165. extern int i915_save_state(struct drm_device *dev);
  2166. extern int i915_restore_state(struct drm_device *dev);
  2167.  
  2168. /* i915_ums.c */
  2169. void i915_save_display_reg(struct drm_device *dev);
  2170. void i915_restore_display_reg(struct drm_device *dev);
  2171.  
  2172. /* i915_sysfs.c */
  2173. void i915_setup_sysfs(struct drm_device *dev_priv);
  2174. void i915_teardown_sysfs(struct drm_device *dev_priv);
  2175.  
  2176. /* intel_i2c.c */
  2177. extern int intel_setup_gmbus(struct drm_device *dev);
  2178. extern void intel_teardown_gmbus(struct drm_device *dev);
  2179. static inline bool intel_gmbus_is_port_valid(unsigned port)
  2180. {
  2181.         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  2182. }
  2183.  
  2184. extern struct i2c_adapter *intel_gmbus_get_adapter(
  2185.                 struct drm_i915_private *dev_priv, unsigned port);
  2186. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  2187. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  2188. static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  2189. {
  2190.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  2191. }
  2192. extern void intel_i2c_reset(struct drm_device *dev);
  2193.  
  2194. /* intel_opregion.c */
  2195. extern int intel_opregion_setup(struct drm_device *dev);
  2196. #ifdef CONFIG_ACPI
  2197. extern void intel_opregion_init(struct drm_device *dev);
  2198. extern void intel_opregion_fini(struct drm_device *dev);
  2199. extern void intel_opregion_asle_intr(struct drm_device *dev);
  2200. #else
  2201. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  2202. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  2203. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  2204. #endif
  2205.  
  2206. /* intel_acpi.c */
  2207. #ifdef CONFIG_ACPI
  2208. extern void intel_register_dsm_handler(void);
  2209. extern void intel_unregister_dsm_handler(void);
  2210. #else
  2211. static inline void intel_register_dsm_handler(void) { return; }
  2212. static inline void intel_unregister_dsm_handler(void) { return; }
  2213. #endif /* CONFIG_ACPI */
  2214.  
  2215. /* modesetting */
  2216. extern void intel_modeset_init_hw(struct drm_device *dev);
  2217. extern void intel_modeset_suspend_hw(struct drm_device *dev);
  2218. extern void intel_modeset_init(struct drm_device *dev);
  2219. extern void intel_modeset_gem_init(struct drm_device *dev);
  2220. extern void intel_modeset_cleanup(struct drm_device *dev);
  2221. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  2222. extern void intel_modeset_setup_hw_state(struct drm_device *dev,
  2223.                                          bool force_restore);
  2224. extern void i915_redisable_vga(struct drm_device *dev);
  2225. extern bool intel_fbc_enabled(struct drm_device *dev);
  2226. extern void intel_disable_fbc(struct drm_device *dev);
  2227. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  2228. extern void intel_init_pch_refclk(struct drm_device *dev);
  2229. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  2230. extern void valleyview_set_rps(struct drm_device *dev, u8 val);
  2231. extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
  2232. extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
  2233. extern void intel_detect_pch(struct drm_device *dev);
  2234. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  2235. extern int intel_enable_rc6(const struct drm_device *dev);
  2236.  
  2237. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  2238. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  2239.                         struct drm_file *file);
  2240.  
  2241. /* overlay */
  2242. #ifdef CONFIG_DEBUG_FS
  2243. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  2244. extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
  2245.                                             struct intel_overlay_error_state *error);
  2246.  
  2247. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  2248. extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
  2249.                                             struct drm_device *dev,
  2250.                                             struct intel_display_error_state *error);
  2251. #endif
  2252.  
  2253. /* On SNB platform, before reading ring registers forcewake bit
  2254.  * must be set to prevent GT core from power down and stale values being
  2255.  * returned.
  2256.  */
  2257. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  2258. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  2259.  
  2260. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
  2261. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
  2262.  
  2263. /* intel_sideband.c */
  2264. u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
  2265. void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
  2266. u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  2267. u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
  2268. void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
  2269. u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  2270.                    enum intel_sbi_destination destination);
  2271. void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  2272.                      enum intel_sbi_destination destination);
  2273.  
  2274. int vlv_gpu_freq(int ddr_freq, int val);
  2275. int vlv_freq_opcode(int ddr_freq, int val);
  2276.  
  2277. #define __i915_read(x) \
  2278.         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
  2279. __i915_read(8)
  2280. __i915_read(16)
  2281. __i915_read(32)
  2282. __i915_read(64)
  2283. #undef __i915_read
  2284.  
  2285. #define __i915_write(x) \
  2286.         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace);
  2287. __i915_write(8)
  2288. __i915_write(16)
  2289. __i915_write(32)
  2290. __i915_write(64)
  2291. #undef __i915_write
  2292.  
  2293. #define I915_READ8(reg)         i915_read8(dev_priv, (reg), true)
  2294. #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val), true)
  2295.  
  2296. #define I915_READ16(reg)        i915_read16(dev_priv, (reg), true)
  2297. #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val), true)
  2298. #define I915_READ16_NOTRACE(reg)        i915_read16(dev_priv, (reg), false)
  2299. #define I915_WRITE16_NOTRACE(reg, val)  i915_write16(dev_priv, (reg), (val), false)
  2300.  
  2301. #define I915_READ(reg)          i915_read32(dev_priv, (reg), true)
  2302. #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val), true)
  2303. #define I915_READ_NOTRACE(reg)          i915_read32(dev_priv, (reg), false)
  2304. #define I915_WRITE_NOTRACE(reg, val)    i915_write32(dev_priv, (reg), (val), false)
  2305.  
  2306. #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val), true)
  2307. #define I915_READ64(reg)        i915_read64(dev_priv, (reg), true)
  2308.  
  2309. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  2310. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  2311.  
  2312. /* "Broadcast RGB" property */
  2313. #define INTEL_BROADCAST_RGB_AUTO 0
  2314. #define INTEL_BROADCAST_RGB_FULL 1
  2315. #define INTEL_BROADCAST_RGB_LIMITED 2
  2316.  
  2317. static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
  2318. {
  2319.         if (HAS_PCH_SPLIT(dev))
  2320.                 return CPU_VGACNTRL;
  2321.         else if (IS_VALLEYVIEW(dev))
  2322.                 return VLV_VGACNTRL;
  2323.         else
  2324.                 return VGACNTRL;
  2325. }
  2326.  
  2327. static inline void __user *to_user_ptr(u64 address)
  2328. {
  2329.         return (void __user *)(uintptr_t)address;
  2330. }
  2331.  
  2332. static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
  2333. {
  2334.         unsigned long j = msecs_to_jiffies(m);
  2335.  
  2336.         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  2337. }
  2338.  
  2339. static inline unsigned long
  2340. timespec_to_jiffies_timeout(const struct timespec *value)
  2341. {
  2342.         unsigned long j = timespec_to_jiffies(value);
  2343.  
  2344.         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  2345. }
  2346.  
  2347. static inline int mutex_trylock(struct mutex *lock)
  2348. {
  2349.     if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1))
  2350.         return 1;
  2351.     return 0;
  2352. }
  2353.  
  2354. typedef struct
  2355. {
  2356.   int width;
  2357.   int height;
  2358.   int bpp;
  2359.   int freq;
  2360. }videomode_t;
  2361.  
  2362. struct cmdtable
  2363. {
  2364.     char *key;
  2365.     int   size;
  2366.     int  *val;
  2367. };
  2368.  
  2369. #define CMDENTRY(key, val) {(key), (sizeof(key)-1), &val}
  2370.  
  2371. void parse_cmdline(char *cmdline, struct cmdtable *table, char *log, videomode_t *mode);
  2372. struct drm_i915_gem_object
  2373. *kos_gem_fb_object_create(struct drm_device *dev, u32 gtt_offset, u32 size);
  2374.  
  2375. extern struct drm_i915_gem_object *fb_obj;
  2376. static struct drm_i915_gem_object *get_fb_obj()
  2377. {
  2378.     return fb_obj;
  2379. };
  2380.  
  2381.  
  2382. #define ioread32(addr)          readl(addr)
  2383.  
  2384.  
  2385. #endif
  2386.