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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #include <linux/device.h>
  31. #include <linux/acpi.h>
  32. #include <drm/drmP.h>
  33. #include <drm/i915_drm.h>
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include "intel_drv.h"
  37.  
  38. #include <linux/module.h>
  39. #include <linux/pm_runtime.h>
  40. #include <linux/mod_devicetable.h>
  41. #include <linux/pci.h>
  42. #include <drm/i915_pciids.h>
  43.  
  44. #include <drm/drm_crtc_helper.h>
  45.  
  46. #include <syscall.h>
  47.  
  48. static struct drm_driver driver;
  49.  
  50. #define GEN_DEFAULT_PIPEOFFSETS \
  51.         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  52.                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  53.         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  54.                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  55.         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  56.  
  57. #define GEN_CHV_PIPEOFFSETS \
  58.         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  59.                           CHV_PIPE_C_OFFSET }, \
  60.         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  61.                            CHV_TRANSCODER_C_OFFSET, }, \
  62.         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  63.                              CHV_PALETTE_C_OFFSET }
  64.  
  65. #define CURSOR_OFFSETS \
  66.         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  67.  
  68. #define IVB_CURSOR_OFFSETS \
  69.         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  70.  
  71. int init_display_kms(struct drm_device *dev);
  72.  
  73.  
  74. extern int intel_agp_enabled;
  75.  
  76. #define PCI_VENDOR_ID_INTEL        0x8086
  77.  
  78.  
  79. static const struct intel_device_info intel_i915g_info = {
  80.         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  81.         .has_overlay = 1, .overlay_needs_physical = 1,
  82.         .ring_mask = RENDER_RING,
  83.         GEN_DEFAULT_PIPEOFFSETS,
  84.         CURSOR_OFFSETS,
  85. };
  86. static const struct intel_device_info intel_i915gm_info = {
  87.         .gen = 3, .is_mobile = 1, .num_pipes = 2,
  88.         .cursor_needs_physical = 1,
  89.         .has_overlay = 1, .overlay_needs_physical = 1,
  90.         .supports_tv = 1,
  91.         .has_fbc = 1,
  92.         .ring_mask = RENDER_RING,
  93.         GEN_DEFAULT_PIPEOFFSETS,
  94.         CURSOR_OFFSETS,
  95. };
  96. static const struct intel_device_info intel_i945g_info = {
  97.         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  98.         .has_overlay = 1, .overlay_needs_physical = 1,
  99.         .ring_mask = RENDER_RING,
  100.         GEN_DEFAULT_PIPEOFFSETS,
  101.         CURSOR_OFFSETS,
  102. };
  103. static const struct intel_device_info intel_i945gm_info = {
  104.         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
  105.         .has_hotplug = 1, .cursor_needs_physical = 1,
  106.         .has_overlay = 1, .overlay_needs_physical = 1,
  107.         .supports_tv = 1,
  108.         .has_fbc = 1,
  109.         .ring_mask = RENDER_RING,
  110.         GEN_DEFAULT_PIPEOFFSETS,
  111.         CURSOR_OFFSETS,
  112. };
  113.  
  114. static const struct intel_device_info intel_i965g_info = {
  115.         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
  116.         .has_hotplug = 1,
  117.         .has_overlay = 1,
  118.         .ring_mask = RENDER_RING,
  119.         GEN_DEFAULT_PIPEOFFSETS,
  120.         CURSOR_OFFSETS,
  121. };
  122.  
  123. static const struct intel_device_info intel_i965gm_info = {
  124.         .gen = 4, .is_crestline = 1, .num_pipes = 2,
  125.         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  126.         .has_overlay = 1,
  127.         .supports_tv = 1,
  128.         .ring_mask = RENDER_RING,
  129.         GEN_DEFAULT_PIPEOFFSETS,
  130.         CURSOR_OFFSETS,
  131. };
  132.  
  133. static const struct intel_device_info intel_g33_info = {
  134.         .gen = 3, .is_g33 = 1, .num_pipes = 2,
  135.         .need_gfx_hws = 1, .has_hotplug = 1,
  136.         .has_overlay = 1,
  137.         .ring_mask = RENDER_RING,
  138.         GEN_DEFAULT_PIPEOFFSETS,
  139.         CURSOR_OFFSETS,
  140. };
  141.  
  142. static const struct intel_device_info intel_g45_info = {
  143.         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
  144.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  145.         .ring_mask = RENDER_RING | BSD_RING,
  146.         GEN_DEFAULT_PIPEOFFSETS,
  147.         CURSOR_OFFSETS,
  148. };
  149.  
  150. static const struct intel_device_info intel_gm45_info = {
  151.         .gen = 4, .is_g4x = 1, .num_pipes = 2,
  152.         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
  153.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  154.         .supports_tv = 1,
  155.         .ring_mask = RENDER_RING | BSD_RING,
  156.         GEN_DEFAULT_PIPEOFFSETS,
  157.         CURSOR_OFFSETS,
  158. };
  159.  
  160. static const struct intel_device_info intel_pineview_info = {
  161.         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
  162.         .need_gfx_hws = 1, .has_hotplug = 1,
  163.         .has_overlay = 1,
  164.         GEN_DEFAULT_PIPEOFFSETS,
  165.         CURSOR_OFFSETS,
  166. };
  167.  
  168. static const struct intel_device_info intel_ironlake_d_info = {
  169.         .gen = 5, .num_pipes = 2,
  170.         .need_gfx_hws = 1, .has_hotplug = 1,
  171.         .ring_mask = RENDER_RING | BSD_RING,
  172.         GEN_DEFAULT_PIPEOFFSETS,
  173.         CURSOR_OFFSETS,
  174. };
  175.  
  176. static const struct intel_device_info intel_ironlake_m_info = {
  177.         .gen = 5, .is_mobile = 1, .num_pipes = 2,
  178.         .need_gfx_hws = 1, .has_hotplug = 1,
  179.         .has_fbc = 1,
  180.         .ring_mask = RENDER_RING | BSD_RING,
  181.         GEN_DEFAULT_PIPEOFFSETS,
  182.         CURSOR_OFFSETS,
  183. };
  184.  
  185. static const struct intel_device_info intel_sandybridge_d_info = {
  186.         .gen = 6, .num_pipes = 2,
  187.         .need_gfx_hws = 1, .has_hotplug = 1,
  188.         .has_fbc = 1,
  189.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
  190.         .has_llc = 1,
  191.         GEN_DEFAULT_PIPEOFFSETS,
  192.         CURSOR_OFFSETS,
  193. };
  194.  
  195. static const struct intel_device_info intel_sandybridge_m_info = {
  196.         .gen = 6, .is_mobile = 1, .num_pipes = 2,
  197.         .need_gfx_hws = 1, .has_hotplug = 1,
  198.         .has_fbc = 1,
  199.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
  200.         .has_llc = 1,
  201.         GEN_DEFAULT_PIPEOFFSETS,
  202.         CURSOR_OFFSETS,
  203. };
  204.  
  205. #define GEN7_FEATURES  \
  206.         .gen = 7, .num_pipes = 3, \
  207.         .need_gfx_hws = 1, .has_hotplug = 1, \
  208.         .has_fbc = 1, \
  209.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
  210.         .has_llc = 1
  211.  
  212. static const struct intel_device_info intel_ivybridge_d_info = {
  213.         GEN7_FEATURES,
  214.         .is_ivybridge = 1,
  215.         GEN_DEFAULT_PIPEOFFSETS,
  216.         IVB_CURSOR_OFFSETS,
  217. };
  218.  
  219. static const struct intel_device_info intel_ivybridge_m_info = {
  220.         GEN7_FEATURES,
  221.         .is_ivybridge = 1,
  222.         .is_mobile = 1,
  223.         GEN_DEFAULT_PIPEOFFSETS,
  224.         IVB_CURSOR_OFFSETS,
  225. };
  226.  
  227. static const struct intel_device_info intel_ivybridge_q_info = {
  228.         GEN7_FEATURES,
  229.         .is_ivybridge = 1,
  230.         .num_pipes = 0, /* legal, last one wins */
  231.         GEN_DEFAULT_PIPEOFFSETS,
  232.         IVB_CURSOR_OFFSETS,
  233. };
  234.  
  235. static const struct intel_device_info intel_valleyview_m_info = {
  236.         GEN7_FEATURES,
  237.         .is_mobile = 1,
  238.         .num_pipes = 2,
  239.         .is_valleyview = 1,
  240.         .display_mmio_offset = VLV_DISPLAY_BASE,
  241.         .has_fbc = 0, /* legal, last one wins */
  242.         .has_llc = 0, /* legal, last one wins */
  243.         GEN_DEFAULT_PIPEOFFSETS,
  244.         CURSOR_OFFSETS,
  245. };
  246.  
  247. static const struct intel_device_info intel_valleyview_d_info = {
  248.         GEN7_FEATURES,
  249.         .num_pipes = 2,
  250.         .is_valleyview = 1,
  251.         .display_mmio_offset = VLV_DISPLAY_BASE,
  252.         .has_fbc = 0, /* legal, last one wins */
  253.         .has_llc = 0, /* legal, last one wins */
  254.         GEN_DEFAULT_PIPEOFFSETS,
  255.         CURSOR_OFFSETS,
  256. };
  257.  
  258. static const struct intel_device_info intel_haswell_d_info = {
  259.         GEN7_FEATURES,
  260.         .is_haswell = 1,
  261.         .has_ddi = 1,
  262.         .has_fpga_dbg = 1,
  263.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  264.         GEN_DEFAULT_PIPEOFFSETS,
  265.         IVB_CURSOR_OFFSETS,
  266. };
  267.  
  268. static const struct intel_device_info intel_haswell_m_info = {
  269.         GEN7_FEATURES,
  270.         .is_haswell = 1,
  271.         .is_mobile = 1,
  272.         .has_ddi = 1,
  273.         .has_fpga_dbg = 1,
  274.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  275.         GEN_DEFAULT_PIPEOFFSETS,
  276.         IVB_CURSOR_OFFSETS,
  277. };
  278.  
  279. static const struct intel_device_info intel_broadwell_d_info = {
  280.         .gen = 8, .num_pipes = 3,
  281.         .need_gfx_hws = 1, .has_hotplug = 1,
  282.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  283.         .has_llc = 1,
  284.         .has_ddi = 1,
  285.         .has_fpga_dbg = 1,
  286.         .has_fbc = 1,
  287.         GEN_DEFAULT_PIPEOFFSETS,
  288.         IVB_CURSOR_OFFSETS,
  289. };
  290.  
  291. static const struct intel_device_info intel_broadwell_m_info = {
  292.         .gen = 8, .is_mobile = 1, .num_pipes = 3,
  293.         .need_gfx_hws = 1, .has_hotplug = 1,
  294.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  295.         .has_llc = 1,
  296.         .has_ddi = 1,
  297.         .has_fpga_dbg = 1,
  298.         .has_fbc = 1,
  299.         GEN_DEFAULT_PIPEOFFSETS,
  300.         IVB_CURSOR_OFFSETS,
  301. };
  302.  
  303. static const struct intel_device_info intel_broadwell_gt3d_info = {
  304.         .gen = 8, .num_pipes = 3,
  305.         .need_gfx_hws = 1, .has_hotplug = 1,
  306.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
  307.         .has_llc = 1,
  308.         .has_ddi = 1,
  309.         .has_fpga_dbg = 1,
  310.         .has_fbc = 1,
  311.         GEN_DEFAULT_PIPEOFFSETS,
  312.         IVB_CURSOR_OFFSETS,
  313. };
  314.  
  315. static const struct intel_device_info intel_broadwell_gt3m_info = {
  316.         .gen = 8, .is_mobile = 1, .num_pipes = 3,
  317.         .need_gfx_hws = 1, .has_hotplug = 1,
  318.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
  319.         .has_llc = 1,
  320.         .has_ddi = 1,
  321.         .has_fpga_dbg = 1,
  322.         .has_fbc = 1,
  323.         GEN_DEFAULT_PIPEOFFSETS,
  324.         IVB_CURSOR_OFFSETS,
  325. };
  326.  
  327. static const struct intel_device_info intel_cherryview_info = {
  328.         .gen = 8, .num_pipes = 3,
  329.         .need_gfx_hws = 1, .has_hotplug = 1,
  330.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  331.         .is_valleyview = 1,
  332.         .display_mmio_offset = VLV_DISPLAY_BASE,
  333.         GEN_CHV_PIPEOFFSETS,
  334.         CURSOR_OFFSETS,
  335. };
  336.  
  337. static const struct intel_device_info intel_skylake_info = {
  338.         .is_skylake = 1,
  339.         .gen = 9, .num_pipes = 3,
  340.         .need_gfx_hws = 1, .has_hotplug = 1,
  341.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  342.         .has_llc = 1,
  343.         .has_ddi = 1,
  344.         .has_fpga_dbg = 1,
  345.         .has_fbc = 1,
  346.         GEN_DEFAULT_PIPEOFFSETS,
  347.         IVB_CURSOR_OFFSETS,
  348. };
  349.  
  350. static const struct intel_device_info intel_skylake_gt3_info = {
  351.         .is_skylake = 1,
  352.         .gen = 9, .num_pipes = 3,
  353.         .need_gfx_hws = 1, .has_hotplug = 1,
  354.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
  355.         .has_llc = 1,
  356.         .has_ddi = 1,
  357.         .has_fpga_dbg = 1,
  358.         .has_fbc = 1,
  359.         GEN_DEFAULT_PIPEOFFSETS,
  360.         IVB_CURSOR_OFFSETS,
  361. };
  362.  
  363. static const struct intel_device_info intel_broxton_info = {
  364.         .is_preliminary = 1,
  365.         .gen = 9,
  366.         .need_gfx_hws = 1, .has_hotplug = 1,
  367.         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
  368.         .num_pipes = 3,
  369.         .has_ddi = 1,
  370.         .has_fpga_dbg = 1,
  371.         .has_fbc = 1,
  372.         GEN_DEFAULT_PIPEOFFSETS,
  373.         IVB_CURSOR_OFFSETS,
  374. };
  375.  
  376. /*
  377.  * Make sure any device matches here are from most specific to most
  378.  * general.  For example, since the Quanta match is based on the subsystem
  379.  * and subvendor IDs, we need it to come before the more general IVB
  380.  * PCI ID matches, otherwise we'll use the wrong info struct above.
  381.  */
  382. #define INTEL_PCI_IDS \
  383.         INTEL_I915G_IDS(&intel_i915g_info),     \
  384.         INTEL_I915GM_IDS(&intel_i915gm_info),   \
  385.         INTEL_I945G_IDS(&intel_i945g_info),     \
  386.         INTEL_I945GM_IDS(&intel_i945gm_info),   \
  387.         INTEL_I965G_IDS(&intel_i965g_info),     \
  388.         INTEL_G33_IDS(&intel_g33_info),         \
  389.         INTEL_I965GM_IDS(&intel_i965gm_info),   \
  390.         INTEL_GM45_IDS(&intel_gm45_info),       \
  391.         INTEL_G45_IDS(&intel_g45_info),         \
  392.         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
  393.         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
  394.         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
  395.         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
  396.         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
  397.         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
  398.         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
  399.         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
  400.         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
  401.         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
  402.         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
  403.         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
  404.         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
  405.         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
  406.         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
  407.         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
  408.         INTEL_CHV_IDS(&intel_cherryview_info),  \
  409.         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
  410.         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
  411.         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),     \
  412.         INTEL_BXT_IDS(&intel_broxton_info)
  413.  
  414. static const struct pci_device_id pciidlist[] = {               /* aka */
  415.         INTEL_PCI_IDS,
  416.         {0, 0, 0}
  417. };
  418.  
  419. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  420. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  421. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  422. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  423. #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
  424. static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
  425. {
  426.         enum intel_pch ret = PCH_NOP;
  427.  
  428.         /*
  429.          * In a virtualized passthrough environment we can be in a
  430.          * setup where the ISA bridge is not able to be passed through.
  431.          * In this case, a south bridge can be emulated and we have to
  432.          * make an educated guess as to which PCH is really there.
  433.          */
  434.  
  435.         if (IS_GEN5(dev)) {
  436.                 ret = PCH_IBX;
  437.                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
  438.         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
  439.                 ret = PCH_CPT;
  440.                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
  441.         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  442.                 ret = PCH_LPT;
  443.                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
  444.         } else if (IS_SKYLAKE(dev)) {
  445.                 ret = PCH_SPT;
  446.                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
  447.         }
  448.  
  449.         return ret;
  450. }
  451.  
  452. void intel_detect_pch(struct drm_device *dev)
  453. {
  454.         struct drm_i915_private *dev_priv = dev->dev_private;
  455.         struct pci_dev *pch = NULL;
  456.  
  457.         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
  458.          * (which really amounts to a PCH but no South Display).
  459.          */
  460.         if (INTEL_INFO(dev)->num_pipes == 0) {
  461.                 dev_priv->pch_type = PCH_NOP;
  462.                 return;
  463.         }
  464.  
  465.         /*
  466.          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  467.          * make graphics device passthrough work easy for VMM, that only
  468.          * need to expose ISA bridge to let driver know the real hardware
  469.          * underneath. This is a requirement from virtualization team.
  470.          *
  471.          * In some virtualized environments (e.g. XEN), there is irrelevant
  472.          * ISA bridge in the system. To work reliably, we should scan trhough
  473.          * all the ISA bridge devices and check for the first match, instead
  474.          * of only checking the first one.
  475.          */
  476.         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
  477.                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  478.                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  479.                         dev_priv->pch_id = id;
  480.  
  481.                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  482.                                 dev_priv->pch_type = PCH_IBX;
  483.                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  484.                                 WARN_ON(!IS_GEN5(dev));
  485.                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  486.                                 dev_priv->pch_type = PCH_CPT;
  487.                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  488.                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  489.                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  490.                                 /* PantherPoint is CPT compatible */
  491.                                 dev_priv->pch_type = PCH_CPT;
  492.                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
  493.                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  494.                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  495.                                 dev_priv->pch_type = PCH_LPT;
  496.                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
  497.                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
  498.                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
  499.                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  500.                                 dev_priv->pch_type = PCH_LPT;
  501.                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
  502.                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
  503.                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
  504.                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
  505.                                 dev_priv->pch_type = PCH_SPT;
  506.                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
  507.                                 WARN_ON(!IS_SKYLAKE(dev));
  508.                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
  509.                                 dev_priv->pch_type = PCH_SPT;
  510.                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
  511.                                 WARN_ON(!IS_SKYLAKE(dev));
  512.                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
  513.                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
  514.                                     pch->subsystem_vendor == 0x1af4 &&
  515.                                     pch->subsystem_device == 0x1100)) {
  516.                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
  517.                         } else
  518.                                 continue;
  519.  
  520.                         break;
  521.                 }
  522.         }
  523.         if (!pch)
  524.                 DRM_DEBUG_KMS("No PCH found.\n");
  525.  
  526. //      pci_dev_put(pch);
  527. }
  528.  
  529. bool i915_semaphore_is_enabled(struct drm_device *dev)
  530. {
  531.         if (INTEL_INFO(dev)->gen < 6)
  532.                 return false;
  533.  
  534.         if (i915.semaphores >= 0)
  535.                 return i915.semaphores;
  536.  
  537.         /* TODO: make semaphores and Execlists play nicely together */
  538.         if (i915.enable_execlists)
  539.                 return false;
  540.  
  541.         /* Until we get further testing... */
  542.         if (IS_GEN8(dev))
  543.                 return false;
  544.  
  545. #ifdef CONFIG_INTEL_IOMMU
  546.         /* Enable semaphores on SNB when IO remapping is off */
  547.         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
  548.                 return false;
  549. #endif
  550.  
  551.         return true;
  552. }
  553.  
  554. #if 0
  555. void i915_firmware_load_error_print(const char *fw_path, int err)
  556. {
  557.         DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
  558.  
  559.         /*
  560.          * If the reason is not known assume -ENOENT since that's the most
  561.          * usual failure mode.
  562.          */
  563.         if (!err)
  564.                 err = -ENOENT;
  565.  
  566.         if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
  567.                 return;
  568.  
  569.         DRM_ERROR(
  570.           "The driver is built-in, so to load the firmware you need to\n"
  571.           "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
  572.           "in your initrd/initramfs image.\n");
  573. }
  574.  
  575. static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
  576. {
  577.         struct drm_device *dev = dev_priv->dev;
  578.         struct drm_encoder *encoder;
  579.  
  580.         drm_modeset_lock_all(dev);
  581.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  582.                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  583.  
  584.                 if (intel_encoder->suspend)
  585.                         intel_encoder->suspend(intel_encoder);
  586.         }
  587.         drm_modeset_unlock_all(dev);
  588. }
  589.  
  590. static int intel_suspend_complete(struct drm_i915_private *dev_priv);
  591. static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
  592.                               bool rpm_resume);
  593. static int skl_resume_prepare(struct drm_i915_private *dev_priv);
  594. static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
  595.  
  596.  
  597. static int i915_drm_suspend(struct drm_device *dev)
  598. {
  599.         struct drm_i915_private *dev_priv = dev->dev_private;
  600.         pci_power_t opregion_target_state;
  601.         int error;
  602.  
  603.         /* ignore lid events during suspend */
  604.         mutex_lock(&dev_priv->modeset_restore_lock);
  605.         dev_priv->modeset_restore = MODESET_SUSPENDED;
  606.         mutex_unlock(&dev_priv->modeset_restore_lock);
  607.  
  608.         /* We do a lot of poking in a lot of registers, make sure they work
  609.          * properly. */
  610.         intel_display_set_init_power(dev_priv, true);
  611.  
  612.         drm_kms_helper_poll_disable(dev);
  613.  
  614.         pci_save_state(dev->pdev);
  615.  
  616.         error = i915_gem_suspend(dev);
  617.         if (error) {
  618.                 dev_err(&dev->pdev->dev,
  619.                         "GEM idle failed, resume might fail\n");
  620.                 return error;
  621.         }
  622.  
  623.         intel_guc_suspend(dev);
  624.  
  625.         intel_suspend_gt_powersave(dev);
  626.  
  627.         /*
  628.          * Disable CRTCs directly since we want to preserve sw state
  629.          * for _thaw. Also, power gate the CRTC power wells.
  630.          */
  631.         drm_modeset_lock_all(dev);
  632.         intel_display_suspend(dev);
  633.         drm_modeset_unlock_all(dev);
  634.  
  635.         intel_dp_mst_suspend(dev);
  636.  
  637.         intel_runtime_pm_disable_interrupts(dev_priv);
  638.         intel_hpd_cancel_work(dev_priv);
  639.  
  640.         intel_suspend_encoders(dev_priv);
  641.  
  642.         intel_suspend_hw(dev);
  643.  
  644.         i915_gem_suspend_gtt_mappings(dev);
  645.  
  646.         i915_save_state(dev);
  647.  
  648.         opregion_target_state = PCI_D3cold;
  649. #if IS_ENABLED(CONFIG_ACPI_SLEEP)
  650.         if (acpi_target_system_state() < ACPI_STATE_S3)
  651.                 opregion_target_state = PCI_D1;
  652. #endif
  653.         intel_opregion_notify_adapter(dev, opregion_target_state);
  654.  
  655.         intel_uncore_forcewake_reset(dev, false);
  656.         intel_opregion_fini(dev);
  657.  
  658.         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
  659.  
  660.         dev_priv->suspend_count++;
  661.  
  662.         intel_display_set_init_power(dev_priv, false);
  663.  
  664.         return 0;
  665. }
  666.  
  667. static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
  668. {
  669.         struct drm_i915_private *dev_priv = drm_dev->dev_private;
  670.         int ret;
  671.  
  672.         ret = intel_suspend_complete(dev_priv);
  673.  
  674.         if (ret) {
  675.                 DRM_ERROR("Suspend complete failed: %d\n", ret);
  676.  
  677.                 return ret;
  678.         }
  679.  
  680.         pci_disable_device(drm_dev->pdev);
  681.         /*
  682.          * During hibernation on some platforms the BIOS may try to access
  683.          * the device even though it's already in D3 and hang the machine. So
  684.          * leave the device in D0 on those platforms and hope the BIOS will
  685.          * power down the device properly. The issue was seen on multiple old
  686.          * GENs with different BIOS vendors, so having an explicit blacklist
  687.          * is inpractical; apply the workaround on everything pre GEN6. The
  688.          * platforms where the issue was seen:
  689.          * Lenovo Thinkpad X301, X61s, X60, T60, X41
  690.          * Fujitsu FSC S7110
  691.          * Acer Aspire 1830T
  692.          */
  693.         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
  694.                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
  695.  
  696.         return 0;
  697. }
  698.  
  699. int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
  700. {
  701.         int error;
  702.  
  703.         if (!dev || !dev->dev_private) {
  704.                 DRM_ERROR("dev: %p\n", dev);
  705.                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
  706.                 return -ENODEV;
  707.         }
  708.  
  709.         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
  710.                          state.event != PM_EVENT_FREEZE))
  711.                 return -EINVAL;
  712.  
  713.         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  714.                 return 0;
  715.  
  716.         error = i915_drm_suspend(dev);
  717.         if (error)
  718.                 return error;
  719.  
  720.         return i915_drm_suspend_late(dev, false);
  721. }
  722.  
  723. static int i915_drm_resume(struct drm_device *dev)
  724. {
  725.         struct drm_i915_private *dev_priv = dev->dev_private;
  726.  
  727.         mutex_lock(&dev->struct_mutex);
  728.         i915_gem_restore_gtt_mappings(dev);
  729.         mutex_unlock(&dev->struct_mutex);
  730.  
  731.         i915_restore_state(dev);
  732.         intel_opregion_setup(dev);
  733.  
  734.         intel_init_pch_refclk(dev);
  735.         drm_mode_config_reset(dev);
  736.  
  737.         /*
  738.          * Interrupts have to be enabled before any batches are run. If not the
  739.          * GPU will hang. i915_gem_init_hw() will initiate batches to
  740.          * update/restore the context.
  741.          *
  742.          * Modeset enabling in intel_modeset_init_hw() also needs working
  743.          * interrupts.
  744.          */
  745.         intel_runtime_pm_enable_interrupts(dev_priv);
  746.  
  747.         mutex_lock(&dev->struct_mutex);
  748.         if (i915_gem_init_hw(dev)) {
  749.                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
  750.                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
  751.         }
  752.         mutex_unlock(&dev->struct_mutex);
  753.  
  754.         intel_guc_resume(dev);
  755.  
  756.         intel_modeset_init_hw(dev);
  757.  
  758.         spin_lock_irq(&dev_priv->irq_lock);
  759.         if (dev_priv->display.hpd_irq_setup)
  760.                 dev_priv->display.hpd_irq_setup(dev);
  761.         spin_unlock_irq(&dev_priv->irq_lock);
  762.  
  763.         drm_modeset_lock_all(dev);
  764.         intel_display_resume(dev);
  765.         drm_modeset_unlock_all(dev);
  766.  
  767.         intel_dp_mst_resume(dev);
  768.  
  769.         /*
  770.          * ... but also need to make sure that hotplug processing
  771.          * doesn't cause havoc. Like in the driver load code we don't
  772.          * bother with the tiny race here where we might loose hotplug
  773.          * notifications.
  774.          * */
  775.         intel_hpd_init(dev_priv);
  776.         /* Config may have changed between suspend and resume */
  777.         drm_helper_hpd_irq_event(dev);
  778.  
  779.         intel_opregion_init(dev);
  780.  
  781.         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
  782.  
  783.         mutex_lock(&dev_priv->modeset_restore_lock);
  784.         dev_priv->modeset_restore = MODESET_DONE;
  785.         mutex_unlock(&dev_priv->modeset_restore_lock);
  786.  
  787.         intel_opregion_notify_adapter(dev, PCI_D0);
  788.  
  789.         drm_kms_helper_poll_enable(dev);
  790.  
  791.         return 0;
  792. }
  793.  
  794. static int i915_drm_resume_early(struct drm_device *dev)
  795. {
  796.         struct drm_i915_private *dev_priv = dev->dev_private;
  797.         int ret = 0;
  798.  
  799.         /*
  800.          * We have a resume ordering issue with the snd-hda driver also
  801.          * requiring our device to be power up. Due to the lack of a
  802.          * parent/child relationship we currently solve this with an early
  803.          * resume hook.
  804.          *
  805.          * FIXME: This should be solved with a special hdmi sink device or
  806.          * similar so that power domains can be employed.
  807.          */
  808.         if (pci_enable_device(dev->pdev))
  809.                 return -EIO;
  810.  
  811.         pci_set_master(dev->pdev);
  812.  
  813.         if (IS_VALLEYVIEW(dev_priv))
  814.                 ret = vlv_resume_prepare(dev_priv, false);
  815.         if (ret)
  816.                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
  817.                           ret);
  818.  
  819.         intel_uncore_early_sanitize(dev, true);
  820.  
  821.         if (IS_BROXTON(dev))
  822.                 ret = bxt_resume_prepare(dev_priv);
  823.         else if (IS_SKYLAKE(dev_priv))
  824.                 ret = skl_resume_prepare(dev_priv);
  825.         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  826.                 hsw_disable_pc8(dev_priv);
  827.  
  828.         intel_uncore_sanitize(dev);
  829.         intel_power_domains_init_hw(dev_priv);
  830.  
  831.         return ret;
  832. }
  833.  
  834. int i915_resume_switcheroo(struct drm_device *dev)
  835. {
  836.         int ret;
  837.  
  838.         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  839.                 return 0;
  840.  
  841.         ret = i915_drm_resume_early(dev);
  842.         if (ret)
  843.                 return ret;
  844.  
  845.         return i915_drm_resume(dev);
  846. }
  847.  
  848. /**
  849.  * i915_reset - reset chip after a hang
  850.  * @dev: drm device to reset
  851.  *
  852.  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
  853.  * reset or otherwise an error code.
  854.  *
  855.  * Procedure is fairly simple:
  856.  *   - reset the chip using the reset reg
  857.  *   - re-init context state
  858.  *   - re-init hardware status page
  859.  *   - re-init ring buffer
  860.  *   - re-init interrupt state
  861.  *   - re-init display
  862.  */
  863. int i915_reset(struct drm_device *dev)
  864. {
  865.         struct drm_i915_private *dev_priv = dev->dev_private;
  866.         bool simulated;
  867.         int ret;
  868.  
  869.         intel_reset_gt_powersave(dev);
  870.  
  871.         mutex_lock(&dev->struct_mutex);
  872.  
  873.         i915_gem_reset(dev);
  874.  
  875.         simulated = dev_priv->gpu_error.stop_rings != 0;
  876.  
  877.         ret = intel_gpu_reset(dev);
  878.  
  879.         /* Also reset the gpu hangman. */
  880.         if (simulated) {
  881.                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
  882.                 dev_priv->gpu_error.stop_rings = 0;
  883.                 if (ret == -ENODEV) {
  884.                         DRM_INFO("Reset not implemented, but ignoring "
  885.                                  "error for simulated gpu hangs\n");
  886.                         ret = 0;
  887.                 }
  888.         }
  889.  
  890.         if (i915_stop_ring_allow_warn(dev_priv))
  891.                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
  892.  
  893.         if (ret) {
  894.                 DRM_ERROR("Failed to reset chip: %i\n", ret);
  895.                 mutex_unlock(&dev->struct_mutex);
  896.                 return ret;
  897.         }
  898.  
  899.         /* Ok, now get things going again... */
  900.  
  901.         /*
  902.          * Everything depends on having the GTT running, so we need to start
  903.          * there.  Fortunately we don't need to do this unless we reset the
  904.          * chip at a PCI level.
  905.          *
  906.          * Next we need to restore the context, but we don't use those
  907.          * yet either...
  908.          *
  909.          * Ring buffer needs to be re-initialized in the KMS case, or if X
  910.          * was running at the time of the reset (i.e. we weren't VT
  911.          * switched away).
  912.          */
  913.  
  914.         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
  915.         dev_priv->gpu_error.reload_in_reset = true;
  916.  
  917.         ret = i915_gem_init_hw(dev);
  918.  
  919.         dev_priv->gpu_error.reload_in_reset = false;
  920.  
  921.         mutex_unlock(&dev->struct_mutex);
  922.         if (ret) {
  923.                 DRM_ERROR("Failed hw init on reset %d\n", ret);
  924.                 return ret;
  925.         }
  926.  
  927.         /*
  928.          * rps/rc6 re-init is necessary to restore state lost after the
  929.          * reset and the re-install of gt irqs. Skip for ironlake per
  930.          * previous concerns that it doesn't respond well to some forms
  931.          * of re-init after reset.
  932.          */
  933.         if (INTEL_INFO(dev)->gen > 5)
  934.                 intel_enable_gt_powersave(dev);
  935.  
  936.         return 0;
  937. }
  938.  
  939. static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  940. {
  941.         struct intel_device_info *intel_info =
  942.                 (struct intel_device_info *) ent->driver_data;
  943.  
  944.         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
  945.                 DRM_INFO("This hardware requires preliminary hardware support.\n"
  946.                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
  947.                 return -ENODEV;
  948.         }
  949.  
  950.         /* Only bind to function 0 of the device. Early generations
  951.          * used function 1 as a placeholder for multi-head. This causes
  952.          * us confusion instead, especially on the systems where both
  953.          * functions have the same PCI-ID!
  954.          */
  955.         if (PCI_FUNC(pdev->devfn))
  956.                 return -ENODEV;
  957.  
  958.         return drm_get_pci_dev(pdev, ent, &driver);
  959. }
  960.  
  961. static void
  962. i915_pci_remove(struct pci_dev *pdev)
  963. {
  964.         struct drm_device *dev = pci_get_drvdata(pdev);
  965.  
  966.         drm_put_dev(dev);
  967. }
  968.  
  969. static int i915_pm_suspend(struct device *dev)
  970. {
  971.         struct pci_dev *pdev = to_pci_dev(dev);
  972.         struct drm_device *drm_dev = pci_get_drvdata(pdev);
  973.  
  974.         if (!drm_dev || !drm_dev->dev_private) {
  975.                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
  976.                 return -ENODEV;
  977.         }
  978.  
  979.         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  980.                 return 0;
  981.  
  982.         return i915_drm_suspend(drm_dev);
  983. }
  984.  
  985. static int i915_pm_suspend_late(struct device *dev)
  986. {
  987.         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
  988.  
  989.         /*
  990.          * We have a suspend ordering issue with the snd-hda driver also
  991.          * requiring our device to be power up. Due to the lack of a
  992.          * parent/child relationship we currently solve this with an late
  993.          * suspend hook.
  994.          *
  995.          * FIXME: This should be solved with a special hdmi sink device or
  996.          * similar so that power domains can be employed.
  997.          */
  998.         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  999.                 return 0;
  1000.  
  1001.         return i915_drm_suspend_late(drm_dev, false);
  1002. }
  1003.  
  1004. static int i915_pm_poweroff_late(struct device *dev)
  1005. {
  1006.         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
  1007.  
  1008.         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  1009.                 return 0;
  1010.  
  1011.         return i915_drm_suspend_late(drm_dev, true);
  1012. }
  1013.  
  1014. static int i915_pm_resume_early(struct device *dev)
  1015. {
  1016.         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
  1017.  
  1018.         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  1019.                 return 0;
  1020.  
  1021.         return i915_drm_resume_early(drm_dev);
  1022. }
  1023.  
  1024. static int i915_pm_resume(struct device *dev)
  1025. {
  1026.         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
  1027.  
  1028.         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  1029.                 return 0;
  1030.  
  1031.         return i915_drm_resume(drm_dev);
  1032. }
  1033.  
  1034. static int skl_suspend_complete(struct drm_i915_private *dev_priv)
  1035. {
  1036.         /* Enabling DC6 is not a hard requirement to enter runtime D3 */
  1037.  
  1038.         skl_uninit_cdclk(dev_priv);
  1039.  
  1040.         return 0;
  1041. }
  1042.  
  1043. static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
  1044. {
  1045.         hsw_enable_pc8(dev_priv);
  1046.  
  1047.         return 0;
  1048. }
  1049.  
  1050. static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
  1051. {
  1052.         struct drm_device *dev = dev_priv->dev;
  1053.  
  1054.         /* TODO: when DC5 support is added disable DC5 here. */
  1055.  
  1056.         broxton_ddi_phy_uninit(dev);
  1057.         broxton_uninit_cdclk(dev);
  1058.         bxt_enable_dc9(dev_priv);
  1059.  
  1060.         return 0;
  1061. }
  1062.  
  1063. static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
  1064. {
  1065.         struct drm_device *dev = dev_priv->dev;
  1066.  
  1067.         /* TODO: when CSR FW support is added make sure the FW is loaded */
  1068.  
  1069.         bxt_disable_dc9(dev_priv);
  1070.  
  1071.         /*
  1072.          * TODO: when DC5 support is added enable DC5 here if the CSR FW
  1073.          * is available.
  1074.          */
  1075.         broxton_init_cdclk(dev);
  1076.         broxton_ddi_phy_init(dev);
  1077.         intel_prepare_ddi(dev);
  1078.  
  1079.         return 0;
  1080. }
  1081.  
  1082. static int skl_resume_prepare(struct drm_i915_private *dev_priv)
  1083. {
  1084.         struct drm_device *dev = dev_priv->dev;
  1085.  
  1086.         skl_init_cdclk(dev_priv);
  1087.         intel_csr_load_program(dev);
  1088.  
  1089.         return 0;
  1090. }
  1091.  
  1092. /*
  1093.  * Save all Gunit registers that may be lost after a D3 and a subsequent
  1094.  * S0i[R123] transition. The list of registers needing a save/restore is
  1095.  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
  1096.  * registers in the following way:
  1097.  * - Driver: saved/restored by the driver
  1098.  * - Punit : saved/restored by the Punit firmware
  1099.  * - No, w/o marking: no need to save/restore, since the register is R/O or
  1100.  *                    used internally by the HW in a way that doesn't depend
  1101.  *                    keeping the content across a suspend/resume.
  1102.  * - Debug : used for debugging
  1103.  *
  1104.  * We save/restore all registers marked with 'Driver', with the following
  1105.  * exceptions:
  1106.  * - Registers out of use, including also registers marked with 'Debug'.
  1107.  *   These have no effect on the driver's operation, so we don't save/restore
  1108.  *   them to reduce the overhead.
  1109.  * - Registers that are fully setup by an initialization function called from
  1110.  *   the resume path. For example many clock gating and RPS/RC6 registers.
  1111.  * - Registers that provide the right functionality with their reset defaults.
  1112.  *
  1113.  * TODO: Except for registers that based on the above 3 criteria can be safely
  1114.  * ignored, we save/restore all others, practically treating the HW context as
  1115.  * a black-box for the driver. Further investigation is needed to reduce the
  1116.  * saved/restored registers even further, by following the same 3 criteria.
  1117.  */
  1118. static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
  1119. {
  1120.         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
  1121.         int i;
  1122.  
  1123.         /* GAM 0x4000-0x4770 */
  1124.         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
  1125.         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
  1126.         s->arb_mode             = I915_READ(ARB_MODE);
  1127.         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
  1128.         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
  1129.  
  1130.         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
  1131.                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
  1132.  
  1133.         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
  1134.         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
  1135.  
  1136.         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
  1137.         s->ecochk               = I915_READ(GAM_ECOCHK);
  1138.         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
  1139.         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
  1140.  
  1141.         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
  1142.  
  1143.         /* MBC 0x9024-0x91D0, 0x8500 */
  1144.         s->g3dctl               = I915_READ(VLV_G3DCTL);
  1145.         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
  1146.         s->mbctl                = I915_READ(GEN6_MBCTL);
  1147.  
  1148.         /* GCP 0x9400-0x9424, 0x8100-0x810C */
  1149.         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
  1150.         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
  1151.         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
  1152.         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
  1153.         s->rstctl               = I915_READ(GEN6_RSTCTL);
  1154.         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
  1155.  
  1156.         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
  1157.         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
  1158.         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
  1159.         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
  1160.         s->ecobus               = I915_READ(ECOBUS);
  1161.         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
  1162.         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
  1163.         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
  1164.         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
  1165.         s->rcedata              = I915_READ(VLV_RCEDATA);
  1166.         s->spare2gh             = I915_READ(VLV_SPAREG2H);
  1167.  
  1168.         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
  1169.         s->gt_imr               = I915_READ(GTIMR);
  1170.         s->gt_ier               = I915_READ(GTIER);
  1171.         s->pm_imr               = I915_READ(GEN6_PMIMR);
  1172.         s->pm_ier               = I915_READ(GEN6_PMIER);
  1173.  
  1174.         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
  1175.                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
  1176.  
  1177.         /* GT SA CZ domain, 0x100000-0x138124 */
  1178.         s->tilectl              = I915_READ(TILECTL);
  1179.         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
  1180.         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
  1181.         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
  1182.         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
  1183.  
  1184.         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
  1185.         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
  1186.         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
  1187.         s->pcbr                 = I915_READ(VLV_PCBR);
  1188.         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
  1189.  
  1190.         /*
  1191.          * Not saving any of:
  1192.          * DFT,         0x9800-0x9EC0
  1193.          * SARB,        0xB000-0xB1FC
  1194.          * GAC,         0x5208-0x524C, 0x14000-0x14C000
  1195.          * PCI CFG
  1196.          */
  1197. }
  1198.  
  1199. static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
  1200. {
  1201.         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
  1202.         u32 val;
  1203.         int i;
  1204.  
  1205.         /* GAM 0x4000-0x4770 */
  1206.         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
  1207.         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
  1208.         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
  1209.         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
  1210.         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
  1211.  
  1212.         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
  1213.                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
  1214.  
  1215.         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
  1216.         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
  1217.  
  1218.         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
  1219.         I915_WRITE(GAM_ECOCHK,          s->ecochk);
  1220.         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
  1221.         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
  1222.  
  1223.         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
  1224.  
  1225.         /* MBC 0x9024-0x91D0, 0x8500 */
  1226.         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
  1227.         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
  1228.         I915_WRITE(GEN6_MBCTL,          s->mbctl);
  1229.  
  1230.         /* GCP 0x9400-0x9424, 0x8100-0x810C */
  1231.         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
  1232.         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
  1233.         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
  1234.         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
  1235.         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
  1236.         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
  1237.  
  1238.         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
  1239.         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
  1240.         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
  1241.         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
  1242.         I915_WRITE(ECOBUS,              s->ecobus);
  1243.         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
  1244.         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
  1245.         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
  1246.         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
  1247.         I915_WRITE(VLV_RCEDATA,         s->rcedata);
  1248.         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
  1249.  
  1250.         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
  1251.         I915_WRITE(GTIMR,               s->gt_imr);
  1252.         I915_WRITE(GTIER,               s->gt_ier);
  1253.         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
  1254.         I915_WRITE(GEN6_PMIER,          s->pm_ier);
  1255.  
  1256.         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
  1257.                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
  1258.  
  1259.         /* GT SA CZ domain, 0x100000-0x138124 */
  1260.         I915_WRITE(TILECTL,                     s->tilectl);
  1261.         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
  1262.         /*
  1263.          * Preserve the GT allow wake and GFX force clock bit, they are not
  1264.          * be restored, as they are used to control the s0ix suspend/resume
  1265.          * sequence by the caller.
  1266.          */
  1267.         val = I915_READ(VLV_GTLC_WAKE_CTRL);
  1268.         val &= VLV_GTLC_ALLOWWAKEREQ;
  1269.         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
  1270.         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
  1271.  
  1272.         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
  1273.         val &= VLV_GFX_CLK_FORCE_ON_BIT;
  1274.         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
  1275.         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
  1276.  
  1277.         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
  1278.  
  1279.         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
  1280.         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
  1281.         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
  1282.         I915_WRITE(VLV_PCBR,                    s->pcbr);
  1283.         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
  1284. }
  1285. #endif
  1286.  
  1287. int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
  1288. {
  1289.         u32 val;
  1290.         int err;
  1291.  
  1292. #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
  1293.  
  1294.         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
  1295.         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
  1296.         if (force_on)
  1297.                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
  1298.         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
  1299.  
  1300.         if (!force_on)
  1301.                 return 0;
  1302.  
  1303.         err = wait_for(COND, 20);
  1304.         if (err)
  1305.                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
  1306.                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
  1307.  
  1308.         return err;
  1309. #undef COND
  1310. }
  1311. #if 0
  1312. static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
  1313. {
  1314.         u32 val;
  1315.         int err = 0;
  1316.  
  1317.         val = I915_READ(VLV_GTLC_WAKE_CTRL);
  1318.         val &= ~VLV_GTLC_ALLOWWAKEREQ;
  1319.         if (allow)
  1320.                 val |= VLV_GTLC_ALLOWWAKEREQ;
  1321.         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
  1322.         POSTING_READ(VLV_GTLC_WAKE_CTRL);
  1323.  
  1324. #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
  1325.               allow)
  1326.         err = wait_for(COND, 1);
  1327.         if (err)
  1328.                 DRM_ERROR("timeout disabling GT waking\n");
  1329.         return err;
  1330. #undef COND
  1331. }
  1332.  
  1333. static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
  1334.                                  bool wait_for_on)
  1335. {
  1336.         u32 mask;
  1337.         u32 val;
  1338.         int err;
  1339.  
  1340.         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
  1341.         val = wait_for_on ? mask : 0;
  1342. #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
  1343.         if (COND)
  1344.                 return 0;
  1345.  
  1346.         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
  1347.                         wait_for_on ? "on" : "off",
  1348.                         I915_READ(VLV_GTLC_PW_STATUS));
  1349.  
  1350.         /*
  1351.          * RC6 transitioning can be delayed up to 2 msec (see
  1352.          * valleyview_enable_rps), use 3 msec for safety.
  1353.          */
  1354.         err = wait_for(COND, 3);
  1355.         if (err)
  1356.                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
  1357.                           wait_for_on ? "on" : "off");
  1358.  
  1359.         return err;
  1360. #undef COND
  1361. }
  1362.  
  1363. static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
  1364. {
  1365.         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
  1366.                 return;
  1367.  
  1368.         DRM_ERROR("GT register access while GT waking disabled\n");
  1369.         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
  1370. }
  1371.  
  1372. static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
  1373. {
  1374.         u32 mask;
  1375.         int err;
  1376.  
  1377.         /*
  1378.          * Bspec defines the following GT well on flags as debug only, so
  1379.          * don't treat them as hard failures.
  1380.          */
  1381.         (void)vlv_wait_for_gt_wells(dev_priv, false);
  1382.  
  1383.         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
  1384.         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
  1385.  
  1386.         vlv_check_no_gt_access(dev_priv);
  1387.  
  1388.         err = vlv_force_gfx_clock(dev_priv, true);
  1389.         if (err)
  1390.                 goto err1;
  1391.  
  1392.         err = vlv_allow_gt_wake(dev_priv, false);
  1393.         if (err)
  1394.                 goto err2;
  1395.  
  1396.         if (!IS_CHERRYVIEW(dev_priv->dev))
  1397.                 vlv_save_gunit_s0ix_state(dev_priv);
  1398.  
  1399.         err = vlv_force_gfx_clock(dev_priv, false);
  1400.         if (err)
  1401.                 goto err2;
  1402.  
  1403.         return 0;
  1404.  
  1405. err2:
  1406.         /* For safety always re-enable waking and disable gfx clock forcing */
  1407.         vlv_allow_gt_wake(dev_priv, true);
  1408. err1:
  1409.         vlv_force_gfx_clock(dev_priv, false);
  1410.  
  1411.         return err;
  1412. }
  1413.  
  1414. static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
  1415.                                 bool rpm_resume)
  1416. {
  1417.         struct drm_device *dev = dev_priv->dev;
  1418.         int err;
  1419.         int ret;
  1420.  
  1421.         /*
  1422.          * If any of the steps fail just try to continue, that's the best we
  1423.          * can do at this point. Return the first error code (which will also
  1424.          * leave RPM permanently disabled).
  1425.          */
  1426.         ret = vlv_force_gfx_clock(dev_priv, true);
  1427.  
  1428.         if (!IS_CHERRYVIEW(dev_priv->dev))
  1429.                 vlv_restore_gunit_s0ix_state(dev_priv);
  1430.  
  1431.         err = vlv_allow_gt_wake(dev_priv, true);
  1432.         if (!ret)
  1433.                 ret = err;
  1434.  
  1435.         err = vlv_force_gfx_clock(dev_priv, false);
  1436.         if (!ret)
  1437.                 ret = err;
  1438.  
  1439.         vlv_check_no_gt_access(dev_priv);
  1440.  
  1441.         if (rpm_resume) {
  1442.                 intel_init_clock_gating(dev);
  1443.                 i915_gem_restore_fences(dev);
  1444.         }
  1445.  
  1446.         return ret;
  1447. }
  1448.  
  1449. static int intel_runtime_suspend(struct device *device)
  1450. {
  1451.         struct pci_dev *pdev = to_pci_dev(device);
  1452.         struct drm_device *dev = pci_get_drvdata(pdev);
  1453.         struct drm_i915_private *dev_priv = dev->dev_private;
  1454.         int ret;
  1455.  
  1456.         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
  1457.                 return -ENODEV;
  1458.  
  1459.         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
  1460.                 return -ENODEV;
  1461.  
  1462.         DRM_DEBUG_KMS("Suspending device\n");
  1463.  
  1464.         /*
  1465.          * We could deadlock here in case another thread holding struct_mutex
  1466.          * calls RPM suspend concurrently, since the RPM suspend will wait
  1467.          * first for this RPM suspend to finish. In this case the concurrent
  1468.          * RPM resume will be followed by its RPM suspend counterpart. Still
  1469.          * for consistency return -EAGAIN, which will reschedule this suspend.
  1470.          */
  1471.         if (!mutex_trylock(&dev->struct_mutex)) {
  1472.                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
  1473.                 /*
  1474.                  * Bump the expiration timestamp, otherwise the suspend won't
  1475.                  * be rescheduled.
  1476.                  */
  1477.                 pm_runtime_mark_last_busy(device);
  1478.  
  1479.                 return -EAGAIN;
  1480.         }
  1481.         /*
  1482.          * We are safe here against re-faults, since the fault handler takes
  1483.          * an RPM reference.
  1484.          */
  1485.         i915_gem_release_all_mmaps(dev_priv);
  1486.         mutex_unlock(&dev->struct_mutex);
  1487.  
  1488.         intel_guc_suspend(dev);
  1489.  
  1490.         intel_suspend_gt_powersave(dev);
  1491.         intel_runtime_pm_disable_interrupts(dev_priv);
  1492.  
  1493.         ret = intel_suspend_complete(dev_priv);
  1494.         if (ret) {
  1495.                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
  1496.                 intel_runtime_pm_enable_interrupts(dev_priv);
  1497.  
  1498.                 return ret;
  1499.         }
  1500.  
  1501.         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
  1502.         intel_uncore_forcewake_reset(dev, false);
  1503.         dev_priv->pm.suspended = true;
  1504.  
  1505.         /*
  1506.          * FIXME: We really should find a document that references the arguments
  1507.          * used below!
  1508.          */
  1509.         if (IS_BROADWELL(dev)) {
  1510.                 /*
  1511.                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
  1512.                  * being detected, and the call we do at intel_runtime_resume()
  1513.                  * won't be able to restore them. Since PCI_D3hot matches the
  1514.                  * actual specification and appears to be working, use it.
  1515.                  */
  1516.                 intel_opregion_notify_adapter(dev, PCI_D3hot);
  1517.         } else {
  1518.                 /*
  1519.                  * current versions of firmware which depend on this opregion
  1520.                  * notification have repurposed the D1 definition to mean
  1521.                  * "runtime suspended" vs. what you would normally expect (D3)
  1522.                  * to distinguish it from notifications that might be sent via
  1523.                  * the suspend path.
  1524.                  */
  1525.                 intel_opregion_notify_adapter(dev, PCI_D1);
  1526.         }
  1527.  
  1528.         assert_forcewakes_inactive(dev_priv);
  1529.  
  1530.         DRM_DEBUG_KMS("Device suspended\n");
  1531.         return 0;
  1532. }
  1533.  
  1534. static int intel_runtime_resume(struct device *device)
  1535. {
  1536.         struct pci_dev *pdev = to_pci_dev(device);
  1537.         struct drm_device *dev = pci_get_drvdata(pdev);
  1538.         struct drm_i915_private *dev_priv = dev->dev_private;
  1539.         int ret = 0;
  1540.  
  1541.         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
  1542.                 return -ENODEV;
  1543.  
  1544.         DRM_DEBUG_KMS("Resuming device\n");
  1545.  
  1546.         intel_opregion_notify_adapter(dev, PCI_D0);
  1547.         dev_priv->pm.suspended = false;
  1548.  
  1549.         intel_guc_resume(dev);
  1550.  
  1551.         if (IS_GEN6(dev_priv))
  1552.                 intel_init_pch_refclk(dev);
  1553.  
  1554.         if (IS_BROXTON(dev))
  1555.                 ret = bxt_resume_prepare(dev_priv);
  1556.         else if (IS_SKYLAKE(dev))
  1557.                 ret = skl_resume_prepare(dev_priv);
  1558.         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  1559.                 hsw_disable_pc8(dev_priv);
  1560.         else if (IS_VALLEYVIEW(dev_priv))
  1561.                 ret = vlv_resume_prepare(dev_priv, true);
  1562.  
  1563.         /*
  1564.          * No point of rolling back things in case of an error, as the best
  1565.          * we can do is to hope that things will still work (and disable RPM).
  1566.          */
  1567.         i915_gem_init_swizzling(dev);
  1568.         gen6_update_ring_freq(dev);
  1569.  
  1570.         intel_runtime_pm_enable_interrupts(dev_priv);
  1571.  
  1572.         /*
  1573.          * On VLV/CHV display interrupts are part of the display
  1574.          * power well, so hpd is reinitialized from there. For
  1575.          * everyone else do it here.
  1576.          */
  1577.         if (!IS_VALLEYVIEW(dev_priv))
  1578.                 intel_hpd_init(dev_priv);
  1579.  
  1580.         intel_enable_gt_powersave(dev);
  1581.  
  1582.         if (ret)
  1583.                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
  1584.         else
  1585.                 DRM_DEBUG_KMS("Device resumed\n");
  1586.  
  1587.         return ret;
  1588. }
  1589.  
  1590. /*
  1591.  * This function implements common functionality of runtime and system
  1592.  * suspend sequence.
  1593.  */
  1594. static int intel_suspend_complete(struct drm_i915_private *dev_priv)
  1595. {
  1596.         int ret;
  1597.  
  1598.         if (IS_BROXTON(dev_priv))
  1599.                 ret = bxt_suspend_complete(dev_priv);
  1600.         else if (IS_SKYLAKE(dev_priv))
  1601.                 ret = skl_suspend_complete(dev_priv);
  1602.         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  1603.                 ret = hsw_suspend_complete(dev_priv);
  1604.         else if (IS_VALLEYVIEW(dev_priv))
  1605.                 ret = vlv_suspend_complete(dev_priv);
  1606.         else
  1607.                 ret = 0;
  1608.  
  1609.         return ret;
  1610. }
  1611.  
  1612. static const struct dev_pm_ops i915_pm_ops = {
  1613.         /*
  1614.          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
  1615.          * PMSG_RESUME]
  1616.          */
  1617.         .suspend = i915_pm_suspend,
  1618.         .suspend_late = i915_pm_suspend_late,
  1619.         .resume_early = i915_pm_resume_early,
  1620.         .resume = i915_pm_resume,
  1621.  
  1622.         /*
  1623.          * S4 event handlers
  1624.          * @freeze, @freeze_late    : called (1) before creating the
  1625.          *                            hibernation image [PMSG_FREEZE] and
  1626.          *                            (2) after rebooting, before restoring
  1627.          *                            the image [PMSG_QUIESCE]
  1628.          * @thaw, @thaw_early       : called (1) after creating the hibernation
  1629.          *                            image, before writing it [PMSG_THAW]
  1630.          *                            and (2) after failing to create or
  1631.          *                            restore the image [PMSG_RECOVER]
  1632.          * @poweroff, @poweroff_late: called after writing the hibernation
  1633.          *                            image, before rebooting [PMSG_HIBERNATE]
  1634.          * @restore, @restore_early : called after rebooting and restoring the
  1635.          *                            hibernation image [PMSG_RESTORE]
  1636.          */
  1637.         .freeze = i915_pm_suspend,
  1638.         .freeze_late = i915_pm_suspend_late,
  1639.         .thaw_early = i915_pm_resume_early,
  1640.         .thaw = i915_pm_resume,
  1641.         .poweroff = i915_pm_suspend,
  1642.         .poweroff_late = i915_pm_poweroff_late,
  1643.         .restore_early = i915_pm_resume_early,
  1644.         .restore = i915_pm_resume,
  1645.  
  1646.         /* S0ix (via runtime suspend) event handlers */
  1647.         .runtime_suspend = intel_runtime_suspend,
  1648.         .runtime_resume = intel_runtime_resume,
  1649. };
  1650.  
  1651. static const struct vm_operations_struct i915_gem_vm_ops = {
  1652.         .fault = i915_gem_fault,
  1653.         .open = drm_gem_vm_open,
  1654.         .close = drm_gem_vm_close,
  1655. };
  1656.  
  1657. static const struct file_operations i915_driver_fops = {
  1658.         .owner = THIS_MODULE,
  1659.         .open = drm_open,
  1660.         .release = drm_release,
  1661.         .unlocked_ioctl = drm_ioctl,
  1662.         .mmap = drm_gem_mmap,
  1663.         .poll = drm_poll,
  1664.         .read = drm_read,
  1665. #ifdef CONFIG_COMPAT
  1666.         .compat_ioctl = i915_compat_ioctl,
  1667. #endif
  1668.         .llseek = noop_llseek,
  1669. };
  1670. #endif
  1671.  
  1672. static struct drm_driver driver = {
  1673.         /* Don't use MTRRs here; the Xserver or userspace app should
  1674.          * deal with them for Intel hardware.
  1675.          */
  1676.         .driver_features =
  1677.             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
  1678.             DRIVER_RENDER | DRIVER_MODESET,
  1679.         .load = i915_driver_load,
  1680. //    .unload = i915_driver_unload,
  1681.       .open = i915_driver_open,
  1682. //    .lastclose = i915_driver_lastclose,
  1683. //    .preclose = i915_driver_preclose,
  1684. //    .postclose = i915_driver_postclose,
  1685. //      .set_busid = drm_pci_set_busid,
  1686.  
  1687. #if defined(CONFIG_DEBUG_FS)
  1688.         .debugfs_init = i915_debugfs_init,
  1689.         .debugfs_cleanup = i915_debugfs_cleanup,
  1690. #endif
  1691.     .gem_free_object = i915_gem_free_object,
  1692.  
  1693. //    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  1694. //    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  1695. //    .gem_prime_export = i915_gem_prime_export,
  1696. //    .gem_prime_import = i915_gem_prime_import,
  1697.  
  1698. //    .dumb_create = i915_gem_dumb_create,
  1699. //    .dumb_map_offset = i915_gem_mmap_gtt,
  1700. //    .dumb_destroy = i915_gem_dumb_destroy,
  1701. //    .ioctls = i915_ioctls,
  1702. //    .fops = &i915_driver_fops,
  1703. //    .name = DRIVER_NAME,
  1704. //    .desc = DRIVER_DESC,
  1705. //    .date = DRIVER_DATE,
  1706. //    .major = DRIVER_MAJOR,
  1707. //    .minor = DRIVER_MINOR,
  1708. //    .patchlevel = DRIVER_PATCHLEVEL,
  1709. };
  1710.  
  1711.  
  1712.  
  1713.  
  1714. int i915_init(void)
  1715. {
  1716.     static pci_dev_t device;
  1717.     const struct pci_device_id  *ent;
  1718.     int  err;
  1719.  
  1720.     ent = find_pci_device(&device, pciidlist);
  1721.     if( unlikely(ent == NULL) )
  1722.     {
  1723.         dbgprintf("device not found\n");
  1724.         return -ENODEV;
  1725.     };
  1726.  
  1727.     drm_core_init();
  1728.  
  1729.     DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
  1730.                                 device.pci_dev.device);
  1731.  
  1732.     driver.driver_features |= DRIVER_MODESET;
  1733.  
  1734.     err = drm_get_pci_dev(&device.pci_dev, ent, &driver);
  1735.  
  1736.     return err;
  1737. }
  1738.  
  1739.  
  1740. MODULE_AUTHOR("Tungsten Graphics, Inc.");
  1741. MODULE_AUTHOR("Intel Corporation");
  1742.  
  1743. MODULE_DESCRIPTION(DRIVER_DESC);
  1744. MODULE_LICENSE("GPL and additional rights");
  1745.