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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. //#include <linux/device.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "intel_drv.h"
  35.  
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/mod_devicetable.h>
  39. #include <errno-base.h>
  40. #include <linux/pci.h>
  41.  
  42. #include <drm/drm_crtc_helper.h>
  43.  
  44. #include <syscall.h>
  45.  
  46. #define __read_mostly
  47.  
  48. int init_display_kms(struct drm_device *dev);
  49.  
  50. struct drm_device *main_device;
  51.  
  52. struct drm_file *drm_file_handlers[256];
  53.  
  54. static int i915_modeset __read_mostly = 1;
  55. module_param_named(modeset, i915_modeset, int, 0400);
  56. MODULE_PARM_DESC(modeset,
  57.                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  58.                 "1=on, -1=force vga console preference [default])");
  59.  
  60.  
  61. int i915_panel_ignore_lid __read_mostly         =  1;
  62. module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  63. MODULE_PARM_DESC(panel_ignore_lid,
  64.                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  65.                 "-1=force lid closed, -2=force lid open)");
  66.  
  67. unsigned int i915_powersave  __read_mostly      =  0;
  68. module_param_named(powersave, i915_powersave, int, 0600);
  69. MODULE_PARM_DESC(powersave,
  70.                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  71.  
  72. int i915_semaphores __read_mostly = -1;
  73. module_param_named(semaphores, i915_semaphores, int, 0600);
  74. MODULE_PARM_DESC(semaphores,
  75.                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  76.  
  77. int i915_enable_rc6 __read_mostly      = 0;
  78. module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  79. MODULE_PARM_DESC(i915_enable_rc6,
  80.                 "Enable power-saving render C-state 6. "
  81.                 "Different stages can be selected via bitmask values "
  82.                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  83.                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  84.                 "default: -1 (use per-chip default)");
  85.  
  86. int i915_enable_fbc __read_mostly      =  0;
  87. module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  88. MODULE_PARM_DESC(i915_enable_fbc,
  89.                 "Enable frame buffer compression for power savings "
  90.                 "(default: -1 (use per-chip default))");
  91.  
  92. unsigned int i915_lvds_downclock  __read_mostly =  0;
  93. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  94. MODULE_PARM_DESC(lvds_downclock,
  95.                 "Use panel (LVDS/eDP) downclocking for power savings "
  96.                 "(default: false)");
  97.  
  98. int i915_lvds_channel_mode __read_mostly;
  99. module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  100. MODULE_PARM_DESC(lvds_channel_mode,
  101.                  "Specify LVDS channel mode "
  102.                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  103.  
  104. int i915_panel_use_ssc __read_mostly = -1;
  105. module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  106. MODULE_PARM_DESC(lvds_use_ssc,
  107.                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  108.                 "(default: auto from VBT)");
  109.  
  110. int i915_vbt_sdvo_panel_type __read_mostly      = -1;
  111. module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  112. MODULE_PARM_DESC(vbt_sdvo_panel_type,
  113.                 "Override/Ignore selection of SDVO panel mode in the VBT "
  114.                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
  115.  
  116. static bool i915_try_reset __read_mostly = true;
  117. module_param_named(reset, i915_try_reset, bool, 0600);
  118. MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  119.  
  120. bool i915_enable_hangcheck __read_mostly = false;
  121. module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
  122. MODULE_PARM_DESC(enable_hangcheck,
  123.                 "Periodically check GPU activity for detecting hangs. "
  124.                 "WARNING: Disabling this can cause system wide hangs. "
  125.                 "(default: true)");
  126.  
  127. int i915_enable_ppgtt __read_mostly = false;
  128. module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
  129. MODULE_PARM_DESC(i915_enable_ppgtt,
  130.                 "Enable PPGTT (default: true)");
  131.  
  132. unsigned int i915_preliminary_hw_support __read_mostly = true;
  133. module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
  134. MODULE_PARM_DESC(preliminary_hw_support,
  135.                 "Enable preliminary hardware support. "
  136.                 "Enable Haswell and ValleyView Support. "
  137.                 "(default: false)");
  138.  
  139.  
  140. #define PCI_VENDOR_ID_INTEL        0x8086
  141.  
  142. #define INTEL_VGA_DEVICE(id, info) {        \
  143.         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
  144.     .class_mask = 0xff0000,                 \
  145.     .vendor = 0x8086,                       \
  146.     .device = id,                           \
  147.     .subvendor = PCI_ANY_ID,                \
  148.     .subdevice = PCI_ANY_ID,                \
  149.     .driver_data = (unsigned long) info }
  150.  
  151.  
  152. static const struct intel_device_info intel_i915g_info = {
  153.         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  154.         .has_overlay = 1, .overlay_needs_physical = 1,
  155. };
  156. static const struct intel_device_info intel_i915gm_info = {
  157.         .gen = 3, .is_mobile = 1,
  158.         .cursor_needs_physical = 1,
  159.         .has_overlay = 1, .overlay_needs_physical = 1,
  160.         .supports_tv = 1,
  161. };
  162. static const struct intel_device_info intel_i945g_info = {
  163.         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  164.         .has_overlay = 1, .overlay_needs_physical = 1,
  165. };
  166. static const struct intel_device_info intel_i945gm_info = {
  167.         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  168.         .has_hotplug = 1, .cursor_needs_physical = 1,
  169.         .has_overlay = 1, .overlay_needs_physical = 1,
  170.         .supports_tv = 1,
  171. };
  172.  
  173. static const struct intel_device_info intel_i965g_info = {
  174.         .gen = 4, .is_broadwater = 1,
  175.         .has_hotplug = 1,
  176.         .has_overlay = 1,
  177. };
  178.  
  179. static const struct intel_device_info intel_i965gm_info = {
  180.         .gen = 4, .is_crestline = 1,
  181.         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  182.         .has_overlay = 1,
  183.         .supports_tv = 1,
  184. };
  185.  
  186. static const struct intel_device_info intel_g33_info = {
  187.         .gen = 3, .is_g33 = 1,
  188.         .need_gfx_hws = 1, .has_hotplug = 1,
  189.         .has_overlay = 1,
  190. };
  191.  
  192. static const struct intel_device_info intel_g45_info = {
  193.         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
  194.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  195.         .has_bsd_ring = 1,
  196. };
  197.  
  198. static const struct intel_device_info intel_gm45_info = {
  199.         .gen = 4, .is_g4x = 1,
  200.         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
  201.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  202.         .supports_tv = 1,
  203.         .has_bsd_ring = 1,
  204. };
  205.  
  206. static const struct intel_device_info intel_pineview_info = {
  207.         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
  208.         .need_gfx_hws = 1, .has_hotplug = 1,
  209.         .has_overlay = 1,
  210. };
  211.  
  212. static const struct intel_device_info intel_ironlake_d_info = {
  213.         .gen = 5,
  214.         .need_gfx_hws = 1, .has_hotplug = 1,
  215.         .has_bsd_ring = 1,
  216. };
  217.  
  218. static const struct intel_device_info intel_ironlake_m_info = {
  219.         .gen = 5, .is_mobile = 1,
  220.         .need_gfx_hws = 1, .has_hotplug = 1,
  221.         .has_fbc = 1,
  222.         .has_bsd_ring = 1,
  223. };
  224.  
  225. static const struct intel_device_info intel_sandybridge_d_info = {
  226.     .gen = 6,
  227.         .need_gfx_hws = 1, .has_hotplug = 1,
  228.     .has_bsd_ring = 1,
  229.     .has_blt_ring = 1,
  230.         .has_llc = 1,
  231.         .has_force_wake = 1,
  232. };
  233.  
  234. static const struct intel_device_info intel_sandybridge_m_info = {
  235.         .gen = 6, .is_mobile = 1,
  236.         .need_gfx_hws = 1, .has_hotplug = 1,
  237.     .has_fbc      = 1,
  238.     .has_bsd_ring = 1,
  239.     .has_blt_ring = 1,
  240.         .has_llc = 1,
  241.         .has_force_wake = 1,
  242. };
  243.  
  244. static const struct intel_device_info intel_ivybridge_d_info = {
  245.         .is_ivybridge = 1, .gen = 7,
  246.         .need_gfx_hws = 1, .has_hotplug = 1,
  247.         .has_bsd_ring = 1,
  248.         .has_blt_ring = 1,
  249.         .has_llc = 1,
  250.         .has_force_wake = 1,
  251. };
  252.  
  253. static const struct intel_device_info intel_ivybridge_m_info = {
  254.         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
  255.         .need_gfx_hws = 1, .has_hotplug = 1,
  256.         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
  257.         .has_bsd_ring = 1,
  258.         .has_blt_ring = 1,
  259.         .has_llc = 1,
  260.         .has_force_wake = 1,
  261. };
  262.  
  263. static const struct intel_device_info intel_valleyview_m_info = {
  264.         .gen = 7, .is_mobile = 1,
  265.         .need_gfx_hws = 1, .has_hotplug = 1,
  266.         .has_fbc = 0,
  267.         .has_bsd_ring = 1,
  268.         .has_blt_ring = 1,
  269.         .is_valleyview = 1,
  270.         .display_mmio_offset = VLV_DISPLAY_BASE,
  271. };
  272.  
  273. static const struct intel_device_info intel_valleyview_d_info = {
  274.         .gen = 7,
  275.         .need_gfx_hws = 1, .has_hotplug = 1,
  276.         .has_fbc = 0,
  277.         .has_bsd_ring = 1,
  278.         .has_blt_ring = 1,
  279.         .is_valleyview = 1,
  280.         .display_mmio_offset = VLV_DISPLAY_BASE,
  281. };
  282.  
  283. static const struct intel_device_info intel_haswell_d_info = {
  284.         .is_haswell = 1, .gen = 7,
  285.         .need_gfx_hws = 1, .has_hotplug = 1,
  286.         .has_bsd_ring = 1,
  287.         .has_blt_ring = 1,
  288.         .has_llc = 1,
  289.         .has_force_wake = 1,
  290. };
  291.  
  292. static const struct intel_device_info intel_haswell_m_info = {
  293.         .is_haswell = 1, .gen = 7, .is_mobile = 1,
  294.         .need_gfx_hws = 1, .has_hotplug = 1,
  295.         .has_bsd_ring = 1,
  296.         .has_blt_ring = 1,
  297.         .has_llc = 1,
  298.         .has_force_wake = 1,
  299. };
  300.  
  301. static const struct pci_device_id pciidlist[] = {       /* aka */
  302.         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
  303.         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
  304.         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
  305.         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
  306.         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
  307.         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
  308.         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
  309.         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
  310.         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
  311.         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
  312.         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
  313.         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
  314.         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
  315.         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
  316.         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
  317.         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
  318.         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
  319.         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
  320.         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
  321.         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
  322.         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
  323.         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
  324.         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  325.         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  326.         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  327.         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  328.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  329.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  330.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  331.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  332.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  333.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  334.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  335.         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
  336.         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
  337.         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
  338.         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
  339.         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
  340.         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
  341.         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
  342.         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
  343.         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
  344.         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
  345.         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
  346.         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
  347.         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
  348.         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
  349.         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
  350.         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
  351.         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
  352.         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
  353.         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
  354.         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
  355.         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
  356.         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
  357.         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
  358.         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
  359.         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
  360.         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
  361.         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
  362.         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
  363.         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
  364.         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
  365.         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
  366.         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
  367.         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
  368.         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
  369.         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
  370.         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
  371.         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
  372.         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
  373.         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
  374.         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
  375.         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
  376.         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
  377.         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
  378.         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
  379.         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
  380.     {0, 0, 0}
  381. };
  382.  
  383. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  384. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  385. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  386. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  387. #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
  388.  
  389. void intel_detect_pch(struct drm_device *dev)
  390. {
  391.     struct drm_i915_private *dev_priv = dev->dev_private;
  392.     struct pci_dev *pch;
  393.  
  394.     /*
  395.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  396.      * make graphics device passthrough work easy for VMM, that only
  397.      * need to expose ISA bridge to let driver know the real hardware
  398.      * underneath. This is a requirement from virtualization team.
  399.      */
  400.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  401.     if (pch) {
  402.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  403.                         unsigned short id;
  404.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  405.                         dev_priv->pch_id = id;
  406.  
  407.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  408.                 dev_priv->pch_type = PCH_IBX;
  409.                                 dev_priv->num_pch_pll = 2;
  410.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  411.                                 WARN_ON(!IS_GEN5(dev));
  412.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  413.                 dev_priv->pch_type = PCH_CPT;
  414.                                 dev_priv->num_pch_pll = 2;
  415.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  416.                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  417.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  418.                 /* PantherPoint is CPT compatible */
  419.                 dev_priv->pch_type = PCH_CPT;
  420.                                 dev_priv->num_pch_pll = 2;
  421.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  422.                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  423.                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  424.                                 dev_priv->pch_type = PCH_LPT;
  425.                                 dev_priv->num_pch_pll = 0;
  426.                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
  427.                                 WARN_ON(!IS_HASWELL(dev));
  428.                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  429.                                 dev_priv->pch_type = PCH_LPT;
  430.                                 dev_priv->num_pch_pll = 0;
  431.                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
  432.                                 WARN_ON(!IS_HASWELL(dev));
  433.             }
  434.                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
  435.         }
  436.     }
  437. }
  438.  
  439. bool i915_semaphore_is_enabled(struct drm_device *dev)
  440. {
  441.         if (INTEL_INFO(dev)->gen < 6)
  442.                 return 0;
  443.  
  444.         if (i915_semaphores >= 0)
  445.                 return i915_semaphores;
  446.  
  447. #ifdef CONFIG_INTEL_IOMMU
  448.         /* Enable semaphores on SNB when IO remapping is off */
  449.         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
  450.                 return false;
  451. #endif
  452.  
  453.         return 1;
  454. }
  455.  
  456.  
  457.  
  458.  
  459.  
  460. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  461.  
  462. int i915_init(void)
  463. {
  464.     static pci_dev_t device;
  465.     const struct pci_device_id  *ent;
  466.     int  err;
  467.  
  468.     ent = find_pci_device(&device, pciidlist);
  469.     if( unlikely(ent == NULL) )
  470.     {
  471.         dbgprintf("device not found\n");
  472.         return -ENODEV;
  473.     };
  474.  
  475.     struct intel_device_info *intel_info =
  476.         (struct intel_device_info *) ent->driver_data;
  477.  
  478.         if (intel_info->is_valleyview)
  479.         if(!i915_preliminary_hw_support) {
  480.             DRM_ERROR("Preliminary hardware support disabled\n");
  481.             return -ENODEV;
  482.         }
  483.  
  484.     DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
  485.                                 device.pci_dev.device);
  486.  
  487.     if (intel_info->gen != 3) {
  488.  
  489.     } else if (init_agp() != 0) {
  490.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  491.         return -ENODEV;
  492.     }
  493.  
  494.     err = drm_get_dev(&device.pci_dev, ent);
  495.  
  496.     return err;
  497. }
  498.  
  499.  
  500.  
  501. static struct drm_driver driver = {
  502.     /* Don't use MTRRs here; the Xserver or userspace app should
  503.      * deal with them for Intel hardware.
  504.      */
  505. //    .driver_features =
  506. //        DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  507. //        DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
  508. //    .load = i915_driver_load,
  509. //    .unload = i915_driver_unload,
  510.       .open = i915_driver_open,
  511. //    .lastclose = i915_driver_lastclose,
  512. //    .preclose = i915_driver_preclose,
  513. //    .postclose = i915_driver_postclose,
  514.  
  515.     /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  516. //    .suspend = i915_suspend,
  517. //    .resume = i915_resume,
  518.  
  519. //    .device_is_agp = i915_driver_device_is_agp,
  520. //    .master_create = i915_master_create,
  521. //    .master_destroy = i915_master_destroy,
  522.     .gem_init_object = i915_gem_init_object,
  523.     .gem_free_object = i915_gem_free_object,
  524. //    .gem_vm_ops = &i915_gem_vm_ops,
  525.  
  526. //    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  527. //    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  528. //    .gem_prime_export = i915_gem_prime_export,
  529. //    .gem_prime_import = i915_gem_prime_import,
  530.  
  531. //    .dumb_create = i915_gem_dumb_create,
  532. //    .dumb_map_offset = i915_gem_mmap_gtt,
  533. //    .dumb_destroy = i915_gem_dumb_destroy,
  534. //    .ioctls = i915_ioctls,
  535. //    .fops = &i915_driver_fops,
  536. //    .name = DRIVER_NAME,
  537. //    .desc = DRIVER_DESC,
  538. //    .date = DRIVER_DATE,
  539. //    .major = DRIVER_MAJOR,
  540. //    .minor = DRIVER_MINOR,
  541. //    .patchlevel = DRIVER_PATCHLEVEL,
  542. };
  543.  
  544.  
  545. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  546. {
  547.     static struct drm_device drm_dev;
  548.     static struct drm_file   drm_file;
  549.  
  550.     struct drm_device *dev;
  551.     struct drm_file   *priv;
  552.  
  553.     int ret;
  554.  
  555.     dev  = &drm_dev;
  556.     priv = &drm_file;
  557.  
  558.     drm_file_handlers[0] = priv;
  559.  
  560.  //   ret = pci_enable_device(pdev);
  561.  //   if (ret)
  562.  //       goto err_g1;
  563.  
  564.     pci_set_master(pdev);
  565.  
  566.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  567.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  568.  //       goto err_g2;
  569.  //   }
  570.  
  571.     dev->pdev = pdev;
  572.     dev->pci_device = pdev->device;
  573.     dev->pci_vendor = pdev->vendor;
  574.  
  575.     INIT_LIST_HEAD(&dev->filelist);
  576.     INIT_LIST_HEAD(&dev->ctxlist);
  577.     INIT_LIST_HEAD(&dev->vmalist);
  578.     INIT_LIST_HEAD(&dev->maplist);
  579.  
  580.     spin_lock_init(&dev->count_lock);
  581.     mutex_init(&dev->struct_mutex);
  582.     mutex_init(&dev->ctxlist_mutex);
  583.  
  584.     INIT_LIST_HEAD(&priv->lhead);
  585.     INIT_LIST_HEAD(&priv->fbs);
  586.     INIT_LIST_HEAD(&priv->event_list);
  587.     init_waitqueue_head(&priv->event_wait);
  588.     priv->event_space = 4096; /* set aside 4k for event buffer */
  589.  
  590.     idr_init(&priv->object_idr);
  591.     spin_lock_init(&priv->table_lock);
  592.  
  593.     dev->driver = &driver;
  594.  
  595.     if (dev->driver->open) {
  596.         ret = dev->driver->open(dev, priv);
  597.         if (ret < 0)
  598.             goto err_g4;
  599.     }
  600.  
  601.     ret = i915_driver_load(dev, ent->driver_data );
  602.  
  603.     if (ret)
  604.         goto err_g4;
  605.  
  606.     ret = init_display_kms(dev);
  607.  
  608.     if (ret)
  609.         goto err_g4;
  610.  
  611.     return 0;
  612.  
  613. err_g4:
  614. //err_g3:
  615. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  616. //        drm_put_minor(&dev->control);
  617. //err_g2:
  618. //    pci_disable_device(pdev);
  619. //err_g1:
  620.  
  621.     return ret;
  622. }
  623.  
  624. /* We give fast paths for the really cool registers */
  625. #define NEEDS_FORCE_WAKE(dev_priv, reg) \
  626.         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
  627.          ((reg) < 0x40000) &&            \
  628.          ((reg) != FORCEWAKE))
  629.  
  630. static bool IS_DISPLAYREG(u32 reg)
  631. {
  632.         /*
  633.          * This should make it easier to transition modules over to the
  634.          * new register block scheme, since we can do it incrementally.
  635.          */
  636.         if (reg >= VLV_DISPLAY_BASE)
  637.                 return false;
  638.  
  639.         if (reg >= RENDER_RING_BASE &&
  640.             reg < RENDER_RING_BASE + 0xff)
  641.                 return false;
  642.         if (reg >= GEN6_BSD_RING_BASE &&
  643.             reg < GEN6_BSD_RING_BASE + 0xff)
  644.                 return false;
  645.         if (reg >= BLT_RING_BASE &&
  646.             reg < BLT_RING_BASE + 0xff)
  647.                 return false;
  648.  
  649.         if (reg == PGTBL_ER)
  650.                 return false;
  651.  
  652.         if (reg >= IPEIR_I965 &&
  653.             reg < HWSTAM)
  654.                 return false;
  655.  
  656.         if (reg == MI_MODE)
  657.                 return false;
  658.  
  659.         if (reg == GFX_MODE_GEN7)
  660.                 return false;
  661.  
  662.         if (reg == RENDER_HWS_PGA_GEN7 ||
  663.             reg == BSD_HWS_PGA_GEN7 ||
  664.             reg == BLT_HWS_PGA_GEN7)
  665.                 return false;
  666.  
  667.         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
  668.             reg == GEN6_BSD_RNCID)
  669.                 return false;
  670.  
  671.         if (reg == GEN6_BLITTER_ECOSKPD)
  672.                 return false;
  673.  
  674.         if (reg >= 0x4000c &&
  675.             reg <= 0x4002c)
  676.                 return false;
  677.  
  678.         if (reg >= 0x4f000 &&
  679.             reg <= 0x4f08f)
  680.                 return false;
  681.  
  682.         if (reg >= 0x4f100 &&
  683.             reg <= 0x4f11f)
  684.                 return false;
  685.  
  686.         if (reg >= VLV_MASTER_IER &&
  687.             reg <= GEN6_PMIER)
  688.                 return false;
  689.  
  690.         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
  691.             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
  692.                 return false;
  693.  
  694.         if (reg >= VLV_IIR_RW &&
  695.             reg <= VLV_ISR)
  696.                 return false;
  697.  
  698.         if (reg == FORCEWAKE_VLV ||
  699.             reg == FORCEWAKE_ACK_VLV)
  700.                 return false;
  701.  
  702.         if (reg == GEN6_GDRST)
  703.                 return false;
  704.  
  705.         switch (reg) {
  706.         case _3D_CHICKEN3:
  707.         case IVB_CHICKEN3:
  708.         case GEN7_COMMON_SLICE_CHICKEN1:
  709.         case GEN7_L3CNTLREG1:
  710.         case GEN7_L3_CHICKEN_MODE_REGISTER:
  711.         case GEN7_ROW_CHICKEN2:
  712.         case GEN7_L3SQCREG4:
  713.         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
  714.         case GEN7_HALF_SLICE_CHICKEN1:
  715.         case GEN6_MBCTL:
  716.         case GEN6_UCGCTL2:
  717.                 return false;
  718.         default:
  719.                 break;
  720.         }
  721.  
  722.         return true;
  723. }
  724.  
  725. static void
  726. ilk_dummy_write(struct drm_i915_private *dev_priv)
  727. {
  728.         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
  729.          * chip from rc6 before touching it for real. MI_MODE is masked, hence
  730.          * harmless to write 0 into. */
  731.         I915_WRITE_NOTRACE(MI_MODE, 0);
  732. }
  733.  
  734. #define __i915_read(x, y) \
  735. u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
  736.         u##x val = 0; \
  737.         if (IS_GEN5(dev_priv->dev)) \
  738.                 ilk_dummy_write(dev_priv); \
  739.         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  740.                 unsigned long irqflags; \
  741.                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
  742.                 if (dev_priv->forcewake_count == 0) \
  743.                         dev_priv->gt.force_wake_get(dev_priv); \
  744.                 val = read##y(dev_priv->regs + reg); \
  745.                 if (dev_priv->forcewake_count == 0) \
  746.                         dev_priv->gt.force_wake_put(dev_priv); \
  747.                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
  748.         } else { \
  749.                 val = read##y(dev_priv->regs + reg); \
  750.         } \
  751.         return val; \
  752. }
  753.  
  754. __i915_read(8, b)
  755. __i915_read(16, w)
  756. __i915_read(32, l)
  757. __i915_read(64, q)
  758. #undef __i915_read
  759.  
  760. #define __i915_write(x, y) \
  761. void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
  762.         u32 __fifo_ret = 0; \
  763.         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
  764.         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  765.                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
  766.         } \
  767.         if (IS_GEN5(dev_priv->dev)) \
  768.                 ilk_dummy_write(dev_priv); \
  769.         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  770.                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
  771.                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
  772.         } \
  773.         write##y(val, dev_priv->regs + reg); \
  774.         if (unlikely(__fifo_ret)) { \
  775.                 gen6_gt_check_fifodbg(dev_priv); \
  776.         } \
  777.         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  778.                 DRM_ERROR("Unclaimed write to %x\n", reg); \
  779.                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
  780.         } \
  781. }
  782. __i915_write(8, b)
  783. __i915_write(16, w)
  784. __i915_write(32, l)
  785. __i915_write(64, q)
  786. #undef __i915_write
  787.