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  1.  
  2. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  3.  */
  4. /*
  5.  *
  6.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  7.  * All Rights Reserved.
  8.  *
  9.  * Permission is hereby granted, free of charge, to any person obtaining a
  10.  * copy of this software and associated documentation files (the
  11.  * "Software"), to deal in the Software without restriction, including
  12.  * without limitation the rights to use, copy, modify, merge, publish,
  13.  * distribute, sub license, and/or sell copies of the Software, and to
  14.  * permit persons to whom the Software is furnished to do so, subject to
  15.  * the following conditions:
  16.  *
  17.  * The above copyright notice and this permission notice (including the
  18.  * next paragraph) shall be included in all copies or substantial portions
  19.  * of the Software.
  20.  *
  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  22.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  24.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  25.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  26.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  27.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28.  *
  29.  */
  30.  
  31. //#include <linux/device.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "intel_drv.h"
  37.  
  38.  
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/mod_devicetable.h>
  42. #include <errno-base.h>
  43. #include <linux/pci.h>
  44.  
  45. #include <syscall.h>
  46.  
  47. #define __read_mostly
  48.  
  49. int init_display_kms(struct drm_device *dev);
  50.  
  51.  
  52. int i915_panel_ignore_lid __read_mostly         =  0;
  53.  
  54. unsigned int i915_powersave  __read_mostly      =  0;
  55.  
  56. unsigned int i915_enable_rc6 __read_mostly      =  0;
  57.  
  58. unsigned int i915_enable_fbc __read_mostly      =  0;
  59.  
  60. unsigned int i915_lvds_downclock  __read_mostly =  0;
  61.  
  62. unsigned int i915_panel_use_ssc __read_mostly   =  1;
  63.  
  64. int i915_vbt_sdvo_panel_type __read_mostly      = -1;
  65.  
  66. #define PCI_VENDOR_ID_INTEL        0x8086
  67.  
  68. #define INTEL_VGA_DEVICE(id, info) {        \
  69.     .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  70.     .class_mask = 0xff0000,                 \
  71.     .vendor = 0x8086,                       \
  72.     .device = id,                           \
  73.     .subvendor = PCI_ANY_ID,                \
  74.     .subdevice = PCI_ANY_ID,                \
  75.     .driver_data = (unsigned long) info }
  76.  
  77. static const struct intel_device_info intel_sandybridge_d_info = {
  78.     .gen = 6,
  79.         .need_gfx_hws = 1, .has_hotplug = 1,
  80.     .has_bsd_ring = 1,
  81.     .has_blt_ring = 1,
  82. };
  83.  
  84. static const struct intel_device_info intel_sandybridge_m_info = {
  85.         .gen = 6, .is_mobile = 1,
  86.         .need_gfx_hws = 1, .has_hotplug = 1,
  87.     .has_fbc      = 1,
  88.     .has_bsd_ring = 1,
  89.     .has_blt_ring = 1,
  90. };
  91.  
  92.  
  93. static const struct pci_device_id pciidlist[] = {       /* aka */
  94.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  95.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  96.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  97.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  98.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  99.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  100.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  101.     {0, 0, 0}
  102. };
  103.  
  104. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  105. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  106. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  107. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  108.  
  109. void intel_detect_pch (struct drm_device *dev)
  110. {
  111.     struct drm_i915_private *dev_priv = dev->dev_private;
  112.     struct pci_dev *pch;
  113.  
  114.     /*
  115.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  116.      * make graphics device passthrough work easy for VMM, that only
  117.      * need to expose ISA bridge to let driver know the real hardware
  118.      * underneath. This is a requirement from virtualization team.
  119.      */
  120.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  121.     if (pch) {
  122.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  123.             int id;
  124.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  125.  
  126.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  127.                 dev_priv->pch_type = PCH_IBX;
  128.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  129.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  130.                 dev_priv->pch_type = PCH_CPT;
  131.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  132.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  133.                 /* PantherPoint is CPT compatible */
  134.                 dev_priv->pch_type = PCH_CPT;
  135.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  136.             }
  137.         }
  138.     }
  139. }
  140.  
  141. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  142. {
  143.     int count;
  144.  
  145.     count = 0;
  146.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  147.         udelay(10);
  148.  
  149.     I915_WRITE_NOTRACE(FORCEWAKE, 1);
  150.     POSTING_READ(FORCEWAKE);
  151.  
  152.     count = 0;
  153.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
  154.         udelay(10);
  155. }
  156.  
  157. /*
  158.  * Generally this is called implicitly by the register read function. However,
  159.  * if some sequence requires the GT to not power down then this function should
  160.  * be called at the beginning of the sequence followed by a call to
  161.  * gen6_gt_force_wake_put() at the end of the sequence.
  162.  */
  163. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  164. {
  165. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  166.  
  167.     /* Forcewake is atomic in case we get in here without the lock */
  168.     if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
  169.         __gen6_gt_force_wake_get(dev_priv);
  170. }
  171.  
  172. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  173. {
  174.     I915_WRITE_NOTRACE(FORCEWAKE, 0);
  175.     POSTING_READ(FORCEWAKE);
  176. }
  177.  
  178. /*
  179.  * see gen6_gt_force_wake_get()
  180.  */
  181. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  182. {
  183. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  184.  
  185.     if (atomic_dec_and_test(&dev_priv->forcewake_count))
  186.         __gen6_gt_force_wake_put(dev_priv);
  187. }
  188.  
  189. void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  190. {
  191.     if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) {
  192.         int loop = 500;
  193.         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  194.         while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  195.             udelay(10);
  196.             fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  197.         }
  198. //        WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
  199.         dev_priv->gt_fifo_count = fifo;
  200.     }
  201.     dev_priv->gt_fifo_count--;
  202. }
  203.  
  204.  
  205.  
  206.  
  207.  
  208. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  209.  
  210. int i915_init(void)
  211. {
  212.     static pci_dev_t device;
  213.     const struct pci_device_id  *ent;
  214.     int  err;
  215.  
  216.     if( init_agp() != 0)
  217.     {
  218.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  219.         return 0;
  220.     };
  221.  
  222.     ent = find_pci_device(&device, pciidlist);
  223.  
  224.     if( unlikely(ent == NULL) )
  225.     {
  226.         dbgprintf("device not found\n");
  227.         return 0;
  228.     };
  229.  
  230.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  231.                                 device.pci_dev.device);
  232.  
  233.     err = drm_get_dev(&device.pci_dev, ent);
  234.  
  235.     return err;
  236. }
  237.  
  238. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  239. {
  240.     static struct drm_device *dev;
  241.     int ret;
  242.  
  243.     ENTER();
  244.  
  245.     dev = kzalloc(sizeof(*dev), 0);
  246.     if (!dev)
  247.         return -ENOMEM;
  248.  
  249.  //   ret = pci_enable_device(pdev);
  250.  //   if (ret)
  251.  //       goto err_g1;
  252.  
  253.  //   pci_set_master(pdev);
  254.  
  255.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  256.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  257.  //       goto err_g2;
  258.  //   }
  259.  
  260.     dev->pdev = pdev;
  261.     dev->pci_device = pdev->device;
  262.     dev->pci_vendor = pdev->vendor;
  263.  
  264.     INIT_LIST_HEAD(&dev->filelist);
  265.     INIT_LIST_HEAD(&dev->ctxlist);
  266.     INIT_LIST_HEAD(&dev->vmalist);
  267.     INIT_LIST_HEAD(&dev->maplist);
  268.  
  269.     spin_lock_init(&dev->count_lock);
  270.     mutex_init(&dev->struct_mutex);
  271.     mutex_init(&dev->ctxlist_mutex);
  272.  
  273.     ret = i915_driver_load(dev, ent->driver_data );
  274.  
  275.     if (ret)
  276.         goto err_g4;
  277.  
  278.     ret = init_display_kms(dev);
  279.  
  280.     if (ret)
  281.         goto err_g4;
  282.  
  283.  
  284. //    if( radeon_modeset )
  285. //        init_display_kms(dev->dev_private, &usermode);
  286. //    else
  287. //        init_display(dev->dev_private, &usermode);
  288.  
  289.     LEAVE();
  290.  
  291.     return 0;
  292.  
  293. err_g4:
  294. //    drm_put_minor(&dev->primary);
  295. //err_g3:
  296. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  297. //        drm_put_minor(&dev->control);
  298. //err_g2:
  299. //    pci_disable_device(pdev);
  300. //err_g1:
  301.     free(dev);
  302.  
  303.     LEAVE();
  304.  
  305.     return ret;
  306. }
  307.  
  308.  
  309.