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  1.  
  2. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  3.  */
  4. /*
  5.  *
  6.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  7.  * All Rights Reserved.
  8.  *
  9.  * Permission is hereby granted, free of charge, to any person obtaining a
  10.  * copy of this software and associated documentation files (the
  11.  * "Software"), to deal in the Software without restriction, including
  12.  * without limitation the rights to use, copy, modify, merge, publish,
  13.  * distribute, sub license, and/or sell copies of the Software, and to
  14.  * permit persons to whom the Software is furnished to do so, subject to
  15.  * the following conditions:
  16.  *
  17.  * The above copyright notice and this permission notice (including the
  18.  * next paragraph) shall be included in all copies or substantial portions
  19.  * of the Software.
  20.  *
  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  22.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  24.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  25.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  26.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  27.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28.  *
  29.  */
  30.  
  31. #include <drm/drmP.h>
  32. #include <drm/drm.h>
  33.  
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/mod_devicetable.h>
  37. #include <errno-base.h>
  38. #include <linux/pci.h>
  39.  
  40. #include "i915_drv.h"
  41. #include <syscall.h>
  42.  
  43. unsigned int i915_lvds_downclock =  0;
  44. int i915_vbt_sdvo_panel_type     = -1;
  45. unsigned int i915_panel_use_ssc  =  1;
  46. unsigned int i915_powersave      =  1;
  47. unsigned int i915_enable_fbc     =  1;
  48.  
  49. #define PCI_VENDOR_ID_INTEL        0x8086
  50.  
  51. #define INTEL_VGA_DEVICE(id, info) {        \
  52.     .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  53.     .class_mask = 0xff0000,                 \
  54.     .vendor = 0x8086,                       \
  55.     .device = id,                           \
  56.     .subvendor = PCI_ANY_ID,                \
  57.     .subdevice = PCI_ANY_ID,                \
  58.     .driver_data = (unsigned long) info }
  59.  
  60. static const struct intel_device_info intel_sandybridge_d_info = {
  61.     .gen = 6,
  62.     .need_gfx_hws = 1,
  63.     .has_hotplug  = 1,
  64.     .has_bsd_ring = 1,
  65.     .has_blt_ring = 1,
  66. };
  67.  
  68. static const struct intel_device_info intel_sandybridge_m_info = {
  69.     .gen = 6,
  70.     .is_mobile    = 1,
  71.     .need_gfx_hws = 1,
  72.     .has_hotplug  = 1,
  73.     .has_fbc      = 1,
  74.     .has_bsd_ring = 1,
  75.     .has_blt_ring = 1,
  76. };
  77.  
  78.  
  79. static const struct pci_device_id pciidlist[] = {       /* aka */
  80.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  81.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  82.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  83.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  84.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  85.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  86.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  87.     {0, 0, 0}
  88. };
  89.  
  90. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  91. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  92. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  93. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  94.  
  95. void intel_detect_pch (struct drm_device *dev)
  96. {
  97.     struct drm_i915_private *dev_priv = dev->dev_private;
  98.     struct pci_dev *pch;
  99.  
  100.     /*
  101.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  102.      * make graphics device passthrough work easy for VMM, that only
  103.      * need to expose ISA bridge to let driver know the real hardware
  104.      * underneath. This is a requirement from virtualization team.
  105.      */
  106.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  107.     if (pch) {
  108.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  109.             int id;
  110.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  111.  
  112.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  113.                 dev_priv->pch_type = PCH_IBX;
  114.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  115.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  116.                 dev_priv->pch_type = PCH_CPT;
  117.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  118.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  119.                 /* PantherPoint is CPT compatible */
  120.                 dev_priv->pch_type = PCH_CPT;
  121.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  122.             }
  123.         }
  124.     }
  125. }
  126.  
  127. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  128. {
  129.     int count;
  130.  
  131.     count = 0;
  132.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  133.         udelay(10);
  134.  
  135.     I915_WRITE_NOTRACE(FORCEWAKE, 1);
  136.     POSTING_READ(FORCEWAKE);
  137.  
  138.     count = 0;
  139.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
  140.         udelay(10);
  141. }
  142.  
  143. /*
  144.  * Generally this is called implicitly by the register read function. However,
  145.  * if some sequence requires the GT to not power down then this function should
  146.  * be called at the beginning of the sequence followed by a call to
  147.  * gen6_gt_force_wake_put() at the end of the sequence.
  148.  */
  149. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  150. {
  151. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  152.  
  153.     /* Forcewake is atomic in case we get in here without the lock */
  154.     if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
  155.         __gen6_gt_force_wake_get(dev_priv);
  156. }
  157.  
  158. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  159. {
  160.     I915_WRITE_NOTRACE(FORCEWAKE, 0);
  161.     POSTING_READ(FORCEWAKE);
  162. }
  163.  
  164. /*
  165.  * see gen6_gt_force_wake_get()
  166.  */
  167. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  168. {
  169. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  170.  
  171.     if (atomic_dec_and_test(&dev_priv->forcewake_count))
  172.         __gen6_gt_force_wake_put(dev_priv);
  173. }
  174.  
  175. void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  176. {
  177.     if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) {
  178.         int loop = 500;
  179.         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  180.         while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  181.             udelay(10);
  182.             fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  183.         }
  184. //        WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
  185.         dev_priv->gt_fifo_count = fifo;
  186.     }
  187.     dev_priv->gt_fifo_count--;
  188. }
  189.  
  190.  
  191.  
  192.  
  193.  
  194. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  195.  
  196. int i915_init(void)
  197. {
  198.     static pci_dev_t device;
  199.     const struct pci_device_id  *ent;
  200.     int  err;
  201.  
  202.     if( init_agp() != 0)
  203.     {
  204.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  205.         return 0;
  206.     };
  207.  
  208.     ent = find_pci_device(&device, pciidlist);
  209.  
  210.     if( unlikely(ent == NULL) )
  211.     {
  212.         dbgprintf("device not found\n");
  213.         return 0;
  214.     };
  215.  
  216.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  217.                                 device.pci_dev.device);
  218.  
  219.     err = drm_get_dev(&device.pci_dev, ent);
  220.  
  221.     return err;
  222. }
  223.  
  224. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  225. {
  226.     static struct drm_device *dev;
  227.     int ret;
  228.  
  229.     ENTER();
  230.  
  231.     dev = kzalloc(sizeof(*dev), 0);
  232.     if (!dev)
  233.         return -ENOMEM;
  234.  
  235.  //   ret = pci_enable_device(pdev);
  236.  //   if (ret)
  237.  //       goto err_g1;
  238.  
  239.  //   pci_set_master(pdev);
  240.  
  241.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  242.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  243.  //       goto err_g2;
  244.  //   }
  245.  
  246.     dev->pdev = pdev;
  247.     dev->pci_device = pdev->device;
  248.     dev->pci_vendor = pdev->vendor;
  249.  
  250.     INIT_LIST_HEAD(&dev->filelist);
  251.     INIT_LIST_HEAD(&dev->ctxlist);
  252.     INIT_LIST_HEAD(&dev->vmalist);
  253.     INIT_LIST_HEAD(&dev->maplist);
  254.  
  255.     spin_lock_init(&dev->count_lock);
  256.     mutex_init(&dev->struct_mutex);
  257.     mutex_init(&dev->ctxlist_mutex);
  258.  
  259. //int i915_driver_load(struct drm_device *dev, unsigned long flags)
  260.  
  261.     ret = i915_driver_load(dev, ent->driver_data );
  262. //    if (ret)
  263. //        goto err_g4;
  264.  
  265. //    if( radeon_modeset )
  266. //        init_display_kms(dev->dev_private, &usermode);
  267. //    else
  268. //        init_display(dev->dev_private, &usermode);
  269.  
  270.     LEAVE();
  271.  
  272.     return 0;
  273.  
  274. err_g4:
  275. //    drm_put_minor(&dev->primary);
  276. //err_g3:
  277. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  278. //        drm_put_minor(&dev->control);
  279. //err_g2:
  280. //    pci_disable_device(pdev);
  281. //err_g1:
  282.     free(dev);
  283.  
  284.     LEAVE();
  285.  
  286.     return ret;
  287. }
  288.  
  289.  
  290.