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  1.  
  2. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  3.  */
  4. /*
  5.  *
  6.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  7.  * All Rights Reserved.
  8.  *
  9.  * Permission is hereby granted, free of charge, to any person obtaining a
  10.  * copy of this software and associated documentation files (the
  11.  * "Software"), to deal in the Software without restriction, including
  12.  * without limitation the rights to use, copy, modify, merge, publish,
  13.  * distribute, sub license, and/or sell copies of the Software, and to
  14.  * permit persons to whom the Software is furnished to do so, subject to
  15.  * the following conditions:
  16.  *
  17.  * The above copyright notice and this permission notice (including the
  18.  * next paragraph) shall be included in all copies or substantial portions
  19.  * of the Software.
  20.  *
  21.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  22.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  24.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  25.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  26.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  27.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28.  *
  29.  */
  30.  
  31. //#include <linux/device.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "intel_drv.h"
  37.  
  38.  
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/mod_devicetable.h>
  42. #include <errno-base.h>
  43. #include <linux/pci.h>
  44.  
  45. #include <syscall.h>
  46.  
  47. #define __read_mostly
  48.  
  49.  
  50. int i915_panel_ignore_lid __read_mostly         =  0;
  51.  
  52. unsigned int i915_powersave  __read_mostly      =  0;
  53.  
  54. unsigned int i915_enable_rc6 __read_mostly      =  0;
  55.  
  56. unsigned int i915_enable_fbc __read_mostly      =  1;
  57.  
  58. unsigned int i915_lvds_downclock  __read_mostly =  0;
  59.  
  60. unsigned int i915_panel_use_ssc __read_mostly   =  1;
  61.  
  62. int i915_vbt_sdvo_panel_type __read_mostly      = -1;
  63.  
  64. #define PCI_VENDOR_ID_INTEL        0x8086
  65.  
  66. #define INTEL_VGA_DEVICE(id, info) {        \
  67.     .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  68.     .class_mask = 0xff0000,                 \
  69.     .vendor = 0x8086,                       \
  70.     .device = id,                           \
  71.     .subvendor = PCI_ANY_ID,                \
  72.     .subdevice = PCI_ANY_ID,                \
  73.     .driver_data = (unsigned long) info }
  74.  
  75. static const struct intel_device_info intel_sandybridge_d_info = {
  76.     .gen = 6,
  77.         .need_gfx_hws = 1, .has_hotplug = 1,
  78.     .has_bsd_ring = 1,
  79.     .has_blt_ring = 1,
  80. };
  81.  
  82. static const struct intel_device_info intel_sandybridge_m_info = {
  83.         .gen = 6, .is_mobile = 1,
  84.         .need_gfx_hws = 1, .has_hotplug = 1,
  85.     .has_fbc      = 1,
  86.     .has_bsd_ring = 1,
  87.     .has_blt_ring = 1,
  88. };
  89.  
  90.  
  91. static const struct pci_device_id pciidlist[] = {       /* aka */
  92.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  93.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  94.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  95.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  96.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  97.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  98.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  99.     {0, 0, 0}
  100. };
  101.  
  102. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  103. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  104. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  105. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  106.  
  107. void intel_detect_pch (struct drm_device *dev)
  108. {
  109.     struct drm_i915_private *dev_priv = dev->dev_private;
  110.     struct pci_dev *pch;
  111.  
  112.     /*
  113.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  114.      * make graphics device passthrough work easy for VMM, that only
  115.      * need to expose ISA bridge to let driver know the real hardware
  116.      * underneath. This is a requirement from virtualization team.
  117.      */
  118.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  119.     if (pch) {
  120.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  121.             int id;
  122.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  123.  
  124.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  125.                 dev_priv->pch_type = PCH_IBX;
  126.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  127.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  128.                 dev_priv->pch_type = PCH_CPT;
  129.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  130.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  131.                 /* PantherPoint is CPT compatible */
  132.                 dev_priv->pch_type = PCH_CPT;
  133.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  134.             }
  135.         }
  136.     }
  137. }
  138.  
  139. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  140. {
  141.     int count;
  142.  
  143.     count = 0;
  144.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  145.         udelay(10);
  146.  
  147.     I915_WRITE_NOTRACE(FORCEWAKE, 1);
  148.     POSTING_READ(FORCEWAKE);
  149.  
  150.     count = 0;
  151.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
  152.         udelay(10);
  153. }
  154.  
  155. /*
  156.  * Generally this is called implicitly by the register read function. However,
  157.  * if some sequence requires the GT to not power down then this function should
  158.  * be called at the beginning of the sequence followed by a call to
  159.  * gen6_gt_force_wake_put() at the end of the sequence.
  160.  */
  161. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  162. {
  163. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  164.  
  165.     /* Forcewake is atomic in case we get in here without the lock */
  166.     if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
  167.         __gen6_gt_force_wake_get(dev_priv);
  168. }
  169.  
  170. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  171. {
  172.     I915_WRITE_NOTRACE(FORCEWAKE, 0);
  173.     POSTING_READ(FORCEWAKE);
  174. }
  175.  
  176. /*
  177.  * see gen6_gt_force_wake_get()
  178.  */
  179. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  180. {
  181. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  182.  
  183.     if (atomic_dec_and_test(&dev_priv->forcewake_count))
  184.         __gen6_gt_force_wake_put(dev_priv);
  185. }
  186.  
  187. void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  188. {
  189.     if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) {
  190.         int loop = 500;
  191.         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  192.         while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  193.             udelay(10);
  194.             fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  195.         }
  196. //        WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
  197.         dev_priv->gt_fifo_count = fifo;
  198.     }
  199.     dev_priv->gt_fifo_count--;
  200. }
  201.  
  202.  
  203.  
  204.  
  205.  
  206. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  207.  
  208. int i915_init(void)
  209. {
  210.     static pci_dev_t device;
  211.     const struct pci_device_id  *ent;
  212.     int  err;
  213.  
  214.     if( init_agp() != 0)
  215.     {
  216.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  217.         return 0;
  218.     };
  219.  
  220.     ent = find_pci_device(&device, pciidlist);
  221.  
  222.     if( unlikely(ent == NULL) )
  223.     {
  224.         dbgprintf("device not found\n");
  225.         return 0;
  226.     };
  227.  
  228.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  229.                                 device.pci_dev.device);
  230.  
  231.     err = drm_get_dev(&device.pci_dev, ent);
  232.  
  233.     return err;
  234. }
  235.  
  236. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  237. {
  238.     static struct drm_device *dev;
  239.     int ret;
  240.  
  241.     ENTER();
  242.  
  243.     dev = kzalloc(sizeof(*dev), 0);
  244.     if (!dev)
  245.         return -ENOMEM;
  246.  
  247.  //   ret = pci_enable_device(pdev);
  248.  //   if (ret)
  249.  //       goto err_g1;
  250.  
  251.  //   pci_set_master(pdev);
  252.  
  253.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  254.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  255.  //       goto err_g2;
  256.  //   }
  257.  
  258.     dev->pdev = pdev;
  259.     dev->pci_device = pdev->device;
  260.     dev->pci_vendor = pdev->vendor;
  261.  
  262.     INIT_LIST_HEAD(&dev->filelist);
  263.     INIT_LIST_HEAD(&dev->ctxlist);
  264.     INIT_LIST_HEAD(&dev->vmalist);
  265.     INIT_LIST_HEAD(&dev->maplist);
  266.  
  267.     spin_lock_init(&dev->count_lock);
  268.     mutex_init(&dev->struct_mutex);
  269.     mutex_init(&dev->ctxlist_mutex);
  270.  
  271.  
  272.  
  273.     ret = i915_driver_load(dev, ent->driver_data );
  274. //    if (ret)
  275. //        goto err_g4;
  276.  
  277. //    if( radeon_modeset )
  278. //        init_display_kms(dev->dev_private, &usermode);
  279. //    else
  280. //        init_display(dev->dev_private, &usermode);
  281.  
  282.     LEAVE();
  283.  
  284.     return 0;
  285.  
  286. err_g4:
  287. //    drm_put_minor(&dev->primary);
  288. //err_g3:
  289. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  290. //        drm_put_minor(&dev->control);
  291. //err_g2:
  292. //    pci_disable_device(pdev);
  293. //err_g1:
  294.     free(dev);
  295.  
  296.     LEAVE();
  297.  
  298.     return ret;
  299. }
  300.  
  301.  
  302.