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  1. /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  2.  */
  3. /*
  4.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5.  * All Rights Reserved.
  6.  *
  7.  * Permission is hereby granted, free of charge, to any person obtaining a
  8.  * copy of this software and associated documentation files (the
  9.  * "Software"), to deal in the Software without restriction, including
  10.  * without limitation the rights to use, copy, modify, merge, publish,
  11.  * distribute, sub license, and/or sell copies of the Software, and to
  12.  * permit persons to whom the Software is furnished to do so, subject to
  13.  * the following conditions:
  14.  *
  15.  * The above copyright notice and this permission notice (including the
  16.  * next paragraph) shall be included in all copies or substantial portions
  17.  * of the Software.
  18.  *
  19.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26.  *
  27.  */
  28.  
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30.  
  31. #include <drm/drmP.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_fb_helper.h>
  34. #include <drm/drm_legacy.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_vgpu.h"
  39. #include "i915_trace.h"
  40. #include <linux/pci.h>
  41. #include <linux/vgaarb.h>
  42. #include <linux/acpi.h>
  43. //#include <linux/pnp.h>
  44. //#include <linux/vga_switcheroo.h>
  45. #include <linux/slab.h>
  46. //#include <acpi/video.h>
  47. #include <linux/pm.h>
  48. #include <linux/pm_runtime.h>
  49.  
  50. void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
  51.  
  52. int i915_getparam(struct drm_device *dev, void *data,
  53.                          struct drm_file *file_priv)
  54. {
  55.         struct drm_i915_private *dev_priv = dev->dev_private;
  56.         drm_i915_getparam_t *param = data;
  57.         int value;
  58.  
  59.         switch (param->param) {
  60.         case I915_PARAM_IRQ_ACTIVE:
  61.         case I915_PARAM_ALLOW_BATCHBUFFER:
  62.         case I915_PARAM_LAST_DISPATCH:
  63.                 /* Reject all old ums/dri params. */
  64.                 return -ENODEV;
  65.         case I915_PARAM_CHIPSET_ID:
  66.                 value = dev->pdev->device;
  67.                 break;
  68.         case I915_PARAM_REVISION:
  69.                 value = dev->pdev->revision;
  70.                 break;
  71.         case I915_PARAM_HAS_GEM:
  72.                 value = 1;
  73.                 break;
  74.         case I915_PARAM_NUM_FENCES_AVAIL:
  75.                 value = dev_priv->num_fence_regs;
  76.                 break;
  77.         case I915_PARAM_HAS_OVERLAY:
  78.                 value = dev_priv->overlay ? 1 : 0;
  79.                 break;
  80.         case I915_PARAM_HAS_PAGEFLIPPING:
  81.                 value = 1;
  82.                 break;
  83.         case I915_PARAM_HAS_EXECBUF2:
  84.                 /* depends on GEM */
  85.                 value = 1;
  86.                 break;
  87.         case I915_PARAM_HAS_BSD:
  88.                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  89.                 break;
  90.         case I915_PARAM_HAS_BLT:
  91.                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  92.                 break;
  93.         case I915_PARAM_HAS_VEBOX:
  94.                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  95.                 break;
  96.         case I915_PARAM_HAS_BSD2:
  97.                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
  98.                 break;
  99.         case I915_PARAM_HAS_RELAXED_FENCING:
  100.                 value = 1;
  101.                 break;
  102.         case I915_PARAM_HAS_COHERENT_RINGS:
  103.                 value = 1;
  104.                 break;
  105.         case I915_PARAM_HAS_EXEC_CONSTANTS:
  106.                 value = INTEL_INFO(dev)->gen >= 4;
  107.                 break;
  108.         case I915_PARAM_HAS_RELAXED_DELTA:
  109.                 value = 1;
  110.                 break;
  111.         case I915_PARAM_HAS_GEN7_SOL_RESET:
  112.                 value = 1;
  113.                 break;
  114.         case I915_PARAM_HAS_LLC:
  115.                 value = HAS_LLC(dev);
  116.                 break;
  117.         case I915_PARAM_HAS_WT:
  118.                 value = HAS_WT(dev);
  119.                 break;
  120.         case I915_PARAM_HAS_ALIASING_PPGTT:
  121.                 value = USES_PPGTT(dev);
  122.                 break;
  123.         case I915_PARAM_HAS_WAIT_TIMEOUT:
  124.                 value = 1;
  125.                 break;
  126.         case I915_PARAM_HAS_SEMAPHORES:
  127.                 value = i915_semaphore_is_enabled(dev);
  128.                 break;
  129.         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
  130.                 value = 1;
  131.                 break;
  132.         case I915_PARAM_HAS_SECURE_BATCHES:
  133.                 value = capable(CAP_SYS_ADMIN);
  134.                 break;
  135.         case I915_PARAM_HAS_PINNED_BATCHES:
  136.                 value = 1;
  137.                 break;
  138.         case I915_PARAM_HAS_EXEC_NO_RELOC:
  139.                 value = 1;
  140.                 break;
  141.         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
  142.                 value = 1;
  143.                 break;
  144.         case I915_PARAM_CMD_PARSER_VERSION:
  145.                 value = i915_cmd_parser_get_version();
  146.                 break;
  147.         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
  148.                 value = 1;
  149.                 break;
  150.         case I915_PARAM_MMAP_VERSION:
  151.                 value = 1;
  152.                 break;
  153.         case I915_PARAM_SUBSLICE_TOTAL:
  154.                 value = INTEL_INFO(dev)->subslice_total;
  155.                 if (!value)
  156.                         return -ENODEV;
  157.                 break;
  158.         case I915_PARAM_EU_TOTAL:
  159.                 value = INTEL_INFO(dev)->eu_total;
  160.                 if (!value)
  161.                         return -ENODEV;
  162.                 break;
  163.         case I915_PARAM_HAS_GPU_RESET:
  164.                 value = i915.enable_hangcheck &&
  165.                         intel_has_gpu_reset(dev);
  166.                 break;
  167.         case I915_PARAM_HAS_RESOURCE_STREAMER:
  168.                 value = HAS_RESOURCE_STREAMER(dev);
  169.                 break;
  170.         default:
  171.                 DRM_DEBUG("Unknown parameter %d\n", param->param);
  172.                 return -EINVAL;
  173.         }
  174.  
  175.     *param->value = value;
  176.  
  177.         return 0;
  178. }
  179.  
  180. static int i915_get_bridge_dev(struct drm_device *dev)
  181. {
  182.         struct drm_i915_private *dev_priv = dev->dev_private;
  183.  
  184.         dev_priv->bridge_dev = _pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
  185.         if (!dev_priv->bridge_dev) {
  186.                 DRM_ERROR("bridge device not found\n");
  187.                 return -1;
  188.         }
  189.         return 0;
  190. }
  191.  
  192. #define MCHBAR_I915 0x44
  193. #define MCHBAR_I965 0x48
  194. #define MCHBAR_SIZE (4*4096)
  195.  
  196. #define DEVEN_REG 0x54
  197. #define   DEVEN_MCHBAR_EN (1 << 28)
  198.  
  199.  
  200. /* Setup MCHBAR if possible, return true if we should disable it again */
  201. static void
  202. intel_setup_mchbar(struct drm_device *dev)
  203. {
  204.         struct drm_i915_private *dev_priv = dev->dev_private;
  205.         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  206.         u32 temp;
  207.         bool enabled;
  208.  
  209.         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
  210.                 return;
  211.  
  212.         dev_priv->mchbar_need_disable = false;
  213.  
  214.         if (IS_I915G(dev) || IS_I915GM(dev)) {
  215.                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  216.                 enabled = !!(temp & DEVEN_MCHBAR_EN);
  217.         } else {
  218.                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  219.                 enabled = temp & 1;
  220.         }
  221.  
  222.         /* If it's already enabled, don't have to do anything */
  223.         if (enabled)
  224.                 return;
  225. /*
  226.         if (intel_alloc_mchbar_resource(dev))
  227.                 return;
  228.  
  229.         God help us all
  230. */
  231.         dev_priv->mchbar_need_disable = true;
  232.  
  233.         /* Space is allocated or reserved, so enable it. */
  234.         if (IS_I915G(dev) || IS_I915GM(dev)) {
  235.                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
  236.                                        temp | DEVEN_MCHBAR_EN);
  237.         } else {
  238.                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  239.                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
  240.         }
  241. }
  242.  
  243. static void
  244. intel_teardown_mchbar(struct drm_device *dev)
  245. {
  246.         struct drm_i915_private *dev_priv = dev->dev_private;
  247.         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  248.         u32 temp;
  249.  
  250.         if (dev_priv->mchbar_need_disable) {
  251.                 if (IS_I915G(dev) || IS_I915GM(dev)) {
  252.                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  253.                         temp &= ~DEVEN_MCHBAR_EN;
  254.                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
  255.                 } else {
  256.                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  257.                         temp &= ~1;
  258.                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
  259.                 }
  260.         }
  261.  
  262.         if (dev_priv->mch_res.start)
  263.                 release_resource(&dev_priv->mch_res);
  264. }
  265.  
  266. /* true = enable decode, false = disable decoder */
  267. static unsigned int i915_vga_set_decode(void *cookie, bool state)
  268. {
  269.         struct drm_device *dev = cookie;
  270.  
  271.         intel_modeset_vga_set_state(dev, state);
  272.         if (state)
  273.                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  274.                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  275.         else
  276.                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  277. }
  278.  
  279.  
  280.  
  281.  
  282.  
  283.  
  284. static int i915_load_modeset_init(struct drm_device *dev)
  285. {
  286.         struct drm_i915_private *dev_priv = dev->dev_private;
  287.         int ret;
  288.  
  289.         ret = intel_bios_init(dev_priv);
  290.         if (ret)
  291.                 DRM_INFO("failed to find VBIOS tables\n");
  292.  
  293.         /* If we have > 1 VGA cards, then we need to arbitrate access
  294.          * to the common VGA resources.
  295.          *
  296.          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
  297.          * then we do not take part in VGA arbitration and the
  298.          * vga_client_register() fails with -ENODEV.
  299.          */
  300.  
  301.         /* Initialise stolen first so that we may reserve preallocated
  302.          * objects for the BIOS to KMS transition.
  303.          */
  304.         ret = i915_gem_init_stolen(dev);
  305.         if (ret)
  306.                 goto cleanup_vga_switcheroo;
  307.  
  308.         intel_power_domains_init_hw(dev_priv, false);
  309.  
  310.         intel_csr_ucode_init(dev_priv);
  311.  
  312.         ret = intel_irq_install(dev_priv);
  313.         if (ret)
  314.                 goto cleanup_gem_stolen;
  315.  
  316.         intel_setup_gmbus(dev);
  317.  
  318.         /* Important: The output setup functions called by modeset_init need
  319.          * working irqs for e.g. gmbus and dp aux transfers. */
  320.         intel_modeset_init(dev);
  321.  
  322.         intel_guc_ucode_init(dev);
  323.  
  324.         ret = i915_gem_init(dev);
  325.         if (ret)
  326.                 goto cleanup_irq;
  327.  
  328.         intel_modeset_gem_init(dev);
  329.  
  330.         /* Always safe in the mode setting case. */
  331.         /* FIXME: do pre/post-mode set stuff in core KMS code */
  332.         dev->vblank_disable_allowed = true;
  333.         if (INTEL_INFO(dev)->num_pipes == 0)
  334.                 return 0;
  335.  
  336.         ret = intel_fbdev_init(dev);
  337.         if (ret)
  338.                 goto cleanup_gem;
  339.  
  340.         /* Only enable hotplug handling once the fbdev is fully set up. */
  341.         intel_hpd_init(dev_priv);
  342.  
  343.         /*
  344.          * Some ports require correctly set-up hpd registers for detection to
  345.          * work properly (leading to ghost connected connector status), e.g. VGA
  346.          * on gm45.  Hence we can only set up the initial fbdev config after hpd
  347.          * irqs are fully enabled. Now we should scan for the initial config
  348.          * only once hotplug handling is enabled, but due to screwed-up locking
  349.          * around kms/fbdev init we can't protect the fdbev initial config
  350.          * scanning against hotplug events. Hence do this first and ignore the
  351.          * tiny window where we will loose hotplug notifactions.
  352.          */
  353.         intel_fbdev_initial_config(dev_priv, 0);
  354.  
  355.         drm_kms_helper_poll_init(dev);
  356.  
  357.         return 0;
  358.  
  359. cleanup_gem:
  360.         mutex_lock(&dev->struct_mutex);
  361.         i915_gem_cleanup_ringbuffer(dev);
  362.         i915_gem_context_fini(dev);
  363.         mutex_unlock(&dev->struct_mutex);
  364. cleanup_irq:
  365.         intel_guc_ucode_fini(dev);
  366. //      drm_irq_uninstall(dev);
  367. cleanup_gem_stolen:
  368.         i915_gem_cleanup_stolen(dev);
  369. cleanup_vga_switcheroo:
  370. //      vga_switcheroo_unregister_client(dev->pdev);
  371. cleanup_vga_client:
  372. //      vga_client_register(dev->pdev, NULL, NULL, NULL);
  373. out:
  374.         return ret;
  375. }
  376.  
  377. #if IS_ENABLED(CONFIG_FB)
  378. static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
  379. {
  380.         struct apertures_struct *ap;
  381.         struct pci_dev *pdev = dev_priv->dev->pdev;
  382.         bool primary;
  383.         int ret;
  384.  
  385.         ap = alloc_apertures(1);
  386.         if (!ap)
  387.                 return -ENOMEM;
  388.  
  389.         ap->ranges[0].base = dev_priv->gtt.mappable_base;
  390.         ap->ranges[0].size = dev_priv->gtt.mappable_end;
  391.  
  392.         primary =
  393.                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  394.  
  395.         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
  396.  
  397.         kfree(ap);
  398.  
  399.         return ret;
  400. }
  401. #else
  402. static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
  403. {
  404.         return 0;
  405. }
  406. #endif
  407.  
  408. #if !defined(CONFIG_VGA_CONSOLE)
  409. static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
  410. {
  411.         return 0;
  412. }
  413. #elif !defined(CONFIG_DUMMY_CONSOLE)
  414. static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
  415. {
  416.         return -ENODEV;
  417. }
  418. #else
  419. static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
  420. {
  421.         int ret = 0;
  422.  
  423.         DRM_INFO("Replacing VGA console driver\n");
  424.  
  425.         console_lock();
  426.         if (con_is_bound(&vga_con))
  427.                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
  428.         if (ret == 0) {
  429.                 ret = do_unregister_con_driver(&vga_con);
  430.  
  431.                 /* Ignore "already unregistered". */
  432.                 if (ret == -ENODEV)
  433.                         ret = 0;
  434.         }
  435.         console_unlock();
  436.  
  437.         return ret;
  438. }
  439. #endif
  440.  
  441. static void i915_dump_device_info(struct drm_i915_private *dev_priv)
  442. {
  443.         const struct intel_device_info *info = &dev_priv->info;
  444.  
  445. #define PRINT_S(name) "%s"
  446. #define SEP_EMPTY
  447. #define PRINT_FLAG(name) info->name ? #name "," : ""
  448. #define SEP_COMMA ,
  449.         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
  450.                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
  451.                          info->gen,
  452.                          dev_priv->dev->pdev->device,
  453.                          dev_priv->dev->pdev->revision,
  454.                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
  455. #undef PRINT_S
  456. #undef SEP_EMPTY
  457. #undef PRINT_FLAG
  458. #undef SEP_COMMA
  459. }
  460.  
  461. static void cherryview_sseu_info_init(struct drm_device *dev)
  462. {
  463.         struct drm_i915_private *dev_priv = dev->dev_private;
  464.         struct intel_device_info *info;
  465.         u32 fuse, eu_dis;
  466.  
  467.         info = (struct intel_device_info *)&dev_priv->info;
  468.         fuse = I915_READ(CHV_FUSE_GT);
  469.  
  470.         info->slice_total = 1;
  471.  
  472.         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
  473.                 info->subslice_per_slice++;
  474.                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
  475.                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
  476.                 info->eu_total += 8 - hweight32(eu_dis);
  477.         }
  478.  
  479.         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
  480.                 info->subslice_per_slice++;
  481.                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
  482.                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
  483.                 info->eu_total += 8 - hweight32(eu_dis);
  484.         }
  485.  
  486.         info->subslice_total = info->subslice_per_slice;
  487.         /*
  488.          * CHV expected to always have a uniform distribution of EU
  489.          * across subslices.
  490.         */
  491.         info->eu_per_subslice = info->subslice_total ?
  492.                                 info->eu_total / info->subslice_total :
  493.                                 0;
  494.         /*
  495.          * CHV supports subslice power gating on devices with more than
  496.          * one subslice, and supports EU power gating on devices with
  497.          * more than one EU pair per subslice.
  498.         */
  499.         info->has_slice_pg = 0;
  500.         info->has_subslice_pg = (info->subslice_total > 1);
  501.         info->has_eu_pg = (info->eu_per_subslice > 2);
  502. }
  503.  
  504. static void gen9_sseu_info_init(struct drm_device *dev)
  505. {
  506.         struct drm_i915_private *dev_priv = dev->dev_private;
  507.         struct intel_device_info *info;
  508.         int s_max = 3, ss_max = 4, eu_max = 8;
  509.         int s, ss;
  510.         u32 fuse2, s_enable, ss_disable, eu_disable;
  511.         u8 eu_mask = 0xff;
  512.  
  513.         info = (struct intel_device_info *)&dev_priv->info;
  514.         fuse2 = I915_READ(GEN8_FUSE2);
  515.         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
  516.                    GEN8_F2_S_ENA_SHIFT;
  517.         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
  518.                      GEN9_F2_SS_DIS_SHIFT;
  519.  
  520.         info->slice_total = hweight32(s_enable);
  521.         /*
  522.          * The subslice disable field is global, i.e. it applies
  523.          * to each of the enabled slices.
  524.         */
  525.         info->subslice_per_slice = ss_max - hweight32(ss_disable);
  526.         info->subslice_total = info->slice_total *
  527.                                info->subslice_per_slice;
  528.  
  529.         /*
  530.          * Iterate through enabled slices and subslices to
  531.          * count the total enabled EU.
  532.         */
  533.         for (s = 0; s < s_max; s++) {
  534.                 if (!(s_enable & (0x1 << s)))
  535.                         /* skip disabled slice */
  536.                         continue;
  537.  
  538.                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
  539.                 for (ss = 0; ss < ss_max; ss++) {
  540.                         int eu_per_ss;
  541.  
  542.                         if (ss_disable & (0x1 << ss))
  543.                                 /* skip disabled subslice */
  544.                                 continue;
  545.  
  546.                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
  547.                                                       eu_mask);
  548.  
  549.                         /*
  550.                          * Record which subslice(s) has(have) 7 EUs. we
  551.                          * can tune the hash used to spread work among
  552.                          * subslices if they are unbalanced.
  553.                          */
  554.                         if (eu_per_ss == 7)
  555.                                 info->subslice_7eu[s] |= 1 << ss;
  556.  
  557.                         info->eu_total += eu_per_ss;
  558.                 }
  559.         }
  560.  
  561.         /*
  562.          * SKL is expected to always have a uniform distribution
  563.          * of EU across subslices with the exception that any one
  564.          * EU in any one subslice may be fused off for die
  565.          * recovery. BXT is expected to be perfectly uniform in EU
  566.          * distribution.
  567.         */
  568.         info->eu_per_subslice = info->subslice_total ?
  569.                                 DIV_ROUND_UP(info->eu_total,
  570.                                              info->subslice_total) : 0;
  571.         /*
  572.          * SKL supports slice power gating on devices with more than
  573.          * one slice, and supports EU power gating on devices with
  574.          * more than one EU pair per subslice. BXT supports subslice
  575.          * power gating on devices with more than one subslice, and
  576.          * supports EU power gating on devices with more than one EU
  577.          * pair per subslice.
  578.         */
  579.         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
  580.                                (info->slice_total > 1));
  581.         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
  582.         info->has_eu_pg = (info->eu_per_subslice > 2);
  583. }
  584.  
  585. static void broadwell_sseu_info_init(struct drm_device *dev)
  586. {
  587.         struct drm_i915_private *dev_priv = dev->dev_private;
  588.         struct intel_device_info *info;
  589.         const int s_max = 3, ss_max = 3, eu_max = 8;
  590.         int s, ss;
  591.         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
  592.  
  593.         fuse2 = I915_READ(GEN8_FUSE2);
  594.         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
  595.         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
  596.  
  597.         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
  598.         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
  599.                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
  600.                          (32 - GEN8_EU_DIS0_S1_SHIFT));
  601.         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
  602.                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
  603.                          (32 - GEN8_EU_DIS1_S2_SHIFT));
  604.  
  605.  
  606.         info = (struct intel_device_info *)&dev_priv->info;
  607.         info->slice_total = hweight32(s_enable);
  608.  
  609.         /*
  610.          * The subslice disable field is global, i.e. it applies
  611.          * to each of the enabled slices.
  612.          */
  613.         info->subslice_per_slice = ss_max - hweight32(ss_disable);
  614.         info->subslice_total = info->slice_total * info->subslice_per_slice;
  615.  
  616.         /*
  617.          * Iterate through enabled slices and subslices to
  618.          * count the total enabled EU.
  619.          */
  620.         for (s = 0; s < s_max; s++) {
  621.                 if (!(s_enable & (0x1 << s)))
  622.                         /* skip disabled slice */
  623.                         continue;
  624.  
  625.                 for (ss = 0; ss < ss_max; ss++) {
  626.                         u32 n_disabled;
  627.  
  628.                         if (ss_disable & (0x1 << ss))
  629.                                 /* skip disabled subslice */
  630.                                 continue;
  631.  
  632.                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
  633.  
  634.                         /*
  635.                          * Record which subslices have 7 EUs.
  636.                          */
  637.                         if (eu_max - n_disabled == 7)
  638.                                 info->subslice_7eu[s] |= 1 << ss;
  639.  
  640.                         info->eu_total += eu_max - n_disabled;
  641.                 }
  642.         }
  643.  
  644.         /*
  645.          * BDW is expected to always have a uniform distribution of EU across
  646.          * subslices with the exception that any one EU in any one subslice may
  647.          * be fused off for die recovery.
  648.          */
  649.         info->eu_per_subslice = info->subslice_total ?
  650.                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
  651.  
  652.         /*
  653.          * BDW supports slice power gating on devices with more than
  654.          * one slice.
  655.          */
  656.         info->has_slice_pg = (info->slice_total > 1);
  657.         info->has_subslice_pg = 0;
  658.         info->has_eu_pg = 0;
  659. }
  660.  
  661. /*
  662.  * Determine various intel_device_info fields at runtime.
  663.  *
  664.  * Use it when either:
  665.  *   - it's judged too laborious to fill n static structures with the limit
  666.  *     when a simple if statement does the job,
  667.  *   - run-time checks (eg read fuse/strap registers) are needed.
  668.  *
  669.  * This function needs to be called:
  670.  *   - after the MMIO has been setup as we are reading registers,
  671.  *   - after the PCH has been detected,
  672.  *   - before the first usage of the fields it can tweak.
  673.  */
  674. static void intel_device_info_runtime_init(struct drm_device *dev)
  675. {
  676.         struct drm_i915_private *dev_priv = dev->dev_private;
  677.         struct intel_device_info *info;
  678.         enum pipe pipe;
  679.  
  680.         info = (struct intel_device_info *)&dev_priv->info;
  681.  
  682.         /*
  683.          * Skylake and Broxton currently don't expose the topmost plane as its
  684.          * use is exclusive with the legacy cursor and we only want to expose
  685.          * one of those, not both. Until we can safely expose the topmost plane
  686.          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
  687.          * we don't expose the topmost plane at all to prevent ABI breakage
  688.          * down the line.
  689.          */
  690.         if (IS_BROXTON(dev)) {
  691.                 info->num_sprites[PIPE_A] = 2;
  692.                 info->num_sprites[PIPE_B] = 2;
  693.                 info->num_sprites[PIPE_C] = 1;
  694.         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
  695.                 for_each_pipe(dev_priv, pipe)
  696.                         info->num_sprites[pipe] = 2;
  697.         else
  698.                 for_each_pipe(dev_priv, pipe)
  699.                         info->num_sprites[pipe] = 1;
  700.  
  701.         if (i915.disable_display) {
  702.                 DRM_INFO("Display disabled (module parameter)\n");
  703.                 info->num_pipes = 0;
  704.         } else if (info->num_pipes > 0 &&
  705.                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
  706.                    HAS_PCH_SPLIT(dev)) {
  707.                 u32 fuse_strap = I915_READ(FUSE_STRAP);
  708.                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
  709.  
  710.                 /*
  711.                  * SFUSE_STRAP is supposed to have a bit signalling the display
  712.                  * is fused off. Unfortunately it seems that, at least in
  713.                  * certain cases, fused off display means that PCH display
  714.                  * reads don't land anywhere. In that case, we read 0s.
  715.                  *
  716.                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
  717.                  * should be set when taking over after the firmware.
  718.                  */
  719.                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
  720.                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
  721.                     (dev_priv->pch_type == PCH_CPT &&
  722.                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
  723.                         DRM_INFO("Display fused off, disabling\n");
  724.                         info->num_pipes = 0;
  725.                 }
  726.         }
  727.  
  728.         /* Initialize slice/subslice/EU info */
  729.         if (IS_CHERRYVIEW(dev))
  730.                 cherryview_sseu_info_init(dev);
  731.         else if (IS_BROADWELL(dev))
  732.                 broadwell_sseu_info_init(dev);
  733.         else if (INTEL_INFO(dev)->gen >= 9)
  734.                 gen9_sseu_info_init(dev);
  735.  
  736.         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
  737.         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
  738.         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
  739.         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
  740.         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
  741.         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
  742.                          info->has_slice_pg ? "y" : "n");
  743.         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
  744.                          info->has_subslice_pg ? "y" : "n");
  745.         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
  746.                          info->has_eu_pg ? "y" : "n");
  747. }
  748.  
  749. static void intel_init_dpio(struct drm_i915_private *dev_priv)
  750. {
  751.         /*
  752.          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
  753.          * CHV x1 PHY (DP/HDMI D)
  754.          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
  755.          */
  756.         if (IS_CHERRYVIEW(dev_priv)) {
  757.                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
  758.                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
  759.         } else if (IS_VALLEYVIEW(dev_priv)) {
  760.                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
  761.         }
  762. }
  763.  
  764. /**
  765.  * i915_driver_load - setup chip and create an initial config
  766.  * @dev: DRM device
  767.  * @flags: startup flags
  768.  *
  769.  * The driver load routine has to do several things:
  770.  *   - drive output discovery via intel_modeset_init()
  771.  *   - initialize the memory manager
  772.  *   - allocate initial config memory
  773.  *   - setup the DRM framebuffer with the allocated memory
  774.  */
  775. int i915_driver_load(struct drm_device *dev, unsigned long flags)
  776. {
  777.         struct drm_i915_private *dev_priv;
  778.         struct intel_device_info *info, *device_info;
  779.         int ret = 0, mmio_bar, mmio_size;
  780.         uint32_t aperture_size;
  781.  
  782.         info = (struct intel_device_info *) flags;
  783.  
  784.         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
  785.         if (dev_priv == NULL)
  786.                 return -ENOMEM;
  787.  
  788.         dev->dev_private = dev_priv;
  789.         dev_priv->dev = dev;
  790.  
  791.         /* Setup the write-once "constant" device info */
  792.         device_info = (struct intel_device_info *)&dev_priv->info;
  793.         memcpy(device_info, info, sizeof(dev_priv->info));
  794.         device_info->device_id = dev->pdev->device;
  795.  
  796.         spin_lock_init(&dev_priv->irq_lock);
  797.         spin_lock_init(&dev_priv->gpu_error.lock);
  798.         mutex_init(&dev_priv->backlight_lock);
  799.         spin_lock_init(&dev_priv->uncore.lock);
  800.         spin_lock_init(&dev_priv->mm.object_stat_lock);
  801.         spin_lock_init(&dev_priv->mmio_flip_lock);
  802.         mutex_init(&dev_priv->sb_lock);
  803.         mutex_init(&dev_priv->modeset_restore_lock);
  804.         mutex_init(&dev_priv->av_mutex);
  805.  
  806.         intel_pm_setup(dev);
  807.  
  808.         intel_runtime_pm_get(dev_priv);
  809.  
  810.         intel_display_crc_init(dev);
  811.  
  812.         i915_dump_device_info(dev_priv);
  813.  
  814.         /* Not all pre-production machines fall into this category, only the
  815.          * very first ones. Almost everything should work, except for maybe
  816.          * suspend/resume. And we don't implement workarounds that affect only
  817.          * pre-production machines. */
  818.         if (IS_HSW_EARLY_SDV(dev))
  819.                 DRM_INFO("This is an early pre-production Haswell machine. "
  820.                          "It may not be fully functional.\n");
  821.  
  822.         if (i915_get_bridge_dev(dev)) {
  823.                 ret = -EIO;
  824.                 goto free_priv;
  825.         }
  826.  
  827.         mmio_bar = IS_GEN2(dev) ? 1 : 0;
  828.         /* Before gen4, the registers and the GTT are behind different BARs.
  829.          * However, from gen4 onwards, the registers and the GTT are shared
  830.          * in the same BAR, so we want to restrict this ioremap from
  831.          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
  832.          * the register BAR remains the same size for all the earlier
  833.          * generations up to Ironlake.
  834.          */
  835.         if (info->gen < 5)
  836.                 mmio_size = 512*1024;
  837.         else
  838.                 mmio_size = 2*1024*1024;
  839.  
  840.         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
  841.         if (!dev_priv->regs) {
  842.                 DRM_ERROR("failed to map registers\n");
  843.                 ret = -EIO;
  844.                 goto put_bridge;
  845.         }
  846.  
  847.         set_fake_framebuffer();
  848.  
  849.         /* This must be called before any calls to HAS_PCH_* */
  850.         intel_detect_pch(dev);
  851.  
  852.         intel_uncore_init(dev);
  853.  
  854.         ret = i915_gem_gtt_init(dev);
  855.         if (ret)
  856.                 goto out_freecsr;
  857.  
  858.         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
  859.          * otherwise the vga fbdev driver falls over. */
  860.         ret = i915_kick_out_firmware_fb(dev_priv);
  861.         if (ret) {
  862.                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
  863.                 goto out_gtt;
  864.         }
  865.  
  866.         ret = i915_kick_out_vgacon(dev_priv);
  867.         if (ret) {
  868.                 DRM_ERROR("failed to remove conflicting VGA console\n");
  869.                 goto out_gtt;
  870.         }
  871.  
  872.         pci_set_master(dev->pdev);
  873.  
  874.  
  875.         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
  876.          * using 32bit addressing, overwriting memory if HWS is located
  877.          * above 4GB.
  878.          *
  879.          * The documentation also mentions an issue with undefined
  880.          * behaviour if any general state is accessed within a page above 4GB,
  881.          * which also needs to be handled carefully.
  882.          */
  883.  
  884.         aperture_size = dev_priv->gtt.mappable_end;
  885.  
  886.         dev_priv->gtt.mappable = AllocKernelSpace(8192);
  887.         if (dev_priv->gtt.mappable == NULL) {
  888.                 ret = -EIO;
  889.                 goto out_gtt;
  890.         }
  891.  
  892.  
  893.         /* The i915 workqueue is primarily used for batched retirement of
  894.          * requests (and thus managing bo) once the task has been completed
  895.          * by the GPU. i915_gem_retire_requests() is called directly when we
  896.          * need high-priority retirement, such as waiting for an explicit
  897.          * bo.
  898.          *
  899.          * It is also used for periodic low-priority events, such as
  900.          * idle-timers and recording error state.
  901.          *
  902.          * All tasks on the workqueue are expected to acquire the dev mutex
  903.          * so there is no point in running more than one instance of the
  904.          * workqueue at any time.  Use an ordered one.
  905.          */
  906.         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
  907.         if (dev_priv->wq == NULL) {
  908.                 DRM_ERROR("Failed to create our workqueue.\n");
  909.                 ret = -ENOMEM;
  910.                 goto out_mtrrfree;
  911.         }
  912.     system_wq = dev_priv->wq;
  913.  
  914.         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
  915.         if (dev_priv->hotplug.dp_wq == NULL) {
  916.                 DRM_ERROR("Failed to create our dp workqueue.\n");
  917.                 ret = -ENOMEM;
  918.                 goto out_freewq;
  919.         }
  920.  
  921.         intel_irq_init(dev_priv);
  922.         intel_uncore_sanitize(dev);
  923.  
  924.         /* Try to make sure MCHBAR is enabled before poking at it */
  925.         intel_setup_mchbar(dev);
  926.         intel_opregion_setup(dev);
  927.  
  928.         i915_gem_load(dev);
  929.  
  930.         /* On the 945G/GM, the chipset reports the MSI capability on the
  931.          * integrated graphics even though the support isn't actually there
  932.          * according to the published specs.  It doesn't appear to function
  933.          * correctly in testing on 945G.
  934.          * This may be a side effect of MSI having been made available for PEG
  935.          * and the registers being closely associated.
  936.          *
  937.          * According to chipset errata, on the 965GM, MSI interrupts may
  938.          * be lost or delayed, but we use them anyways to avoid
  939.          * stuck interrupts on some machines.
  940.          */
  941.  
  942.         intel_device_info_runtime_init(dev);
  943.  
  944.         intel_init_dpio(dev_priv);
  945.  
  946.         if (INTEL_INFO(dev)->num_pipes) {
  947.                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
  948.                 if (ret)
  949.                         goto out_gem_unload;
  950.         }
  951.  
  952.         intel_power_domains_init(dev_priv);
  953.  
  954.         ret = i915_load_modeset_init(dev);
  955.         if (ret < 0) {
  956.                 DRM_ERROR("failed to init modeset\n");
  957.                 goto out_power_well;
  958.         }
  959.  
  960.         /*
  961.          * Notify a valid surface after modesetting,
  962.          * when running inside a VM.
  963.          */
  964.         if (intel_vgpu_active(dev))
  965.                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
  966.  
  967.         if (INTEL_INFO(dev)->num_pipes) {
  968.                 /* Must be done after probing outputs */
  969.                 intel_opregion_init(dev);
  970.         }
  971.  
  972.         if (IS_GEN5(dev))
  973.                 intel_gpu_ips_init(dev_priv);
  974.  
  975. //   intel_runtime_pm_enable(dev_priv);
  976.  
  977.         main_device = dev;
  978.  
  979.         return 0;
  980.  
  981. out_power_well:
  982.         drm_vblank_cleanup(dev);
  983. out_gem_unload:
  984.  
  985. out_freewq:
  986. out_mtrrfree:
  987. out_gtt:
  988.         i915_global_gtt_cleanup(dev);
  989. out_freecsr:
  990. put_bridge:
  991. free_priv:
  992.     kfree(dev_priv);
  993.     return ret;
  994. }
  995.  
  996. #if 0
  997. int i915_driver_unload(struct drm_device *dev)
  998. {
  999.         struct drm_i915_private *dev_priv = dev->dev_private;
  1000.         int ret;
  1001.  
  1002.         intel_fbdev_fini(dev);
  1003.  
  1004.         i915_audio_component_cleanup(dev_priv);
  1005.  
  1006.         ret = i915_gem_suspend(dev);
  1007.         if (ret) {
  1008.                 DRM_ERROR("failed to idle hardware: %d\n", ret);
  1009.                 return ret;
  1010.         }
  1011.  
  1012.         intel_power_domains_fini(dev_priv);
  1013.  
  1014.         intel_gpu_ips_teardown();
  1015.  
  1016.         i915_teardown_sysfs(dev);
  1017.  
  1018.         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
  1019.         unregister_shrinker(&dev_priv->mm.shrinker);
  1020.  
  1021.         io_mapping_free(dev_priv->gtt.mappable);
  1022.         arch_phys_wc_del(dev_priv->gtt.mtrr);
  1023.  
  1024.         acpi_video_unregister();
  1025.  
  1026.         drm_vblank_cleanup(dev);
  1027.  
  1028.         intel_modeset_cleanup(dev);
  1029.  
  1030.         /*
  1031.          * free the memory space allocated for the child device
  1032.          * config parsed from VBT
  1033.          */
  1034.         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
  1035.                 kfree(dev_priv->vbt.child_dev);
  1036.                 dev_priv->vbt.child_dev = NULL;
  1037.                 dev_priv->vbt.child_dev_num = 0;
  1038.         }
  1039.         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
  1040.         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
  1041.         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
  1042.         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
  1043.  
  1044.         vga_switcheroo_unregister_client(dev->pdev);
  1045.         vga_client_register(dev->pdev, NULL, NULL, NULL);
  1046.  
  1047.         /* Free error state after interrupts are fully disabled. */
  1048.         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
  1049.         i915_destroy_error_state(dev);
  1050.  
  1051.         if (dev->pdev->msi_enabled)
  1052.                 pci_disable_msi(dev->pdev);
  1053.  
  1054.         intel_opregion_fini(dev);
  1055.  
  1056.         /* Flush any outstanding unpin_work. */
  1057.         flush_workqueue(dev_priv->wq);
  1058.  
  1059.         intel_guc_ucode_fini(dev);
  1060.         mutex_lock(&dev->struct_mutex);
  1061.         i915_gem_cleanup_ringbuffer(dev);
  1062.         i915_gem_context_fini(dev);
  1063.         mutex_unlock(&dev->struct_mutex);
  1064.         intel_fbc_cleanup_cfb(dev_priv);
  1065.         i915_gem_cleanup_stolen(dev);
  1066.  
  1067.         intel_csr_ucode_fini(dev_priv);
  1068.  
  1069.         intel_teardown_mchbar(dev);
  1070.  
  1071.         destroy_workqueue(dev_priv->hotplug.dp_wq);
  1072.         destroy_workqueue(dev_priv->wq);
  1073.         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
  1074.         pm_qos_remove_request(&dev_priv->pm_qos);
  1075.  
  1076.         i915_global_gtt_cleanup(dev);
  1077.  
  1078.         intel_uncore_fini(dev);
  1079.         if (dev_priv->regs != NULL)
  1080.                 pci_iounmap(dev->pdev, dev_priv->regs);
  1081.  
  1082.         kmem_cache_destroy(dev_priv->requests);
  1083.         kmem_cache_destroy(dev_priv->vmas);
  1084.         kmem_cache_destroy(dev_priv->objects);
  1085.         pci_dev_put(dev_priv->bridge_dev);
  1086.         kfree(dev_priv);
  1087.  
  1088.         return 0;
  1089. }
  1090. #endif
  1091.  
  1092. int i915_driver_open(struct drm_device *dev, struct drm_file *file)
  1093. {
  1094.         int ret;
  1095.  
  1096.         ret = i915_gem_open(dev, file);
  1097.         if (ret)
  1098.                 return ret;
  1099.  
  1100.         return 0;
  1101. }
  1102.  
  1103. #if 0
  1104. /**
  1105.  * i915_driver_lastclose - clean up after all DRM clients have exited
  1106.  * @dev: DRM device
  1107.  *
  1108.  * Take care of cleaning up after all DRM clients have exited.  In the
  1109.  * mode setting case, we want to restore the kernel's initial mode (just
  1110.  * in case the last client left us in a bad state).
  1111.  *
  1112.  * Additionally, in the non-mode setting case, we'll tear down the GTT
  1113.  * and DMA structures, since the kernel won't be using them, and clea
  1114.  * up any GEM state.
  1115.  */
  1116. void i915_driver_lastclose(struct drm_device *dev)
  1117. {
  1118.         intel_fbdev_restore_mode(dev);
  1119.         vga_switcheroo_process_delayed_switch();
  1120. }
  1121.  
  1122. void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
  1123. {
  1124.         mutex_lock(&dev->struct_mutex);
  1125.         i915_gem_context_close(dev, file);
  1126.         i915_gem_release(dev, file);
  1127.         mutex_unlock(&dev->struct_mutex);
  1128.  
  1129.         intel_modeset_preclose(dev, file);
  1130. }
  1131.  
  1132. void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
  1133. {
  1134.         struct drm_i915_file_private *file_priv = file->driver_priv;
  1135.  
  1136.         kfree(file_priv);
  1137. }
  1138.  
  1139. static int
  1140. i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
  1141.                           struct drm_file *file)
  1142. {
  1143.         return -ENODEV;
  1144. }
  1145.  
  1146. const struct drm_ioctl_desc i915_ioctls[] = {
  1147.         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1148.         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
  1149.         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
  1150.         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
  1151.         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
  1152.         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
  1153.         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
  1154.         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1155.         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
  1156.         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
  1157.         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1158.         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
  1159.         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1160.         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1161.         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
  1162.         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
  1163.         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1164.         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1165.         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
  1166.         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
  1167.         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
  1168.         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
  1169.         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
  1170.         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
  1171.         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
  1172.         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
  1173.         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1174.         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1175.         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
  1176.         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
  1177.         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
  1178.         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
  1179.         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
  1180.         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
  1181.         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
  1182.         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
  1183.         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
  1184.         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
  1185.         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
  1186.         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
  1187.         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
  1188.         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
  1189.         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
  1190.         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
  1191.         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
  1192.         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
  1193.         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
  1194.         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
  1195.         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW),
  1196.         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
  1197.         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
  1198.         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
  1199. };
  1200.  
  1201. int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
  1202. #endif
  1203.