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  1.  
  2. #include <assert.h>
  3. #include <stdlib.h>
  4. #include <memory.h>
  5.  
  6. #include <intel_bufmgr.h>
  7. //#include "xf86.h"
  8. #include "uxa/intel.h"
  9. #include "i830_reg.h"
  10. #include "i965_reg.h"
  11.  
  12. /* bring in brw structs */
  13. #include "brw_defines.h"
  14. #include "brw_structs.h"
  15.  
  16. #include "i915_pciids.h"
  17. #include <pixlib2.h>
  18. #include <kos32sys.h>
  19.  
  20. #define PictOpClear             0
  21. #define PictOpSrc               1
  22. #define PictOpDst               2
  23. #define PictOpOver              3
  24. #define PictOpOverReverse       4
  25. #define PictOpIn                5
  26. #define PictOpInReverse         6
  27. #define PictOpOut               7
  28. #define PictOpOutReverse        8
  29. #define PictOpAtop              9
  30. #define PictOpAtopReverse       10
  31. #define PictOpXor               11
  32. #define PictOpAdd               12
  33. #define PictOpSaturate          13
  34. #define PictOpMaximum           13
  35.  
  36. static int    tls_mask;
  37.  
  38. intel_screen_private *driverPrivate;
  39. __LOCK_INIT_RECURSIVE(, __uxa_lock);
  40.  
  41. #define DBG printf
  42.  
  43. typedef struct
  44. {
  45.     struct list     entry;
  46.     uint32_t        width;
  47.     uint32_t        height;
  48.     void           *data;
  49.     uint32_t        pitch;
  50.     drm_intel_bo   *bo;
  51.     uint32_t        bo_size;
  52.     uint32_t        flags;
  53. }surface_t;
  54.  
  55. #define to_surface(x) (surface_t*)((x)->handle)
  56.  
  57. struct _Pixmap fb_pixmap;
  58.  
  59. struct list sf_list;
  60.  
  61. int uxa_update_fb(struct intel_screen_private *intel);
  62.  
  63. int sna_create_mask()
  64. {
  65.     return 0;
  66. };
  67.  
  68. static void i830_done_composite(PixmapPtr dest)
  69. {
  70.         intel_screen_private *intel = intel_get_screen_private();
  71.  
  72.         if (intel->vertex_flush)
  73.                 intel->vertex_flush(intel);
  74.  
  75. //      intel_debug_flush(scrn);
  76. }
  77.  
  78. int sna_bitmap_from_handle(bitmap_t *bitmap, uint32_t handle)
  79. {
  80.         struct intel_screen_private *intel = intel_get_screen_private();
  81.         drm_intel_bo *bo;
  82.     surface_t    *sf;
  83.     unsigned int size;
  84.  
  85.     bitmap->handle = 0;
  86.  
  87.     __lock_acquire_recursive(__uxa_lock);
  88.     list_for_each_entry(sf, &sf_list, entry)
  89.     {
  90.         if (sf->bo->handle == handle)
  91.         {
  92.             bitmap->handle = (uint32_t)sf;
  93.             break;
  94.         }
  95.     }
  96.     __lock_release_recursive(__uxa_lock);
  97.  
  98.     if(bitmap->handle)
  99.         return 0;
  100.  
  101.     sf = malloc(sizeof(*sf));
  102.     if(sf == NULL)
  103.         goto err_1;
  104.  
  105.     size = bitmap->pitch * bitmap->height;
  106.  
  107.     bo = bo_create_from_gem_handle(intel->bufmgr, size, handle);
  108.  
  109.     sf->width   = bitmap->width;
  110.     sf->height  = bitmap->height;
  111.     sf->data    = NULL;
  112.     sf->pitch   = bitmap->pitch;
  113.     sf->bo      = bo;
  114.     sf->bo_size = size;
  115.     sf->flags   = bitmap->flags;
  116.  
  117.     bitmap->handle = (uint32_t)sf;
  118.  
  119.     return 0;
  120.  
  121. err_1:
  122.  
  123.     return -1;
  124. };
  125.  
  126. void sna_set_bo_handle(bitmap_t *bitmap, int handle)
  127. {
  128.     sna_bitmap_from_handle(bitmap, handle);
  129. };
  130.  
  131.  
  132. int sna_blit_tex(bitmap_t *bitmap, bool scale, int dst_x, int dst_y,
  133.                   int w, int h, int src_x, int src_y)
  134. {
  135.     struct _Pixmap pixSrc, pixMask;
  136.     struct intel_pixmap privSrc;
  137.     struct _Picture pictSrc, pictDst;
  138.         struct intel_screen_private *intel = intel_get_screen_private();
  139.  
  140.     surface_t *sf = to_surface(bitmap);
  141.  
  142.     int winx, winy;
  143.  
  144.     char proc_info[1024];
  145.     get_proc_info(proc_info);
  146.     winx = *(uint32_t*)(proc_info+34);
  147.     winy = *(uint32_t*)(proc_info+38);
  148.  
  149.     memset(&pixSrc,  0, sizeof(pixSrc));
  150.     memset(&pixMask, 0, sizeof(pixMask));
  151.     memset(&privSrc, 0, sizeof(pixSrc));
  152.  
  153.     memset(&pictSrc, 0, sizeof(pictSrc));
  154.     memset(&pictDst, 0, sizeof(pictDst));
  155.  
  156.     pixSrc.drawable.bitsPerPixel = 32;
  157.     pixSrc.drawable.width        = sf->width;
  158.     pixSrc.drawable.height       = sf->height;
  159.     pixSrc.devKind               = sf->pitch;
  160.     pixSrc.private               = &privSrc;
  161.  
  162.     list_init(&privSrc.batch);
  163.     privSrc.bo = sf->bo;
  164.     privSrc.stride = sf->pitch;
  165.     privSrc.tiling = I915_TILING_X;
  166.  
  167.     pictSrc.format     = PICT_x8r8g8b8;
  168.     pictSrc.filter     = PictFilterNearest;
  169.     pictSrc.repeatType = RepeatNone;
  170.  
  171.     pictDst.format     = PICT_a8r8g8b8;
  172.     pictDst.filter = PictFilterNearest;
  173.     pictDst.repeatType = RepeatNone;
  174.  
  175.     uxa_update_fb(intel);
  176.  
  177. //    pixDst.drawable.bitsPerPixel = 32;
  178. //    pixDst.drawable.width  = sna_fb.width;
  179. //    pixDst.drawable.height = sna_fb.height;
  180.  
  181. //   pixMask.drawable.bitsPerPixel = 8;
  182. //    pixMask.drawable.width  = update.width;
  183. //    pixMask.drawable.height = update.height;
  184.  
  185.     i965_prepare_composite(PictOpSrc, &pictSrc, NULL, &pictDst,
  186.                            &pixSrc, NULL, &fb_pixmap);
  187.  
  188.  
  189.     i965_composite(&fb_pixmap, src_x, src_y, 0, 0,
  190.                     dst_x, dst_y, w, h);
  191.  
  192.     i830_done_composite(&fb_pixmap);
  193.  
  194.         intel_batch_submit();
  195.  
  196.     return 0;
  197. };
  198.  
  199.  
  200. int uxa_init_fb(struct intel_screen_private *intel)
  201. {
  202.     struct drm_i915_fb_info fb;
  203.     static struct intel_pixmap ipix;
  204.     int ret;
  205.  
  206.     memset(&fb, 0, sizeof(fb));
  207.  
  208.     ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb);
  209.         if( ret != 0 )
  210.             return ret;
  211.  
  212.     intel->front_buffer = intel_bo_gem_create_from_name(intel->bufmgr,"frontbuffer", fb.name);
  213.     if(intel->front_buffer == NULL)
  214.         return -1;
  215.  
  216.     ipix.bo = intel->front_buffer;
  217.     list_init(&ipix.batch);
  218.     ipix.stride = fb.pitch;
  219.     ipix.tiling = fb.tiling;
  220.     ipix.pinned = PIN_SCANOUT;
  221.  
  222.     printf("create frontbuffer name %d bo %x\n", fb.name, ipix.bo);
  223.     printf("size %d, offset %d handle %d\n",ipix.bo->size, ipix.bo->offset, ipix.bo->handle);
  224.  
  225.     fb_pixmap.drawable.bitsPerPixel = 32;
  226.     fb_pixmap.drawable.width  = fb.width;
  227.     fb_pixmap.drawable.height = fb.height;
  228.     fb_pixmap.devKind = fb.pitch;
  229.     fb_pixmap.private = &ipix;
  230.  
  231.     return 0;
  232. }
  233.  
  234. int uxa_update_fb(struct intel_screen_private *intel)
  235. {
  236.     struct drm_i915_fb_info fb;
  237.     struct intel_pixmap *ipix;
  238.     size_t size;
  239.     int ret;
  240.  
  241.     ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb);
  242.         if( ret != 0 )
  243.             return ret;
  244.  
  245.     ipix = (struct intel_pixmap*)fb_pixmap.private;
  246.     ipix->stride = fb.pitch;
  247.     ipix->tiling = fb.tiling;
  248.  
  249.     fb_pixmap.drawable.width  = fb.width;
  250.     fb_pixmap.drawable.height = fb.height;
  251.     fb_pixmap.devKind = fb.pitch;
  252.  
  253.     return 0;
  254. };
  255.  
  256. int uxa_init(uint32_t service)
  257. {
  258.     static struct pci_device device;
  259.         struct intel_screen_private *intel = intel_get_screen_private();
  260.  
  261.     ioctl_t   io;
  262.     int caps = 0;
  263.  
  264.     DBG("%s\n", __FUNCTION__);
  265.  
  266.     __lock_acquire_recursive(__uxa_lock);
  267.  
  268.     if(intel)
  269.         goto done;
  270.  
  271.     io.handle   = service;
  272.     io.io_code  = SRV_GET_PCI_INFO;
  273.     io.input    = &device;
  274.     io.inp_size = sizeof(device);
  275.     io.output   = NULL;
  276.     io.out_size = 0;
  277.  
  278.     if (call_service(&io)!=0)
  279.         goto err1;
  280.  
  281.     intel = (intel_screen_private*)malloc(sizeof(*intel));
  282.     if (intel == NULL)
  283.         goto err1;
  284.  
  285.     list_init(&sf_list);
  286.  
  287.     driverPrivate = intel;
  288.     memset(intel, 0, sizeof(*intel));
  289.  
  290. //    sna->cpu_features = sna_cpu_detect();
  291.  
  292.     intel->PciInfo = &device;
  293.         intel->info = intel_detect_chipset(intel->PciInfo);
  294.     intel->scrn = service;
  295.  
  296.     intel->bufmgr = intel_bufmgr_gem_init(service, 8192);
  297.     if(intel->bufmgr == NULL)
  298.     {
  299.                 printf("Memory manager initialization failed\n");
  300.                 goto err1;
  301.     };
  302.  
  303.     if( uxa_init_fb(intel) != 0)
  304.         goto err1;
  305.  
  306.         intel_batch_init();
  307.  
  308.         if (INTEL_INFO(intel)->gen >= 040)
  309.                 gen4_render_state_init();
  310.  
  311.         if (!intel_uxa_init()) {
  312.                 printf("Hardware acceleration initialization failed\n");
  313.                 goto err1;
  314.         }
  315.  
  316.     tls_mask = tls_alloc();
  317.  
  318. //    printf("tls mask %x\n", tls_mask);
  319.  
  320. done:
  321. //    caps = sna_device->render.caps;
  322.  
  323. err1:
  324.     __lock_release_recursive(__uxa_lock);
  325.  
  326.     LEAVE();
  327.     return caps;
  328. }
  329.  
  330.  
  331.  
  332. static void
  333. gen6_context_switch(intel_screen_private *intel,
  334.                     int new_mode)
  335. {
  336.         intel_batch_submit(intel->scrn);
  337. }
  338.  
  339. static void
  340. gen5_context_switch(intel_screen_private *intel,
  341.                     int new_mode)
  342. {
  343.         /* Ironlake has a limitation that a 3D or Media command can't
  344.          * be the first command after a BLT, unless it's
  345.          * non-pipelined.  Instead of trying to track it and emit a
  346.          * command at the right time, we just emit a dummy
  347.          * non-pipelined 3D instruction after each blit.
  348.          */
  349.  
  350.         if (new_mode == I915_EXEC_BLT) {
  351.                 OUT_BATCH(MI_FLUSH |
  352.                           MI_STATE_INSTRUCTION_CACHE_FLUSH |
  353.                           MI_INHIBIT_RENDER_CACHE_FLUSH);
  354.         } else {
  355.                 OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
  356.                 OUT_BATCH(0);
  357.         }
  358. }
  359.  
  360. static void
  361. gen4_context_switch(intel_screen_private *intel,
  362.                     int new_mode)
  363. {
  364.         if (new_mode == I915_EXEC_BLT) {
  365.                 OUT_BATCH(MI_FLUSH |
  366.                           MI_STATE_INSTRUCTION_CACHE_FLUSH |
  367.                           MI_INHIBIT_RENDER_CACHE_FLUSH);
  368.         }
  369. }
  370.  
  371. static void
  372. intel_limits_init(intel_screen_private *intel)
  373. {
  374.         /* Limits are described in the BLT engine chapter under Graphics Data Size
  375.          * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
  376.          * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
  377.          *
  378.          * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
  379.          *
  380.          * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
  381.          * i965 limits 3D surface to 4kB-aligned offset if tiled.
  382.          * i965 limits 3D surfaces to w,h of ?,8192.
  383.          * i965 limits 3D surface to pitch of 1B - 128kB.
  384.          * i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
  385.          * i965 limits 3D surface pitch alignment to 512B if tiled.
  386.          * i965 limits 3D destination drawing rect to w,h of 8192,8192.
  387.          *
  388.          * i915 limits 3D textures to 4B-aligned offset if un-tiled.
  389.          * i915 limits 3D textures to ~4kB-aligned offset if tiled.
  390.          * i915 limits 3D textures to width,height of 2048,2048.
  391.          * i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
  392.          * i915 limits 3D destination to ~4kB-aligned offset if tiled.
  393.          * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
  394.          * i915 limits 3D destination to pitch 64B-aligned if used with depth.
  395.          * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
  396.          * i915 limits 3D destination to POT aligned pitch if tiled.
  397.          * i915 limits 3D destination drawing rect to w,h of 2048,2048.
  398.          *
  399.          * i845 limits 3D textures to 4B-aligned offset if un-tiled.
  400.          * i845 limits 3D textures to ~4kB-aligned offset if tiled.
  401.          * i845 limits 3D textures to width,height of 2048,2048.
  402.          * i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
  403.          * i845 limits 3D destination to 4B-aligned offset if un-tiled.
  404.          * i845 limits 3D destination to ~4kB-aligned offset if tiled.
  405.          * i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
  406.          * i845 limits 3D destination drawing rect to w,h of 2048,2048.
  407.          *
  408.          * For the tiled issues, the only tiled buffer we draw to should be
  409.          * the front, which will have an appropriate pitch/offset already set up,
  410.          * so UXA doesn't need to worry.
  411.          */
  412.         if (INTEL_INFO(intel)->gen >= 040) {
  413.                 intel->accel_pixmap_offset_alignment = 4 * 2;
  414.                 intel->accel_max_x = 8192;
  415.                 intel->accel_max_y = 8192;
  416.         } else {
  417.                 intel->accel_pixmap_offset_alignment = 4;
  418.                 intel->accel_max_x = 2048;
  419.                 intel->accel_max_y = 2048;
  420.         }
  421. }
  422.  
  423.  
  424. Bool intel_uxa_init()
  425. {
  426.         intel_screen_private *intel = intel_get_screen_private();
  427.  
  428.         intel_limits_init(intel);
  429.  
  430.         intel->prim_offset = 0;
  431.         intel->vertex_count = 0;
  432.         intel->vertex_offset = 0;
  433.         intel->vertex_used = 0;
  434.         intel->floats_per_vertex = 0;
  435.         intel->last_floats_per_vertex = 0;
  436.         intel->vertex_bo = NULL;
  437.         intel->surface_used = 0;
  438.         intel->surface_reloc = 0;
  439.  
  440. /*
  441.         intel->uxa_driver->check_composite = i965_check_composite;
  442.         intel->uxa_driver->check_composite_texture = i965_check_composite_texture;
  443.         intel->uxa_driver->prepare_composite = i965_prepare_composite;
  444.         intel->uxa_driver->composite = i965_composite;
  445.         intel->uxa_driver->done_composite = i830_done_composite;
  446. */
  447.         intel->vertex_flush = i965_vertex_flush;
  448.         intel->batch_flush = i965_batch_flush;
  449.         intel->batch_commit_notify = i965_batch_commit_notify;
  450.  
  451.         if (IS_GEN4(intel)) {
  452.                 intel->context_switch = gen4_context_switch;
  453.         } else if (IS_GEN5(intel)) {
  454.                 intel->context_switch = gen5_context_switch;
  455.         } else {
  456.                 intel->context_switch = gen6_context_switch;
  457.         }
  458.  
  459.         return TRUE;
  460. }
  461.  
  462.  
  463. static const struct intel_device_info intel_generic_info = {
  464.         .gen = -1,
  465. };
  466.  
  467. static const struct intel_device_info intel_i915_info = {
  468.         .gen = 030,
  469. };
  470. static const struct intel_device_info intel_i945_info = {
  471.         .gen = 031,
  472. };
  473.  
  474. static const struct intel_device_info intel_g33_info = {
  475.         .gen = 033,
  476. };
  477.  
  478. static const struct intel_device_info intel_i965_info = {
  479.         .gen = 040,
  480. };
  481.  
  482. static const struct intel_device_info intel_g4x_info = {
  483.         .gen = 045,
  484. };
  485.  
  486. static const struct intel_device_info intel_ironlake_info = {
  487.         .gen = 050,
  488. };
  489.  
  490. static const struct intel_device_info intel_sandybridge_info = {
  491.         .gen = 060,
  492. };
  493.  
  494. static const struct intel_device_info intel_ivybridge_info = {
  495.         .gen = 070,
  496. };
  497.  
  498. static const struct intel_device_info intel_valleyview_info = {
  499.         .gen = 071,
  500. };
  501.  
  502. static const struct intel_device_info intel_haswell_info = {
  503.         .gen = 075,
  504. };
  505.  
  506. #define INTEL_DEVICE_MATCH(d,i) \
  507.     { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) }
  508.  
  509.  
  510. static const struct pci_id_match intel_device_match[] = {
  511.  
  512.         INTEL_I915G_IDS(&intel_i915_info),
  513.         INTEL_I915GM_IDS(&intel_i915_info),
  514.         INTEL_I945G_IDS(&intel_i945_info),
  515.         INTEL_I945GM_IDS(&intel_i945_info),
  516.  
  517.         INTEL_G33_IDS(&intel_g33_info),
  518.         INTEL_PINEVIEW_IDS(&intel_g33_info),
  519.  
  520.         INTEL_I965G_IDS(&intel_i965_info),
  521.         INTEL_I965GM_IDS(&intel_i965_info),
  522.  
  523.         INTEL_G45_IDS(&intel_g4x_info),
  524.         INTEL_GM45_IDS(&intel_g4x_info),
  525.  
  526.         INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
  527.         INTEL_IRONLAKE_M_IDS(&intel_ironlake_info),
  528.  
  529.         INTEL_SNB_D_IDS(&intel_sandybridge_info),
  530.         INTEL_SNB_M_IDS(&intel_sandybridge_info),
  531.  
  532.         INTEL_IVB_D_IDS(&intel_ivybridge_info),
  533.         INTEL_IVB_M_IDS(&intel_ivybridge_info),
  534.  
  535.         INTEL_HSW_D_IDS(&intel_haswell_info),
  536.         INTEL_HSW_M_IDS(&intel_haswell_info),
  537.  
  538.         INTEL_VLV_D_IDS(&intel_valleyview_info),
  539.         INTEL_VLV_M_IDS(&intel_valleyview_info),
  540.  
  541.         INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
  542.  
  543.         { 0, 0, 0 },
  544. };
  545.  
  546. const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list)
  547. {
  548.     while(list->device_id)
  549.     {
  550.         if(dev==list->device_id)
  551.             return list;
  552.         list++;
  553.     }
  554.     return NULL;
  555. }
  556.  
  557.  
  558. const struct intel_device_info *
  559. intel_detect_chipset(struct pci_device *pci)
  560. {
  561.     const struct pci_id_match *ent = NULL;
  562.  
  563.     ent = PciDevMatch(pci->device_id, intel_device_match);
  564.  
  565.     if(ent != NULL)
  566.         return (const struct intel_device_info*)ent->match_data;
  567.     else
  568.         return &intel_generic_info;
  569. }
  570.  
  571.