Subversion Repositories Kolibri OS

Rev

Go to most recent revision | Blame | Last modification | View Log | Download | RSS feed

  1.  
  2.  
  3. #pragma pack(push, 1)
  4. typedef struct
  5. {
  6.      u16_t device;
  7.      u16_t ChipSet;
  8. }PciChipset_t;
  9. #pragma pack(pop)
  10.  
  11. #define VENDOR_ATI                 0x1002
  12.  
  13.  
  14. #define PCI_CLASS_DISPLAY_VGA      0x0300
  15. /*
  16.  * Under PCI, each device has 256 bytes of configuration address space,
  17.  * of which the first 64 bytes are standardized as follows:
  18.  */
  19. #define PCI_VENDOR_ID                   0x000    /* 16 bits */
  20. #define PCI_DEVICE_ID                   0x002    /* 16 bits */
  21. #define PCI_COMMAND                     0x004    /* 16 bits */
  22. #define  PCI_COMMAND_IO                 0x001    /* Enable response in I/O space */
  23. #define  PCI_COMMAND_MEMORY             0x002    /* Enable response in Memory space */
  24. #define  PCI_COMMAND_MASTER             0x004    /* Enable bus mastering */
  25. #define  PCI_COMMAND_SPECIAL            0x008    /* Enable response to special cycles */
  26. #define  PCI_COMMAND_INVALIDATE         0x010    /* Use memory write and invalidate */
  27. #define  PCI_COMMAND_VGA_PALETTE        0x020    /* Enable palette snooping */
  28. #define  PCI_COMMAND_PARITY             0x040    /* Enable parity checking */
  29. #define  PCI_COMMAND_WAIT               0x080    /* Enable address/data stepping */
  30. #define  PCI_COMMAND_SERR               0x100    /* Enable SERR */
  31. #define  PCI_COMMAND_FAST_BACK          0x200    /* Enable back-to-back writes */
  32. #define  PCI_COMMAND_INTX_DISABLE       0x400    /* INTx Emulation Disable */
  33.  
  34. #define PCI_STATUS                      0x006    /* 16 bits */
  35. #define  PCI_STATUS_CAP_LIST            0x010    /* Support Capability List */
  36. #define  PCI_STATUS_66MHZ               0x020    /* Support 66 Mhz PCI 2.1 bus */
  37. #define  PCI_STATUS_UDF                 0x040    /* Support User Definable Features [obsolete] */
  38. #define  PCI_STATUS_FAST_BACK           0x080    /* Accept fast-back to back */
  39. #define  PCI_STATUS_PARITY              0x100    /* Detected parity error */
  40. #define  PCI_STATUS_DEVSEL_MASK         0x600    /* DEVSEL timing */
  41. #define  PCI_STATUS_DEVSEL_FAST         0x000
  42. #define  PCI_STATUS_DEVSEL_MEDIUM       0x200
  43. #define  PCI_STATUS_DEVSEL_SLOW         0x400
  44. #define  PCI_STATUS_SIG_TARGET_ABORT    0x800    /* Set on target abort */
  45. #define  PCI_STATUS_REC_TARGET_ABORT    0x1000   /* Master ack of " */
  46. #define  PCI_STATUS_REC_MASTER_ABORT    0x2000   /* Set on master abort */
  47. #define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000   /* Set when we drive SERR */
  48. #define  PCI_STATUS_DETECTED_PARITY     0x8000   /* Set on parity error */
  49.  
  50. #define PCI_CLASS_REVISION               0x08    /* High 24 bits are class, low 8 revision */
  51. #define PCI_REVISION_ID                  0x08    /* Revision ID */
  52. #define PCI_CLASS_PROG                   0x09    /* Reg. Level Programming Interface */
  53. #define PCI_CLASS_DEVICE                 0x0a    /* Device class */
  54.  
  55. #define PCI_CACHE_LINE_SIZE              0x0c    /* 8 bits */
  56. #define PCI_LATENCY_TIMER                0x0d    /* 8 bits */
  57. #define PCI_HEADER_TYPE                  0x0e    /* 8 bits */
  58. #define  PCI_HEADER_TYPE_NORMAL             0
  59. #define  PCI_HEADER_TYPE_BRIDGE             1
  60. #define  PCI_HEADER_TYPE_CARDBUS            2
  61.  
  62. #define PCI_BIST                         0x0f    /* 8 bits */
  63. #define  PCI_BIST_CODE_MASK              0x0f    /* Return result */
  64. #define  PCI_BIST_START                  0x40    /* 1 to start BIST, 2 secs or less */
  65. #define  PCI_BIST_CAPABLE                0x80    /* 1 if BIST capable */
  66.  
  67. #define PCI_CAPABILITY_LIST              0x34    /* Offset of first capability list entry */
  68. #define PCI_CB_CAPABILITY_LIST           0x14
  69. /* Capability lists */
  70.  
  71. #define PCI_CAP_LIST_ID                  0       /* Capability ID */
  72. #define  PCI_CAP_ID_PM                   0x01    /* Power Management */
  73. #define  PCI_CAP_ID_AGP                  0x02    /* Accelerated Graphics Port */
  74. #define  PCI_CAP_ID_VPD                  0x03    /* Vital Product Data */
  75. #define  PCI_CAP_ID_SLOTID               0x04    /* Slot Identification */
  76. #define  PCI_CAP_ID_MSI                  0x05    /* Message Signalled Interrupts */
  77. #define  PCI_CAP_ID_CHSWP                0x06    /* CompactPCI HotSwap */
  78. #define  PCI_CAP_ID_PCIX                 0x07    /* PCI-X */
  79. #define  PCI_CAP_ID_HT                   0x08    /* HyperTransport */
  80. #define  PCI_CAP_ID_VNDR                 0x09    /* Vendor specific capability */
  81. #define  PCI_CAP_ID_SHPC                 0x0C    /* PCI Standard Hot-Plug Controller */
  82. #define  PCI_CAP_ID_EXP                  0x10    /* PCI Express */
  83. #define  PCI_CAP_ID_MSIX                 0x11    /* MSI-X */
  84. #define PCI_CAP_LIST_NEXT                1       /* Next capability in the list */
  85. #define PCI_CAP_FLAGS                    2       /* Capability defined flags (16 bits) */
  86. #define PCI_CAP_SIZEOF                   4
  87.  
  88.  
  89. /* AGP registers */
  90.  
  91. #define PCI_AGP_VERSION                     2   /* BCD version number */
  92. #define PCI_AGP_RFU                         3   /* Rest of capability flags */
  93. #define PCI_AGP_STATUS                      4   /* Status register */
  94. #define  PCI_AGP_STATUS_RQ_MASK        0xff000000  /* Maximum number of requests - 1 */
  95. #define  PCI_AGP_STATUS_SBA            0x0200   /* Sideband addressing supported */
  96. #define  PCI_AGP_STATUS_64BIT          0x0020   /* 64-bit addressing supported */
  97. #define  PCI_AGP_STATUS_FW             0x0010   /* FW transfers supported */
  98. #define  PCI_AGP_STATUS_RATE4          0x0004   /* 4x transfer rate supported */
  99. #define  PCI_AGP_STATUS_RATE2          0x0002   /* 2x transfer rate supported */
  100. #define  PCI_AGP_STATUS_RATE1          0x0001   /* 1x transfer rate supported */
  101. #define PCI_AGP_COMMAND                     8   /* Control register */
  102. #define  PCI_AGP_COMMAND_RQ_MASK    0xff000000  /* Master: Maximum number of requests */
  103. #define  PCI_AGP_COMMAND_SBA           0x0200   /* Sideband addressing enabled */
  104. #define  PCI_AGP_COMMAND_AGP           0x0100   /* Allow processing of AGP transactions */
  105. #define  PCI_AGP_COMMAND_64BIT         0x0020   /* Allow processing of 64-bit addresses */
  106. #define  PCI_AGP_COMMAND_FW            0x0010   /* Force FW transfers */
  107. #define  PCI_AGP_COMMAND_RATE4         0x0004   /* Use 4x rate */
  108. #define  PCI_AGP_COMMAND_RATE2         0x0002   /* Use 2x rate */
  109. #define  PCI_AGP_COMMAND_RATE1         0x0001   /* Use 1x rate */
  110. #define PCI_AGP_SIZEOF                     12
  111.  
  112.  
  113. #define PCI_MAP_REG_START                   0x10
  114. #define PCI_MAP_REG_END                     0x28
  115. #define PCI_MAP_ROM_REG                     0x30
  116.  
  117. #define PCI_MAP_MEMORY                0x00000000
  118. #define PCI_MAP_IO                    0x00000001
  119.  
  120. #define PCI_MAP_MEMORY_TYPE           0x00000007
  121. #define PCI_MAP_IO_TYPE               0x00000003
  122.  
  123. #define PCI_MAP_MEMORY_TYPE_32BIT     0x00000000
  124. #define PCI_MAP_MEMORY_TYPE_32BIT_1M  0x00000002
  125. #define PCI_MAP_MEMORY_TYPE_64BIT     0x00000004
  126. #define PCI_MAP_MEMORY_TYPE_MASK      0x00000006
  127. #define PCI_MAP_MEMORY_CACHABLE       0x00000008
  128. #define PCI_MAP_MEMORY_ATTR_MASK      0x0000000e
  129. #define PCI_MAP_MEMORY_ADDRESS_MASK   0xfffffff0
  130.  
  131. #define PCI_MAP_IO_ATTR_MASK          0x00000003
  132.  
  133.  
  134.  
  135. #define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
  136. #define PCI_MAP_IS_MEM(b)       (!PCI_MAP_IS_IO(b))
  137.  
  138. #define PCI_MAP_IS64BITMEM(b)   \
  139.         (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
  140.  
  141. #define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
  142. #define PCIGETMEMORY64HIGH(b)   (*((CARD32*)&b + 1))
  143. #define PCIGETMEMORY64(b)       \
  144.         (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
  145.  
  146. #define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc
  147.  
  148. #define PCIGETIO(b)             ((b) & PCI_MAP_IO_ADDRESS_MASK)
  149.  
  150. #define PCI_MAP_ROM_DECODE_ENABLE     0x00000001
  151. #define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800
  152.  
  153. #define PCIGETROM(b)            ((b) & PCI_MAP_ROM_ADDRESS_MASK)
  154.  
  155.  
  156. #ifndef PCI_DOM_MASK
  157. # define PCI_DOM_MASK 0x0ffu
  158. #endif
  159. #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
  160.  
  161. #define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
  162.                               (((d) & 0x00001fu) << 11) | \
  163.                               (((f) & 0x000007u) << 8))
  164.  
  165. #define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
  166. #define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
  167. #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
  168. #define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
  169.  
  170.  
  171. #define PCI_CMD_STAT_REG        0x04
  172.  
  173.  
  174. typedef unsigned int PCITAG;
  175.  
  176. extern inline PCITAG
  177. pciTag(int busnum, int devnum, int funcnum)
  178. {
  179.         return(PCI_MAKE_TAG(busnum,devnum,funcnum));
  180. }
  181.  
  182. const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list);
  183. u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);
  184.