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  1. /*
  2.  * Copyright © 2007-2008 Intel Corporation
  3.  *   Jesse Barnes <jesse.barnes@intel.com>
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice shall be included in
  13.  * all copies or substantial portions of the Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21.  * OTHER DEALINGS IN THE SOFTWARE.
  22.  */
  23. #ifndef __DRM_EDID_H__
  24. #define __DRM_EDID_H__
  25.  
  26. #include <linux/types.h>
  27.  
  28. #define EDID_LENGTH 128
  29. #define DDC_ADDR 0x50
  30.  
  31. #define CEA_EXT     0x02
  32. #define VTB_EXT     0x10
  33. #define DI_EXT      0x40
  34. #define LS_EXT      0x50
  35. #define MI_EXT      0x60
  36.  
  37. struct est_timings {
  38.         u8 t1;
  39.         u8 t2;
  40.         u8 mfg_rsvd;
  41. } __attribute__((packed));
  42.  
  43. /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
  44. #define EDID_TIMING_ASPECT_SHIFT 6
  45. #define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)
  46.  
  47. /* need to add 60 */
  48. #define EDID_TIMING_VFREQ_SHIFT  0
  49. #define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)
  50.  
  51. struct std_timing {
  52.         u8 hsize; /* need to multiply by 8 then add 248 */
  53.         u8 vfreq_aspect;
  54. } __attribute__((packed));
  55.  
  56. #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
  57. #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
  58. #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
  59. #define DRM_EDID_PT_STEREO         (1 << 5)
  60. #define DRM_EDID_PT_INTERLACED     (1 << 7)
  61.  
  62. /* If detailed data is pixel timing */
  63. struct detailed_pixel_timing {
  64.         u8 hactive_lo;
  65.         u8 hblank_lo;
  66.         u8 hactive_hblank_hi;
  67.         u8 vactive_lo;
  68.         u8 vblank_lo;
  69.         u8 vactive_vblank_hi;
  70.         u8 hsync_offset_lo;
  71.         u8 hsync_pulse_width_lo;
  72.         u8 vsync_offset_pulse_width_lo;
  73.         u8 hsync_vsync_offset_pulse_width_hi;
  74.         u8 width_mm_lo;
  75.         u8 height_mm_lo;
  76.         u8 width_height_mm_hi;
  77.         u8 hborder;
  78.         u8 vborder;
  79.         u8 misc;
  80. } __attribute__((packed));
  81.  
  82. /* If it's not pixel timing, it'll be one of the below */
  83. struct detailed_data_string {
  84.         u8 str[13];
  85. } __attribute__((packed));
  86.  
  87. struct detailed_data_monitor_range {
  88.         u8 min_vfreq;
  89.         u8 max_vfreq;
  90.         u8 min_hfreq_khz;
  91.         u8 max_hfreq_khz;
  92.         u8 pixel_clock_mhz; /* need to multiply by 10 */
  93.         __le16 sec_gtf_toggle; /* A000=use above, 20=use below */
  94.         u8 hfreq_start_khz; /* need to multiply by 2 */
  95.         u8 c; /* need to divide by 2 */
  96.         __le16 m;
  97.         u8 k;
  98.         u8 j; /* need to divide by 2 */
  99. } __attribute__((packed));
  100.  
  101. struct detailed_data_wpindex {
  102.         u8 white_yx_lo; /* Lower 2 bits each */
  103.         u8 white_x_hi;
  104.         u8 white_y_hi;
  105.         u8 gamma; /* need to divide by 100 then add 1 */
  106. } __attribute__((packed));
  107.  
  108. struct detailed_data_color_point {
  109.         u8 windex1;
  110.         u8 wpindex1[3];
  111.         u8 windex2;
  112.         u8 wpindex2[3];
  113. } __attribute__((packed));
  114.  
  115. struct cvt_timing {
  116.         u8 code[3];
  117. } __attribute__((packed));
  118.  
  119. struct detailed_non_pixel {
  120.         u8 pad1;
  121.         u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
  122.                     fb=color point data, fa=standard timing data,
  123.                     f9=undefined, f8=mfg. reserved */
  124.         u8 pad2;
  125.         union {
  126.                 struct detailed_data_string str;
  127.                 struct detailed_data_monitor_range range;
  128.                 struct detailed_data_wpindex color;
  129.                 struct std_timing timings[6];
  130.                 struct cvt_timing cvt[4];
  131.         } data;
  132. } __attribute__((packed));
  133.  
  134. #define EDID_DETAIL_EST_TIMINGS 0xf7
  135. #define EDID_DETAIL_CVT_3BYTE 0xf8
  136. #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
  137. #define EDID_DETAIL_STD_MODES 0xfa
  138. #define EDID_DETAIL_MONITOR_CPDATA 0xfb
  139. #define EDID_DETAIL_MONITOR_NAME 0xfc
  140. #define EDID_DETAIL_MONITOR_RANGE 0xfd
  141. #define EDID_DETAIL_MONITOR_STRING 0xfe
  142. #define EDID_DETAIL_MONITOR_SERIAL 0xff
  143.  
  144. struct detailed_timing {
  145.         __le16 pixel_clock; /* need to multiply by 10 KHz */
  146.         union {
  147.                 struct detailed_pixel_timing pixel_data;
  148.                 struct detailed_non_pixel other_data;
  149.         } data;
  150. } __attribute__((packed));
  151.  
  152. #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
  153. #define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
  154. #define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
  155. #define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
  156. #define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
  157. #define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
  158. #define DRM_EDID_INPUT_DIGITAL         (1 << 7)
  159. #define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4)
  160. #define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4)
  161. #define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4)
  162. #define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4)
  163. #define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4)
  164. #define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4)
  165. #define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4)
  166. #define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4)
  167. #define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4)
  168. #define DRM_EDID_DIGITAL_TYPE_UNDEF    (0)
  169. #define DRM_EDID_DIGITAL_TYPE_DVI      (1)
  170. #define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2)
  171. #define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3)
  172. #define DRM_EDID_DIGITAL_TYPE_MDDI     (4)
  173. #define DRM_EDID_DIGITAL_TYPE_DP       (5)
  174.  
  175. #define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
  176. #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
  177. #define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
  178. /* If analog */
  179. #define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
  180. /* If digital */
  181. #define DRM_EDID_FEATURE_COLOR_MASK       (3 << 3)
  182. #define DRM_EDID_FEATURE_RGB              (0 << 3)
  183. #define DRM_EDID_FEATURE_RGB_YCRCB444     (1 << 3)
  184. #define DRM_EDID_FEATURE_RGB_YCRCB422     (2 << 3)
  185. #define DRM_EDID_FEATURE_RGB_YCRCB        (3 << 3) /* both 4:4:4 and 4:2:2 */
  186.  
  187. #define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
  188. #define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
  189. #define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
  190.  
  191. struct edid {
  192.         u8 header[8];
  193.         /* Vendor & product info */
  194.         u8 mfg_id[2];
  195.         u8 prod_code[2];
  196.         u32 serial; /* FIXME: byte order */
  197.         u8 mfg_week;
  198.         u8 mfg_year;
  199.         /* EDID version */
  200.         u8 version;
  201.         u8 revision;
  202.         /* Display info: */
  203.         u8 input;
  204.         u8 width_cm;
  205.         u8 height_cm;
  206.         u8 gamma;
  207.         u8 features;
  208.         /* Color characteristics */
  209.         u8 red_green_lo;
  210.         u8 black_white_lo;
  211.         u8 red_x;
  212.         u8 red_y;
  213.         u8 green_x;
  214.         u8 green_y;
  215.         u8 blue_x;
  216.         u8 blue_y;
  217.         u8 white_x;
  218.         u8 white_y;
  219.         /* Est. timings and mfg rsvd timings*/
  220.         struct est_timings established_timings;
  221.         /* Standard timings 1-8*/
  222.         struct std_timing standard_timings[8];
  223.         /* Detailing timings 1-4 */
  224.         struct detailed_timing detailed_timings[4];
  225.         /* Number of 128 byte ext. blocks */
  226.         u8 extensions;
  227.         /* Checksum */
  228.         u8 checksum;
  229. } __attribute__((packed));
  230.  
  231. #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
  232.  
  233. struct drm_encoder;
  234. struct drm_connector;
  235. struct drm_display_mode;
  236. void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
  237. int drm_av_sync_delay(struct drm_connector *connector,
  238.                       struct drm_display_mode *mode);
  239. struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
  240.                                      struct drm_display_mode *mode);
  241.  
  242. #endif /* __DRM_EDID_H__ */
  243.