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  1. /*
  2.  * Copyright © 2008 Keith Packard
  3.  *
  4.  * Permission to use, copy, modify, distribute, and sell this software and its
  5.  * documentation for any purpose is hereby granted without fee, provided that
  6.  * the above copyright notice appear in all copies and that both that copyright
  7.  * notice and this permission notice appear in supporting documentation, and
  8.  * that the name of the copyright holders not be used in advertising or
  9.  * publicity pertaining to distribution of the software without specific,
  10.  * written prior permission.  The copyright holders make no representations
  11.  * about the suitability of this software for any purpose.  It is provided "as
  12.  * is" without express or implied warranty.
  13.  *
  14.  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15.  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16.  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17.  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18.  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19.  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20.  * OF THIS SOFTWARE.
  21.  */
  22.  
  23. #ifndef _DRM_DP_HELPER_H_
  24. #define _DRM_DP_HELPER_H_
  25.  
  26. /* From the VESA DisplayPort spec */
  27.  
  28. #define AUX_NATIVE_WRITE        0x8
  29. #define AUX_NATIVE_READ         0x9
  30. #define AUX_I2C_WRITE           0x0
  31. #define AUX_I2C_READ            0x1
  32. #define AUX_I2C_STATUS          0x2
  33. #define AUX_I2C_MOT             0x4
  34.  
  35. #define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
  36. #define AUX_NATIVE_REPLY_NACK   (0x1 << 4)
  37. #define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
  38. #define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
  39.  
  40. #define AUX_I2C_REPLY_ACK       (0x0 << 6)
  41. #define AUX_I2C_REPLY_NACK      (0x1 << 6)
  42. #define AUX_I2C_REPLY_DEFER     (0x2 << 6)
  43. #define AUX_I2C_REPLY_MASK      (0x3 << 6)
  44.  
  45. /* AUX CH addresses */
  46. /* DPCD */
  47. #define DP_DPCD_REV                         0x000
  48.  
  49. #define DP_MAX_LINK_RATE                    0x001
  50.  
  51. #define DP_MAX_LANE_COUNT                   0x002
  52. # define DP_MAX_LANE_COUNT_MASK             0x1f
  53. # define DP_ENHANCED_FRAME_CAP              (1 << 7)
  54.  
  55. #define DP_MAX_DOWNSPREAD                   0x003
  56. # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
  57.  
  58. #define DP_NORP                             0x004
  59.  
  60. #define DP_DOWNSTREAMPORT_PRESENT           0x005
  61. # define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
  62. # define DP_DWN_STRM_PORT_TYPE_MASK         0x06
  63. /* 00b = DisplayPort */
  64. /* 01b = Analog */
  65. /* 10b = TMDS or HDMI */
  66. /* 11b = Other */
  67. # define DP_FORMAT_CONVERSION               (1 << 3)
  68.  
  69. #define DP_MAIN_LINK_CHANNEL_CODING         0x006
  70.  
  71. /* link configuration */
  72. #define DP_LINK_BW_SET                      0x100
  73. # define DP_LINK_BW_1_62                    0x06
  74. # define DP_LINK_BW_2_7                     0x0a
  75.  
  76. #define DP_LANE_COUNT_SET                   0x101
  77. # define DP_LANE_COUNT_MASK                 0x0f
  78. # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
  79.  
  80. #define DP_TRAINING_PATTERN_SET             0x102
  81. # define DP_TRAINING_PATTERN_DISABLE        0
  82. # define DP_TRAINING_PATTERN_1              1
  83. # define DP_TRAINING_PATTERN_2              2
  84. # define DP_TRAINING_PATTERN_MASK           0x3
  85.  
  86. # define DP_LINK_QUAL_PATTERN_DISABLE       (0 << 2)
  87. # define DP_LINK_QUAL_PATTERN_D10_2         (1 << 2)
  88. # define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
  89. # define DP_LINK_QUAL_PATTERN_PRBS7         (3 << 2)
  90. # define DP_LINK_QUAL_PATTERN_MASK          (3 << 2)
  91.  
  92. # define DP_RECOVERED_CLOCK_OUT_EN          (1 << 4)
  93. # define DP_LINK_SCRAMBLING_DISABLE         (1 << 5)
  94.  
  95. # define DP_SYMBOL_ERROR_COUNT_BOTH         (0 << 6)
  96. # define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
  97. # define DP_SYMBOL_ERROR_COUNT_SYMBOL       (2 << 6)
  98. # define DP_SYMBOL_ERROR_COUNT_MASK         (3 << 6)
  99.  
  100. #define DP_TRAINING_LANE0_SET               0x103
  101. #define DP_TRAINING_LANE1_SET               0x104
  102. #define DP_TRAINING_LANE2_SET               0x105
  103. #define DP_TRAINING_LANE3_SET               0x106
  104.  
  105. # define DP_TRAIN_VOLTAGE_SWING_MASK        0x3
  106. # define DP_TRAIN_VOLTAGE_SWING_SHIFT       0
  107. # define DP_TRAIN_MAX_SWING_REACHED         (1 << 2)
  108. # define DP_TRAIN_VOLTAGE_SWING_400         (0 << 0)
  109. # define DP_TRAIN_VOLTAGE_SWING_600         (1 << 0)
  110. # define DP_TRAIN_VOLTAGE_SWING_800         (2 << 0)
  111. # define DP_TRAIN_VOLTAGE_SWING_1200        (3 << 0)
  112.  
  113. # define DP_TRAIN_PRE_EMPHASIS_MASK         (3 << 3)
  114. # define DP_TRAIN_PRE_EMPHASIS_0            (0 << 3)
  115. # define DP_TRAIN_PRE_EMPHASIS_3_5          (1 << 3)
  116. # define DP_TRAIN_PRE_EMPHASIS_6            (2 << 3)
  117. # define DP_TRAIN_PRE_EMPHASIS_9_5          (3 << 3)
  118.  
  119. # define DP_TRAIN_PRE_EMPHASIS_SHIFT        3
  120. # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
  121.  
  122. #define DP_DOWNSPREAD_CTRL                  0x107
  123. # define DP_SPREAD_AMP_0_5                  (1 << 4)
  124.  
  125. #define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
  126. # define DP_SET_ANSI_8B10B                  (1 << 0)
  127.  
  128. #define DP_LANE0_1_STATUS                   0x202
  129. #define DP_LANE2_3_STATUS                   0x203
  130. # define DP_LANE_CR_DONE                    (1 << 0)
  131. # define DP_LANE_CHANNEL_EQ_DONE            (1 << 1)
  132. # define DP_LANE_SYMBOL_LOCKED              (1 << 2)
  133.  
  134. #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |           \
  135.                             DP_LANE_CHANNEL_EQ_DONE |   \
  136.                             DP_LANE_SYMBOL_LOCKED)
  137.  
  138. #define DP_LANE_ALIGN_STATUS_UPDATED        0x204
  139.  
  140. #define DP_INTERLANE_ALIGN_DONE             (1 << 0)
  141. #define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
  142. #define DP_LINK_STATUS_UPDATED              (1 << 7)
  143.  
  144. #define DP_SINK_STATUS                      0x205
  145.  
  146. #define DP_RECEIVE_PORT_0_STATUS            (1 << 0)
  147. #define DP_RECEIVE_PORT_1_STATUS            (1 << 1)
  148.  
  149. #define DP_ADJUST_REQUEST_LANE0_1           0x206
  150. #define DP_ADJUST_REQUEST_LANE2_3           0x207
  151. # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
  152. # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
  153. # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
  154. # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
  155. # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
  156. # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
  157. # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
  158. # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
  159.  
  160. #define DP_SET_POWER                        0x600
  161. # define DP_SET_POWER_D0                    0x1
  162. # define DP_SET_POWER_D3                    0x2
  163.  
  164. #define MODE_I2C_START  1
  165. #define MODE_I2C_WRITE  2
  166. #define MODE_I2C_READ   4
  167. #define MODE_I2C_STOP   8
  168.  
  169. struct i2c_algo_dp_aux_data {
  170.         bool running;
  171.         u16 address;
  172.         int (*aux_ch) (struct i2c_adapter *adapter,
  173.                        int mode, uint8_t write_byte,
  174.                        uint8_t *read_byte);
  175. };
  176.  
  177. int
  178. i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
  179.  
  180. #endif /* _DRM_DP_HELPER_H_ */
  181.