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  1. #ifndef _ASM_X86_MSR_INDEX_H
  2. #define _ASM_X86_MSR_INDEX_H
  3.  
  4. /*
  5.  * CPU model specific register (MSR) numbers.
  6.  *
  7.  * Do not add new entries to this file unless the definitions are shared
  8.  * between multiple compilation units.
  9.  */
  10.  
  11. /* x86-64 specific MSRs */
  12. #define MSR_EFER                0xc0000080 /* extended feature register */
  13. #define MSR_STAR                0xc0000081 /* legacy mode SYSCALL target */
  14. #define MSR_LSTAR               0xc0000082 /* long mode SYSCALL target */
  15. #define MSR_CSTAR               0xc0000083 /* compat mode SYSCALL target */
  16. #define MSR_SYSCALL_MASK        0xc0000084 /* EFLAGS mask for syscall */
  17. #define MSR_FS_BASE             0xc0000100 /* 64bit FS base */
  18. #define MSR_GS_BASE             0xc0000101 /* 64bit GS base */
  19. #define MSR_KERNEL_GS_BASE      0xc0000102 /* SwapGS GS shadow */
  20. #define MSR_TSC_AUX             0xc0000103 /* Auxiliary TSC */
  21.  
  22. /* EFER bits: */
  23. #define _EFER_SCE               0  /* SYSCALL/SYSRET */
  24. #define _EFER_LME               8  /* Long mode enable */
  25. #define _EFER_LMA               10 /* Long mode active (read-only) */
  26. #define _EFER_NX                11 /* No execute enable */
  27. #define _EFER_SVME              12 /* Enable virtualization */
  28. #define _EFER_LMSLE             13 /* Long Mode Segment Limit Enable */
  29. #define _EFER_FFXSR             14 /* Enable Fast FXSAVE/FXRSTOR */
  30.  
  31. #define EFER_SCE                (1<<_EFER_SCE)
  32. #define EFER_LME                (1<<_EFER_LME)
  33. #define EFER_LMA                (1<<_EFER_LMA)
  34. #define EFER_NX                 (1<<_EFER_NX)
  35. #define EFER_SVME               (1<<_EFER_SVME)
  36. #define EFER_LMSLE              (1<<_EFER_LMSLE)
  37. #define EFER_FFXSR              (1<<_EFER_FFXSR)
  38.  
  39. /* Intel MSRs. Some also available on other CPUs */
  40. #define MSR_IA32_PERFCTR0               0x000000c1
  41. #define MSR_IA32_PERFCTR1               0x000000c2
  42. #define MSR_FSB_FREQ                    0x000000cd
  43. #define MSR_PLATFORM_INFO               0x000000ce
  44.  
  45. #define MSR_NHM_SNB_PKG_CST_CFG_CTL     0x000000e2
  46. #define NHM_C3_AUTO_DEMOTE              (1UL << 25)
  47. #define NHM_C1_AUTO_DEMOTE              (1UL << 26)
  48. #define ATM_LNC_C6_AUTO_DEMOTE          (1UL << 25)
  49. #define SNB_C1_AUTO_UNDEMOTE            (1UL << 27)
  50. #define SNB_C3_AUTO_UNDEMOTE            (1UL << 28)
  51.  
  52. #define MSR_MTRRcap                     0x000000fe
  53. #define MSR_IA32_BBL_CR_CTL             0x00000119
  54. #define MSR_IA32_BBL_CR_CTL3            0x0000011e
  55.  
  56. #define MSR_IA32_SYSENTER_CS            0x00000174
  57. #define MSR_IA32_SYSENTER_ESP           0x00000175
  58. #define MSR_IA32_SYSENTER_EIP           0x00000176
  59.  
  60. #define MSR_IA32_MCG_CAP                0x00000179
  61. #define MSR_IA32_MCG_STATUS             0x0000017a
  62. #define MSR_IA32_MCG_CTL                0x0000017b
  63. #define MSR_IA32_MCG_EXT_CTL            0x000004d0
  64.  
  65. #define MSR_OFFCORE_RSP_0               0x000001a6
  66. #define MSR_OFFCORE_RSP_1               0x000001a7
  67. #define MSR_NHM_TURBO_RATIO_LIMIT       0x000001ad
  68. #define MSR_IVT_TURBO_RATIO_LIMIT       0x000001ae
  69. #define MSR_TURBO_RATIO_LIMIT           0x000001ad
  70. #define MSR_TURBO_RATIO_LIMIT1          0x000001ae
  71. #define MSR_TURBO_RATIO_LIMIT2          0x000001af
  72.  
  73. #define MSR_LBR_SELECT                  0x000001c8
  74. #define MSR_LBR_TOS                     0x000001c9
  75. #define MSR_LBR_NHM_FROM                0x00000680
  76. #define MSR_LBR_NHM_TO                  0x000006c0
  77. #define MSR_LBR_CORE_FROM               0x00000040
  78. #define MSR_LBR_CORE_TO                 0x00000060
  79.  
  80. #define MSR_LBR_INFO_0                  0x00000dc0 /* ... 0xddf for _31 */
  81. #define LBR_INFO_MISPRED                BIT_ULL(63)
  82. #define LBR_INFO_IN_TX                  BIT_ULL(62)
  83. #define LBR_INFO_ABORT                  BIT_ULL(61)
  84. #define LBR_INFO_CYCLES                 0xffff
  85.  
  86. #define MSR_IA32_PEBS_ENABLE            0x000003f1
  87. #define MSR_IA32_DS_AREA                0x00000600
  88. #define MSR_IA32_PERF_CAPABILITIES      0x00000345
  89. #define MSR_PEBS_LD_LAT_THRESHOLD       0x000003f6
  90.  
  91. #define MSR_IA32_RTIT_CTL               0x00000570
  92. #define RTIT_CTL_TRACEEN                BIT(0)
  93. #define RTIT_CTL_CYCLEACC               BIT(1)
  94. #define RTIT_CTL_OS                     BIT(2)
  95. #define RTIT_CTL_USR                    BIT(3)
  96. #define RTIT_CTL_CR3EN                  BIT(7)
  97. #define RTIT_CTL_TOPA                   BIT(8)
  98. #define RTIT_CTL_MTC_EN                 BIT(9)
  99. #define RTIT_CTL_TSC_EN                 BIT(10)
  100. #define RTIT_CTL_DISRETC                BIT(11)
  101. #define RTIT_CTL_BRANCH_EN              BIT(13)
  102. #define RTIT_CTL_MTC_RANGE_OFFSET       14
  103. #define RTIT_CTL_MTC_RANGE              (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
  104. #define RTIT_CTL_CYC_THRESH_OFFSET      19
  105. #define RTIT_CTL_CYC_THRESH             (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
  106. #define RTIT_CTL_PSB_FREQ_OFFSET        24
  107. #define RTIT_CTL_PSB_FREQ               (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
  108. #define MSR_IA32_RTIT_STATUS            0x00000571
  109. #define RTIT_STATUS_CONTEXTEN           BIT(1)
  110. #define RTIT_STATUS_TRIGGEREN           BIT(2)
  111. #define RTIT_STATUS_ERROR               BIT(4)
  112. #define RTIT_STATUS_STOPPED             BIT(5)
  113. #define MSR_IA32_RTIT_CR3_MATCH         0x00000572
  114. #define MSR_IA32_RTIT_OUTPUT_BASE       0x00000560
  115. #define MSR_IA32_RTIT_OUTPUT_MASK       0x00000561
  116.  
  117. #define MSR_MTRRfix64K_00000            0x00000250
  118. #define MSR_MTRRfix16K_80000            0x00000258
  119. #define MSR_MTRRfix16K_A0000            0x00000259
  120. #define MSR_MTRRfix4K_C0000             0x00000268
  121. #define MSR_MTRRfix4K_C8000             0x00000269
  122. #define MSR_MTRRfix4K_D0000             0x0000026a
  123. #define MSR_MTRRfix4K_D8000             0x0000026b
  124. #define MSR_MTRRfix4K_E0000             0x0000026c
  125. #define MSR_MTRRfix4K_E8000             0x0000026d
  126. #define MSR_MTRRfix4K_F0000             0x0000026e
  127. #define MSR_MTRRfix4K_F8000             0x0000026f
  128. #define MSR_MTRRdefType                 0x000002ff
  129.  
  130. #define MSR_IA32_CR_PAT                 0x00000277
  131.  
  132. #define MSR_IA32_DEBUGCTLMSR            0x000001d9
  133. #define MSR_IA32_LASTBRANCHFROMIP       0x000001db
  134. #define MSR_IA32_LASTBRANCHTOIP         0x000001dc
  135. #define MSR_IA32_LASTINTFROMIP          0x000001dd
  136. #define MSR_IA32_LASTINTTOIP            0x000001de
  137.  
  138. /* DEBUGCTLMSR bits (others vary by model): */
  139. #define DEBUGCTLMSR_LBR                 (1UL <<  0) /* last branch recording */
  140. #define DEBUGCTLMSR_BTF                 (1UL <<  1) /* single-step on branches */
  141. #define DEBUGCTLMSR_TR                  (1UL <<  6)
  142. #define DEBUGCTLMSR_BTS                 (1UL <<  7)
  143. #define DEBUGCTLMSR_BTINT               (1UL <<  8)
  144. #define DEBUGCTLMSR_BTS_OFF_OS          (1UL <<  9)
  145. #define DEBUGCTLMSR_BTS_OFF_USR         (1UL << 10)
  146. #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI  (1UL << 11)
  147.  
  148. #define MSR_PEBS_FRONTEND               0x000003f7
  149.  
  150. #define MSR_IA32_POWER_CTL              0x000001fc
  151.  
  152. #define MSR_IA32_MC0_CTL                0x00000400
  153. #define MSR_IA32_MC0_STATUS             0x00000401
  154. #define MSR_IA32_MC0_ADDR               0x00000402
  155. #define MSR_IA32_MC0_MISC               0x00000403
  156.  
  157. /* C-state Residency Counters */
  158. #define MSR_PKG_C3_RESIDENCY            0x000003f8
  159. #define MSR_PKG_C6_RESIDENCY            0x000003f9
  160. #define MSR_PKG_C7_RESIDENCY            0x000003fa
  161. #define MSR_CORE_C3_RESIDENCY           0x000003fc
  162. #define MSR_CORE_C6_RESIDENCY           0x000003fd
  163. #define MSR_CORE_C7_RESIDENCY           0x000003fe
  164. #define MSR_KNL_CORE_C6_RESIDENCY       0x000003ff
  165. #define MSR_PKG_C2_RESIDENCY            0x0000060d
  166. #define MSR_PKG_C8_RESIDENCY            0x00000630
  167. #define MSR_PKG_C9_RESIDENCY            0x00000631
  168. #define MSR_PKG_C10_RESIDENCY           0x00000632
  169.  
  170. /* Interrupt Response Limit */
  171. #define MSR_PKGC3_IRTL                  0x0000060a
  172. #define MSR_PKGC6_IRTL                  0x0000060b
  173. #define MSR_PKGC7_IRTL                  0x0000060c
  174. #define MSR_PKGC8_IRTL                  0x00000633
  175. #define MSR_PKGC9_IRTL                  0x00000634
  176. #define MSR_PKGC10_IRTL                 0x00000635
  177.  
  178. /* Run Time Average Power Limiting (RAPL) Interface */
  179.  
  180. #define MSR_RAPL_POWER_UNIT             0x00000606
  181.  
  182. #define MSR_PKG_POWER_LIMIT             0x00000610
  183. #define MSR_PKG_ENERGY_STATUS           0x00000611
  184. #define MSR_PKG_PERF_STATUS             0x00000613
  185. #define MSR_PKG_POWER_INFO              0x00000614
  186.  
  187. #define MSR_DRAM_POWER_LIMIT            0x00000618
  188. #define MSR_DRAM_ENERGY_STATUS          0x00000619
  189. #define MSR_DRAM_PERF_STATUS            0x0000061b
  190. #define MSR_DRAM_POWER_INFO             0x0000061c
  191.  
  192. #define MSR_PP0_POWER_LIMIT             0x00000638
  193. #define MSR_PP0_ENERGY_STATUS           0x00000639
  194. #define MSR_PP0_POLICY                  0x0000063a
  195. #define MSR_PP0_PERF_STATUS             0x0000063b
  196.  
  197. #define MSR_PP1_POWER_LIMIT             0x00000640
  198. #define MSR_PP1_ENERGY_STATUS           0x00000641
  199. #define MSR_PP1_POLICY                  0x00000642
  200.  
  201. /* Config TDP MSRs */
  202. #define MSR_CONFIG_TDP_NOMINAL          0x00000648
  203. #define MSR_CONFIG_TDP_LEVEL_1          0x00000649
  204. #define MSR_CONFIG_TDP_LEVEL_2          0x0000064A
  205. #define MSR_CONFIG_TDP_CONTROL          0x0000064B
  206. #define MSR_TURBO_ACTIVATION_RATIO      0x0000064C
  207.  
  208. #define MSR_PKG_WEIGHTED_CORE_C0_RES    0x00000658
  209. #define MSR_PKG_ANY_CORE_C0_RES         0x00000659
  210. #define MSR_PKG_ANY_GFXE_C0_RES         0x0000065A
  211. #define MSR_PKG_BOTH_CORE_GFXE_C0_RES   0x0000065B
  212.  
  213. #define MSR_CORE_C1_RES                 0x00000660
  214.  
  215. #define MSR_CC6_DEMOTION_POLICY_CONFIG  0x00000668
  216. #define MSR_MC6_DEMOTION_POLICY_CONFIG  0x00000669
  217.  
  218. #define MSR_CORE_PERF_LIMIT_REASONS     0x00000690
  219. #define MSR_GFX_PERF_LIMIT_REASONS      0x000006B0
  220. #define MSR_RING_PERF_LIMIT_REASONS     0x000006B1
  221.  
  222. /* Hardware P state interface */
  223. #define MSR_PPERF                       0x0000064e
  224. #define MSR_PERF_LIMIT_REASONS          0x0000064f
  225. #define MSR_PM_ENABLE                   0x00000770
  226. #define MSR_HWP_CAPABILITIES            0x00000771
  227. #define MSR_HWP_REQUEST_PKG             0x00000772
  228. #define MSR_HWP_INTERRUPT               0x00000773
  229. #define MSR_HWP_REQUEST                 0x00000774
  230. #define MSR_HWP_STATUS                  0x00000777
  231.  
  232. /* CPUID.6.EAX */
  233. #define HWP_BASE_BIT                    (1<<7)
  234. #define HWP_NOTIFICATIONS_BIT           (1<<8)
  235. #define HWP_ACTIVITY_WINDOW_BIT         (1<<9)
  236. #define HWP_ENERGY_PERF_PREFERENCE_BIT  (1<<10)
  237. #define HWP_PACKAGE_LEVEL_REQUEST_BIT   (1<<11)
  238.  
  239. /* IA32_HWP_CAPABILITIES */
  240. #define HWP_HIGHEST_PERF(x)             (((x) >> 0) & 0xff)
  241. #define HWP_GUARANTEED_PERF(x)          (((x) >> 8) & 0xff)
  242. #define HWP_MOSTEFFICIENT_PERF(x)       (((x) >> 16) & 0xff)
  243. #define HWP_LOWEST_PERF(x)              (((x) >> 24) & 0xff)
  244.  
  245. /* IA32_HWP_REQUEST */
  246. #define HWP_MIN_PERF(x)                 (x & 0xff)
  247. #define HWP_MAX_PERF(x)                 ((x & 0xff) << 8)
  248. #define HWP_DESIRED_PERF(x)             ((x & 0xff) << 16)
  249. #define HWP_ENERGY_PERF_PREFERENCE(x)   ((x & 0xff) << 24)
  250. #define HWP_ACTIVITY_WINDOW(x)          ((x & 0xff3) << 32)
  251. #define HWP_PACKAGE_CONTROL(x)          ((x & 0x1) << 42)
  252.  
  253. /* IA32_HWP_STATUS */
  254. #define HWP_GUARANTEED_CHANGE(x)        (x & 0x1)
  255. #define HWP_EXCURSION_TO_MINIMUM(x)     (x & 0x4)
  256.  
  257. /* IA32_HWP_INTERRUPT */
  258. #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
  259. #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
  260.  
  261. #define MSR_AMD64_MC0_MASK              0xc0010044
  262.  
  263. #define MSR_IA32_MCx_CTL(x)             (MSR_IA32_MC0_CTL + 4*(x))
  264. #define MSR_IA32_MCx_STATUS(x)          (MSR_IA32_MC0_STATUS + 4*(x))
  265. #define MSR_IA32_MCx_ADDR(x)            (MSR_IA32_MC0_ADDR + 4*(x))
  266. #define MSR_IA32_MCx_MISC(x)            (MSR_IA32_MC0_MISC + 4*(x))
  267.  
  268. #define MSR_AMD64_MCx_MASK(x)           (MSR_AMD64_MC0_MASK + (x))
  269.  
  270. /* These are consecutive and not in the normal 4er MCE bank block */
  271. #define MSR_IA32_MC0_CTL2               0x00000280
  272. #define MSR_IA32_MCx_CTL2(x)            (MSR_IA32_MC0_CTL2 + (x))
  273.  
  274. #define MSR_P6_PERFCTR0                 0x000000c1
  275. #define MSR_P6_PERFCTR1                 0x000000c2
  276. #define MSR_P6_EVNTSEL0                 0x00000186
  277. #define MSR_P6_EVNTSEL1                 0x00000187
  278.  
  279. #define MSR_KNC_PERFCTR0               0x00000020
  280. #define MSR_KNC_PERFCTR1               0x00000021
  281. #define MSR_KNC_EVNTSEL0               0x00000028
  282. #define MSR_KNC_EVNTSEL1               0x00000029
  283.  
  284. /* Alternative perfctr range with full access. */
  285. #define MSR_IA32_PMC0                   0x000004c1
  286.  
  287. /* AMD64 MSRs. Not complete. See the architecture manual for a more
  288.    complete list. */
  289.  
  290. #define MSR_AMD64_PATCH_LEVEL           0x0000008b
  291. #define MSR_AMD64_TSC_RATIO             0xc0000104
  292. #define MSR_AMD64_NB_CFG                0xc001001f
  293. #define MSR_AMD64_PATCH_LOADER          0xc0010020
  294. #define MSR_AMD64_OSVW_ID_LENGTH        0xc0010140
  295. #define MSR_AMD64_OSVW_STATUS           0xc0010141
  296. #define MSR_AMD64_LS_CFG                0xc0011020
  297. #define MSR_AMD64_DC_CFG                0xc0011022
  298. #define MSR_AMD64_BU_CFG2               0xc001102a
  299. #define MSR_AMD64_IBSFETCHCTL           0xc0011030
  300. #define MSR_AMD64_IBSFETCHLINAD         0xc0011031
  301. #define MSR_AMD64_IBSFETCHPHYSAD        0xc0011032
  302. #define MSR_AMD64_IBSFETCH_REG_COUNT    3
  303. #define MSR_AMD64_IBSFETCH_REG_MASK     ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
  304. #define MSR_AMD64_IBSOPCTL              0xc0011033
  305. #define MSR_AMD64_IBSOPRIP              0xc0011034
  306. #define MSR_AMD64_IBSOPDATA             0xc0011035
  307. #define MSR_AMD64_IBSOPDATA2            0xc0011036
  308. #define MSR_AMD64_IBSOPDATA3            0xc0011037
  309. #define MSR_AMD64_IBSDCLINAD            0xc0011038
  310. #define MSR_AMD64_IBSDCPHYSAD           0xc0011039
  311. #define MSR_AMD64_IBSOP_REG_COUNT       7
  312. #define MSR_AMD64_IBSOP_REG_MASK        ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
  313. #define MSR_AMD64_IBSCTL                0xc001103a
  314. #define MSR_AMD64_IBSBRTARGET           0xc001103b
  315. #define MSR_AMD64_IBSOPDATA4            0xc001103d
  316. #define MSR_AMD64_IBS_REG_COUNT_MAX     8 /* includes MSR_AMD64_IBSBRTARGET */
  317.  
  318. /* Fam 16h MSRs */
  319. #define MSR_F16H_L2I_PERF_CTL           0xc0010230
  320. #define MSR_F16H_L2I_PERF_CTR           0xc0010231
  321. #define MSR_F16H_DR1_ADDR_MASK          0xc0011019
  322. #define MSR_F16H_DR2_ADDR_MASK          0xc001101a
  323. #define MSR_F16H_DR3_ADDR_MASK          0xc001101b
  324. #define MSR_F16H_DR0_ADDR_MASK          0xc0011027
  325.  
  326. /* Fam 15h MSRs */
  327. #define MSR_F15H_PERF_CTL               0xc0010200
  328. #define MSR_F15H_PERF_CTR               0xc0010201
  329. #define MSR_F15H_NB_PERF_CTL            0xc0010240
  330. #define MSR_F15H_NB_PERF_CTR            0xc0010241
  331. #define MSR_F15H_IC_CFG                 0xc0011021
  332.  
  333. /* Fam 10h MSRs */
  334. #define MSR_FAM10H_MMIO_CONF_BASE       0xc0010058
  335. #define FAM10H_MMIO_CONF_ENABLE         (1<<0)
  336. #define FAM10H_MMIO_CONF_BUSRANGE_MASK  0xf
  337. #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
  338. #define FAM10H_MMIO_CONF_BASE_MASK      0xfffffffULL
  339. #define FAM10H_MMIO_CONF_BASE_SHIFT     20
  340. #define MSR_FAM10H_NODE_ID              0xc001100c
  341.  
  342. /* K8 MSRs */
  343. #define MSR_K8_TOP_MEM1                 0xc001001a
  344. #define MSR_K8_TOP_MEM2                 0xc001001d
  345. #define MSR_K8_SYSCFG                   0xc0010010
  346. #define MSR_K8_INT_PENDING_MSG          0xc0010055
  347. /* C1E active bits in int pending message */
  348. #define K8_INTP_C1E_ACTIVE_MASK         0x18000000
  349. #define MSR_K8_TSEG_ADDR                0xc0010112
  350. #define MSR_K8_TSEG_MASK                0xc0010113
  351. #define K8_MTRRFIXRANGE_DRAM_ENABLE     0x00040000 /* MtrrFixDramEn bit    */
  352. #define K8_MTRRFIXRANGE_DRAM_MODIFY     0x00080000 /* MtrrFixDramModEn bit */
  353. #define K8_MTRR_RDMEM_WRMEM_MASK        0x18181818 /* Mask: RdMem|WrMem    */
  354.  
  355. /* K7 MSRs */
  356. #define MSR_K7_EVNTSEL0                 0xc0010000
  357. #define MSR_K7_PERFCTR0                 0xc0010004
  358. #define MSR_K7_EVNTSEL1                 0xc0010001
  359. #define MSR_K7_PERFCTR1                 0xc0010005
  360. #define MSR_K7_EVNTSEL2                 0xc0010002
  361. #define MSR_K7_PERFCTR2                 0xc0010006
  362. #define MSR_K7_EVNTSEL3                 0xc0010003
  363. #define MSR_K7_PERFCTR3                 0xc0010007
  364. #define MSR_K7_CLK_CTL                  0xc001001b
  365. #define MSR_K7_HWCR                     0xc0010015
  366. #define MSR_K7_FID_VID_CTL              0xc0010041
  367. #define MSR_K7_FID_VID_STATUS           0xc0010042
  368.  
  369. /* K6 MSRs */
  370. #define MSR_K6_WHCR                     0xc0000082
  371. #define MSR_K6_UWCCR                    0xc0000085
  372. #define MSR_K6_EPMR                     0xc0000086
  373. #define MSR_K6_PSOR                     0xc0000087
  374. #define MSR_K6_PFIR                     0xc0000088
  375.  
  376. /* Centaur-Hauls/IDT defined MSRs. */
  377. #define MSR_IDT_FCR1                    0x00000107
  378. #define MSR_IDT_FCR2                    0x00000108
  379. #define MSR_IDT_FCR3                    0x00000109
  380. #define MSR_IDT_FCR4                    0x0000010a
  381.  
  382. #define MSR_IDT_MCR0                    0x00000110
  383. #define MSR_IDT_MCR1                    0x00000111
  384. #define MSR_IDT_MCR2                    0x00000112
  385. #define MSR_IDT_MCR3                    0x00000113
  386. #define MSR_IDT_MCR4                    0x00000114
  387. #define MSR_IDT_MCR5                    0x00000115
  388. #define MSR_IDT_MCR6                    0x00000116
  389. #define MSR_IDT_MCR7                    0x00000117
  390. #define MSR_IDT_MCR_CTRL                0x00000120
  391.  
  392. /* VIA Cyrix defined MSRs*/
  393. #define MSR_VIA_FCR                     0x00001107
  394. #define MSR_VIA_LONGHAUL                0x0000110a
  395. #define MSR_VIA_RNG                     0x0000110b
  396. #define MSR_VIA_BCR2                    0x00001147
  397.  
  398. /* Transmeta defined MSRs */
  399. #define MSR_TMTA_LONGRUN_CTRL           0x80868010
  400. #define MSR_TMTA_LONGRUN_FLAGS          0x80868011
  401. #define MSR_TMTA_LRTI_READOUT           0x80868018
  402. #define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
  403.  
  404. /* Intel defined MSRs. */
  405. #define MSR_IA32_P5_MC_ADDR             0x00000000
  406. #define MSR_IA32_P5_MC_TYPE             0x00000001
  407. #define MSR_IA32_TSC                    0x00000010
  408. #define MSR_IA32_PLATFORM_ID            0x00000017
  409. #define MSR_IA32_EBL_CR_POWERON         0x0000002a
  410. #define MSR_EBC_FREQUENCY_ID            0x0000002c
  411. #define MSR_SMI_COUNT                   0x00000034
  412. #define MSR_IA32_FEATURE_CONTROL        0x0000003a
  413. #define MSR_IA32_TSC_ADJUST             0x0000003b
  414. #define MSR_IA32_BNDCFGS                0x00000d90
  415.  
  416. #define MSR_IA32_XSS                    0x00000da0
  417.  
  418. #define FEATURE_CONTROL_LOCKED                          (1<<0)
  419. #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX        (1<<1)
  420. #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX       (1<<2)
  421. #define FEATURE_CONTROL_LMCE                            (1<<20)
  422.  
  423. #define MSR_IA32_APICBASE               0x0000001b
  424. #define MSR_IA32_APICBASE_BSP           (1<<8)
  425. #define MSR_IA32_APICBASE_ENABLE        (1<<11)
  426. #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
  427.  
  428. #define MSR_IA32_TSCDEADLINE            0x000006e0
  429.  
  430. #define MSR_IA32_UCODE_WRITE            0x00000079
  431. #define MSR_IA32_UCODE_REV              0x0000008b
  432.  
  433. #define MSR_IA32_SMM_MONITOR_CTL        0x0000009b
  434. #define MSR_IA32_SMBASE                 0x0000009e
  435.  
  436. #define MSR_IA32_PERF_STATUS            0x00000198
  437. #define MSR_IA32_PERF_CTL               0x00000199
  438. #define INTEL_PERF_CTL_MASK             0xffff
  439. #define MSR_AMD_PSTATE_DEF_BASE         0xc0010064
  440. #define MSR_AMD_PERF_STATUS             0xc0010063
  441. #define MSR_AMD_PERF_CTL                0xc0010062
  442.  
  443. #define MSR_IA32_MPERF                  0x000000e7
  444. #define MSR_IA32_APERF                  0x000000e8
  445.  
  446. #define MSR_IA32_THERM_CONTROL          0x0000019a
  447. #define MSR_IA32_THERM_INTERRUPT        0x0000019b
  448.  
  449. #define THERM_INT_HIGH_ENABLE           (1 << 0)
  450. #define THERM_INT_LOW_ENABLE            (1 << 1)
  451. #define THERM_INT_PLN_ENABLE            (1 << 24)
  452.  
  453. #define MSR_IA32_THERM_STATUS           0x0000019c
  454.  
  455. #define THERM_STATUS_PROCHOT            (1 << 0)
  456. #define THERM_STATUS_POWER_LIMIT        (1 << 10)
  457.  
  458. #define MSR_THERM2_CTL                  0x0000019d
  459.  
  460. #define MSR_THERM2_CTL_TM_SELECT        (1ULL << 16)
  461.  
  462. #define MSR_IA32_MISC_ENABLE            0x000001a0
  463.  
  464. #define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
  465.  
  466. #define MSR_MISC_PWR_MGMT               0x000001aa
  467.  
  468. #define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
  469. #define ENERGY_PERF_BIAS_PERFORMANCE    0
  470. #define ENERGY_PERF_BIAS_NORMAL         6
  471. #define ENERGY_PERF_BIAS_POWERSAVE      15
  472.  
  473. #define MSR_IA32_PACKAGE_THERM_STATUS           0x000001b1
  474.  
  475. #define PACKAGE_THERM_STATUS_PROCHOT            (1 << 0)
  476. #define PACKAGE_THERM_STATUS_POWER_LIMIT        (1 << 10)
  477.  
  478. #define MSR_IA32_PACKAGE_THERM_INTERRUPT        0x000001b2
  479.  
  480. #define PACKAGE_THERM_INT_HIGH_ENABLE           (1 << 0)
  481. #define PACKAGE_THERM_INT_LOW_ENABLE            (1 << 1)
  482. #define PACKAGE_THERM_INT_PLN_ENABLE            (1 << 24)
  483.  
  484. /* Thermal Thresholds Support */
  485. #define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
  486. #define THERM_SHIFT_THRESHOLD0        8
  487. #define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
  488. #define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
  489. #define THERM_SHIFT_THRESHOLD1        16
  490. #define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
  491. #define THERM_STATUS_THRESHOLD0        (1 << 6)
  492. #define THERM_LOG_THRESHOLD0           (1 << 7)
  493. #define THERM_STATUS_THRESHOLD1        (1 << 8)
  494. #define THERM_LOG_THRESHOLD1           (1 << 9)
  495.  
  496. /* MISC_ENABLE bits: architectural */
  497. #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT            0
  498. #define MSR_IA32_MISC_ENABLE_FAST_STRING                (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
  499. #define MSR_IA32_MISC_ENABLE_TCC_BIT                    1
  500. #define MSR_IA32_MISC_ENABLE_TCC                        (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
  501. #define MSR_IA32_MISC_ENABLE_EMON_BIT                   7
  502. #define MSR_IA32_MISC_ENABLE_EMON                       (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
  503. #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT            11
  504. #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL                (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
  505. #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT           12
  506. #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL               (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
  507. #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT     16
  508. #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP         (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
  509. #define MSR_IA32_MISC_ENABLE_MWAIT_BIT                  18
  510. #define MSR_IA32_MISC_ENABLE_MWAIT                      (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
  511. #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT            22
  512. #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID                (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
  513. #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT           23
  514. #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE               (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
  515. #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT             34
  516. #define MSR_IA32_MISC_ENABLE_XD_DISABLE                 (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
  517.  
  518. /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
  519. #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT             2
  520. #define MSR_IA32_MISC_ENABLE_X87_COMPAT                 (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
  521. #define MSR_IA32_MISC_ENABLE_TM1_BIT                    3
  522. #define MSR_IA32_MISC_ENABLE_TM1                        (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
  523. #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT     4
  524. #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE         (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
  525. #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT        6
  526. #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE            (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
  527. #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT          8
  528. #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK              (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
  529. #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT       9
  530. #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
  531. #define MSR_IA32_MISC_ENABLE_FERR_BIT                   10
  532. #define MSR_IA32_MISC_ENABLE_FERR                       (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
  533. #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT         10
  534. #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX             (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
  535. #define MSR_IA32_MISC_ENABLE_TM2_BIT                    13
  536. #define MSR_IA32_MISC_ENABLE_TM2                        (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
  537. #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT       19
  538. #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
  539. #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT         20
  540. #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK             (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
  541. #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT            24
  542. #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT                (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
  543. #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT       37
  544. #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
  545. #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT          38
  546. #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE              (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
  547. #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT        39
  548. #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE            (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
  549.  
  550. #define MSR_IA32_TSC_DEADLINE           0x000006E0
  551.  
  552. /* P4/Xeon+ specific */
  553. #define MSR_IA32_MCG_EAX                0x00000180
  554. #define MSR_IA32_MCG_EBX                0x00000181
  555. #define MSR_IA32_MCG_ECX                0x00000182
  556. #define MSR_IA32_MCG_EDX                0x00000183
  557. #define MSR_IA32_MCG_ESI                0x00000184
  558. #define MSR_IA32_MCG_EDI                0x00000185
  559. #define MSR_IA32_MCG_EBP                0x00000186
  560. #define MSR_IA32_MCG_ESP                0x00000187
  561. #define MSR_IA32_MCG_EFLAGS             0x00000188
  562. #define MSR_IA32_MCG_EIP                0x00000189
  563. #define MSR_IA32_MCG_RESERVED           0x0000018a
  564.  
  565. /* Pentium IV performance counter MSRs */
  566. #define MSR_P4_BPU_PERFCTR0             0x00000300
  567. #define MSR_P4_BPU_PERFCTR1             0x00000301
  568. #define MSR_P4_BPU_PERFCTR2             0x00000302
  569. #define MSR_P4_BPU_PERFCTR3             0x00000303
  570. #define MSR_P4_MS_PERFCTR0              0x00000304
  571. #define MSR_P4_MS_PERFCTR1              0x00000305
  572. #define MSR_P4_MS_PERFCTR2              0x00000306
  573. #define MSR_P4_MS_PERFCTR3              0x00000307
  574. #define MSR_P4_FLAME_PERFCTR0           0x00000308
  575. #define MSR_P4_FLAME_PERFCTR1           0x00000309
  576. #define MSR_P4_FLAME_PERFCTR2           0x0000030a
  577. #define MSR_P4_FLAME_PERFCTR3           0x0000030b
  578. #define MSR_P4_IQ_PERFCTR0              0x0000030c
  579. #define MSR_P4_IQ_PERFCTR1              0x0000030d
  580. #define MSR_P4_IQ_PERFCTR2              0x0000030e
  581. #define MSR_P4_IQ_PERFCTR3              0x0000030f
  582. #define MSR_P4_IQ_PERFCTR4              0x00000310
  583. #define MSR_P4_IQ_PERFCTR5              0x00000311
  584. #define MSR_P4_BPU_CCCR0                0x00000360
  585. #define MSR_P4_BPU_CCCR1                0x00000361
  586. #define MSR_P4_BPU_CCCR2                0x00000362
  587. #define MSR_P4_BPU_CCCR3                0x00000363
  588. #define MSR_P4_MS_CCCR0                 0x00000364
  589. #define MSR_P4_MS_CCCR1                 0x00000365
  590. #define MSR_P4_MS_CCCR2                 0x00000366
  591. #define MSR_P4_MS_CCCR3                 0x00000367
  592. #define MSR_P4_FLAME_CCCR0              0x00000368
  593. #define MSR_P4_FLAME_CCCR1              0x00000369
  594. #define MSR_P4_FLAME_CCCR2              0x0000036a
  595. #define MSR_P4_FLAME_CCCR3              0x0000036b
  596. #define MSR_P4_IQ_CCCR0                 0x0000036c
  597. #define MSR_P4_IQ_CCCR1                 0x0000036d
  598. #define MSR_P4_IQ_CCCR2                 0x0000036e
  599. #define MSR_P4_IQ_CCCR3                 0x0000036f
  600. #define MSR_P4_IQ_CCCR4                 0x00000370
  601. #define MSR_P4_IQ_CCCR5                 0x00000371
  602. #define MSR_P4_ALF_ESCR0                0x000003ca
  603. #define MSR_P4_ALF_ESCR1                0x000003cb
  604. #define MSR_P4_BPU_ESCR0                0x000003b2
  605. #define MSR_P4_BPU_ESCR1                0x000003b3
  606. #define MSR_P4_BSU_ESCR0                0x000003a0
  607. #define MSR_P4_BSU_ESCR1                0x000003a1
  608. #define MSR_P4_CRU_ESCR0                0x000003b8
  609. #define MSR_P4_CRU_ESCR1                0x000003b9
  610. #define MSR_P4_CRU_ESCR2                0x000003cc
  611. #define MSR_P4_CRU_ESCR3                0x000003cd
  612. #define MSR_P4_CRU_ESCR4                0x000003e0
  613. #define MSR_P4_CRU_ESCR5                0x000003e1
  614. #define MSR_P4_DAC_ESCR0                0x000003a8
  615. #define MSR_P4_DAC_ESCR1                0x000003a9
  616. #define MSR_P4_FIRM_ESCR0               0x000003a4
  617. #define MSR_P4_FIRM_ESCR1               0x000003a5
  618. #define MSR_P4_FLAME_ESCR0              0x000003a6
  619. #define MSR_P4_FLAME_ESCR1              0x000003a7
  620. #define MSR_P4_FSB_ESCR0                0x000003a2
  621. #define MSR_P4_FSB_ESCR1                0x000003a3
  622. #define MSR_P4_IQ_ESCR0                 0x000003ba
  623. #define MSR_P4_IQ_ESCR1                 0x000003bb
  624. #define MSR_P4_IS_ESCR0                 0x000003b4
  625. #define MSR_P4_IS_ESCR1                 0x000003b5
  626. #define MSR_P4_ITLB_ESCR0               0x000003b6
  627. #define MSR_P4_ITLB_ESCR1               0x000003b7
  628. #define MSR_P4_IX_ESCR0                 0x000003c8
  629. #define MSR_P4_IX_ESCR1                 0x000003c9
  630. #define MSR_P4_MOB_ESCR0                0x000003aa
  631. #define MSR_P4_MOB_ESCR1                0x000003ab
  632. #define MSR_P4_MS_ESCR0                 0x000003c0
  633. #define MSR_P4_MS_ESCR1                 0x000003c1
  634. #define MSR_P4_PMH_ESCR0                0x000003ac
  635. #define MSR_P4_PMH_ESCR1                0x000003ad
  636. #define MSR_P4_RAT_ESCR0                0x000003bc
  637. #define MSR_P4_RAT_ESCR1                0x000003bd
  638. #define MSR_P4_SAAT_ESCR0               0x000003ae
  639. #define MSR_P4_SAAT_ESCR1               0x000003af
  640. #define MSR_P4_SSU_ESCR0                0x000003be
  641. #define MSR_P4_SSU_ESCR1                0x000003bf /* guess: not in manual */
  642.  
  643. #define MSR_P4_TBPU_ESCR0               0x000003c2
  644. #define MSR_P4_TBPU_ESCR1               0x000003c3
  645. #define MSR_P4_TC_ESCR0                 0x000003c4
  646. #define MSR_P4_TC_ESCR1                 0x000003c5
  647. #define MSR_P4_U2L_ESCR0                0x000003b0
  648. #define MSR_P4_U2L_ESCR1                0x000003b1
  649.  
  650. #define MSR_P4_PEBS_MATRIX_VERT         0x000003f2
  651.  
  652. /* Intel Core-based CPU performance counters */
  653. #define MSR_CORE_PERF_FIXED_CTR0        0x00000309
  654. #define MSR_CORE_PERF_FIXED_CTR1        0x0000030a
  655. #define MSR_CORE_PERF_FIXED_CTR2        0x0000030b
  656. #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x0000038d
  657. #define MSR_CORE_PERF_GLOBAL_STATUS     0x0000038e
  658. #define MSR_CORE_PERF_GLOBAL_CTRL       0x0000038f
  659. #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x00000390
  660.  
  661. /* Geode defined MSRs */
  662. #define MSR_GEODE_BUSCONT_CONF0         0x00001900
  663.  
  664. /* Intel VT MSRs */
  665. #define MSR_IA32_VMX_BASIC              0x00000480
  666. #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
  667. #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
  668. #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
  669. #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
  670. #define MSR_IA32_VMX_MISC               0x00000485
  671. #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
  672. #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
  673. #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
  674. #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
  675. #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
  676. #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
  677. #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
  678. #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
  679. #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
  680. #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
  681. #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
  682. #define MSR_IA32_VMX_VMFUNC             0x00000491
  683.  
  684. /* VMX_BASIC bits and bitmasks */
  685. #define VMX_BASIC_VMCS_SIZE_SHIFT       32
  686. #define VMX_BASIC_TRUE_CTLS             (1ULL << 55)
  687. #define VMX_BASIC_64            0x0001000000000000LLU
  688. #define VMX_BASIC_MEM_TYPE_SHIFT        50
  689. #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
  690. #define VMX_BASIC_MEM_TYPE_WB   6LLU
  691. #define VMX_BASIC_INOUT         0x0040000000000000LLU
  692.  
  693. /* MSR_IA32_VMX_MISC bits */
  694. #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
  695. #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
  696. /* AMD-V MSRs */
  697.  
  698. #define MSR_VM_CR                       0xc0010114
  699. #define MSR_VM_IGNNE                    0xc0010115
  700. #define MSR_VM_HSAVE_PA                 0xc0010117
  701.  
  702. #endif /* _ASM_X86_MSR_INDEX_H */
  703.