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  1.  
  2. #include <ddk.h>
  3. #include <linux/errno.h>
  4. #include <mutex.h>
  5. #include <pci.h>
  6. #include <list.h>
  7. #include <syscall.h>
  8.  
  9. LIST_HEAD(pci_root_buses);
  10.  
  11. #define IO_SPACE_LIMIT 0xffff
  12.  
  13.  
  14.  
  15.  
  16. #define LEGACY_IO_RESOURCE  (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
  17.  
  18. #define CARDBUS_LATENCY_TIMER   176 /* secondary latency timer */
  19. #define CARDBUS_RESERVE_BUSNR   3
  20.  
  21. static int pcibios_assign_all_busses(void)
  22. {
  23.     return 0;
  24. };
  25.  
  26. /**
  27.  * pci_ari_enabled - query ARI forwarding status
  28.  * @bus: the PCI bus
  29.  *
  30.  * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
  31.  */
  32. static inline int pci_ari_enabled(struct pci_bus *bus)
  33. {
  34.     return bus->self && bus->self->ari_enabled;
  35. }
  36.  
  37. /*
  38.  * Translate the low bits of the PCI base
  39.  * to the resource type
  40.  */
  41. static inline unsigned int pci_calc_resource_flags(unsigned int flags)
  42. {
  43.     if (flags & PCI_BASE_ADDRESS_SPACE_IO)
  44.         return IORESOURCE_IO;
  45.  
  46.     if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
  47.         return IORESOURCE_MEM | IORESOURCE_PREFETCH;
  48.  
  49.     return IORESOURCE_MEM;
  50. }
  51.  
  52. static u64 pci_size(u64 base, u64 maxbase, u64 mask)
  53. {
  54.     u64 size = mask & maxbase;  /* Find the significant bits */
  55.     if (!size)
  56.         return 0;
  57.  
  58.     /* Get the lowest of them to find the decode size, and
  59.        from that the extent.  */
  60.     size = (size & ~(size-1)) - 1;
  61.  
  62.     /* base == maxbase can be valid only if the BAR has
  63.        already been programmed with all 1s.  */
  64.     if (base == maxbase && ((base | size) & mask) != mask)
  65.         return 0;
  66.  
  67.     return size;
  68. }
  69.  
  70. static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
  71. {
  72.     if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
  73.         res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
  74.         return pci_bar_io;
  75.     }
  76.  
  77.     res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
  78.  
  79.     if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
  80.         return pci_bar_mem64;
  81.     return pci_bar_mem32;
  82. }
  83.  
  84.  
  85.  
  86. /**
  87.  * pci_read_base - read a PCI BAR
  88.  * @dev: the PCI device
  89.  * @type: type of the BAR
  90.  * @res: resource buffer to be filled in
  91.  * @pos: BAR position in the config space
  92.  *
  93.  * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
  94.  */
  95. int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
  96.             struct resource *res, unsigned int pos)
  97. {
  98.     u32 l, sz, mask;
  99.     u16 orig_cmd;
  100.  
  101.     mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
  102.  
  103.     if (!dev->mmio_always_on) {
  104.         pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
  105.         pci_write_config_word(dev, PCI_COMMAND,
  106.             orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
  107.     }
  108.  
  109.     res->name = pci_name(dev);
  110.  
  111.     pci_read_config_dword(dev, pos, &l);
  112.     pci_write_config_dword(dev, pos, l | mask);
  113.     pci_read_config_dword(dev, pos, &sz);
  114.     pci_write_config_dword(dev, pos, l);
  115.  
  116.     if (!dev->mmio_always_on)
  117.         pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
  118.  
  119.     /*
  120.      * All bits set in sz means the device isn't working properly.
  121.      * If the BAR isn't implemented, all bits must be 0.  If it's a
  122.      * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
  123.      * 1 must be clear.
  124.      */
  125.     if (!sz || sz == 0xffffffff)
  126.         goto fail;
  127.  
  128.     /*
  129.      * I don't know how l can have all bits set.  Copied from old code.
  130.      * Maybe it fixes a bug on some ancient platform.
  131.      */
  132.     if (l == 0xffffffff)
  133.         l = 0;
  134.  
  135.     if (type == pci_bar_unknown) {
  136.         type = decode_bar(res, l);
  137.         res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
  138.         if (type == pci_bar_io) {
  139.             l &= PCI_BASE_ADDRESS_IO_MASK;
  140.             mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
  141.         } else {
  142.             l &= PCI_BASE_ADDRESS_MEM_MASK;
  143.             mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  144.         }
  145.     } else {
  146.         res->flags |= (l & IORESOURCE_ROM_ENABLE);
  147.         l &= PCI_ROM_ADDRESS_MASK;
  148.         mask = (u32)PCI_ROM_ADDRESS_MASK;
  149.     }
  150.  
  151.     if (type == pci_bar_mem64) {
  152.         u64 l64 = l;
  153.         u64 sz64 = sz;
  154.         u64 mask64 = mask | (u64)~0 << 32;
  155.  
  156.         pci_read_config_dword(dev, pos + 4, &l);
  157.         pci_write_config_dword(dev, pos + 4, ~0);
  158.         pci_read_config_dword(dev, pos + 4, &sz);
  159.         pci_write_config_dword(dev, pos + 4, l);
  160.  
  161.         l64 |= ((u64)l << 32);
  162.         sz64 |= ((u64)sz << 32);
  163.  
  164.         sz64 = pci_size(l64, sz64, mask64);
  165.  
  166.         if (!sz64)
  167.             goto fail;
  168.  
  169.         if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
  170.             dbgprintf("%s reg %x: can't handle 64-bit BAR\n",
  171.                 __FUNCTION__, pos);
  172.             goto fail;
  173.         }
  174.  
  175.         res->flags |= IORESOURCE_MEM_64;
  176.         if ((sizeof(resource_size_t) < 8) && l) {
  177.             /* Address above 32-bit boundary; disable the BAR */
  178.             pci_write_config_dword(dev, pos, 0);
  179.             pci_write_config_dword(dev, pos + 4, 0);
  180.             res->start = 0;
  181.             res->end = sz64;
  182.         } else {
  183.             res->start = l64;
  184.             res->end = l64 + sz64;
  185.         dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
  186.         }
  187.     } else {
  188.         sz = pci_size(l, sz, mask);
  189.  
  190.         if (!sz)
  191.             goto fail;
  192.  
  193.         res->start = l;
  194.         res->end = l + sz;
  195.  
  196.         dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
  197.     }
  198.  
  199.  out:
  200.     return (type == pci_bar_mem64) ? 1 : 0;
  201.  fail:
  202.     res->flags = 0;
  203.     goto out;
  204. }
  205.  
  206. static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
  207. {
  208.     unsigned int pos, reg;
  209.  
  210.     for (pos = 0; pos < howmany; pos++) {
  211.         struct resource *res = &dev->resource[pos];
  212.         reg = PCI_BASE_ADDRESS_0 + (pos << 2);
  213.         pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
  214.     }
  215.  
  216.     if (rom) {
  217.         struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
  218.         dev->rom_base_reg = rom;
  219.         res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
  220.                 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
  221.                 IORESOURCE_SIZEALIGN;
  222.         __pci_read_base(dev, pci_bar_mem32, res, rom);
  223.     }
  224. }
  225.  
  226. #if 0
  227.  
  228. void pci_read_bridge_bases(struct pci_bus *child)
  229. {
  230.     struct pci_dev *dev = child->self;
  231.     struct resource *res;
  232.     int i;
  233.  
  234.     if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
  235.         return;
  236.  
  237.     dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",
  238.          child->secondary, child->subordinate,
  239.          dev->transparent ? " (subtractive decode)" : "");
  240.  
  241.     pci_bus_remove_resources(child);
  242.     for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
  243.         child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
  244.  
  245.     pci_read_bridge_io(child);
  246.     pci_read_bridge_mmio(child);
  247.     pci_read_bridge_mmio_pref(child);
  248.  
  249.     if (dev->transparent) {
  250.         pci_bus_for_each_resource(child->parent, res, i) {
  251.             if (res) {
  252.                 pci_bus_add_resource(child, res,
  253.                              PCI_SUBTRACTIVE_DECODE);
  254.                 dbgprintf("  bridge window %pR (subtractive decode)\n", res);
  255.             }
  256.         }
  257.     }
  258. }
  259.  
  260. #endif
  261.  
  262. static struct pci_bus * pci_alloc_bus(void)
  263. {
  264.     struct pci_bus *b;
  265.  
  266.     b = kzalloc(sizeof(*b), GFP_KERNEL);
  267.     if (b) {
  268.         INIT_LIST_HEAD(&b->node);
  269.         INIT_LIST_HEAD(&b->children);
  270.         INIT_LIST_HEAD(&b->devices);
  271.         INIT_LIST_HEAD(&b->slots);
  272.         INIT_LIST_HEAD(&b->resources);
  273. //        b->max_bus_speed = PCI_SPEED_UNKNOWN;
  274. //        b->cur_bus_speed = PCI_SPEED_UNKNOWN;
  275.     }
  276.     return b;
  277. }
  278.  
  279.  
  280. #if 0
  281.  
  282. static unsigned char pcix_bus_speed[] = {
  283.     PCI_SPEED_UNKNOWN,      /* 0 */
  284.     PCI_SPEED_66MHz_PCIX,       /* 1 */
  285.     PCI_SPEED_100MHz_PCIX,      /* 2 */
  286.     PCI_SPEED_133MHz_PCIX,      /* 3 */
  287.     PCI_SPEED_UNKNOWN,      /* 4 */
  288.     PCI_SPEED_66MHz_PCIX_ECC,   /* 5 */
  289.     PCI_SPEED_100MHz_PCIX_ECC,  /* 6 */
  290.     PCI_SPEED_133MHz_PCIX_ECC,  /* 7 */
  291.     PCI_SPEED_UNKNOWN,      /* 8 */
  292.     PCI_SPEED_66MHz_PCIX_266,   /* 9 */
  293.     PCI_SPEED_100MHz_PCIX_266,  /* A */
  294.     PCI_SPEED_133MHz_PCIX_266,  /* B */
  295.     PCI_SPEED_UNKNOWN,      /* C */
  296.     PCI_SPEED_66MHz_PCIX_533,   /* D */
  297.     PCI_SPEED_100MHz_PCIX_533,  /* E */
  298.     PCI_SPEED_133MHz_PCIX_533   /* F */
  299. };
  300.  
  301. static unsigned char pcie_link_speed[] = {
  302.     PCI_SPEED_UNKNOWN,      /* 0 */
  303.     PCIE_SPEED_2_5GT,       /* 1 */
  304.     PCIE_SPEED_5_0GT,       /* 2 */
  305.     PCIE_SPEED_8_0GT,       /* 3 */
  306.     PCI_SPEED_UNKNOWN,      /* 4 */
  307.     PCI_SPEED_UNKNOWN,      /* 5 */
  308.     PCI_SPEED_UNKNOWN,      /* 6 */
  309.     PCI_SPEED_UNKNOWN,      /* 7 */
  310.     PCI_SPEED_UNKNOWN,      /* 8 */
  311.     PCI_SPEED_UNKNOWN,      /* 9 */
  312.     PCI_SPEED_UNKNOWN,      /* A */
  313.     PCI_SPEED_UNKNOWN,      /* B */
  314.     PCI_SPEED_UNKNOWN,      /* C */
  315.     PCI_SPEED_UNKNOWN,      /* D */
  316.     PCI_SPEED_UNKNOWN,      /* E */
  317.     PCI_SPEED_UNKNOWN       /* F */
  318. };
  319.  
  320.  
  321. static void pci_set_bus_speed(struct pci_bus *bus)
  322. {
  323.     struct pci_dev *bridge = bus->self;
  324.     int pos;
  325.  
  326.     pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
  327.     if (!pos)
  328.         pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
  329.     if (pos) {
  330.         u32 agpstat, agpcmd;
  331.  
  332.         pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
  333.         bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
  334.  
  335.         pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
  336.         bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
  337.     }
  338.  
  339.     pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
  340.     if (pos) {
  341.         u16 status;
  342.         enum pci_bus_speed max;
  343.         pci_read_config_word(bridge, pos + 2, &status);
  344.  
  345.         if (status & 0x8000) {
  346.             max = PCI_SPEED_133MHz_PCIX_533;
  347.         } else if (status & 0x4000) {
  348.             max = PCI_SPEED_133MHz_PCIX_266;
  349.         } else if (status & 0x0002) {
  350.             if (((status >> 12) & 0x3) == 2) {
  351.                 max = PCI_SPEED_133MHz_PCIX_ECC;
  352.             } else {
  353.                 max = PCI_SPEED_133MHz_PCIX;
  354.             }
  355.         } else {
  356.             max = PCI_SPEED_66MHz_PCIX;
  357.         }
  358.  
  359.         bus->max_bus_speed = max;
  360.         bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
  361.  
  362.         return;
  363.     }
  364.  
  365.     pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
  366.     if (pos) {
  367.         u32 linkcap;
  368.         u16 linksta;
  369.  
  370.         pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
  371.         bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
  372.  
  373.         pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
  374.         pcie_update_link_speed(bus, linksta);
  375.     }
  376. }
  377.  
  378. #endif
  379.  
  380.  
  381. static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
  382.                        struct pci_dev *bridge, int busnr)
  383. {
  384.     struct pci_bus *child;
  385.     int i;
  386.  
  387.     /*
  388.      * Allocate a new bus, and inherit stuff from the parent..
  389.      */
  390.     child = pci_alloc_bus();
  391.     if (!child)
  392.         return NULL;
  393.  
  394.     child->parent = parent;
  395.     child->ops = parent->ops;
  396.     child->sysdata = parent->sysdata;
  397.     child->bus_flags = parent->bus_flags;
  398.  
  399.     /* initialize some portions of the bus device, but don't register it
  400.      * now as the parent is not properly set up yet.  This device will get
  401.      * registered later in pci_bus_add_devices()
  402.      */
  403. //    child->dev.class = &pcibus_class;
  404. //    dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
  405.  
  406.     /*
  407.      * Set up the primary, secondary and subordinate
  408.      * bus numbers.
  409.      */
  410.     child->number = child->secondary = busnr;
  411.     child->primary = parent->secondary;
  412.     child->subordinate = 0xff;
  413.  
  414.     if (!bridge)
  415.         return child;
  416.  
  417.     child->self = bridge;
  418. //    child->bridge = get_device(&bridge->dev);
  419.  
  420. //    pci_set_bus_speed(child);
  421.  
  422.     /* Set up default resource pointers and names.. */
  423.     for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
  424.         child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
  425.         child->resource[i]->name = child->name;
  426.     }
  427.     bridge->subordinate = child;
  428.  
  429.     return child;
  430. }
  431.  
  432. struct pci_bus* pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
  433. {
  434.     struct pci_bus *child;
  435.  
  436.     child = pci_alloc_child_bus(parent, dev, busnr);
  437.     if (child) {
  438. //        down_write(&pci_bus_sem);
  439.         list_add_tail(&child->node, &parent->children);
  440. //        up_write(&pci_bus_sem);
  441.     }
  442.     return child;
  443. }
  444.  
  445.  
  446. static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
  447. {
  448.     struct pci_bus *parent = child->parent;
  449.  
  450.     /* Attempts to fix that up are really dangerous unless
  451.        we're going to re-assign all bus numbers. */
  452.     if (!pcibios_assign_all_busses())
  453.         return;
  454.  
  455.     while (parent->parent && parent->subordinate < max) {
  456.         parent->subordinate = max;
  457.         pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
  458.         parent = parent->parent;
  459.     }
  460. }
  461.  
  462.  
  463. /*
  464.  * If it's a bridge, configure it and scan the bus behind it.
  465.  * For CardBus bridges, we don't scan behind as the devices will
  466.  * be handled by the bridge driver itself.
  467.  *
  468.  * We need to process bridges in two passes -- first we scan those
  469.  * already configured by the BIOS and after we are done with all of
  470.  * them, we proceed to assigning numbers to the remaining buses in
  471.  * order to avoid overlaps between old and new bus numbers.
  472.  */
  473. int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
  474. {
  475.     struct pci_bus *child;
  476.     int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
  477.     u32 buses, i, j = 0;
  478.     u16 bctl;
  479.     u8 primary, secondary, subordinate;
  480.     int broken = 0;
  481.  
  482.     pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
  483.     primary = buses & 0xFF;
  484.     secondary = (buses >> 8) & 0xFF;
  485.     subordinate = (buses >> 16) & 0xFF;
  486.  
  487.     dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",
  488.         secondary, subordinate, pass);
  489.  
  490.     /* Check if setup is sensible at all */
  491.     if (!pass &&
  492.         (primary != bus->number || secondary <= bus->number)) {
  493.         dbgprintf("bus configuration invalid, reconfiguring\n");
  494.         broken = 1;
  495.     }
  496.  
  497.     /* Disable MasterAbortMode during probing to avoid reporting
  498.        of bus errors (in some architectures) */
  499.     pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
  500.     pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
  501.                   bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
  502.  
  503.     if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
  504.         !is_cardbus && !broken) {
  505.         unsigned int cmax;
  506.         /*
  507.          * Bus already configured by firmware, process it in the first
  508.          * pass and just note the configuration.
  509.          */
  510.         if (pass)
  511.             goto out;
  512.  
  513.         /*
  514.          * If we already got to this bus through a different bridge,
  515.          * don't re-add it. This can happen with the i450NX chipset.
  516.          *
  517.          * However, we continue to descend down the hierarchy and
  518.          * scan remaining child buses.
  519.          */
  520.         child = pci_find_bus(pci_domain_nr(bus), secondary);
  521.         if (!child) {
  522.             child = pci_add_new_bus(bus, dev, secondary);
  523.             if (!child)
  524.                 goto out;
  525.             child->primary = primary;
  526.             child->subordinate = subordinate;
  527.             child->bridge_ctl = bctl;
  528.         }
  529.  
  530.         cmax = pci_scan_child_bus(child);
  531.         if (cmax > max)
  532.             max = cmax;
  533.         if (child->subordinate > max)
  534.             max = child->subordinate;
  535.     } else {
  536.         /*
  537.          * We need to assign a number to this bus which we always
  538.          * do in the second pass.
  539.          */
  540.         if (!pass) {
  541.             if (pcibios_assign_all_busses() || broken)
  542.                 /* Temporarily disable forwarding of the
  543.                    configuration cycles on all bridges in
  544.                    this bus segment to avoid possible
  545.                    conflicts in the second pass between two
  546.                    bridges programmed with overlapping
  547.                    bus ranges. */
  548.                 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
  549.                                buses & ~0xffffff);
  550.             goto out;
  551.         }
  552.  
  553.         /* Clear errors */
  554.         pci_write_config_word(dev, PCI_STATUS, 0xffff);
  555.  
  556.         /* Prevent assigning a bus number that already exists.
  557.          * This can happen when a bridge is hot-plugged */
  558.         if (pci_find_bus(pci_domain_nr(bus), max+1))
  559.             goto out;
  560.         child = pci_add_new_bus(bus, dev, ++max);
  561.         buses = (buses & 0xff000000)
  562.               | ((unsigned int)(child->primary)     <<  0)
  563.               | ((unsigned int)(child->secondary)   <<  8)
  564.               | ((unsigned int)(child->subordinate) << 16);
  565.  
  566.         /*
  567.          * yenta.c forces a secondary latency timer of 176.
  568.          * Copy that behaviour here.
  569.          */
  570.         if (is_cardbus) {
  571.             buses &= ~0xff000000;
  572.             buses |= CARDBUS_LATENCY_TIMER << 24;
  573.         }
  574.  
  575.         /*
  576.          * We need to blast all three values with a single write.
  577.          */
  578.         pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
  579.  
  580.         if (!is_cardbus) {
  581.             child->bridge_ctl = bctl;
  582.             /*
  583.              * Adjust subordinate busnr in parent buses.
  584.              * We do this before scanning for children because
  585.              * some devices may not be detected if the bios
  586.              * was lazy.
  587.              */
  588.             pci_fixup_parent_subordinate_busnr(child, max);
  589.             /* Now we can scan all subordinate buses... */
  590.             max = pci_scan_child_bus(child);
  591.             /*
  592.              * now fix it up again since we have found
  593.              * the real value of max.
  594.              */
  595.             pci_fixup_parent_subordinate_busnr(child, max);
  596.         } else {
  597.             /*
  598.              * For CardBus bridges, we leave 4 bus numbers
  599.              * as cards with a PCI-to-PCI bridge can be
  600.              * inserted later.
  601.              */
  602.             for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
  603.                 struct pci_bus *parent = bus;
  604.                 if (pci_find_bus(pci_domain_nr(bus),
  605.                             max+i+1))
  606.                     break;
  607.                 while (parent->parent) {
  608.                     if ((!pcibios_assign_all_busses()) &&
  609.                         (parent->subordinate > max) &&
  610.                         (parent->subordinate <= max+i)) {
  611.                         j = 1;
  612.                     }
  613.                     parent = parent->parent;
  614.                 }
  615.                 if (j) {
  616.                     /*
  617.                      * Often, there are two cardbus bridges
  618.                      * -- try to leave one valid bus number
  619.                      * for each one.
  620.                      */
  621.                     i /= 2;
  622.                     break;
  623.                 }
  624.             }
  625.             max += i;
  626.             pci_fixup_parent_subordinate_busnr(child, max);
  627.         }
  628.         /*
  629.          * Set the subordinate bus number to its real value.
  630.          */
  631.         child->subordinate = max;
  632.         pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
  633.     }
  634.  
  635.     vsprintf(child->name,
  636.         (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
  637.         pci_domain_nr(bus), child->number);
  638.  
  639.     /* Has only triggered on CardBus, fixup is in yenta_socket */
  640.     while (bus->parent) {
  641.         if ((child->subordinate > bus->subordinate) ||
  642.             (child->number > bus->subordinate) ||
  643.             (child->number < bus->number) ||
  644.             (child->subordinate < bus->number)) {
  645.             dbgprintf("[bus %02x-%02x] %s "
  646.                 "hidden behind%s bridge %s [bus %02x-%02x]\n",
  647.                 child->number, child->subordinate,
  648.                 (bus->number > child->subordinate &&
  649.                  bus->subordinate < child->number) ?
  650.                     "wholly" : "partially",
  651.                 bus->self->transparent ? " transparent" : "",
  652.                 "FIX BRIDGE NAME",
  653.                 bus->number, bus->subordinate);
  654.         }
  655.         bus = bus->parent;
  656.     }
  657.  
  658. out:
  659.     pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
  660.  
  661.     return max;
  662. }
  663.  
  664. void set_pcie_port_type(struct pci_dev *pdev)
  665. {
  666.     int pos;
  667.     u16 reg16;
  668.  
  669.     pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  670.     if (!pos)
  671.         return;
  672.     pdev->is_pcie = 1;
  673.     pdev->pcie_cap = pos;
  674.     pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
  675.     pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
  676. }
  677.  
  678. void set_pcie_hotplug_bridge(struct pci_dev *pdev)
  679. {
  680.     int pos;
  681.     u16 reg16;
  682.     u32 reg32;
  683.  
  684.     pos = pci_pcie_cap(pdev);
  685.     if (!pos)
  686.         return;
  687.     pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
  688.     if (!(reg16 & PCI_EXP_FLAGS_SLOT))
  689.         return;
  690.     pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
  691.     if (reg32 & PCI_EXP_SLTCAP_HPC)
  692.         pdev->is_hotplug_bridge = 1;
  693. }
  694.  
  695. /*
  696.  * Read interrupt line and base address registers.
  697.  * The architecture-dependent code can tweak these, of course.
  698.  */
  699. static void pci_read_irq(struct pci_dev *dev)
  700. {
  701.     unsigned char irq;
  702.  
  703.     pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
  704.     dev->pin = irq;
  705.     if (irq)
  706.         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  707.     dev->irq = irq;
  708. }
  709.  
  710.  
  711. /**
  712.  * pci_setup_device - fill in class and map information of a device
  713.  * @dev: the device structure to fill
  714.  *
  715.  * Initialize the device structure with information about the device's
  716.  * vendor,class,memory and IO-space addresses,IRQ lines etc.
  717.  * Called at initialisation of the PCI subsystem and by CardBus services.
  718.  * Returns 0 on success and negative if unknown type of device (not normal,
  719.  * bridge or CardBus).
  720.  */
  721. int pci_setup_device(struct pci_dev *dev)
  722. {
  723.     u32 class;
  724.     u8 hdr_type;
  725.     struct pci_slot *slot;
  726.     int pos = 0;
  727.  
  728.     if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
  729.         return -EIO;
  730.  
  731.     dev->sysdata = dev->bus->sysdata;
  732. //    dev->dev.parent = dev->bus->bridge;
  733. //    dev->dev.bus = &pci_bus_type;
  734.     dev->hdr_type = hdr_type & 0x7f;
  735.     dev->multifunction = !!(hdr_type & 0x80);
  736.     dev->error_state = pci_channel_io_normal;
  737.     set_pcie_port_type(dev);
  738.  
  739.     list_for_each_entry(slot, &dev->bus->slots, list)
  740.         if (PCI_SLOT(dev->devfn) == slot->number)
  741.             dev->slot = slot;
  742.  
  743.     /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
  744.        set this higher, assuming the system even supports it.  */
  745.     dev->dma_mask = 0xffffffff;
  746.  
  747. //    dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
  748. //             dev->bus->number, PCI_SLOT(dev->devfn),
  749. //             PCI_FUNC(dev->devfn));
  750.  
  751.     pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
  752.     dev->revision = class & 0xff;
  753.     class >>= 8;                    /* upper 3 bytes */
  754.     dev->class = class;
  755.     class >>= 8;
  756.  
  757.     dbgprintf("found [%04x:%04x] class %06x header type %02x\n",
  758.          dev->vendor, dev->device, class, dev->hdr_type);
  759.  
  760.     /* need to have dev->class ready */
  761.     dev->cfg_size = pci_cfg_space_size(dev);
  762.  
  763.     /* "Unknown power state" */
  764.     dev->current_state = PCI_UNKNOWN;
  765.  
  766.     /* Early fixups, before probing the BARs */
  767. //    pci_fixup_device(pci_fixup_early, dev);
  768.     /* device class may be changed after fixup */
  769.     class = dev->class >> 8;
  770.  
  771.     switch (dev->hdr_type) {            /* header type */
  772.     case PCI_HEADER_TYPE_NORMAL:            /* standard header */
  773.         if (class == PCI_CLASS_BRIDGE_PCI)
  774.             goto bad;
  775.         pci_read_irq(dev);
  776.         pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
  777.         pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
  778.         pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
  779.  
  780.         /*
  781.          *  Do the ugly legacy mode stuff here rather than broken chip
  782.          *  quirk code. Legacy mode ATA controllers have fixed
  783.          *  addresses. These are not always echoed in BAR0-3, and
  784.          *  BAR0-3 in a few cases contain junk!
  785.          */
  786.         if (class == PCI_CLASS_STORAGE_IDE) {
  787.             u8 progif;
  788.             pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
  789.             if ((progif & 1) == 0) {
  790.                 dev->resource[0].start = 0x1F0;
  791.                 dev->resource[0].end = 0x1F7;
  792.                 dev->resource[0].flags = LEGACY_IO_RESOURCE;
  793.                 dev->resource[1].start = 0x3F6;
  794.                 dev->resource[1].end = 0x3F6;
  795.                 dev->resource[1].flags = LEGACY_IO_RESOURCE;
  796.             }
  797.             if ((progif & 4) == 0) {
  798.                 dev->resource[2].start = 0x170;
  799.                 dev->resource[2].end = 0x177;
  800.                 dev->resource[2].flags = LEGACY_IO_RESOURCE;
  801.                 dev->resource[3].start = 0x376;
  802.                 dev->resource[3].end = 0x376;
  803.                 dev->resource[3].flags = LEGACY_IO_RESOURCE;
  804.             }
  805.         }
  806.         break;
  807.  
  808.     case PCI_HEADER_TYPE_BRIDGE:            /* bridge header */
  809.         if (class != PCI_CLASS_BRIDGE_PCI)
  810.             goto bad;
  811.         /* The PCI-to-PCI bridge spec requires that subtractive
  812.            decoding (i.e. transparent) bridge must have programming
  813.            interface code of 0x01. */
  814.         pci_read_irq(dev);
  815.         dev->transparent = ((dev->class & 0xff) == 1);
  816.         pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
  817.         set_pcie_hotplug_bridge(dev);
  818.         pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
  819.         if (pos) {
  820.             pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
  821.             pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
  822.         }
  823.         break;
  824.  
  825.     case PCI_HEADER_TYPE_CARDBUS:           /* CardBus bridge header */
  826.         if (class != PCI_CLASS_BRIDGE_CARDBUS)
  827.             goto bad;
  828.         pci_read_irq(dev);
  829.         pci_read_bases(dev, 1, 0);
  830.         pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
  831.         pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
  832.         break;
  833.  
  834.     default:                    /* unknown header */
  835.         dbgprintf("unknown header type %02x, "
  836.             "ignoring device\n", dev->hdr_type);
  837.         return -EIO;
  838.  
  839.     bad:
  840.         dbgprintf("ignoring class %02x (doesn't match header "
  841.             "type %02x)\n", class, dev->hdr_type);
  842.         dev->class = PCI_CLASS_NOT_DEFINED;
  843.     }
  844.  
  845.     /* We found a fine healthy device, go go go... */
  846.     return 0;
  847. }
  848.  
  849.  
  850.  
  851. struct pci_dev *alloc_pci_dev(void)
  852. {
  853.     struct pci_dev *dev;
  854.  
  855.     dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
  856.     if (!dev)
  857.         return NULL;
  858.  
  859.     INIT_LIST_HEAD(&dev->bus_list);
  860.  
  861.     return dev;
  862. }
  863.  
  864. /*
  865.  * Read the config data for a PCI device, sanity-check it
  866.  * and fill in the dev structure...
  867.  */
  868. static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
  869. {
  870.     struct pci_dev *dev;
  871.     u32 l;
  872.     int timeout = 10;
  873.  
  874.     if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
  875.         return NULL;
  876.  
  877.     /* some broken boards return 0 or ~0 if a slot is empty: */
  878.     if (l == 0xffffffff || l == 0x00000000 ||
  879.         l == 0x0000ffff || l == 0xffff0000)
  880.         return NULL;
  881.  
  882.     /* Configuration request Retry Status */
  883.     while (l == 0xffff0001) {
  884.         delay(timeout/10);
  885.         timeout *= 2;
  886.         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
  887.             return NULL;
  888.         /* Card hasn't responded in 60 seconds?  Must be stuck. */
  889.         if (timeout > 60 * 1000) {
  890.             printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
  891.                     "responding\n", pci_domain_nr(bus),
  892.                     bus->number, PCI_SLOT(devfn),
  893.                     PCI_FUNC(devfn));
  894.             return NULL;
  895.         }
  896.     }
  897.  
  898.     dev = alloc_pci_dev();
  899.     if (!dev)
  900.         return NULL;
  901.  
  902.     dev->bus = bus;
  903.     dev->busnr = bus->number;
  904.     dev->devfn = devfn;
  905.     dev->vendor = l & 0xffff;
  906.     dev->device = (l >> 16) & 0xffff;
  907.  
  908.     if (pci_setup_device(dev)) {
  909.         kfree(dev);
  910.         return NULL;
  911.     }
  912.  
  913.     return dev;
  914. }
  915.  
  916. void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
  917. {
  918. //    device_initialize(&dev->dev);
  919. //    dev->dev.release = pci_release_dev;
  920. //    pci_dev_get(dev);
  921.  
  922. //    dev->dev.dma_mask = &dev->dma_mask;
  923. //    dev->dev.dma_parms = &dev->dma_parms;
  924. //    dev->dev.coherent_dma_mask = 0xffffffffull;
  925.  
  926. //    pci_set_dma_max_seg_size(dev, 65536);
  927. //    pci_set_dma_seg_boundary(dev, 0xffffffff);
  928.  
  929.     /* Fix up broken headers */
  930. //    pci_fixup_device(pci_fixup_header, dev);
  931.  
  932.     /* Clear the state_saved flag. */
  933.     dev->state_saved = false;
  934.  
  935.     /* Initialize various capabilities */
  936. //    pci_init_capabilities(dev);
  937.  
  938.     /*
  939.      * Add the device to our list of discovered devices
  940.      * and the bus list for fixup functions, etc.
  941.      */
  942. //    down_write(&pci_bus_sem);
  943.     list_add_tail(&dev->bus_list, &bus->devices);
  944. //    up_write(&pci_bus_sem);
  945. }
  946.  
  947. struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn)
  948. {
  949.     struct pci_dev *dev;
  950.  
  951.     dev = pci_get_slot(bus, devfn);
  952.     if (dev) {
  953. //        pci_dev_put(dev);
  954.         return dev;
  955.     }
  956.  
  957.     dev = pci_scan_device(bus, devfn);
  958.     if (!dev)
  959.         return NULL;
  960.  
  961.     pci_device_add(dev, bus);
  962.  
  963.     return dev;
  964. }
  965.  
  966. static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
  967. {
  968.     u16 cap;
  969.     unsigned pos, next_fn;
  970.  
  971.     if (!dev)
  972.         return 0;
  973.  
  974.     pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
  975.     if (!pos)
  976.         return 0;
  977.     pci_read_config_word(dev, pos + 4, &cap);
  978.     next_fn = cap >> 8;
  979.     if (next_fn <= fn)
  980.         return 0;
  981.     return next_fn;
  982. }
  983.  
  984. static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
  985. {
  986.     return (fn + 1) % 8;
  987. }
  988.  
  989. static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
  990. {
  991.     return 0;
  992. }
  993.  
  994. static int only_one_child(struct pci_bus *bus)
  995. {
  996.     struct pci_dev *parent = bus->self;
  997.     if (!parent || !pci_is_pcie(parent))
  998.         return 0;
  999.     if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
  1000.         parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
  1001.         return 1;
  1002.     return 0;
  1003. }
  1004.  
  1005. /**
  1006.  * pci_scan_slot - scan a PCI slot on a bus for devices.
  1007.  * @bus: PCI bus to scan
  1008.  * @devfn: slot number to scan (must have zero function.)
  1009.  *
  1010.  * Scan a PCI slot on the specified PCI bus for devices, adding
  1011.  * discovered devices to the @bus->devices list.  New devices
  1012.  * will not have is_added set.
  1013.  *
  1014.  * Returns the number of new devices found.
  1015.  */
  1016. int pci_scan_slot(struct pci_bus *bus, int devfn)
  1017. {
  1018.     unsigned fn, nr = 0;
  1019.     struct pci_dev *dev;
  1020.     unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
  1021.  
  1022.     if (only_one_child(bus) && (devfn > 0))
  1023.         return 0; /* Already scanned the entire slot */
  1024.  
  1025.     dev = pci_scan_single_device(bus, devfn);
  1026.     if (!dev)
  1027.         return 0;
  1028.     if (!dev->is_added)
  1029.         nr++;
  1030.  
  1031.     if (pci_ari_enabled(bus))
  1032.         next_fn = next_ari_fn;
  1033.     else if (dev->multifunction)
  1034.         next_fn = next_trad_fn;
  1035.  
  1036.     for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
  1037.         dev = pci_scan_single_device(bus, devfn + fn);
  1038.         if (dev) {
  1039.             if (!dev->is_added)
  1040.                 nr++;
  1041.             dev->multifunction = 1;
  1042.         }
  1043.     }
  1044.  
  1045.     /* only one slot has pcie device */
  1046. //    if (bus->self && nr)
  1047. //        pcie_aspm_init_link_state(bus->self);
  1048.  
  1049.     return nr;
  1050. }
  1051.  
  1052.  
  1053. unsigned int pci_scan_child_bus(struct pci_bus *bus)
  1054. {
  1055.     unsigned int devfn, pass, max = bus->secondary;
  1056.     struct pci_dev *dev;
  1057.  
  1058.     dbgprintf("scanning bus\n");
  1059.  
  1060.     /* Go find them, Rover! */
  1061.     for (devfn = 0; devfn < 0x100; devfn += 8)
  1062.         pci_scan_slot(bus, devfn);
  1063.  
  1064.     /* Reserve buses for SR-IOV capability. */
  1065.     max += pci_iov_bus_range(bus);
  1066.  
  1067.     /*
  1068.      * After performing arch-dependent fixup of the bus, look behind
  1069.      * all PCI-to-PCI bridges on this bus.
  1070.      */
  1071.     if (!bus->is_added) {
  1072.         dbgprintf("fixups for bus\n");
  1073. //        pcibios_fixup_bus(bus);
  1074.         if (pci_is_root_bus(bus))
  1075.             bus->is_added = 1;
  1076.     }
  1077.  
  1078.     for (pass=0; pass < 2; pass++)
  1079.         list_for_each_entry(dev, &bus->devices, bus_list) {
  1080.             if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
  1081.                 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  1082.                 max = pci_scan_bridge(bus, dev, max, pass);
  1083.         }
  1084.  
  1085.     /*
  1086.      * We've scanned the bus and so we know all about what's on
  1087.      * the other side of any bridges that may be on this bus plus
  1088.      * any devices.
  1089.      *
  1090.      * Return how far we've got finding sub-buses.
  1091.      */
  1092.     dbgprintf("bus scan returning with max=%02x\n", max);
  1093.     return max;
  1094. }
  1095.  
  1096. /**
  1097.  * pci_cfg_space_size - get the configuration space size of the PCI device.
  1098.  * @dev: PCI device
  1099.  *
  1100.  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
  1101.  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
  1102.  * access it.  Maybe we don't have a way to generate extended config space
  1103.  * accesses, or the device is behind a reverse Express bridge.  So we try
  1104.  * reading the dword at 0x100 which must either be 0 or a valid extended
  1105.  * capability header.
  1106.  */
  1107. int pci_cfg_space_size_ext(struct pci_dev *dev)
  1108. {
  1109.     u32 status;
  1110.     int pos = PCI_CFG_SPACE_SIZE;
  1111.  
  1112.     if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
  1113.         goto fail;
  1114.     if (status == 0xffffffff)
  1115.         goto fail;
  1116.  
  1117.     return PCI_CFG_SPACE_EXP_SIZE;
  1118.  
  1119.  fail:
  1120.     return PCI_CFG_SPACE_SIZE;
  1121. }
  1122.  
  1123. int pci_cfg_space_size(struct pci_dev *dev)
  1124. {
  1125.     int pos;
  1126.     u32 status;
  1127.     u16 class;
  1128.  
  1129.     class = dev->class >> 8;
  1130.     if (class == PCI_CLASS_BRIDGE_HOST)
  1131.         return pci_cfg_space_size_ext(dev);
  1132.  
  1133.     pos = pci_pcie_cap(dev);
  1134.     if (!pos) {
  1135.         pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
  1136.         if (!pos)
  1137.             goto fail;
  1138.  
  1139.         pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
  1140.         if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
  1141.             goto fail;
  1142.     }
  1143.  
  1144.     return pci_cfg_space_size_ext(dev);
  1145.  
  1146.  fail:
  1147.     return PCI_CFG_SPACE_SIZE;
  1148. }
  1149.  
  1150.  
  1151.  
  1152. struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata)
  1153. {
  1154.     int error;
  1155.     struct pci_bus *b, *b2;
  1156.  
  1157.     b = pci_alloc_bus();
  1158.     if (!b)
  1159.         return NULL;
  1160.  
  1161.     b->sysdata = sysdata;
  1162.     b->ops = ops;
  1163.  
  1164.     b2 = pci_find_bus(pci_domain_nr(b), bus);
  1165.     if (b2) {
  1166.         /* If we already got to this bus through a different bridge, ignore it */
  1167.         dbgprintf("bus already known\n");
  1168.         goto err_out;
  1169.     }
  1170.  
  1171. //    down_write(&pci_bus_sem);
  1172.     list_add_tail(&b->node, &pci_root_buses);
  1173. //    up_write(&pci_bus_sem);
  1174.  
  1175.     b->number = b->secondary = bus;
  1176.     b->resource[0] = &ioport_resource;
  1177.     b->resource[1] = &iomem_resource;
  1178.  
  1179.     return b;
  1180.  
  1181. err_out:
  1182.     kfree(b);
  1183.     return NULL;
  1184. }
  1185.  
  1186.