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  1. /* Opcode decoder for the Renesas RL78
  2.    Copyright (C) 2011-2015 Free Software Foundation, Inc.
  3.    Written by DJ Delorie <dj@redhat.com>
  4.  
  5.    This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
  6.  
  7.    This program is free software; you can redistribute it and/or modify
  8.    it under the terms of the GNU General Public License as published by
  9.    the Free Software Foundation; either version 3 of the License, or
  10.    (at your option) any later version.
  11.  
  12.    This program is distributed in the hope that it will be useful,
  13.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.    GNU General Public License for more details.
  16.  
  17.    You should have received a copy of the GNU General Public License
  18.    along with this program; if not, write to the Free Software
  19.    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  20.    02110-1301, USA.  */
  21.  
  22. /* The RL78 decoder in libopcodes is used by the simulator, gdb's
  23.    analyzer, and the disassembler.  Given an opcode data source, it
  24.    decodes the next opcode into the following structures.  */
  25.  
  26. #ifndef RL78_OPCODES_H_INCLUDED
  27. #define RL78_OPCODES_H_INCLUDED
  28.  
  29. #ifdef __cplusplus
  30. extern "C" {
  31. #endif
  32.  
  33. typedef enum {
  34.   RL78_ISA_DEFAULT,
  35.   RL78_ISA_G10,
  36.   RL78_ISA_G13,
  37.   RL78_ISA_G14,
  38. } RL78_Dis_Isa;
  39.  
  40. /* For the purposes of these structures, the RL78 registers are as
  41.    follows, despite most of these being memory-mapped and
  42.    bank-switched:  */
  43. typedef enum {
  44.   RL78_Reg_None,
  45.   /* The order of these matches the encodings.  */
  46.   RL78_Reg_X,
  47.   RL78_Reg_A,
  48.   RL78_Reg_C,
  49.   RL78_Reg_B,
  50.   RL78_Reg_E,
  51.   RL78_Reg_D,
  52.   RL78_Reg_L,
  53.   RL78_Reg_H,
  54.   /* The order of these matches the encodings.  */
  55.   RL78_Reg_AX,
  56.   RL78_Reg_BC,
  57.   RL78_Reg_DE,
  58.   RL78_Reg_HL,
  59.   /* Unordered.  */
  60.   RL78_Reg_SP,
  61.   RL78_Reg_PSW,
  62.   RL78_Reg_CS,
  63.   RL78_Reg_ES,
  64.   RL78_Reg_PMC,
  65.   RL78_Reg_MEM
  66. } RL78_Register;
  67.  
  68. typedef enum
  69. {
  70.   RL78_Byte = 0,
  71.   RL78_Word
  72. } RL78_Size;
  73.  
  74. typedef enum {
  75.   RL78_Condition_T,
  76.   RL78_Condition_F,
  77.   RL78_Condition_C,
  78.   RL78_Condition_NC,
  79.   RL78_Condition_H,
  80.   RL78_Condition_NH,
  81.   RL78_Condition_Z,
  82.   RL78_Condition_NZ
  83. } RL78_Condition;
  84.  
  85. typedef enum {
  86.   RL78_Operand_None = 0,
  87.   RL78_Operand_Immediate,       /* #addend */
  88.   RL78_Operand_Register,        /* reg */
  89.   RL78_Operand_Indirect,        /* [reg + reg2 + addend] */
  90.   RL78_Operand_Bit,             /* reg.bit */
  91.   RL78_Operand_BitIndirect,     /* [reg+reg2+addend].bit */
  92.   RL78_Operand_PreDec,          /* [--reg] = push */
  93.   RL78_Operand_PostInc          /* [reg++] = pop */
  94. } RL78_Operand_Type;
  95.  
  96. typedef enum
  97. {
  98.   RLO_unknown,
  99.   RLO_add,                      /* d += s */
  100.   RLO_addc,                     /* d += s + CY */
  101.   RLO_and,                      /* d &= s (byte, word, bit) */
  102.   RLO_branch,                   /* pc = d */
  103.   RLO_branch_cond,              /* pc = d if cond(src) */
  104.   RLO_branch_cond_clear,        /* pc = d if cond(src), and clear(src) */
  105.   RLO_break,                    /* BRK */
  106.   RLO_call,                     /* call */
  107.   RLO_cmp,                      /* cmp d, s */
  108.   RLO_divhu,                    /* DIVHU */
  109.   RLO_divwu,                    /* DIVWU */
  110.   RLO_halt,                     /* HALT */
  111.   RLO_mov,                      /* d = s */
  112.   RLO_mach,                     /* MACH */
  113.   RLO_machu,                    /* MACHU */
  114.   RLO_mulu,                     /* MULU */
  115.   RLO_mulh,                     /* MULH */
  116.   RLO_mulhu,                    /* MULHU */
  117.   RLO_nop,                      /* NOP */
  118.   RLO_or,                       /* d |= s */
  119.   RLO_ret,                      /* RET */
  120.   RLO_reti,                     /* RETI */
  121.   RLO_rol,                      /* d <<= s, MSB to LSB and CY */
  122.   RLO_rolc,                     /* d <<= s, MSB to CY, CY, to LSB */
  123.   RLO_ror,                      /* d >>= s, LSB to MSB and CY */
  124.   RLO_rorc,                     /* d >>= s, LSB to CY, CY, to MSB */
  125.   RLO_sar,                      /* d >>= s, signed */
  126.   RLO_sel,                      /* rb = s */
  127.   RLO_shr,                      /* d >>= s, unsigned */
  128.   RLO_shl,                      /* d <<= s */
  129.   RLO_skip,                     /* skip next insn is cond(s) */
  130.   RLO_stop,                     /* STOP */
  131.   RLO_sub,                      /* d -= s */
  132.   RLO_subc,                     /* d -= s - CY */
  133.   RLO_xch,                      /* swap d, s  */
  134.   RLO_xor,                      /* d ^= s */
  135. } RL78_Opcode_ID;
  136.  
  137. typedef struct {
  138.   RL78_Operand_Type  type;
  139.   int              addend;
  140.   RL78_Register    reg : 8;
  141.   RL78_Register    reg2 : 8;
  142.   unsigned char    bit_number : 4;
  143.   unsigned char    condition : 3;
  144.   unsigned char    use_es : 1;
  145. } RL78_Opcode_Operand;
  146.  
  147. /* PSW flag bits */
  148. #define RL78_PSW_IE     0x80
  149. #define RL78_PSW_Z      0x40
  150. #define RL78_PSW_RBS1   0x20
  151. #define RL78_PSW_AC     0x10
  152. #define RL78_PSW_RBS0   0x08
  153. #define RL78_PSW_ISP1   0x04
  154. #define RL78_PSW_ISP0   0x02
  155. #define RL78_PSW_CY     0x01
  156.  
  157. #define RL78_SFR_SP     0xffff8
  158. #define RL78_SFR_PSW    0xffffa
  159. #define RL78_SFR_CS     0xffffc
  160. #define RL78_SFR_ES     0xffffd
  161. #define RL78_SFR_PMC    0xffffe
  162. #define RL78_SFR_MEM    0xfffff
  163.  
  164. typedef struct
  165. {
  166.   int lineno;
  167.   RL78_Opcode_ID        id:24;
  168.   unsigned              flags:8; /* PSW mask, for side effects only */
  169.   int                   n_bytes;
  170.   char *                syntax;
  171.   RL78_Size             size;
  172.   /* By convention, these are destination, source.  */
  173.   RL78_Opcode_Operand   op[2];
  174. } RL78_Opcode_Decoded;
  175.  
  176. int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa);
  177.  
  178. #ifdef __cplusplus
  179. }
  180. #endif
  181.  
  182. #endif
  183.