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  1. ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
  2. ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny26.xml ************
  3. ;*************************************************************************
  4. ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
  5. ;*
  6. ;* Number            : AVR000
  7. ;* File Name         : "tn26def.inc"
  8. ;* Title             : Register/Bit Definitions for the ATtiny26
  9. ;* Date              : 2005-01-11
  10. ;* Version           : 2.14
  11. ;* Support E-mail    : avr@atmel.com
  12. ;* Target MCU        : ATtiny26
  13. ;*
  14. ;* DESCRIPTION
  15. ;* When including this file in the assembly program file, all I/O register
  16. ;* names and I/O register bit names appearing in the data book can be used.
  17. ;* In addition, the six registers forming the three data pointers X, Y and
  18. ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
  19. ;* SRAM is also defined
  20. ;*
  21. ;* The Register names are represented by their hexadecimal address.
  22. ;*
  23. ;* The Register Bit names are represented by their bit number (0-7).
  24. ;*
  25. ;* Please observe the difference in using the bit names with instructions
  26. ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
  27. ;* (skip if bit in register set/cleared). The following example illustrates
  28. ;* this:
  29. ;*
  30. ;* in    r16,PORTB             ;read PORTB latch
  31. ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
  32. ;* out   PORTB,r16             ;output to PORTB
  33. ;*
  34. ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
  35. ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
  36. ;* rjmp  TOV0_is_set           ;jump if set
  37. ;* ...                         ;otherwise do something else
  38. ;*************************************************************************
  39.  
  40. #ifndef _TN26DEF_INC_
  41. #define _TN26DEF_INC_
  42.  
  43.  
  44. #pragma partinc 0
  45.  
  46. ; ***** SPECIFY DEVICE ***************************************************
  47. .device ATtiny26
  48. #pragma AVRPART ADMIN PART_NAME ATtiny26
  49. .equ    SIGNATURE_000   = 0x1e
  50. .equ    SIGNATURE_001   = 0x91
  51. .equ    SIGNATURE_002   = 0x09
  52.  
  53. #pragma AVRPART CORE CORE_VERSION V1
  54. #pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z
  55.  
  56.  
  57. ; ***** I/O REGISTER DEFINITIONS *****************************************
  58. ; NOTE:
  59. ; Definitions marked "MEMORY MAPPED"are extended I/O ports
  60. ; and cannot be used with IN/OUT instructions
  61. .equ    SREG    = 0x3f
  62. .equ    SP      = 0x3d
  63. .equ    GIMSK   = 0x3b
  64. .equ    GIFR    = 0x3a
  65. .equ    TIMSK   = 0x39
  66. .equ    TIFR    = 0x38
  67. .equ    MCUCR   = 0x35
  68. .equ    MCUSR   = 0x34
  69. .equ    TCCR0   = 0x33
  70. .equ    TCNT0   = 0x32
  71. .equ    OSCCAL  = 0x31
  72. .equ    TCCR1A  = 0x30
  73. .equ    TCCR1B  = 0x2f
  74. .equ    TCNT1   = 0x2e
  75. .equ    OCR1A   = 0x2d
  76. .equ    OCR1B   = 0x2c
  77. .equ    OCR1C   = 0x2b
  78. .equ    PLLCSR  = 0x29
  79. .equ    WDTCR   = 0x21
  80. .equ    EEAR    = 0x1e
  81. .equ    EEDR    = 0x1d
  82. .equ    EECR    = 0x1c
  83. .equ    PORTA   = 0x1b
  84. .equ    DDRA    = 0x1a
  85. .equ    PINA    = 0x19
  86. .equ    PORTB   = 0x18
  87. .equ    DDRB    = 0x17
  88. .equ    PINB    = 0x16
  89. .equ    USIDR   = 0x0f
  90. .equ    USISR   = 0x0e
  91. .equ    USICR   = 0x0d
  92. .equ    ACSR    = 0x08
  93. .equ    ADMUX   = 0x07
  94. .equ    ADCSRA  = 0x06
  95. .equ    ADCH    = 0x05
  96. .equ    ADCL    = 0x04
  97.  
  98.  
  99. ; ***** BIT DEFINITIONS **************************************************
  100.  
  101. ; ***** AD_CONVERTER *****************
  102. ; ADMUX - The ADC multiplexer Selection Register
  103. .equ    MUX0    = 0     ; Analog Channel and Gain Selection Bits
  104. .equ    MUX1    = 1     ; Analog Channel and Gain Selection Bits
  105. .equ    MUX2    = 2     ; Analog Channel and Gain Selection Bits
  106. .equ    MUX3    = 3     ; Analog Channel and Gain Selection Bits
  107. .equ    MUX4    = 4     ; Analog Channel and Gain Selection Bits
  108. .equ    ADLAR   = 5     ; Left Adjust Result
  109. .equ    REFS0   = 6     ; Reference Selection Bit 0
  110. .equ    REFS1   = 7     ; Reference Selection Bit 1
  111.  
  112. ; ADCSRA - The ADC Control and Status register
  113. .equ    ADCSR   = ADCSRA        ; For compatibility
  114. .equ    ADPS0   = 0     ; ADC  Prescaler Select Bits
  115. .equ    ADPS1   = 1     ; ADC  Prescaler Select Bits
  116. .equ    ADPS2   = 2     ; ADC  Prescaler Select Bits
  117. .equ    ADIE    = 3     ; ADC Interrupt Enable
  118. .equ    ADIF    = 4     ; ADC Interrupt Flag
  119. .equ    ADFR    = 5     ; ADC  Free Running Select
  120. .equ    ADSC    = 6     ; ADC Start Conversion
  121. .equ    ADEN    = 7     ; ADC Enable
  122.  
  123. ; ADCH - ADC Data Register High Byte
  124. .equ    ADCH0   = 0     ; ADC Data Register High Byte Bit 0
  125. .equ    ADCH1   = 1     ; ADC Data Register High Byte Bit 1
  126. .equ    ADCH2   = 2     ; ADC Data Register High Byte Bit 2
  127. .equ    ADCH3   = 3     ; ADC Data Register High Byte Bit 3
  128. .equ    ADCH4   = 4     ; ADC Data Register High Byte Bit 4
  129. .equ    ADCH5   = 5     ; ADC Data Register High Byte Bit 5
  130. .equ    ADCH6   = 6     ; ADC Data Register High Byte Bit 6
  131. .equ    ADCH7   = 7     ; ADC Data Register High Byte Bit 7
  132.  
  133. ; ADCL - ADC Data Register Low Byte
  134. .equ    ADCL0   = 0     ; ADC Data Register Low Byte Bit 0
  135. .equ    ADCL1   = 1     ; ADC Data Register Low Byte Bit 1
  136. .equ    ADCL2   = 2     ; ADC Data Register Low Byte Bit 2
  137. .equ    ADCL3   = 3     ; ADC Data Register Low Byte Bit 3
  138. .equ    ADCL4   = 4     ; ADC Data Register Low Byte Bit 4
  139. .equ    ADCL5   = 5     ; ADC Data Register Low Byte Bit 5
  140. .equ    ADCL6   = 6     ; ADC Data Register Low Byte Bit 6
  141. .equ    ADCL7   = 7     ; ADC Data Register Low Byte Bit 7
  142.  
  143.  
  144. ; ***** ANALOG_COMPARATOR ************
  145. ; ACSR - Analog Comparator Control And Status Register
  146. .equ    ACIS0   = 0     ; Analog Comparator Interrupt Mode Select bit 0
  147. .equ    ACIS1   = 1     ; Analog Comparator Interrupt Mode Select bit 1
  148. .equ    ACME    = 2     ; Analog Comparator Multiplexer Enable
  149. .equ    ACIE    = 3     ; Analog Comparator Interrupt Enable
  150. .equ    ACI     = 4     ; Analog Comparator Interrupt Flag
  151. .equ    ACO     = 5     ; Analog Compare Output
  152. .equ    ACBG    = 6     ; Analog Comparator Bandgap Select
  153. .equ    ACD     = 7     ; Analog Comparator Disable
  154.  
  155.  
  156. ; ***** USI **************************
  157. ; USIDR - USI Data Register
  158. .equ    USIDR0  = 0     ; USI Data Register bit 0
  159. .equ    USIDR1  = 1     ; USI Data Register bit 1
  160. .equ    USIDR2  = 2     ; USI Data Register bit 2
  161. .equ    USIDR3  = 3     ; USI Data Register bit 3
  162. .equ    USIDR4  = 4     ; USI Data Register bit 4
  163. .equ    USIDR5  = 5     ; USI Data Register bit 5
  164. .equ    USIDR6  = 6     ; USI Data Register bit 6
  165. .equ    USIDR7  = 7     ; USI Data Register bit 7
  166.  
  167. ; USISR - USI Status Register
  168. .equ    USICNT0 = 0     ; USI Counter Value Bit 0
  169. .equ    USICNT1 = 1     ; USI Counter Value Bit 1
  170. .equ    USICNT2 = 2     ; USI Counter Value Bit 2
  171. .equ    USICNT3 = 3     ; USI Counter Value Bit 3
  172. .equ    USIDC   = 4     ; Data Output Collision
  173. .equ    USIPF   = 5     ; Stop Condition Flag
  174. .equ    USIOIF  = 6     ; Counter Overflow Interrupt Flag
  175. .equ    USISIF  = 7     ; Start Condition Interrupt Flag
  176.  
  177. ; USICR - USI Control Register
  178. .equ    USITC   = 0     ; Toggle Clock Port Pin
  179. .equ    USICLK  = 1     ; Clock Strobe
  180. .equ    USICS0  = 2     ; USI Clock Source Select Bit 0
  181. .equ    USICS1  = 3     ; USI Clock Source Select Bit 1
  182. .equ    USIWM0  = 4     ; USI Wire Mode Bit 0
  183. .equ    USIWM1  = 5     ; USI Wire Mode Bit 1
  184. .equ    USIOIE  = 6     ; Counter Overflow Interrupt Enable
  185. .equ    USISIE  = 7     ; Start Condition Interrupt Enable
  186.  
  187.  
  188. ; ***** PORTA ************************
  189. ; PORTA - Port A Data Register
  190. .equ    PORTA0  = 0     ; Port A Data Register bit 0
  191. .equ    PA0     = 0     ; For compatibility
  192. .equ    PORTA1  = 1     ; Port A Data Register bit 1
  193. .equ    PA1     = 1     ; For compatibility
  194. .equ    PORTA2  = 2     ; Port A Data Register bit 2
  195. .equ    PA2     = 2     ; For compatibility
  196. .equ    PORTA3  = 3     ; Port A Data Register bit 3
  197. .equ    PA3     = 3     ; For compatibility
  198. .equ    PORTA4  = 4     ; Port A Data Register bit 4
  199. .equ    PA4     = 4     ; For compatibility
  200. .equ    PORTA5  = 5     ; Port A Data Register bit 5
  201. .equ    PA5     = 5     ; For compatibility
  202. .equ    PORTA6  = 6     ; Port A Data Register bit 6
  203. .equ    PA6     = 6     ; For compatibility
  204. .equ    PORTA7  = 7     ; Port A Data Register bit 7
  205. .equ    PA7     = 7     ; For compatibility
  206.  
  207. ; DDRA - Port A Data Direction Register
  208. .equ    DDA0    = 0     ; Data Direction Register, Port A, bit 0
  209. .equ    DDA1    = 1     ; Data Direction Register, Port A, bit 1
  210. .equ    DDA2    = 2     ; Data Direction Register, Port A, bit 2
  211. .equ    DDA3    = 3     ; Data Direction Register, Port A, bit 3
  212. .equ    DDA4    = 4     ; Data Direction Register, Port A, bit 4
  213. .equ    DDA5    = 5     ; Data Direction Register, Port A, bit 5
  214. .equ    DDA6    = 6     ; Data Direction Register, Port A, bit 6
  215. .equ    DDA7    = 7     ; Data Direction Register, Port A, bit 7
  216.  
  217. ; PINA - Port A Input Pins
  218. .equ    PINA0   = 0     ; Input Pins, Port A bit 0
  219. .equ    PINA1   = 1     ; Input Pins, Port A bit 1
  220. .equ    PINA2   = 2     ; Input Pins, Port A bit 2
  221. .equ    PINA3   = 3     ; Input Pins, Port A bit 3
  222. .equ    PINA4   = 4     ; Input Pins, Port A bit 4
  223. .equ    PINA5   = 5     ; Input Pins, Port A bit 5
  224. .equ    PINA6   = 6     ; Input Pins, Port A bit 6
  225. .equ    PINA7   = 7     ; Input Pins, Port A bit 7
  226.  
  227.  
  228. ; ***** PORTB ************************
  229. ; PORTB - Port B Data Register
  230. .equ    PORTB0  = 0     ; Port B Data Register bit 0
  231. .equ    PB0     = 0     ; For compatibility
  232. .equ    PORTB1  = 1     ; Port B Data Register bit 1
  233. .equ    PB1     = 1     ; For compatibility
  234. .equ    PORTB2  = 2     ; Port B Data Register bit 2
  235. .equ    PB2     = 2     ; For compatibility
  236. .equ    PORTB3  = 3     ; Port B Data Register bit 3
  237. .equ    PB3     = 3     ; For compatibility
  238. .equ    PORTB4  = 4     ; Port B Data Register bit 4
  239. .equ    PB4     = 4     ; For compatibility
  240. .equ    PORTB5  = 5     ; Port B Data Register bit 5
  241. .equ    PB5     = 5     ; For compatibility
  242. .equ    PORTB6  = 6     ; Port B Data Register bit 6
  243. .equ    PB6     = 6     ; For compatibility
  244. .equ    PORTB7  = 7     ; Port B Data Register bit 7
  245. .equ    PB7     = 7     ; For compatibility
  246.  
  247. ; DDRB - Port B Data Direction Register
  248. .equ    DDB0    = 0     ; Port B Data Direction Register bit 0
  249. .equ    DDB1    = 1     ; Port B Data Direction Register bit 1
  250. .equ    DDB2    = 2     ; Port B Data Direction Register bit 2
  251. .equ    DDB3    = 3     ; Port B Data Direction Register bit 3
  252. .equ    DDB4    = 4     ; Port B Data Direction Register bit 4
  253. .equ    DDB5    = 5     ; Port B Data Direction Register bit 5
  254. .equ    DDB6    = 6     ; Port B Data Direction Register bit 6
  255. .equ    DDB7    = 7     ; Port B Data Direction Register bit 7
  256.  
  257. ; PINB - Port B Input Pins
  258. .equ    PINB0   = 0     ; Port B Input Pins bit 0
  259. .equ    PINB1   = 1     ; Port B Input Pins bit 1
  260. .equ    PINB2   = 2     ; Port B Input Pins bit 2
  261. .equ    PINB3   = 3     ; Port B Input Pins bit 3
  262. .equ    PINB4   = 4     ; Port B Input Pins bit 4
  263. .equ    PINB5   = 5     ; Port B Input Pins bit 5
  264. .equ    PINB6   = 6     ; Port B Input Pins bit 6
  265. .equ    PINB7   = 7     ; Port B Input Pins bit 7
  266.  
  267.  
  268. ; ***** EEPROM ***********************
  269. ; EEAR - EEPROM Read/Write Access
  270. .equ    EEAR0   = 0     ; EEPROM Read/Write Access bit 0
  271. .equ    EEAR1   = 1     ; EEPROM Read/Write Access bit 1
  272. .equ    EEAR2   = 2     ; EEPROM Read/Write Access bit 2
  273. .equ    EEAR3   = 3     ; EEPROM Read/Write Access bit 3
  274. .equ    EEAR4   = 4     ; EEPROM Read/Write Access bit 4
  275. .equ    EEAR5   = 5     ; EEPROM Read/Write Access bit 5
  276. .equ    EEAR6   = 6     ; EEPROM Read/Write Access bit 6
  277.  
  278. ; EEDR - EEPROM Data Register
  279. .equ    EEDR0   = 0     ; EEPROM Data Register bit 0
  280. .equ    EEDR1   = 1     ; EEPROM Data Register bit 1
  281. .equ    EEDR2   = 2     ; EEPROM Data Register bit 2
  282. .equ    EEDR3   = 3     ; EEPROM Data Register bit 3
  283. .equ    EEDR4   = 4     ; EEPROM Data Register bit 4
  284. .equ    EEDR5   = 5     ; EEPROM Data Register bit 5
  285. .equ    EEDR6   = 6     ; EEPROM Data Register bit 6
  286. .equ    EEDR7   = 7     ; EEPROM Data Register bit 7
  287.  
  288. ; EECR - EEPROM Control Register
  289. .equ    EERE    = 0     ; EEPROM Read Enable
  290. .equ    EEWE    = 1     ; EEPROM Write Enable
  291. .equ    EEMWE   = 2     ; EEPROM Master Write Enable
  292. .equ    EERIE   = 3     ; EEProm Ready Interrupt Enable
  293.  
  294.  
  295. ; ***** WATCHDOG *********************
  296. ; WDTCR - Watchdog Timer Control Register
  297. .equ    WDTCSR  = WDTCR ; For compatibility
  298. .equ    WDP0    = 0     ; Watch Dog Timer Prescaler bit 0
  299. .equ    WDP1    = 1     ; Watch Dog Timer Prescaler bit 1
  300. .equ    WDP2    = 2     ; Watch Dog Timer Prescaler bit 2
  301. .equ    WDE     = 3     ; Watch Dog Enable
  302. .equ    WDCE    = 4     ; Watchdog Change Enable
  303. .equ    WDTOE   = WDCE  ; For compatibility
  304.  
  305.  
  306. ; ***** CPU **************************
  307. ; SREG - Status Register
  308. .equ    SREG_C  = 0     ; Carry Flag
  309. .equ    SREG_Z  = 1     ; Zero Flag
  310. .equ    SREG_N  = 2     ; Negative Flag
  311. .equ    SREG_V  = 3     ; Two's Complement Overflow Flag
  312. .equ    SREG_S  = 4     ; Sign Bit
  313. .equ    SREG_H  = 5     ; Half Carry Flag
  314. .equ    SREG_T  = 6     ; Bit Copy Storage
  315. .equ    SREG_I  = 7     ; Global Interrupt Enable
  316.  
  317. ; SP - Stack Pointer
  318. .equ    SP0     = 0     ; Stack Pointer Bit 0
  319. .equ    SP1     = 1     ; Stack Pointer Bit 1
  320. .equ    SP2     = 2     ; Stack Pointer Bit 2
  321. .equ    SP3     = 3     ; Stack Pointer Bit 3
  322. .equ    SP4     = 4
  323. .equ    SP5     = 5     ; Stack Pointer Bit 5
  324. .equ    SP6     = 6     ; Stack Pointer Bit 6
  325. .equ    SP7     = 7     ; Stack Pointer Bit 7
  326.  
  327. ; MCUCR - MCU Control Register
  328. .equ    ISC00   = 0     ; Interrupt Sense Control 0 bit 0
  329. .equ    ISC01   = 1     ; Interrupt Sense Control 0 bit 1
  330. .equ    SM0     = 3     ; Sleep Mode Select Bit 0
  331. .equ    SM1     = 4     ; Sleep Mode Select Bit 1
  332. .equ    SE      = 5     ; Sleep Enable
  333. .equ    PUD     = 6     ; Pull-up Disable
  334.  
  335. ; MCUSR - MCU Status register
  336. .equ    PORF    = 0     ; Power-On Reset Flag
  337. .equ    EXTRF   = 1     ; External Reset Flag
  338. .equ    BORF    = 2     ; Brown-out Reset Flag
  339. .equ    WDRF    = 3     ; Watchdog Reset Flag
  340.  
  341. ; OSCCAL - Status Register
  342. .equ    CAL0    = 0     ; Oscillator Calibration Value Bit 0
  343. .equ    OSCCAL0 = CAL0  ; For compatibility
  344. .equ    CAL1    = 1     ; Oscillator Calibration Value Bit 1
  345. .equ    OSCCAL1 = CAL1  ; For compatibility
  346. .equ    CAL2    = 2     ; Oscillator Calibration Value Bit 2
  347. .equ    OSCCAL2 = CAL2  ; For compatibility
  348. .equ    CAL3    = 3     ; Oscillator Calibration Value Bit 3
  349. .equ    OSCCAL3 = CAL3  ; For compatibility
  350. .equ    CAL4    = 4
  351. .equ    OSCCAL4 = CAL4  ; For compatibility
  352. .equ    CAL5    = 5     ; Oscillator Calibration Value Bit 5
  353. .equ    CAL6    = 6     ; Oscillator Calibration Value Bit 6
  354. .equ    CAL7    = 7     ; Oscillator Calibration Value Bit 7
  355.  
  356.  
  357. ; ***** TIMER_COUNTER_0 **************
  358. ; TIMSK - Timer/Counter Interrupt Mask Register
  359. .equ    TOIE0   = 1     ; Timer/Counter0 Overflow Interrupt Enable
  360.  
  361. ; TIFR - Timer/Counter Interrupt Flag register
  362. .equ    TOV0    = 1     ; Timer/Counter0 Overflow Flag
  363.  
  364. ; TCCR0 - Timer/Counter0 Control Register
  365. .equ    CS00    = 0     ; Clock Select0 bit 0
  366. .equ    CS01    = 1     ; Clock Select0 bit 1
  367. .equ    CS02    = 2     ; Clock Select0 bit 2
  368. .equ    PSR0    = 3     ; Prescaler Reset Timer/Counter0
  369.  
  370. ; TCNT0 - Timer Counter 0
  371. .equ    TCNT00  = 0     ; Timer Counter 0 bit 0
  372. .equ    TCNT01  = 1     ; Timer Counter 0 bit 1
  373. .equ    TCNT02  = 2     ; Timer Counter 0 bit 2
  374. .equ    TCNT03  = 3     ; Timer Counter 0 bit 3
  375. .equ    TCNT04  = 4     ; Timer Counter 0 bit 4
  376. .equ    TCNT05  = 5     ; Timer Counter 0 bit 5
  377. .equ    TCNT06  = 6     ; Timer Counter 0 bit 6
  378. .equ    TCNT07  = 7     ; Timer Counter 0 bit 7
  379.  
  380.  
  381. ; ***** TIMER_COUNTER_1 **************
  382. ; TCCR1A - Timer/Counter Control Register A
  383. .equ    PWM1B   = 0     ; Pulse Width Modulator B Enable
  384. .equ    PWM1A   = 1     ; Pulse Width Modulator A Enable
  385. .equ    FOC1B   = 2     ; Force Output Compare Match 1B
  386. .equ    FOC1A   = 3     ; Force Output Compare Match 1A
  387. .equ    COM1B0  = 4     ; Comparator B Output Mode Bit 0
  388. .equ    COM1B1  = 5     ; Comparator B Output Mode Bit 1
  389. .equ    COM1A0  = 6     ; Comparator A Output Mode Bit 0
  390. .equ    COM1A1  = 7     ; Comparator A Output Mode Bit 1
  391.  
  392. ; TCCR1B - Timer/Counter Control Register B
  393. .equ    CS10    = 0     ; Clock Select Bits
  394. .equ    CS11    = 1     ; Clock Select Bits
  395. .equ    CS12    = 2     ; Clock Select Bits
  396. .equ    CS13    = 3     ; Clock Select Bits
  397. .equ    PSR1    = 6     ; Prescaler Reset Timer/Counter1
  398. .equ    CTC1    = 7     ; Clear Timer/Counter on Compare Match
  399.  
  400. ; TCNT1 - Timer/Counter Register
  401. .equ    TCNT1_0 = 0     ; Timer/Counter Register Bit 0
  402. .equ    TCNT1_1 = 1     ; Timer/Counter Register Bit 1
  403. .equ    TCNT1_2 = 2     ; Timer/Counter Register Bit 2
  404. .equ    TCNT1_3 = 3     ; Timer/Counter Register Bit 3
  405. .equ    TCNT1_4 = 4     ; Timer/Counter Register Bit 4
  406. .equ    TCNT1_5 = 5     ; Timer/Counter Register Bit 5
  407. .equ    TCNT1_6 = 6     ; Timer/Counter Register Bit 6
  408. .equ    TCNT1_7 = 7     ; Timer/Counter Register Bit 7
  409.  
  410. ; OCR1A - Output Compare Register
  411. .equ    OCR1A0  = 0     ; Output Compare Register A Bit 0
  412. .equ    OCR1A1  = 1     ; Output Compare Register A Bit 1
  413. .equ    OCR1A2  = 2     ; Output Compare Register A Bit 2
  414. .equ    OCR1A3  = 3     ; Output Compare Register A Bit 3
  415. .equ    OCR1A4  = 4     ; Output Compare Register A Bit 4
  416. .equ    OCR1A5  = 5     ; Output Compare Register A Bit 5
  417. .equ    OCR1A6  = 6     ; Output Compare Register A Bit 6
  418. .equ    OCR1A7  = 7     ; Output Compare Register A Bit 7
  419.  
  420. ; OCR1B - Output Compare Register
  421. .equ    OCR1B0  = 0     ; Output Compare Register B Bit 0
  422. .equ    OCR1B1  = 1     ; Output Compare Register B Bit 1
  423. .equ    OCR1B2  = 2     ; Output Compare Register B Bit 2
  424. .equ    OCR1B3  = 3     ; Output Compare Register B Bit 3
  425. .equ    OCR1B4  = 4     ; Output Compare Register B Bit 4
  426. .equ    OCR1B5  = 5     ; Output Compare Register B Bit 5
  427. .equ    OCR1B6  = 6     ; Output Compare Register B Bit 6
  428. .equ    OCR1B7  = 7     ; Output Compare Register B Bit 7
  429.  
  430. ; OCR1C - Output Compare Register
  431. .equ    OCR1C0  = 0     ; Output Compare Register C Bit 0
  432. .equ    OCR1C1  = 1     ; Output Compare Register C Bit 1
  433. .equ    OCR1C2  = 2     ; Output Compare Register C Bit 2
  434. .equ    OCR1C3  = 3     ; Output Compare Register C Bit 3
  435. .equ    OCR1C4  = 4     ; Output Compare Register C Bit 4
  436. .equ    OCR1C5  = 5     ; Output Compare Register C Bit 5
  437. .equ    OCR1C6  = 6     ; Output Compare Register C Bit 6
  438. .equ    OCR1C7  = 7     ; Output Compare Register C Bit 7
  439.  
  440. ; TIMSK - Timer/Counter Interrupt Mask Register
  441. ;.equ   TOIE0   = 1     ; Timer/Counter1 Overflow Interrupt Enable
  442. .equ    TOIE1   = 2     ; Timer/Counter1 Overflow Interrupt Enable
  443. .equ    OCIE1B  = 5     ; Timer/Counter1 Output Compare Interrupt Enable
  444. .equ    OCIE1A  = 6     ; Timer/Counter1 Output Compare Interrupt Enable
  445.  
  446. ; TIFR - Timer/Counter Interrupt Flag Register
  447. .equ    TOV1    = 2     ; Timer/Counter1 Overflow Flag
  448. .equ    OCF1B   = 5     ; Timer/Counter1 Output Compare Flag 1B
  449. .equ    OCF1A   = 6     ; Timer/Counter1 Output Compare Flag 1A
  450.  
  451. ; PLLCSR - PLL Control and Status Register
  452. .equ    PLOCK   = 0     ; PLL Lock Detector
  453. .equ    PLLE    = 1     ; PLL Enable
  454. .equ    PCKE    = 2     ; PCK Enable
  455.  
  456.  
  457. ; ***** EXTERNAL_INTERRUPT ***********
  458. ; GIMSK - General Interrupt Mask Register
  459. .equ    PCIE0   = 4     ; Pin Change Interrupt Enable 0
  460. .equ    PCIE1   = 5     ; Pin Change Interrupt Enable 1
  461. .equ    INT0    = 6     ; External Interrupt Request 0 Enable
  462.  
  463. ; GIFR - General Interrupt Flag register
  464. .equ    PCIF    = 5     ; Pin Change Interrupt Flag
  465. .equ    INTF0   = 6     ; External Interrupt Flag 0
  466.  
  467.  
  468.  
  469. ; ***** LOCKSBITS ********************************************************
  470. .equ    LB1     = 0     ; Lockbit
  471. .equ    LB2     = 1     ; Lockbit
  472.  
  473.  
  474. ; ***** FUSES ************************************************************
  475. ; LOW fuse bits
  476. .equ    CKSEL0  = 0     ; Select Clock Source
  477. .equ    CKSEL1  = 1     ; Select Clock Source
  478. .equ    CKSEL2  = 2     ; Select Clock Source
  479. .equ    CKSEL3  = 3     ; Select Clock Source
  480. .equ    SUT0    = 4     ; Select start-up time
  481. .equ    SUT1    = 5     ; Select start-up time
  482. .equ    CKOPT   = 6     ; Oscillator options
  483. .equ    PLLCK   = 7     ; Use PLL for internal clock
  484.  
  485. ; HIGH fuse bits
  486. .equ    BODEN   = 0     ; Brown out detector enable
  487. .equ    BODLEVEL        = 1     ; Brown out detector trigger level
  488. .equ    EESAVE  = 2     ; EEPROM memory is preserved through the Chip Erase
  489. .equ    SPIEN   = 3     ; Enable Serial Program and Data Downloading
  490. .equ    RSTDISBL        = 4     ; Select if PB/ is I/O pin or RESET pin
  491.  
  492.  
  493.  
  494. ; ***** CPU REGISTER DEFINITIONS *****************************************
  495. .def    XH      = r27
  496. .def    XL      = r26
  497. .def    YH      = r29
  498. .def    YL      = r28
  499. .def    ZH      = r31
  500. .def    ZL      = r30
  501.  
  502.  
  503.  
  504. ; ***** DATA MEMORY DECLARATIONS *****************************************
  505. .equ    FLASHEND        = 0x03ff        ; Note: Word address
  506. .equ    IOEND   = 0x003f
  507. .equ    SRAM_START      = 0x0060
  508. .equ    SRAM_SIZE       = 128
  509. .equ    RAMEND  = 0x00df
  510. .equ    XRAMEND = 0x0000
  511. .equ    E2END   = 0x007f
  512. .equ    EEPROMEND       = 0x007f
  513. .equ    EEADRBITS       = 7
  514. #pragma AVRPART MEMORY PROG_FLASH 2048
  515. #pragma AVRPART MEMORY EEPROM 128
  516. #pragma AVRPART MEMORY INT_SRAM SIZE 128
  517. #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
  518.  
  519.  
  520.  
  521.  
  522.  
  523. ; ***** INTERRUPT VECTORS ************************************************
  524. .equ    INT0addr        = 0x0001        ; External Interrupt 0
  525. .equ    PCI0addr        = 0x0002        ; External Interrupt Request 0
  526. .equ    OC1Aaddr        = 0x0003        ; Timer/Counter1 Compare Match 1A
  527. .equ    OC1Baddr        = 0x0004        ; Timer/Counter1 Compare Match 1B
  528. .equ    OVF1addr        = 0x0005        ; Timer/Counter1 Overflow
  529. .equ    OVF0addr        = 0x0006        ; Timer/Counter0 Overflow
  530. .equ    USI_STARTaddr   = 0x0007        ; USI Start
  531. .equ    USI_OVFaddr     = 0x0008        ; USI Overflow
  532. .equ    ERDYaddr        = 0x0009        ; EEPROM Ready
  533. .equ    ACIaddr = 0x000a        ; Analog Comparator
  534. .equ    ADCCaddr        = 0x000b        ; ADC Conversion Complete
  535.  
  536. .equ    INT_VECTORS_SIZE        = 12    ; size in words
  537.  
  538. #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
  539.  
  540. #endif  /* _TN26DEF_INC_ */
  541.  
  542. ; ***** END OF FILE ******************************************************
  543.