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  1. ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
  2. ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny12.xml ************
  3. ;*************************************************************************
  4. ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
  5. ;*
  6. ;* Number            : AVR000
  7. ;* File Name         : "tn12def.inc"
  8. ;* Title             : Register/Bit Definitions for the ATtiny12
  9. ;* Date              : 2005-01-11
  10. ;* Version           : 2.14
  11. ;* Support E-mail    : avr@atmel.com
  12. ;* Target MCU        : ATtiny12
  13. ;*
  14. ;* DESCRIPTION
  15. ;* When including this file in the assembly program file, all I/O register
  16. ;* names and I/O register bit names appearing in the data book can be used.
  17. ;* In addition, the six registers forming the three data pointers X, Y and
  18. ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
  19. ;* SRAM is also defined
  20. ;*
  21. ;* The Register names are represented by their hexadecimal address.
  22. ;*
  23. ;* The Register Bit names are represented by their bit number (0-7).
  24. ;*
  25. ;* Please observe the difference in using the bit names with instructions
  26. ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
  27. ;* (skip if bit in register set/cleared). The following example illustrates
  28. ;* this:
  29. ;*
  30. ;* in    r16,PORTB             ;read PORTB latch
  31. ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
  32. ;* out   PORTB,r16             ;output to PORTB
  33. ;*
  34. ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
  35. ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
  36. ;* rjmp  TOV0_is_set           ;jump if set
  37. ;* ...                         ;otherwise do something else
  38. ;*************************************************************************
  39.  
  40. #ifndef _TN12DEF_INC_
  41. #define _TN12DEF_INC_
  42.  
  43.  
  44. #pragma partinc 0
  45.  
  46. ; ***** SPECIFY DEVICE ***************************************************
  47. .device ATtiny12
  48. #pragma AVRPART ADMIN PART_NAME ATtiny12
  49. .equ    SIGNATURE_000   = 0x1e
  50. .equ    SIGNATURE_001   = 0x90
  51. .equ    SIGNATURE_002   = 0x05
  52.  
  53. #pragma AVRPART CORE CORE_VERSION V0E
  54.  
  55.  
  56. ; ***** I/O REGISTER DEFINITIONS *****************************************
  57. ; NOTE:
  58. ; Definitions marked "MEMORY MAPPED"are extended I/O ports
  59. ; and cannot be used with IN/OUT instructions
  60. .equ    SREG    = 0x3f
  61. .equ    GIMSK   = 0x3b
  62. .equ    GIFR    = 0x3a
  63. .equ    TIMSK   = 0x39
  64. .equ    TIFR    = 0x38
  65. .equ    MCUCR   = 0x35
  66. .equ    MCUSR   = 0x34
  67. .equ    TCCR0   = 0x33
  68. .equ    TCNT0   = 0x32
  69. .equ    OSCCAL  = 0x31
  70. .equ    WDTCR   = 0x21
  71. .equ    EEAR    = 0x1e
  72. .equ    EEDR    = 0x1d
  73. .equ    EECR    = 0x1c
  74. .equ    PORTB   = 0x18
  75. .equ    DDRB    = 0x17
  76. .equ    PINB    = 0x16
  77. .equ    ACSR    = 0x08
  78.  
  79.  
  80. ; ***** BIT DEFINITIONS **************************************************
  81.  
  82. ; ***** ANALOG_COMPARATOR ************
  83. ; ACSR - Analog Comparator Control And Status Register
  84. .equ    ACIS0   = 0     ; Analog Comparator Interrupt Mode Select bit 0
  85. .equ    ACIS1   = 1     ; Analog Comparator Interrupt Mode Select bit 1
  86. .equ    ACIE    = 3     ; Analog Comparator Interrupt Enable
  87. .equ    ACI     = 4     ; Analog Comparator Interrupt Flag
  88. .equ    ACO     = 5     ; Analog Comparator Output
  89. .equ    AINBG   = 6     ; Analog Comparator Bandgap Select
  90. .equ    ACD     = 7     ; Analog Comparator Disable
  91.  
  92.  
  93. ; ***** CPU **************************
  94. ; SREG - Status Register
  95. .equ    SREG_C  = 0     ; Carry Flag
  96. .equ    SREG_Z  = 1     ; Zero Flag
  97. .equ    SREG_N  = 2     ; Negative Flag
  98. .equ    SREG_V  = 3     ; Two's Complement Overflow Flag
  99. .equ    SREG_S  = 4     ; Sign Bit
  100. .equ    SREG_H  = 5     ; Half Carry Flag
  101. .equ    SREG_T  = 6     ; Bit Copy Storage
  102. .equ    SREG_I  = 7     ; Global Interrupt Enable
  103.  
  104. ; MCUCR - MCU Control Register
  105. .equ    ISC00   = 0     ; Interrupt Sense Control 0 bit 0
  106. .equ    ISC01   = 1     ; Interrupt Sense Control 0 bit 1
  107. .equ    SM      = 4     ; Sleep Mode
  108. .equ    SE      = 5     ; Sleep Enable
  109. .equ    PUD     = 6     ; Pull-up Disable
  110.  
  111. ; MCUSR - MCU Status register
  112. .equ    PORF    = 0     ; Power-On Reset Flag
  113. .equ    EXTRF   = 1     ; External Reset Flag
  114. .equ    BORF    = 2     ; Brown-out Reset Flag
  115. .equ    WDRF    = 3     ; Watchdog Reset Flag
  116.  
  117. ; OSCCAL - Status Register
  118. .equ    CAL0    = 0     ; Oscillator Calibration Value Bit 0
  119. .equ    CAL1    = 1     ; Oscillator Calibration Value Bit 1
  120. .equ    CAL2    = 2     ; Oscillator Calibration Value Bit 2
  121. .equ    CAL3    = 3     ; Oscillator Calibration Value Bit 3
  122. .equ    CAL4    = 4
  123. .equ    CAL5    = 5     ; Oscillator Calibration Value Bit 5
  124. .equ    CAL6    = 6     ; Oscillator Calibration Value Bit 6
  125. .equ    CAL7    = 7     ; Oscillator Calibration Value Bit 7
  126.  
  127.  
  128. ; ***** EXTERNAL_INTERRUPT ***********
  129. ; GIMSK - General Interrupt Mask Register
  130. .equ    PCIE    = 5     ; Pin Change Interrupt Enable
  131. .equ    INT0    = 6     ; External Interrupt Request 0 Enable
  132.  
  133. ; GIFR - General Interrupt Flag register
  134. .equ    PCIF    = 5     ; Pin Change Interrupt Flag
  135. .equ    INTF0   = 6     ; External Interrupt Flag 0
  136.  
  137.  
  138. ; ***** EEPROM ***********************
  139. ; EEAR - EEPROM Read/Write Access
  140. .equ    EEAR0   = 0     ; EEPROM Read/Write Access bit 0
  141. .equ    EEAR1   = 1     ; EEPROM Read/Write Access bit 1
  142. .equ    EEAR2   = 2     ; EEPROM Read/Write Access bit 2
  143. .equ    EEAR3   = 3     ; EEPROM Read/Write Access bit 3
  144. .equ    EEAR4   = 4     ; EEPROM Read/Write Access bit 4
  145. .equ    EEAR5   = 5     ; EEPROM Read/Write Access bit 5
  146.  
  147. ; EEDR - EEPROM Data Register
  148. .equ    EEDR0   = 0     ; EEPROM Data Register bit 0
  149. .equ    EEDR1   = 1     ; EEPROM Data Register bit 1
  150. .equ    EEDR2   = 2     ; EEPROM Data Register bit 2
  151. .equ    EEDR3   = 3     ; EEPROM Data Register bit 3
  152. .equ    EEDR4   = 4     ; EEPROM Data Register bit 4
  153. .equ    EEDR5   = 5     ; EEPROM Data Register bit 5
  154. .equ    EEDR6   = 6     ; EEPROM Data Register bit 6
  155. .equ    EEDR7   = 7     ; EEPROM Data Register bit 7
  156.  
  157. ; EECR - EEPROM Control Register
  158. .equ    EERE    = 0     ; EEPROM Read Enable
  159. .equ    EEWE    = 1     ; EEPROM Write Enable
  160. .equ    EEMWE   = 2     ; EEPROM Master Write Enable
  161. .equ    EERIE   = 3     ; EEProm Ready Interrupt Enable
  162.  
  163.  
  164. ; ***** PORTB ************************
  165. ; PORTB - Data Register, Port B
  166. .equ    PORTB0  = 0     ;
  167. .equ    PB0     = 0     ; For compatibility
  168. .equ    PORTB1  = 1     ;
  169. .equ    PB1     = 1     ; For compatibility
  170. .equ    PORTB2  = 2     ;
  171. .equ    PB2     = 2     ; For compatibility
  172. .equ    PORTB3  = 3     ;
  173. .equ    PB3     = 3     ; For compatibility
  174. .equ    PORTB4  = 4     ;
  175. .equ    PB4     = 4     ; For compatibility
  176.  
  177. ; DDRB - Data Direction Register, Port B
  178. .equ    DDB0    = 0     ;
  179. .equ    DDB1    = 1     ;
  180. .equ    DDB2    = 2     ;
  181. .equ    DDB3    = 3     ;
  182. .equ    DDB4    = 4     ;
  183. .equ    DDB5    = 5     ;
  184.  
  185. ; PINB - Input Pins, Port B
  186. .equ    PINB0   = 0     ;
  187. .equ    PINB1   = 1     ;
  188. .equ    PINB2   = 2     ;
  189. .equ    PINB3   = 3     ;
  190. .equ    PINB4   = 4     ;
  191. .equ    PINB5   = 5     ;
  192.  
  193.  
  194. ; ***** TIMER_COUNTER_0 **************
  195. ; TIMSK - Timer/Counter Interrupt Mask Register
  196. .equ    TOIE0   = 1     ; Timer/Counter0 Overflow Interrupt Enable
  197.  
  198. ; TIFR - Timer/Counter Interrupt Flag register
  199. .equ    TOV0    = 1     ; Timer/Counter0 Overflow Flag
  200.  
  201. ; TCCR0 - Timer/Counter0 Control Register
  202. .equ    CS00    = 0     ; Clock Select0 bit 0
  203. .equ    CS01    = 1     ; Clock Select0 bit 1
  204. .equ    CS02    = 2     ; Clock Select0 bit 2
  205.  
  206. ; TCNT0 - Timer Counter 0
  207. .equ    TCNT00  = 0     ; Timer Counter 0 bit 0
  208. .equ    TCNT01  = 1     ; Timer Counter 0 bit 1
  209. .equ    TCNT02  = 2     ; Timer Counter 0 bit 2
  210. .equ    TCNT03  = 3     ; Timer Counter 0 bit 3
  211. .equ    TCNT04  = 4     ; Timer Counter 0 bit 4
  212. .equ    TCNT05  = 5     ; Timer Counter 0 bit 5
  213. .equ    TCNT06  = 6     ; Timer Counter 0 bit 6
  214. .equ    TCNT07  = 7     ; Timer Counter 0 bit 7
  215.  
  216.  
  217. ; ***** WATCHDOG *********************
  218. ; WDTCR - Watchdog Timer Control Register
  219. .equ    WDP0    = 0     ; Watch Dog Timer Prescaler bit 0
  220. .equ    WDP1    = 1     ; Watch Dog Timer Prescaler bit 1
  221. .equ    WDP2    = 2     ; Watch Dog Timer Prescaler bit 2
  222. .equ    WDE     = 3     ; Watch Dog Enable
  223. .equ    WDTOE   = 4     ; RW
  224. .equ    WDDE    = WDTOE ; For compatibility
  225.  
  226.  
  227.  
  228. ; ***** LOCKSBITS ********************************************************
  229. .equ    LB1     = 0     ; Lockbit
  230. .equ    LB2     = 1     ; Lockbit
  231.  
  232.  
  233. ; ***** FUSES ************************************************************
  234. ; LOW fuse bits
  235.  
  236.  
  237.  
  238. ; ***** CPU REGISTER DEFINITIONS *****************************************
  239. .def    XH      = r27
  240. .def    XL      = r26
  241. .def    YH      = r29
  242. .def    YL      = r28
  243. .def    ZH      = r31
  244. .def    ZL      = r30
  245.  
  246.  
  247.  
  248. ; ***** DATA MEMORY DECLARATIONS *****************************************
  249. .equ    FLASHEND        = 0x01ff        ; Note: Word address
  250. .equ    IOEND   = 0x003f
  251. .equ    SRAM_SIZE       = 0
  252. .equ    RAMEND  = 0x0000
  253. .equ    XRAMEND = 0x0000
  254. .equ    E2END   = 0x003f
  255. .equ    EEPROMEND       = 0x003f
  256. .equ    EEADRBITS       = 6
  257. #pragma AVRPART MEMORY PROG_FLASH 1024
  258. #pragma AVRPART MEMORY EEPROM 64
  259. #pragma AVRPART MEMORY INT_SRAM SIZE 0
  260. #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0
  261.  
  262.  
  263.  
  264.  
  265.  
  266. ; ***** INTERRUPT VECTORS ************************************************
  267. .equ    INT0addr        = 0x0001        ; External Interrupt 0
  268. .equ    PCI0addr        = 0x0002        ; External Interrupt Request 0
  269. .equ    OVF0addr        = 0x0003        ; Timer/Counter0 Overflow
  270. .equ    ERDYaddr        = 0x0004        ; EEPROM Ready
  271. .equ    ACIaddr = 0x0005        ; Analog Comparator
  272.  
  273. .equ    INT_VECTORS_SIZE        = 6     ; size in words
  274.  
  275. #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
  276.  
  277. #endif  /* _TN12DEF_INC_ */
  278.  
  279. ; ***** END OF FILE ******************************************************
  280.