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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  */
  25.  
  26. #include <stdio.h>
  27. #include <stdlib.h>
  28. #include <string.h>
  29. #include <assert.h>
  30.  
  31. #include "intel_batchbuffer.h"
  32. #include "intel_driver.h"
  33. #include "i965_defines.h"
  34. #include "i965_structs.h"
  35. #include "i965_drv_video.h"
  36. #include "i965_post_processing.h"
  37. #include "i965_render.h"
  38. #include "intel_media.h"
  39.  
  40. #include "gen8_post_processing.h"
  41.  
  42. static const uint32_t pp_null_gen9[][4] = {
  43. };
  44.  
  45. static const uint32_t pp_nv12_load_save_nv12_gen9[][4] = {
  46. #include "shaders/post_processing/gen9/pl2_to_pl2.g9b"
  47. };
  48.  
  49. static const uint32_t pp_nv12_load_save_pl3_gen9[][4] = {
  50. #include "shaders/post_processing/gen9/pl2_to_pl3.g9b"
  51. };
  52.  
  53. static const uint32_t pp_pl3_load_save_nv12_gen9[][4] = {
  54. #include "shaders/post_processing/gen9/pl3_to_pl2.g9b"
  55. };
  56.  
  57. static const uint32_t pp_pl3_load_save_pl3_gen9[][4] = {
  58. #include "shaders/post_processing/gen9/pl3_to_pl3.g9b"
  59. };
  60.  
  61. static const uint32_t pp_nv12_scaling_gen9[][4] = {
  62. #include "shaders/post_processing/gen9/pl2_to_pl2.g9b"
  63. };
  64.  
  65. static const uint32_t pp_nv12_avs_gen9[][4] = {
  66. #include "shaders/post_processing/gen9/pl2_to_pl2.g9b"
  67. };
  68.  
  69. static const uint32_t pp_nv12_dndi_gen9[][4] = {
  70. };
  71.  
  72. static const uint32_t pp_nv12_dn_gen9[][4] = {
  73. };
  74.  
  75. static const uint32_t pp_nv12_load_save_pa_gen9[][4] = {
  76. #include "shaders/post_processing/gen9/pl2_to_pa.g9b"
  77. };
  78.  
  79. static const uint32_t pp_pl3_load_save_pa_gen9[][4] = {
  80. #include "shaders/post_processing/gen9/pl3_to_pa.g9b"
  81. };
  82.  
  83. static const uint32_t pp_pa_load_save_nv12_gen9[][4] = {
  84. #include "shaders/post_processing/gen9/pa_to_pl2.g9b"
  85. };
  86.  
  87. static const uint32_t pp_pa_load_save_pl3_gen9[][4] = {
  88. #include "shaders/post_processing/gen9/pa_to_pl3.g9b"
  89. };
  90.  
  91. static const uint32_t pp_pa_load_save_pa_gen9[][4] = {
  92. #include "shaders/post_processing/gen9/pa_to_pa.g9b"
  93. };
  94.  
  95. static const uint32_t pp_rgbx_load_save_nv12_gen9[][4] = {
  96. #include "shaders/post_processing/gen9/rgbx_to_nv12.g9b"
  97. };
  98.  
  99. static const uint32_t pp_nv12_load_save_rgbx_gen9[][4] = {
  100. #include "shaders/post_processing/gen9/pl2_to_rgbx.g9b"
  101. };
  102.  
  103. static const uint32_t pp_nv12_blending_gen9[][4] = {
  104. };
  105.  
  106. static struct pp_module pp_modules_gen9[] = {
  107.     {
  108.         {
  109.             "NULL module (for testing)",
  110.             PP_NULL,
  111.             pp_null_gen9,
  112.             sizeof(pp_null_gen9),
  113.             NULL,
  114.         },
  115.  
  116.         pp_null_initialize,
  117.     },
  118.  
  119.     {
  120.         {
  121.             "NV12_NV12",
  122.             PP_NV12_LOAD_SAVE_N12,
  123.             pp_nv12_load_save_nv12_gen9,
  124.             sizeof(pp_nv12_load_save_nv12_gen9),
  125.             NULL,
  126.         },
  127.  
  128.         gen8_pp_plx_avs_initialize,
  129.     },
  130.  
  131.     {
  132.         {
  133.             "NV12_PL3",
  134.             PP_NV12_LOAD_SAVE_PL3,
  135.             pp_nv12_load_save_pl3_gen9,
  136.             sizeof(pp_nv12_load_save_pl3_gen9),
  137.             NULL,
  138.         },
  139.         gen8_pp_plx_avs_initialize,
  140.     },
  141.  
  142.     {
  143.         {
  144.             "PL3_NV12",
  145.             PP_PL3_LOAD_SAVE_N12,
  146.             pp_pl3_load_save_nv12_gen9,
  147.             sizeof(pp_pl3_load_save_nv12_gen9),
  148.             NULL,
  149.         },
  150.  
  151.         gen8_pp_plx_avs_initialize,
  152.     },
  153.  
  154.     {
  155.         {
  156.             "PL3_PL3",
  157.             PP_PL3_LOAD_SAVE_PL3,
  158.             pp_pl3_load_save_pl3_gen9,
  159.             sizeof(pp_pl3_load_save_pl3_gen9),
  160.             NULL,
  161.         },
  162.  
  163.         gen8_pp_plx_avs_initialize,
  164.     },
  165.  
  166.     {
  167.         {
  168.             "NV12 Scaling module",
  169.             PP_NV12_SCALING,
  170.             pp_nv12_scaling_gen9,
  171.             sizeof(pp_nv12_scaling_gen9),
  172.             NULL,
  173.         },
  174.  
  175.         gen8_pp_plx_avs_initialize,
  176.     },
  177.  
  178.     {
  179.         {
  180.             "NV12 AVS module",
  181.             PP_NV12_AVS,
  182.             pp_nv12_avs_gen9,
  183.             sizeof(pp_nv12_avs_gen9),
  184.             NULL,
  185.         },
  186.  
  187.         gen8_pp_plx_avs_initialize,
  188.     },
  189.  
  190.     {
  191.         {
  192.             "NV12 DNDI module",
  193.             PP_NV12_DNDI,
  194.             pp_nv12_dndi_gen9,
  195.             sizeof(pp_nv12_dndi_gen9),
  196.             NULL,
  197.         },
  198.  
  199.         pp_null_initialize,
  200.     },
  201.  
  202.     {
  203.         {
  204.             "NV12 DN module",
  205.             PP_NV12_DN,
  206.             pp_nv12_dn_gen9,
  207.             sizeof(pp_nv12_dn_gen9),
  208.             NULL,
  209.         },
  210.  
  211.         pp_null_initialize,
  212.     },
  213.     {
  214.         {
  215.             "NV12_PA module",
  216.             PP_NV12_LOAD_SAVE_PA,
  217.             pp_nv12_load_save_pa_gen9,
  218.             sizeof(pp_nv12_load_save_pa_gen9),
  219.             NULL,
  220.         },
  221.  
  222.         gen8_pp_plx_avs_initialize,
  223.     },
  224.  
  225.     {
  226.         {
  227.             "PL3_PA module",
  228.             PP_PL3_LOAD_SAVE_PA,
  229.             pp_pl3_load_save_pa_gen9,
  230.             sizeof(pp_pl3_load_save_pa_gen9),
  231.             NULL,
  232.         },
  233.  
  234.         gen8_pp_plx_avs_initialize,
  235.     },
  236.  
  237.     {
  238.         {
  239.             "PA_NV12 module",
  240.             PP_PA_LOAD_SAVE_NV12,
  241.             pp_pa_load_save_nv12_gen9,
  242.             sizeof(pp_pa_load_save_nv12_gen9),
  243.             NULL,
  244.         },
  245.  
  246.         gen8_pp_plx_avs_initialize,
  247.     },
  248.  
  249.     {
  250.         {
  251.             "PA_PL3 module",
  252.             PP_PA_LOAD_SAVE_PL3,
  253.             pp_pa_load_save_pl3_gen9,
  254.             sizeof(pp_pa_load_save_pl3_gen9),
  255.             NULL,
  256.         },
  257.  
  258.         gen8_pp_plx_avs_initialize,
  259.     },
  260.  
  261.     {
  262.         {
  263.             "PA_PA module",
  264.             PP_PA_LOAD_SAVE_PA,
  265.             pp_pa_load_save_pa_gen9,
  266.             sizeof(pp_pa_load_save_pa_gen9),
  267.             NULL,
  268.         },
  269.  
  270.         gen8_pp_plx_avs_initialize,
  271.     },
  272.  
  273.     {
  274.         {
  275.             "RGBX_NV12 module",
  276.             PP_RGBX_LOAD_SAVE_NV12,
  277.             pp_rgbx_load_save_nv12_gen9,
  278.             sizeof(pp_rgbx_load_save_nv12_gen9),
  279.             NULL,
  280.         },
  281.  
  282.         gen8_pp_plx_avs_initialize,
  283.     },
  284.  
  285.     {
  286.         {
  287.             "NV12_RGBX module",
  288.             PP_NV12_LOAD_SAVE_RGBX,
  289.             pp_nv12_load_save_rgbx_gen9,
  290.             sizeof(pp_nv12_load_save_rgbx_gen9),
  291.             NULL,
  292.         },
  293.  
  294.         gen8_pp_plx_avs_initialize,
  295.     },
  296. };
  297.  
  298. static const AVSConfig gen9_avs_config = {
  299.     .coeff_frac_bits = 6,
  300.     .coeff_epsilon = 1.0f / (1U << 6),
  301.     .num_phases = 31,
  302.     .num_luma_coeffs = 8,
  303.     .num_chroma_coeffs = 4,
  304.  
  305.     .coeff_range = {
  306.         .lower_bound = {
  307.             .y_k_h = { -2, -2, -2, -2, -2, -2, -2, -2 },
  308.             .y_k_v = { -2, -2, -2, -2, -2, -2, -2, -2 },
  309.             .uv_k_h = { -2, -2, -2, -2 },
  310.             .uv_k_v = { -2, -2, -2, -2 },
  311.         },
  312.         .upper_bound = {
  313.             .y_k_h = { 2, 2, 2, 2, 2, 2, 2, 2 },
  314.             .y_k_v = { 2, 2, 2, 2, 2, 2, 2, 2 },
  315.             .uv_k_h = { 2, 2, 2, 2 },
  316.             .uv_k_v = { 2, 2, 2, 2 },
  317.         },
  318.     },
  319. };
  320.  
  321. static void
  322. gen9_pp_pipeline_select(VADriverContextP ctx,
  323.                         struct i965_post_processing_context *pp_context)
  324. {
  325.     struct intel_batchbuffer *batch = pp_context->batch;
  326.  
  327.     BEGIN_BATCH(batch, 1);
  328.     OUT_BATCH(batch,
  329.               CMD_PIPELINE_SELECT |
  330.               PIPELINE_SELECT_MEDIA |
  331.               GEN9_FORCE_MEDIA_AWAKE_ON |
  332.               GEN9_MEDIA_DOP_GATE_OFF |
  333.               GEN9_PIPELINE_SELECTION_MASK |
  334.               GEN9_MEDIA_DOP_GATE_MASK |
  335.               GEN9_FORCE_MEDIA_AWAKE_MASK);
  336.     ADVANCE_BATCH(batch);
  337. }
  338.  
  339. static void
  340. gen9_pp_state_base_address(VADriverContextP ctx,
  341.                            struct i965_post_processing_context *pp_context)
  342. {
  343.     struct intel_batchbuffer *batch = pp_context->batch;
  344.  
  345.     BEGIN_BATCH(batch, 19);
  346.     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (19 - 2));
  347.     /* DW1 Generate state address */
  348.     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  349.     OUT_BATCH(batch, 0);
  350.     OUT_BATCH(batch, 0);
  351.     /* DW4-5 Surface state address */
  352.     OUT_RELOC64(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
  353.     /* DW6-7 Dynamic state address */
  354.     OUT_RELOC64(batch, pp_context->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
  355.               0, 0 | BASE_ADDRESS_MODIFY);
  356.  
  357.     /* DW8. Indirect object address */
  358.     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  359.     OUT_BATCH(batch, 0);
  360.  
  361.     /* DW10-11 Instruction base address */
  362.     OUT_RELOC64(batch, pp_context->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
  363.  
  364.     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
  365.     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
  366.     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
  367.     OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
  368.  
  369.     /* Bindless surface state base address */
  370.     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  371.     OUT_BATCH(batch, 0);
  372.     OUT_BATCH(batch, 0xfffff000);
  373.  
  374.     ADVANCE_BATCH(batch);
  375. }
  376.  
  377. static void
  378. gen9_pp_end_pipeline(VADriverContextP ctx,
  379.                      struct i965_post_processing_context *pp_context)
  380. {
  381.     struct intel_batchbuffer *batch = pp_context->batch;
  382.  
  383.     BEGIN_BATCH(batch, 1);
  384.     OUT_BATCH(batch,
  385.               CMD_PIPELINE_SELECT |
  386.               PIPELINE_SELECT_MEDIA |
  387.               GEN9_FORCE_MEDIA_AWAKE_OFF |
  388.               GEN9_MEDIA_DOP_GATE_ON |
  389.               GEN9_PIPELINE_SELECTION_MASK |
  390.               GEN9_MEDIA_DOP_GATE_MASK |
  391.               GEN9_FORCE_MEDIA_AWAKE_MASK);
  392.     ADVANCE_BATCH(batch);
  393. }
  394.  
  395. static void
  396. gen9_pp_pipeline_setup(VADriverContextP ctx,
  397.                        struct i965_post_processing_context *pp_context)
  398. {
  399.     struct intel_batchbuffer *batch = pp_context->batch;
  400.  
  401.     intel_batchbuffer_start_atomic(batch, 0x1000);
  402.     intel_batchbuffer_emit_mi_flush(batch);
  403.     gen9_pp_pipeline_select(ctx, pp_context);
  404.     gen9_pp_state_base_address(ctx, pp_context);
  405.     gen8_pp_vfe_state(ctx, pp_context);
  406.     gen8_pp_curbe_load(ctx, pp_context);
  407.     gen8_interface_descriptor_load(ctx, pp_context);
  408.     gen8_pp_object_walker(ctx, pp_context);
  409.     gen9_pp_end_pipeline(ctx, pp_context);
  410.     intel_batchbuffer_end_atomic(batch);
  411. }
  412.  
  413. static VAStatus
  414. gen9_post_processing(VADriverContextP ctx,
  415.                      struct i965_post_processing_context *pp_context,
  416.                      const struct i965_surface *src_surface,
  417.                      const VARectangle *src_rect,
  418.                      struct i965_surface *dst_surface,
  419.                      const VARectangle *dst_rect,
  420.                      int pp_index,
  421.                      void * filter_param)
  422. {
  423.     VAStatus va_status;
  424.  
  425.     va_status = gen8_pp_initialize(ctx, pp_context,
  426.                                    src_surface,
  427.                                    src_rect,
  428.                                    dst_surface,
  429.                                    dst_rect,
  430.                                    pp_index,
  431.                                    filter_param);
  432.  
  433.     if (va_status == VA_STATUS_SUCCESS) {
  434.         gen8_pp_states_setup(ctx, pp_context);
  435.         gen9_pp_pipeline_setup(ctx, pp_context);
  436.     }
  437.  
  438.     return va_status;
  439. }
  440.  
  441. void
  442. gen9_post_processing_context_init(VADriverContextP ctx,
  443.                                   void *data,
  444.                                   struct intel_batchbuffer *batch)
  445. {
  446.     struct i965_post_processing_context *pp_context = data;
  447.  
  448.     gen8_post_processing_context_common_init(ctx, data, pp_modules_gen9, ARRAY_ELEMS(pp_modules_gen9), batch);
  449.     avs_init_state(&pp_context->pp_avs_context.state, &gen9_avs_config);
  450.  
  451.     pp_context->intel_post_processing = gen9_post_processing;
  452. }
  453.