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  1. /*
  2.  * Copyright © 2010 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  */
  24.  
  25. include(`exa_wm.g4i')
  26.  
  27. /*
  28.  * Prepare data in m2-m3 for Red channel, m4-m5 for Green channel,
  29.  * m6-m7 for Blue and m8-m9 for Alpha channel
  30.  */
  31. define(`slot_r_00',     `m2')
  32. define(`slot_r_01',     `m3')
  33. define(`slot_g_00',     `m4')
  34. define(`slot_g_01',     `m5')
  35. define(`slot_b_00',     `m6')
  36. define(`slot_b_01',     `m7')
  37. define(`slot_a_00',     `m8')
  38. define(`slot_a_01',     `m9')
  39. define(`data_port_msg_2_ind',   `2')
  40.  
  41. mov (8) slot_r_00<1>F     src_sample_r_01<8,8,1>F { align1 };
  42. mov (8) slot_r_01<1>F     src_sample_r_23<8,8,1>F { align1 };
  43.  
  44. mov (8) slot_g_00<1>F     src_sample_g_01<8,8,1>F { align1 };
  45. mov (8) slot_g_01<1>F     src_sample_g_23<8,8,1>F { align1 };
  46.  
  47. mov (8) slot_b_00<1>F     src_sample_b_01<8,8,1>F { align1 };
  48. mov (8) slot_b_01<1>F     src_sample_b_23<8,8,1>F { align1 };
  49.  
  50. mov (8) slot_a_00<1>F     src_sample_a_01<8,8,1>F { align1 };
  51. mov (8) slot_a_01<1>F     src_sample_a_23<8,8,1>F { align1 };
  52.  
  53. /* write */
  54. send (16)
  55.         data_port_msg_2_ind
  56.         acc0<1>UW
  57.         null
  58.         write (
  59.                0,  /* binding_table */
  60.                16,  /* pixel scordboard clear, msg type simd16 single source */
  61.                12,  /* render target write */
  62.                0,   /* no write commit message */
  63.                0  /* headerless render target write */
  64.         )
  65.         mlen 8
  66.         rlen 0
  67.         { align1 EOT };
  68.  
  69. nop;
  70. nop;
  71. nop;
  72. nop;
  73. nop;
  74. nop;
  75. nop;
  76. nop;
  77.  
  78.