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  1. /*
  2.  * Copyright © 2010 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Xiang Haihao <haihao.xiang@intel.com>
  26.  *
  27.  */
  28.  
  29. #ifndef __I965_POST_PROCESSING_H__
  30. #define __I965_POST_PROCESSING_H__
  31.  
  32. #define MAX_PP_SURFACES                 48
  33.  
  34. #define I965_PP_FLAG_TOP_FIELD          1
  35. #define I965_PP_FLAG_BOTTOM_FIELD       2
  36. #define I965_PP_FLAG_MCDI               4
  37. #define I965_PP_FLAG_AVS                8
  38.  
  39. enum
  40. {
  41.     PP_NULL = 0,
  42.     PP_NV12_LOAD_SAVE_N12,
  43.     PP_NV12_LOAD_SAVE_PL3,
  44.     PP_PL3_LOAD_SAVE_N12,
  45.     PP_PL3_LOAD_SAVE_PL3,
  46.     PP_NV12_SCALING,
  47.     PP_NV12_AVS,
  48.     PP_NV12_DNDI,
  49.     PP_NV12_DN,
  50.     PP_NV12_LOAD_SAVE_PA,
  51.     PP_PL3_LOAD_SAVE_PA,
  52.     PP_PA_LOAD_SAVE_NV12,
  53.     PP_PA_LOAD_SAVE_PL3,
  54.     PP_PA_LOAD_SAVE_PA,
  55.     PP_RGBX_LOAD_SAVE_NV12,
  56.     PP_NV12_LOAD_SAVE_RGBX,
  57.     NUM_PP_MODULES,
  58. };
  59.  
  60. struct i965_post_processing_context;
  61.  
  62. struct pp_load_save_context
  63. {
  64.     int dest_x;
  65.     int dest_y;
  66.     int dest_w;
  67.     int dest_h;
  68. };
  69.  
  70. struct pp_scaling_context
  71. {
  72.     int dest_x; /* in pixel */
  73.     int dest_y; /* in pixel */
  74.     int dest_w;
  75.     int dest_h;
  76.     float src_normalized_x;
  77.     float src_normalized_y;
  78. };
  79.  
  80. struct pp_avs_context
  81. {
  82.     int dest_x; /* in pixel */
  83.     int dest_y; /* in pixel */
  84.     int dest_w;
  85.     int dest_h;
  86.     float src_normalized_x;
  87.     float src_normalized_y;
  88.     int src_w;
  89.     int src_h;
  90.     float horiz_range;
  91. };
  92.  
  93. struct pp_dndi_context
  94. {
  95.     int dest_w;
  96.     int dest_h;
  97.     dri_bo *stmm_bo;
  98.     int frame_order; /* -1 for the first frame */
  99.     VASurfaceID current_out_surface;
  100.     struct object_surface *current_out_obj_surface;
  101. };
  102.  
  103. struct pp_dn_context
  104. {
  105.     int dest_w;
  106.     int dest_h;
  107.     dri_bo *stmm_bo;
  108. };
  109.  
  110. struct i965_post_processing_context;
  111.  
  112. struct pp_module
  113. {
  114.     struct i965_kernel kernel;
  115.    
  116.     /* others */
  117.     VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  118.                            const struct i965_surface *src_surface,
  119.                            const VARectangle *src_rect,
  120.                            struct i965_surface *dst_surface,
  121.                            const VARectangle *dst_rect,
  122.                            void *filter_param);
  123. };
  124.  
  125. struct pp_static_parameter
  126. {
  127.     struct {
  128.         /* Procamp r1.0 */
  129.         float procamp_constant_c0;
  130.        
  131.         /* Load and Same r1.1 */
  132.         unsigned int source_packed_y_offset:8;
  133.         unsigned int source_packed_u_offset:8;
  134.         unsigned int source_packed_v_offset:8;
  135.         unsigned int source_rgb_layout:8;       // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
  136.  
  137.         union {
  138.             /* Load and Save r1.2 */
  139.             struct {
  140.                 unsigned int destination_packed_y_offset:8;
  141.                 unsigned int destination_packed_u_offset:8;
  142.                 unsigned int destination_packed_v_offset:8;
  143.                 unsigned int pad0:8;
  144.             } load_and_save;
  145.  
  146.             /* CSC r1.2 */
  147.             struct {
  148.                 unsigned int pad0:24;
  149.                 unsigned int destination_rgb_layout:8;  // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
  150.             } csc;
  151.         } r1_2;
  152.        
  153.         /* Procamp r1.3 */
  154.         float procamp_constant_c1;
  155.  
  156.         /* Procamp r1.4 */
  157.         float procamp_constant_c2;
  158.  
  159.         /* DI r1.5 */
  160.         unsigned int statistics_surface_picth:16;  /* Devided by 2 */
  161.         unsigned int pad1:16;
  162.  
  163.         union {
  164.             /* DI r1.6 */
  165.             struct {
  166.                 unsigned int pad0:24;
  167.                 unsigned int top_field_first:8;
  168.             } di;
  169.  
  170.             /* AVS/Scaling r1.6 */
  171.             float normalized_video_y_scaling_step;
  172.         } r1_6;
  173.  
  174.         /* Procamp r1.7 */
  175.         float procamp_constant_c5;
  176.     } grf1;
  177.    
  178.     struct {
  179.         /* Procamp r2.0 */
  180.         float procamp_constant_c3;
  181.  
  182.         /* MBZ r2.1*/
  183.         unsigned int pad0;
  184.  
  185.         /* WG+CSC r2.2 */
  186.         float wg_csc_constant_c4;
  187.  
  188.         /* WG+CSC r2.3 */
  189.         float wg_csc_constant_c8;
  190.  
  191.         /* Procamp r2.4 */
  192.         float procamp_constant_c4;
  193.  
  194.         /* MBZ r2.5 */
  195.         unsigned int pad1;
  196.  
  197.         /* MBZ r2.6 */
  198.         unsigned int pad2;
  199.  
  200.         /* WG+CSC r2.7 */
  201.         float wg_csc_constant_c9;
  202.     } grf2;
  203.  
  204.     struct {
  205.         /* WG+CSC r3.0 */
  206.         float wg_csc_constant_c0;
  207.  
  208.         /* Blending r3.1 */
  209.         float scaling_step_ratio;
  210.  
  211.         /* Blending r3.2 */
  212.         float normalized_alpha_y_scaling;
  213.        
  214.         /* WG+CSC r3.3 */
  215.         float wg_csc_constant_c4;
  216.  
  217.         /* WG+CSC r3.4 */
  218.         float wg_csc_constant_c1;
  219.  
  220.         /* ALL r3.5 */
  221.         int horizontal_origin_offset:16;
  222.         int vertical_origin_offset:16;
  223.  
  224.         /* Shared r3.6*/
  225.         union {
  226.             /* Color filll */
  227.             unsigned int color_pixel;
  228.  
  229.             /* WG+CSC */
  230.             float wg_csc_constant_c2;
  231.         } r3_6;
  232.  
  233.         /* WG+CSC r3.7 */
  234.         float wg_csc_constant_c3;
  235.     } grf3;
  236.  
  237.     struct {
  238.         /* WG+CSC r4.0 */
  239.         float wg_csc_constant_c6;
  240.  
  241.         /* ALL r4.1 MBZ ???*/
  242.         unsigned int pad0;
  243.  
  244.         /* Shared r4.2 */
  245.         union {
  246.             /* AVS */
  247.             struct {
  248.                 unsigned int pad1:15;
  249.                 unsigned int nlas:1;
  250.                 unsigned int pad2:16;
  251.             } avs;
  252.  
  253.             /* DI */
  254.             struct {
  255.                 unsigned int motion_history_coefficient_m2:8;
  256.                 unsigned int motion_history_coefficient_m1:8;
  257.                 unsigned int pad0:16;
  258.             } di;
  259.         } r4_2;
  260.  
  261.         /* WG+CSC r4.3 */
  262.         float wg_csc_constant_c7;
  263.  
  264.         /* WG+CSC r4.4 */
  265.         float wg_csc_constant_c10;
  266.  
  267.         /* AVS r4.5 */
  268.         float source_video_frame_normalized_horizontal_origin;
  269.  
  270.         /* MBZ r4.6 */
  271.         unsigned int pad1;
  272.  
  273.         /* WG+CSC r4.7 */
  274.         float wg_csc_constant_c11;
  275.     } grf4;
  276. };
  277.  
  278. struct pp_inline_parameter
  279. {
  280.     struct {
  281.         /* ALL r5.0 */
  282.         int destination_block_horizontal_origin:16;
  283.         int destination_block_vertical_origin:16;
  284.  
  285.         /* Shared r5.1 */
  286.         union {
  287.             /* AVS/Scaling */
  288.             float source_surface_block_normalized_horizontal_origin;
  289.  
  290.             /* FMD */
  291.             struct {
  292.                 unsigned int variance_surface_vertical_origin:16;
  293.                 unsigned int pad0:16;
  294.             } fmd;
  295.         } r5_1;
  296.  
  297.         /* AVS/Scaling r5.2 */
  298.         float source_surface_block_normalized_vertical_origin;
  299.  
  300.         /* Alpha r5.3 */
  301.         float alpha_surface_block_normalized_horizontal_origin;
  302.  
  303.         /* Alpha r5.4 */
  304.         float alpha_surface_block_normalized_vertical_origin;
  305.  
  306.         /* Alpha r5.5 */
  307.         unsigned int alpha_mask_x:16;
  308.         unsigned int alpha_mask_y:8;
  309.         unsigned int block_count_x:8;
  310.  
  311.         /* r5.6 */
  312.         /* we only support M*1 or 1*N block partitation now.
  313.          *   -- it means asm code only need update this mask from grf6 for the last block
  314.          */
  315.         unsigned int block_horizontal_mask:16;
  316.         unsigned int block_vertical_mask:8;
  317.         unsigned int number_blocks:8;
  318.  
  319.         /* AVS/Scaling r5.7 */
  320.         float normalized_video_x_scaling_step;
  321.     } grf5;
  322.  
  323.     struct {
  324.         /* AVS r6.0 */
  325.         float video_step_delta;
  326.  
  327.         /* r6.1 */    // sizeof(int) == 4?    
  328.         unsigned int block_horizontal_mask_right:16;
  329.         unsigned int block_vertical_mask_bottom:8;
  330.         unsigned int pad1:8;
  331.  
  332.         /* r6.2 */
  333.         unsigned int block_horizontal_mask_middle:16;
  334.         unsigned int pad2:16;
  335.  
  336.         /* r6.3-r6.7 */
  337.         unsigned int padx[5];
  338.     } grf6;
  339. };
  340.  
  341. struct gen7_pp_static_parameter
  342. {
  343.     struct {
  344.         /* r1.0-r1.5 */
  345.         unsigned int padx[6];
  346.         /* r1.6 */
  347.         unsigned int di_statistics_surface_pitch_div2:16;
  348.         unsigned int di_statistics_surface_height_div4:16;
  349.         /* r1.7 */
  350.         unsigned int di_top_field_first:8;
  351.         unsigned int pad0:16;
  352.         unsigned int pointer_to_inline_parameter:8; /* value: 7 */
  353.     } grf1;
  354.  
  355.     struct {
  356.         /* r2.0 */
  357.         /* Indicates whether the rgb is swapped for the src surface
  358.          * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
  359.          */
  360.         unsigned int src_avs_rgb_swap:1;
  361.         unsigned int pad3:31;
  362.  
  363.         /* r2.1 */
  364.         unsigned int pad2:16;
  365.         unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
  366.         unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
  367.         unsigned int ief_enable:1;
  368.         unsigned int avs_wa_width:13;
  369.  
  370.         /* 2.2 */
  371.         float avs_wa_one_div_256_width;
  372.  
  373.         /* 2.3 */
  374.         float avs_wa_five_div_256_width;
  375.        
  376.         /* 2.4 - 2.6 */
  377.         unsigned int padx[3];
  378.  
  379.         /* r2.7 */
  380.         unsigned int di_destination_packed_y_component_offset:8;
  381.         unsigned int di_destination_packed_u_component_offset:8;
  382.         unsigned int di_destination_packed_v_component_offset:8;
  383.         unsigned int alpha:8;
  384.     } grf2;
  385.  
  386.     struct {
  387.         float sampler_load_horizontal_scaling_step_ratio;
  388.         unsigned int padx[7];
  389.     } grf3;
  390.  
  391.     struct {
  392.         float sampler_load_vertical_scaling_step;
  393.         unsigned int pad0;
  394.         unsigned int di_hoffset_svf_from_dvf:16;
  395.         unsigned int di_voffset_svf_from_dvf:16;
  396.         unsigned int padx[5];
  397.     } grf4;
  398.  
  399.     struct {
  400.         float sampler_load_vertical_frame_origin;
  401.         unsigned int padx[7];
  402.     } grf5;
  403.  
  404.     struct {
  405.         float sampler_load_horizontal_frame_origin;
  406.         unsigned int padx[7];
  407.     } grf6;
  408. };
  409.  
  410. struct gen7_pp_inline_parameter
  411. {
  412.     struct {
  413.         /* r7.0 */
  414.         unsigned int destination_block_horizontal_origin:16;
  415.         unsigned int destination_block_vertical_origin:16;
  416.         /* r7.1: 0xffffffff */
  417.         unsigned int constant_0;
  418.         /* r7.2 */
  419.         unsigned int pad0;
  420.         /* r7.3 */
  421.         unsigned int pad1;
  422.         /* r7.4 */
  423.         float sampler_load_main_video_x_scaling_step;
  424.         /* r7.5 */
  425.         unsigned int pad2;
  426.         /* r7.6: must be zero */
  427.         unsigned int avs_vertical_block_number;
  428.         /* r7.7: 0 */
  429.         unsigned int group_id_number;
  430.     } grf7;
  431.  
  432.     struct {
  433.         unsigned int padx[8];
  434.     } grf8;
  435. };
  436.  
  437. struct i965_post_processing_context
  438. {
  439.     int current_pp;
  440.     struct pp_module pp_modules[NUM_PP_MODULES];
  441.     void *pp_static_parameter;
  442.     void *pp_inline_parameter;
  443.  
  444.     struct {
  445.         dri_bo *bo;
  446.     } surface_state_binding_table;
  447.  
  448.     struct {
  449.         dri_bo *bo;
  450.     } curbe;
  451.  
  452.     struct {
  453.         dri_bo *bo;
  454.         int num_interface_descriptors;
  455.     } idrt;
  456.  
  457.     struct {
  458.         dri_bo *bo;
  459.     } vfe_state;
  460.  
  461.     struct {
  462.         dri_bo *bo;
  463.         dri_bo *bo_8x8;
  464.         dri_bo *bo_8x8_uv;
  465.     } sampler_state_table;
  466.  
  467.     struct {
  468.         unsigned int size;
  469.  
  470.         unsigned int vfe_start;
  471.         unsigned int cs_start;
  472.  
  473.         unsigned int num_vfe_entries;
  474.         unsigned int num_cs_entries;
  475.  
  476.         unsigned int size_vfe_entry;
  477.         unsigned int size_cs_entry;
  478.     } urb;
  479.  
  480.     struct {
  481.         unsigned int gpgpu_mode : 1;
  482.         unsigned int pad0 : 7;
  483.         unsigned int max_num_threads : 16;
  484.         unsigned int num_urb_entries : 8;
  485.         unsigned int urb_entry_size : 16;
  486.         unsigned int curbe_allocation_size : 16;
  487.     } vfe_gpu_state;
  488.  
  489.     struct pp_load_save_context pp_load_save_context;
  490.     struct pp_scaling_context pp_scaling_context;
  491.     struct pp_avs_context pp_avs_context;
  492.     struct pp_dndi_context pp_dndi_context;
  493.     struct pp_dn_context pp_dn_context;
  494.     void *private_context; /* pointer to the current private context */
  495.     void *pipeline_param;  /* pointer to the pipeline parameter */
  496.  
  497.     int (*pp_x_steps)(void *private_context);
  498.     int (*pp_y_steps)(void *private_context);
  499.     int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
  500.  
  501.     struct intel_batchbuffer *batch;
  502.  
  503.     unsigned int block_horizontal_mask_left:16;
  504.     unsigned int block_horizontal_mask_right:16;
  505.     unsigned int block_vertical_mask_bottom:8;
  506.  
  507.     struct {
  508.         dri_bo *bo;
  509.         int bo_size;
  510.         unsigned int end_offset;
  511.     } instruction_state;
  512.  
  513.     struct {
  514.         dri_bo *bo;
  515.     } indirect_state;
  516.  
  517.     struct {
  518.         dri_bo *bo;
  519.         int bo_size;
  520.         unsigned int end_offset;
  521.     } dynamic_state;
  522.  
  523.     unsigned int sampler_offset;
  524.     int sampler_size;
  525.     unsigned int idrt_offset;
  526.     int idrt_size;
  527.     unsigned int curbe_offset;
  528.     int curbe_size;
  529.  
  530.     VAStatus (*intel_post_processing)(VADriverContextP   ctx,
  531.                                 struct i965_post_processing_context *pp_context,
  532.                                 const struct i965_surface *src_surface,
  533.                                 const VARectangle *src_rect,
  534.                                 struct i965_surface *dst_surface,
  535.                                 const VARectangle *dst_rect,
  536.                                 int   pp_index,
  537.                                 void * filter_param);
  538.     void (*finalize)(struct i965_post_processing_context *pp_context);
  539. };
  540.  
  541. struct i965_proc_context
  542. {
  543.     struct hw_context base;
  544.     struct i965_post_processing_context pp_context;
  545. };
  546.  
  547. VASurfaceID
  548. i965_post_processing(
  549.     VADriverContextP   ctx,
  550.     struct object_surface *obj_surface,
  551.     const VARectangle *src_rect,
  552.     const VARectangle *dst_rect,
  553.     unsigned int       flags,
  554.     int                *has_done_scaling
  555. );
  556.  
  557. VAStatus
  558. i965_scaling_processing(
  559.     VADriverContextP   ctx,
  560.     struct object_surface *src_surface_obj,
  561.     const VARectangle *src_rect,
  562.     struct object_surface *dst_surface_obj,
  563.     const VARectangle *dst_rect,
  564.     unsigned int       flags
  565. );
  566.  
  567. VAStatus
  568. i965_image_processing(VADriverContextP ctx,
  569.                       const struct i965_surface *src_surface,
  570.                       const VARectangle *src_rect,
  571.                       struct i965_surface *dst_surface,
  572.                       const VARectangle *dst_rect);
  573.  
  574. void
  575. i965_post_processing_terminate(VADriverContextP ctx);
  576. bool
  577. i965_post_processing_init(VADriverContextP ctx);
  578.  
  579.  
  580. extern VAStatus
  581. i965_proc_picture(VADriverContextP ctx,
  582.                   VAProfile profile,
  583.                   union codec_state *codec_state,
  584.                   struct hw_context *hw_context);
  585.  
  586. #endif /* __I965_POST_PROCESSING_H__ */
  587.