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  1. /*
  2.  * Copyright © 2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #ifdef HAVE_CONFIG_H
  29. #include "config.h"
  30. #endif
  31.  
  32. #include <string.h>
  33. #include <stdlib.h>
  34. #include <stdint.h>
  35. #include <assert.h>
  36. #include <errno.h>
  37. #include <drm.h>
  38. #include <i915_drm.h>
  39. //#include <pciaccess.h>
  40. #include "intel_bufmgr.h"
  41. #include "intel_bufmgr_priv.h"
  42. #include "xf86drm.h"
  43.  
  44. /** @file intel_bufmgr.c
  45.  *
  46.  * Convenience functions for buffer management methods.
  47.  */
  48.  
  49. drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
  50.                                  unsigned long size, unsigned int alignment)
  51. {
  52.         return bufmgr->bo_alloc(bufmgr, name, size, alignment);
  53. }
  54.  
  55. #if 0
  56. drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
  57.                                             const char *name,
  58.                                             unsigned long size,
  59.                                             unsigned int alignment)
  60. {
  61.         return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
  62. }
  63. #endif
  64.  
  65. drm_intel_bo *
  66. drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
  67.                         int x, int y, int cpp, uint32_t *tiling_mode,
  68.                         unsigned long *pitch, unsigned long flags)
  69. {
  70.         return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
  71.                                       tiling_mode, pitch, flags);
  72. }
  73.  
  74. void drm_intel_bo_reference(drm_intel_bo *bo)
  75. {
  76.         bo->bufmgr->bo_reference(bo);
  77. }
  78.  
  79. void drm_intel_bo_unreference(drm_intel_bo *bo)
  80. {
  81.         if (bo == NULL)
  82.                 return;
  83.  
  84.         bo->bufmgr->bo_unreference(bo);
  85. }
  86.  
  87. int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
  88. {
  89.         return buf->bufmgr->bo_map(buf, write_enable);
  90. }
  91.  
  92. int drm_intel_bo_unmap(drm_intel_bo *buf)
  93. {
  94.         return buf->bufmgr->bo_unmap(buf);
  95. }
  96.  
  97. int
  98. drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
  99.                      unsigned long size, const void *data)
  100. {
  101.         return bo->bufmgr->bo_subdata(bo, offset, size, data);
  102. }
  103.  
  104. int
  105. drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
  106.                          unsigned long size, void *data)
  107. {
  108.         int ret;
  109. //      if (bo->bufmgr->bo_get_subdata)
  110. //              return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
  111.  
  112.         if (size == 0 || data == NULL)
  113.                 return 0;
  114.  
  115.         ret = drm_intel_bo_map(bo, 0);
  116.         if (ret)
  117.                 return ret;
  118.         memcpy(data, (unsigned char *)bo->virtual + offset, size);
  119.         drm_intel_bo_unmap(bo);
  120.         return 0;
  121. }
  122.  
  123. void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
  124. {
  125.         bo->bufmgr->bo_wait_rendering(bo);
  126. }
  127.  
  128. void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
  129. {
  130.         bufmgr->destroy(bufmgr);
  131. }
  132.  
  133. int
  134. drm_intel_bo_exec(drm_intel_bo *bo, int used,
  135.                   drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
  136. {
  137.         return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
  138. }
  139.  
  140. int
  141. drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
  142.                 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
  143.                 unsigned int rings)
  144. {
  145.         if (bo->bufmgr->bo_mrb_exec)
  146.                 return bo->bufmgr->bo_mrb_exec(bo, used,
  147.                                         cliprects, num_cliprects, DR4,
  148.                                         rings);
  149.  
  150.         switch (rings) {
  151.         case I915_EXEC_DEFAULT:
  152.         case I915_EXEC_RENDER:
  153.                 return bo->bufmgr->bo_exec(bo, used,
  154.                                            cliprects, num_cliprects, DR4);
  155.         default:
  156.                 return -ENODEV;
  157.         }
  158. }
  159.  
  160. void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
  161. {
  162.         bufmgr->debug = enable_debug;
  163. }
  164.  
  165. int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
  166. {
  167.         return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
  168. }
  169.  
  170. int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
  171. {
  172.         if (bo->bufmgr->bo_flink)
  173.                 return bo->bufmgr->bo_flink(bo, name);
  174.  
  175.         return -ENODEV;
  176. }
  177.  
  178. int
  179. drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
  180.                         drm_intel_bo *target_bo, uint32_t target_offset,
  181.                         uint32_t read_domains, uint32_t write_domain)
  182. {
  183.         return bo->bufmgr->bo_emit_reloc(bo, offset,
  184.                                          target_bo, target_offset,
  185.                                          read_domains, write_domain);
  186. }
  187.  
  188. /* For fence registers, not GL fences */
  189. int
  190. drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
  191.                               drm_intel_bo *target_bo, uint32_t target_offset,
  192.                               uint32_t read_domains, uint32_t write_domain)
  193. {
  194.         return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
  195.                                                target_bo, target_offset,
  196.                                                read_domains, write_domain);
  197. }
  198.  
  199.  
  200. int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
  201. {
  202.         if (bo->bufmgr->bo_pin)
  203.                 return bo->bufmgr->bo_pin(bo, alignment);
  204.  
  205.         return -ENODEV;
  206. }
  207.  
  208. int drm_intel_bo_unpin(drm_intel_bo *bo)
  209. {
  210.         if (bo->bufmgr->bo_unpin)
  211.                 return bo->bufmgr->bo_unpin(bo);
  212.  
  213.         return -ENODEV;
  214. }
  215.  
  216. int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
  217.                             uint32_t stride)
  218. {
  219.         if (bo->bufmgr->bo_set_tiling)
  220.                 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
  221.  
  222.         *tiling_mode = I915_TILING_NONE;
  223.         return 0;
  224. }
  225.  
  226. int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
  227.                             uint32_t * swizzle_mode)
  228. {
  229.         if (bo->bufmgr->bo_get_tiling)
  230.                 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
  231.  
  232.         *tiling_mode = I915_TILING_NONE;
  233.         *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
  234.         return 0;
  235. }
  236.  
  237. int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
  238. {
  239.         if (bo->bufmgr->bo_disable_reuse)
  240.                 return bo->bufmgr->bo_disable_reuse(bo);
  241.         return 0;
  242. }
  243.  
  244. int drm_intel_bo_is_reusable(drm_intel_bo *bo)
  245. {
  246.         if (bo->bufmgr->bo_is_reusable)
  247.                 return bo->bufmgr->bo_is_reusable(bo);
  248.         return 0;
  249. }
  250.  
  251. int drm_intel_bo_busy(drm_intel_bo *bo)
  252. {
  253.         if (bo->bufmgr->bo_busy)
  254.                 return bo->bufmgr->bo_busy(bo);
  255.         return 0;
  256. }
  257.  
  258. int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
  259. {
  260.         if (bo->bufmgr->bo_madvise)
  261.                 return bo->bufmgr->bo_madvise(bo, madv);
  262.         return -1;
  263. }
  264.  
  265. int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
  266. {
  267.         return bo->bufmgr->bo_references(bo, target_bo);
  268. }
  269.  
  270.  
  271.  
  272. #if 0
  273. static size_t
  274. drm_intel_probe_agp_aperture_size(int fd)
  275. {
  276.         struct pci_device *pci_dev;
  277.         size_t size = 0;
  278.         int ret;
  279.  
  280.         ret = pci_system_init();
  281.         if (ret)
  282.                 goto err;
  283.  
  284.         /* XXX handle multiple adaptors? */
  285.         pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
  286.         if (pci_dev == NULL)
  287.                 goto err;
  288.  
  289.         ret = pci_device_probe(pci_dev);
  290.         if (ret)
  291.                 goto err;
  292.  
  293.         size = pci_dev->regions[2].size;
  294. err:
  295.         pci_system_cleanup ();
  296.         return size;
  297. }
  298. #endif
  299.  
  300. int drm_intel_get_aperture_sizes(int fd,
  301.                                  size_t *mappable,
  302.                                  size_t *total)
  303. {
  304.  
  305.         struct drm_i915_gem_get_aperture aperture;
  306.         int ret;
  307.  
  308.         ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
  309.         if (ret)
  310.                 return ret;
  311.  
  312.         /* XXX add a query for the kernel value? */
  313.     *mappable = 512 * 1024 * 1024; /* minimum possible value */
  314.         *total = aperture.aper_size;
  315.         return 0;
  316. }
  317.