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  1. /*
  2.  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
  3.  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
  4.  develop this 3D driver.
  5.  
  6.  Permission is hereby granted, free of charge, to any person obtaining
  7.  a copy of this software and associated documentation files (the
  8.  "Software"), to deal in the Software without restriction, including
  9.  without limitation the rights to use, copy, modify, merge, publish,
  10.  distribute, sublicense, and/or sell copies of the Software, and to
  11.  permit persons to whom the Software is furnished to do so, subject to
  12.  the following conditions:
  13.  
  14.  The above copyright notice and this permission notice (including the
  15.  next paragraph) shall be included in all copies or substantial
  16.  portions of the Software.
  17.  
  18.  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19.  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20.  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21.  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22.  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23.  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24.  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  
  26.  **********************************************************************/
  27.  /*
  28.   * Authors:
  29.   *   Keith Whitwell <keith@tungstengraphics.com>
  30.   */
  31.            
  32.  
  33.  
  34. #include "brw_context.h"
  35. #include "brw_state.h"
  36. #include "brw_defines.h"
  37. #include "main/macros.h"
  38.  
  39. static void
  40. brw_upload_vs_unit(struct brw_context *brw)
  41. {
  42.    struct brw_vs_unit_state *vs;
  43.  
  44.    vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
  45.                         sizeof(*vs), 32, &brw->vs.state_offset);
  46.    memset(vs, 0, sizeof(*vs));
  47.  
  48.    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
  49.    vs->thread0.grf_reg_count =
  50.       ALIGN(brw->vs.prog_data->base.total_grf, 16) / 16 - 1;
  51.    vs->thread0.kernel_start_pointer =
  52.       brw_program_reloc(brw,
  53.                         brw->vs.state_offset +
  54.                         offsetof(struct brw_vs_unit_state, thread0),
  55.                         brw->vs.prog_offset +
  56.                         (vs->thread0.grf_reg_count << 1)) >> 6;
  57.  
  58.    /* Use ALT floating point mode for ARB vertex programs, because they
  59.     * require 0^0 == 1.
  60.     */
  61.    if (brw->ctx.Shader.CurrentVertexProgram == NULL)
  62.       vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  63.    else
  64.       vs->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
  65.  
  66.    /* Choosing multiple program flow means that we may get 2-vertex threads,
  67.     * which will have the channel mask for dwords 4-7 enabled in the thread,
  68.     * and those dwords will be written to the second URB handle when we
  69.     * brw_urb_WRITE() results.
  70.     */
  71.    /* Force single program flow on Ironlake.  We cannot reliably get
  72.     * all applications working without it.  See:
  73.     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  74.     *
  75.     * The most notable and reliably failing application is the Humus
  76.     * demo "CelShading"
  77.    */
  78.    vs->thread1.single_program_flow = (brw->gen == 5);
  79.  
  80.    vs->thread1.binding_table_entry_count = 0;
  81.  
  82.    if (brw->vs.prog_data->base.total_scratch != 0) {
  83.       vs->thread2.scratch_space_base_pointer =
  84.          brw->vs.scratch_bo->offset >> 10; /* reloc */
  85.       vs->thread2.per_thread_scratch_space =
  86.          ffs(brw->vs.prog_data->base.total_scratch) - 11;
  87.    } else {
  88.       vs->thread2.scratch_space_base_pointer = 0;
  89.       vs->thread2.per_thread_scratch_space = 0;
  90.    }
  91.  
  92.    vs->thread3.urb_entry_read_length = brw->vs.prog_data->base.urb_read_length;
  93.    vs->thread3.const_urb_entry_read_length
  94.       = brw->vs.prog_data->base.curb_read_length;
  95.    vs->thread3.dispatch_grf_start_reg = 1;
  96.    vs->thread3.urb_entry_read_offset = 0;
  97.  
  98.    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */
  99.    vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
  100.  
  101.    /* BRW_NEW_URB_FENCE */
  102.    if (brw->gen == 5) {
  103.       switch (brw->urb.nr_vs_entries) {
  104.       case 8:
  105.       case 12:
  106.       case 16:
  107.       case 32:
  108.       case 64:
  109.       case 96:
  110.       case 128:
  111.       case 168:
  112.       case 192:
  113.       case 224:
  114.       case 256:
  115.          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
  116.          break;
  117.       default:
  118.          assert(0);
  119.       }
  120.    } else {
  121.       switch (brw->urb.nr_vs_entries) {
  122.       case 8:
  123.       case 12:
  124.       case 16:
  125.       case 32:
  126.          break;
  127.       case 64:
  128.          assert(brw->is_g4x);
  129.          break;
  130.       default:
  131.          assert(0);
  132.       }
  133.       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
  134.    }
  135.  
  136.    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
  137.  
  138.    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
  139.                                    1, brw->max_vs_threads) - 1;
  140.  
  141.    if (brw->gen == 5)
  142.       vs->vs5.sampler_count = 0; /* hardware requirement */
  143.    else {
  144.       /* CACHE_NEW_SAMPLER */
  145.       vs->vs5.sampler_count = (brw->sampler.count + 3) / 4;
  146.    }
  147.  
  148.  
  149.    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
  150.       vs->thread4.stats_enable = 1;
  151.  
  152.    /* Vertex program always enabled:
  153.     */
  154.    vs->vs6.vs_enable = 1;
  155.  
  156.    /* Set the sampler state pointer, and its reloc
  157.     */
  158.    if (brw->sampler.count) {
  159.       vs->vs5.sampler_state_pointer =
  160.          (brw->batch.bo->offset + brw->sampler.offset) >> 5;
  161.       drm_intel_bo_emit_reloc(brw->batch.bo,
  162.                               brw->vs.state_offset +
  163.                               offsetof(struct brw_vs_unit_state, vs5),
  164.                               brw->batch.bo,
  165.                               brw->sampler.offset | vs->vs5.sampler_count,
  166.                               I915_GEM_DOMAIN_INSTRUCTION, 0);
  167.    }
  168.  
  169.    /* Emit scratch space relocation */
  170.    if (brw->vs.prog_data->base.total_scratch != 0) {
  171.       drm_intel_bo_emit_reloc(brw->batch.bo,
  172.                               brw->vs.state_offset +
  173.                               offsetof(struct brw_vs_unit_state, thread2),
  174.                               brw->vs.scratch_bo,
  175.                               vs->thread2.per_thread_scratch_space,
  176.                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
  177.    }
  178.  
  179.    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
  180. }
  181.  
  182. const struct brw_tracked_state brw_vs_unit = {
  183.    .dirty = {
  184.       .mesa  = _NEW_TRANSFORM,
  185.       .brw   = (BRW_NEW_BATCH |
  186.                 BRW_NEW_PROGRAM_CACHE |
  187.                 BRW_NEW_CURBE_OFFSETS |
  188.                 BRW_NEW_URB_FENCE |
  189.                 BRW_NEW_VERTEX_PROGRAM),
  190.       .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
  191.    },
  192.    .emit = brw_upload_vs_unit,
  193. };
  194.