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  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  */
  23.  
  24. #ifndef BRW_VEC4_H
  25. #define BRW_VEC4_H
  26.  
  27. #include <stdint.h>
  28. #include "brw_shader.h"
  29. #include "main/compiler.h"
  30. #include "program/hash_table.h"
  31.  
  32. extern "C" {
  33. #include "brw_vs.h"
  34. #include "brw_context.h"
  35. #include "brw_eu.h"
  36. };
  37.  
  38. #include "glsl/ir.h"
  39.  
  40. namespace brw {
  41.  
  42. class dst_reg;
  43.  
  44. unsigned
  45. swizzle_for_size(int size);
  46.  
  47. class reg
  48. {
  49. public:
  50.    /** Register file: ARF, GRF, MRF, IMM. */
  51.    enum register_file file;
  52.    /** virtual register number.  0 = fixed hw reg */
  53.    int reg;
  54.    /** Offset within the virtual register. */
  55.    int reg_offset;
  56.    /** Register type.  BRW_REGISTER_TYPE_* */
  57.    int type;
  58.    struct brw_reg fixed_hw_reg;
  59.  
  60.    /** Value for file == BRW_IMMMEDIATE_FILE */
  61.    union {
  62.       int32_t i;
  63.       uint32_t u;
  64.       float f;
  65.    } imm;
  66. };
  67.  
  68. class src_reg : public reg
  69. {
  70. public:
  71.    /* Callers of this ralloc-based new need not call delete. It's
  72.     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
  73.    static void* operator new(size_t size, void *ctx)
  74.    {
  75.       void *node;
  76.  
  77.       node = ralloc_size(ctx, size);
  78.       assert(node != NULL);
  79.  
  80.       return node;
  81.    }
  82.  
  83.    void init();
  84.  
  85.    src_reg(register_file file, int reg, const glsl_type *type);
  86.    src_reg();
  87.    src_reg(float f);
  88.    src_reg(uint32_t u);
  89.    src_reg(int32_t i);
  90.  
  91.    bool equals(src_reg *r);
  92.    bool is_zero() const;
  93.    bool is_one() const;
  94.  
  95.    src_reg(class vec4_visitor *v, const struct glsl_type *type);
  96.  
  97.    explicit src_reg(dst_reg reg);
  98.  
  99.    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
  100.    bool negate;
  101.    bool abs;
  102.  
  103.    src_reg *reladdr;
  104. };
  105.  
  106. class dst_reg : public reg
  107. {
  108. public:
  109.    /* Callers of this ralloc-based new need not call delete. It's
  110.     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
  111.    static void* operator new(size_t size, void *ctx)
  112.    {
  113.       void *node;
  114.  
  115.       node = ralloc_size(ctx, size);
  116.       assert(node != NULL);
  117.  
  118.       return node;
  119.    }
  120.  
  121.    void init();
  122.  
  123.    dst_reg();
  124.    dst_reg(register_file file, int reg);
  125.    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
  126.    dst_reg(struct brw_reg reg);
  127.    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
  128.  
  129.    explicit dst_reg(src_reg reg);
  130.  
  131.    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
  132.  
  133.    src_reg *reladdr;
  134. };
  135.  
  136. class vec4_instruction : public backend_instruction {
  137. public:
  138.    /* Callers of this ralloc-based new need not call delete. It's
  139.     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
  140.    static void* operator new(size_t size, void *ctx)
  141.    {
  142.       void *node;
  143.  
  144.       node = rzalloc_size(ctx, size);
  145.       assert(node != NULL);
  146.  
  147.       return node;
  148.    }
  149.  
  150.    vec4_instruction(vec4_visitor *v, enum opcode opcode,
  151.                     dst_reg dst = dst_reg(),
  152.                     src_reg src0 = src_reg(),
  153.                     src_reg src1 = src_reg(),
  154.                     src_reg src2 = src_reg());
  155.  
  156.    struct brw_reg get_dst(void);
  157.    struct brw_reg get_src(int i);
  158.  
  159.    dst_reg dst;
  160.    src_reg src[3];
  161.  
  162.    bool saturate;
  163.    bool force_writemask_all;
  164.    bool no_dd_clear, no_dd_check;
  165.  
  166.    int conditional_mod; /**< BRW_CONDITIONAL_* */
  167.  
  168.    int sampler;
  169.    uint32_t texture_offset; /**< Texture Offset bitfield */
  170.    int target; /**< MRT target. */
  171.    bool shadow_compare;
  172.  
  173.    bool eot;
  174.    bool header_present;
  175.    int mlen; /**< SEND message length */
  176.    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
  177.  
  178.    uint32_t offset; /* spill/unspill offset */
  179.    /** @{
  180.     * Annotation for the generated IR.  One of the two can be set.
  181.     */
  182.    const void *ir;
  183.    const char *annotation;
  184.  
  185.    bool is_send_from_grf();
  186.    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
  187.    void reswizzle_dst(int dst_writemask, int swizzle);
  188. };
  189.  
  190. /**
  191.  * The vertex shader front-end.
  192.  *
  193.  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  194.  * fixed-function) into VS IR.
  195.  */
  196. class vec4_visitor : public backend_visitor
  197. {
  198. public:
  199.    vec4_visitor(struct brw_context *brw,
  200.                 struct brw_vec4_compile *c,
  201.                 struct gl_program *prog,
  202.                 const struct brw_vec4_prog_key *key,
  203.                 struct brw_vec4_prog_data *prog_data,
  204.                 struct gl_shader_program *shader_prog,
  205.                 struct brw_shader *shader,
  206.                 void *mem_ctx,
  207.                 bool debug_flag);
  208.    ~vec4_visitor();
  209.  
  210.    dst_reg dst_null_f()
  211.    {
  212.       return dst_reg(brw_null_reg());
  213.    }
  214.  
  215.    dst_reg dst_null_d()
  216.    {
  217.       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
  218.    }
  219.  
  220.    struct gl_program *prog;
  221.    struct brw_vec4_compile *c;
  222.    const struct brw_vec4_prog_key *key;
  223.    struct brw_vec4_prog_data *prog_data;
  224.    unsigned int sanity_param_count;
  225.  
  226.    char *fail_msg;
  227.    bool failed;
  228.  
  229.    /**
  230.     * GLSL IR currently being processed, which is associated with our
  231.     * driver IR instructions for debugging purposes.
  232.     */
  233.    const void *base_ir;
  234.    const char *current_annotation;
  235.  
  236.    int *virtual_grf_sizes;
  237.    int virtual_grf_count;
  238.    int virtual_grf_array_size;
  239.    int first_non_payload_grf;
  240.    unsigned int max_grf;
  241.    int *virtual_grf_start;
  242.    int *virtual_grf_end;
  243.    dst_reg userplane[MAX_CLIP_PLANES];
  244.  
  245.    /**
  246.     * This is the size to be used for an array with an element per
  247.     * reg_offset
  248.     */
  249.    int virtual_grf_reg_count;
  250.    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
  251.    int *virtual_grf_reg_map;
  252.  
  253.    bool live_intervals_valid;
  254.  
  255.    dst_reg *variable_storage(ir_variable *var);
  256.  
  257.    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
  258.  
  259.    bool need_all_constants_in_pull_buffer;
  260.  
  261.    /**
  262.     * \name Visit methods
  263.     *
  264.     * As typical for the visitor pattern, there must be one \c visit method for
  265.     * each concrete subclass of \c ir_instruction.  Virtual base classes within
  266.     * the hierarchy should not have \c visit methods.
  267.     */
  268.    /*@{*/
  269.    virtual void visit(ir_variable *);
  270.    virtual void visit(ir_loop *);
  271.    virtual void visit(ir_loop_jump *);
  272.    virtual void visit(ir_function_signature *);
  273.    virtual void visit(ir_function *);
  274.    virtual void visit(ir_expression *);
  275.    virtual void visit(ir_swizzle *);
  276.    virtual void visit(ir_dereference_variable  *);
  277.    virtual void visit(ir_dereference_array *);
  278.    virtual void visit(ir_dereference_record *);
  279.    virtual void visit(ir_assignment *);
  280.    virtual void visit(ir_constant *);
  281.    virtual void visit(ir_call *);
  282.    virtual void visit(ir_return *);
  283.    virtual void visit(ir_discard *);
  284.    virtual void visit(ir_texture *);
  285.    virtual void visit(ir_if *);
  286.    /*@}*/
  287.  
  288.    src_reg result;
  289.  
  290.    /* Regs for vertex results.  Generated at ir_variable visiting time
  291.     * for the ir->location's used.
  292.     */
  293.    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
  294.    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
  295.    int uniform_size[MAX_UNIFORMS];
  296.    int uniform_vector_size[MAX_UNIFORMS];
  297.    int uniforms;
  298.  
  299.    src_reg shader_start_time;
  300.  
  301.    struct hash_table *variable_ht;
  302.  
  303.    bool run(void);
  304.    void fail(const char *msg, ...);
  305.  
  306.    int virtual_grf_alloc(int size);
  307.    void setup_uniform_clipplane_values();
  308.    void setup_uniform_values(ir_variable *ir);
  309.    void setup_builtin_uniform_values(ir_variable *ir);
  310.    int setup_uniforms(int payload_reg);
  311.    void setup_payload();
  312.    bool reg_allocate_trivial();
  313.    bool reg_allocate();
  314.    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
  315.    int choose_spill_reg(struct ra_graph *g);
  316.    void spill_reg(int spill_reg);
  317.    void move_grf_array_access_to_scratch();
  318.    void move_uniform_array_access_to_pull_constants();
  319.    void move_push_constants_to_pull_constants();
  320.    void split_uniform_registers();
  321.    void pack_uniform_registers();
  322.    void calculate_live_intervals();
  323.    void split_virtual_grfs();
  324.    bool dead_code_eliminate();
  325.    bool virtual_grf_interferes(int a, int b);
  326.    bool opt_copy_propagation();
  327.    bool opt_algebraic();
  328.    bool opt_register_coalesce();
  329.    void opt_set_dependency_control();
  330.    void opt_schedule_instructions();
  331.  
  332.    bool can_do_source_mods(vec4_instruction *inst);
  333.  
  334.    vec4_instruction *emit(vec4_instruction *inst);
  335.  
  336.    vec4_instruction *emit(enum opcode opcode);
  337.  
  338.    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
  339.  
  340.    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
  341.                           src_reg src0, src_reg src1);
  342.  
  343.    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
  344.                           src_reg src0, src_reg src1, src_reg src2);
  345.  
  346.    vec4_instruction *emit_before(vec4_instruction *inst,
  347.                                  vec4_instruction *new_inst);
  348.  
  349.    vec4_instruction *MOV(dst_reg dst, src_reg src0);
  350.    vec4_instruction *NOT(dst_reg dst, src_reg src0);
  351.    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
  352.    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
  353.    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
  354.    vec4_instruction *FRC(dst_reg dst, src_reg src0);
  355.    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
  356.    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
  357.    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
  358.    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
  359.    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
  360.    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
  361.    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
  362.    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
  363.    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
  364.    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
  365.    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
  366.    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
  367.    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
  368.    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
  369.    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
  370.    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
  371.                          uint32_t condition);
  372.    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
  373.    vec4_instruction *IF(uint32_t predicate);
  374.    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
  375.    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
  376.    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
  377.    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
  378.    vec4_instruction *BFREV(dst_reg dst, src_reg value);
  379.    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
  380.    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
  381.    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
  382.    vec4_instruction *FBH(dst_reg dst, src_reg value);
  383.    vec4_instruction *FBL(dst_reg dst, src_reg value);
  384.    vec4_instruction *CBIT(dst_reg dst, src_reg value);
  385.  
  386.    int implied_mrf_writes(vec4_instruction *inst);
  387.  
  388.    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
  389.                                dst_reg dst,
  390.                                src_reg src,
  391.                                vec4_instruction *pre_rhs_inst,
  392.                                vec4_instruction *last_rhs_inst);
  393.  
  394.    bool try_copy_propagation(vec4_instruction *inst, int arg,
  395.                              src_reg *values[4]);
  396.  
  397.    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
  398.    void visit_instructions(const exec_list *list);
  399.  
  400.    void emit_vp_sop(uint32_t condmod, dst_reg dst,
  401.                     src_reg src0, src_reg src1, src_reg one);
  402.  
  403.    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
  404.    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
  405.    void emit_if_gen6(ir_if *ir);
  406.  
  407.    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
  408.  
  409.    void emit_block_move(dst_reg *dst, src_reg *src,
  410.                         const struct glsl_type *type, uint32_t predicate);
  411.  
  412.    void emit_constant_values(dst_reg *dst, ir_constant *value);
  413.  
  414.    /**
  415.     * Emit the correct dot-product instruction for the type of arguments
  416.     */
  417.    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
  418.  
  419.    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
  420.                     dst_reg dst, src_reg src0);
  421.  
  422.    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
  423.                     dst_reg dst, src_reg src0, src_reg src1);
  424.  
  425.    void emit_scs(ir_instruction *ir, enum prog_opcode op,
  426.                  dst_reg dst, const src_reg &src);
  427.  
  428.    src_reg fix_3src_operand(src_reg src);
  429.  
  430.    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
  431.    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
  432.    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
  433.    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
  434.    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
  435.    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
  436.    src_reg fix_math_operand(src_reg src);
  437.  
  438.    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
  439.    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
  440.  
  441.    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
  442.  
  443.    void emit_ndc_computation();
  444.    void emit_psiz_and_flags(struct brw_reg reg);
  445.    void emit_clip_distances(struct brw_reg reg, int offset);
  446.    void emit_generic_urb_slot(dst_reg reg, int varying);
  447.    void emit_urb_slot(int mrf, int varying);
  448.  
  449.    void emit_shader_time_begin();
  450.    void emit_shader_time_end();
  451.    void emit_shader_time_write(enum shader_time_shader_type type,
  452.                                src_reg value);
  453.  
  454.    src_reg get_scratch_offset(vec4_instruction *inst,
  455.                               src_reg *reladdr, int reg_offset);
  456.    src_reg get_pull_constant_offset(vec4_instruction *inst,
  457.                                     src_reg *reladdr, int reg_offset);
  458.    void emit_scratch_read(vec4_instruction *inst,
  459.                           dst_reg dst,
  460.                           src_reg orig_src,
  461.                           int base_offset);
  462.    void emit_scratch_write(vec4_instruction *inst,
  463.                            int base_offset);
  464.    void emit_pull_constant_load(vec4_instruction *inst,
  465.                                 dst_reg dst,
  466.                                 src_reg orig_src,
  467.                                 int base_offset);
  468.  
  469.    bool try_emit_sat(ir_expression *ir);
  470.    bool try_emit_mad(ir_expression *ir, int mul_arg);
  471.    void resolve_ud_negate(src_reg *reg);
  472.  
  473.    src_reg get_timestamp();
  474.  
  475.    bool process_move_condition(ir_rvalue *ir);
  476.  
  477.    void dump_instruction(backend_instruction *inst);
  478.  
  479. protected:
  480.    void emit_vertex();
  481.    void lower_attributes_to_hw_regs(const int *attribute_map);
  482.    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
  483.    virtual int setup_attributes(int payload_reg) = 0;
  484.    virtual void emit_prolog() = 0;
  485.    virtual void emit_program_code() = 0;
  486.    virtual void emit_thread_end() = 0;
  487.    virtual void emit_urb_write_header(int mrf) = 0;
  488.    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
  489.    virtual int compute_array_stride(ir_dereference_array *ir);
  490.  
  491.    const bool debug_flag;
  492. };
  493.  
  494. class vec4_vs_visitor : public vec4_visitor
  495. {
  496. public:
  497.    vec4_vs_visitor(struct brw_context *brw,
  498.                    struct brw_vs_compile *vs_compile,
  499.                    struct brw_vs_prog_data *vs_prog_data,
  500.                    struct gl_shader_program *prog,
  501.                    struct brw_shader *shader,
  502.                    void *mem_ctx);
  503.  
  504. protected:
  505.    virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
  506.    virtual int setup_attributes(int payload_reg);
  507.    virtual void emit_prolog();
  508.    virtual void emit_program_code();
  509.    virtual void emit_thread_end();
  510.    virtual void emit_urb_write_header(int mrf);
  511.    virtual vec4_instruction *emit_urb_write_opcode(bool complete);
  512.  
  513. private:
  514.    void setup_vp_regs();
  515.    dst_reg get_vp_dst_reg(const prog_dst_register &dst);
  516.    src_reg get_vp_src_reg(const prog_src_register &src);
  517.  
  518.    struct brw_vs_compile * const vs_compile;
  519.    struct brw_vs_prog_data * const vs_prog_data;
  520.    src_reg *vp_temp_regs;
  521.    src_reg vp_addr_reg;
  522. };
  523.  
  524. /**
  525.  * The vertex shader code generator.
  526.  *
  527.  * Translates VS IR to actual i965 assembly code.
  528.  */
  529. class vec4_generator
  530. {
  531. public:
  532.    vec4_generator(struct brw_context *brw,
  533.                   struct gl_shader_program *shader_prog,
  534.                   struct gl_program *prog,
  535.                   void *mem_ctx,
  536.                   bool debug_flag);
  537.    ~vec4_generator();
  538.  
  539.    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
  540.  
  541. private:
  542.    void generate_code(exec_list *instructions);
  543.    void generate_vec4_instruction(vec4_instruction *inst,
  544.                                   struct brw_reg dst,
  545.                                   struct brw_reg *src);
  546.  
  547.    void generate_math1_gen4(vec4_instruction *inst,
  548.                             struct brw_reg dst,
  549.                             struct brw_reg src);
  550.    void generate_math1_gen6(vec4_instruction *inst,
  551.                             struct brw_reg dst,
  552.                             struct brw_reg src);
  553.    void generate_math2_gen4(vec4_instruction *inst,
  554.                             struct brw_reg dst,
  555.                             struct brw_reg src0,
  556.                             struct brw_reg src1);
  557.    void generate_math2_gen6(vec4_instruction *inst,
  558.                             struct brw_reg dst,
  559.                             struct brw_reg src0,
  560.                             struct brw_reg src1);
  561.    void generate_math2_gen7(vec4_instruction *inst,
  562.                             struct brw_reg dst,
  563.                             struct brw_reg src0,
  564.                             struct brw_reg src1);
  565.  
  566.    void generate_tex(vec4_instruction *inst,
  567.                      struct brw_reg dst,
  568.                      struct brw_reg src);
  569.  
  570.    void generate_urb_write(vec4_instruction *inst);
  571.    void generate_oword_dual_block_offsets(struct brw_reg m1,
  572.                                           struct brw_reg index);
  573.    void generate_scratch_write(vec4_instruction *inst,
  574.                                struct brw_reg dst,
  575.                                struct brw_reg src,
  576.                                struct brw_reg index);
  577.    void generate_scratch_read(vec4_instruction *inst,
  578.                               struct brw_reg dst,
  579.                               struct brw_reg index);
  580.    void generate_pull_constant_load(vec4_instruction *inst,
  581.                                     struct brw_reg dst,
  582.                                     struct brw_reg index,
  583.                                     struct brw_reg offset);
  584.    void generate_pull_constant_load_gen7(vec4_instruction *inst,
  585.                                          struct brw_reg dst,
  586.                                          struct brw_reg surf_index,
  587.                                          struct brw_reg offset);
  588.  
  589.    struct brw_context *brw;
  590.    struct gl_context *ctx;
  591.  
  592.    struct brw_compile *p;
  593.  
  594.    struct gl_shader_program *shader_prog;
  595.    struct gl_shader *shader;
  596.    const struct gl_program *prog;
  597.  
  598.    void *mem_ctx;
  599.    const bool debug_flag;
  600. };
  601.  
  602. } /* namespace brw */
  603.  
  604. #endif /* BRW_VEC4_H */
  605.