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  1. /*
  2.  * Copyright © 2012 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  */
  23.  
  24. #include "main/teximage.h"
  25. #include "main/fbobject.h"
  26. #include "main/renderbuffer.h"
  27.  
  28. #include "glsl/ralloc.h"
  29.  
  30. #include "intel_fbo.h"
  31.  
  32. #include "brw_blorp.h"
  33. #include "brw_context.h"
  34. #include "brw_eu.h"
  35. #include "brw_state.h"
  36.  
  37. #define FILE_DEBUG_FLAG DEBUG_BLORP
  38.  
  39. /**
  40.  * Helper function for handling mirror image blits.
  41.  *
  42.  * If coord0 > coord1, swap them and invert the "mirror" boolean.
  43.  */
  44. static inline void
  45. fixup_mirroring(bool &mirror, GLfloat &coord0, GLfloat &coord1)
  46. {
  47.    if (coord0 > coord1) {
  48.       mirror = !mirror;
  49.       GLfloat tmp = coord0;
  50.       coord0 = coord1;
  51.       coord1 = tmp;
  52.    }
  53. }
  54.  
  55.  
  56. /**
  57.  * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
  58.  * destination coordinates.
  59.  *
  60.  * Return true if there is still blitting to do, false if all pixels got
  61.  * rejected by the clip and/or scissor.
  62.  *
  63.  * For clarity, the nomenclature of this function assumes we are clipping and
  64.  * scissoring the X coordinate; the exact same logic applies for Y
  65.  * coordinates.
  66.  *
  67.  * Note: this function may also be used to account for clipping of source
  68.  * coordinates, by swapping the roles of src and dst.
  69.  */
  70. static inline bool
  71. clip_or_scissor(bool mirror, GLfloat &src_x0, GLfloat &src_x1, GLfloat &dst_x0,
  72.                 GLfloat &dst_x1, GLfloat fb_xmin, GLfloat fb_xmax)
  73. {
  74.    float scale = (float) (src_x1 - src_x0) / (dst_x1 - dst_x0);
  75.    /* If we are going to scissor everything away, stop. */
  76.    if (!(fb_xmin < fb_xmax &&
  77.          dst_x0 < fb_xmax &&
  78.          fb_xmin < dst_x1 &&
  79.          dst_x0 < dst_x1)) {
  80.       return false;
  81.    }
  82.  
  83.    /* Clip the destination rectangle, and keep track of how many pixels we
  84.     * clipped off of the left and right sides of it.
  85.     */
  86.    GLint pixels_clipped_left = 0;
  87.    GLint pixels_clipped_right = 0;
  88.    if (dst_x0 < fb_xmin) {
  89.       pixels_clipped_left = fb_xmin - dst_x0;
  90.       dst_x0 = fb_xmin;
  91.    }
  92.    if (fb_xmax < dst_x1) {
  93.       pixels_clipped_right = dst_x1 - fb_xmax;
  94.       dst_x1 = fb_xmax;
  95.    }
  96.  
  97.    /* If we are mirrored, then before applying pixels_clipped_{left,right} to
  98.     * the source coordinates, we need to flip them to account for the
  99.     * mirroring.
  100.     */
  101.    if (mirror) {
  102.       GLint tmp = pixels_clipped_left;
  103.       pixels_clipped_left = pixels_clipped_right;
  104.       pixels_clipped_right = tmp;
  105.    }
  106.  
  107.    /* Adjust the source rectangle to remove the pixels corresponding to those
  108.     * that were clipped/scissored out of the destination rectangle.
  109.     */
  110.    src_x0 += pixels_clipped_left * scale;
  111.    src_x1 -= pixels_clipped_right * scale;
  112.  
  113.    return true;
  114. }
  115.  
  116.  
  117. static struct intel_mipmap_tree *
  118. find_miptree(GLbitfield buffer_bit, struct intel_renderbuffer *irb)
  119. {
  120.    struct intel_mipmap_tree *mt = irb->mt;
  121.    if (buffer_bit == GL_STENCIL_BUFFER_BIT && mt->stencil_mt)
  122.       mt = mt->stencil_mt;
  123.    return mt;
  124. }
  125.  
  126. void
  127. brw_blorp_blit_miptrees(struct brw_context *brw,
  128.                         struct intel_mipmap_tree *src_mt,
  129.                         unsigned src_level, unsigned src_layer,
  130.                         struct intel_mipmap_tree *dst_mt,
  131.                         unsigned dst_level, unsigned dst_layer,
  132.                         float src_x0, float src_y0,
  133.                         float src_x1, float src_y1,
  134.                         float dst_x0, float dst_y0,
  135.                         float dst_x1, float dst_y1,
  136.                         bool mirror_x, bool mirror_y)
  137. {
  138.    /* Get ready to blit.  This includes depth resolving the src and dst
  139.     * buffers if necessary.  Note: it's not necessary to do a color resolve on
  140.     * the destination buffer because we use the standard render path to render
  141.     * to destination color buffers, and the standard render path is
  142.     * fast-color-aware.
  143.     */
  144.    intel_miptree_resolve_color(brw, src_mt);
  145.    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
  146.    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
  147.  
  148.    DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
  149.        "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
  150.        __FUNCTION__,
  151.        _mesa_get_format_name(src_mt->format), src_mt,
  152.        src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
  153.        _mesa_get_format_name(dst_mt->format), dst_mt,
  154.        dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
  155.        mirror_x, mirror_y);
  156.  
  157.    brw_blorp_blit_params params(brw,
  158.                                 src_mt, src_level, src_layer,
  159.                                 dst_mt, dst_level, dst_layer,
  160.                                 src_x0, src_y0,
  161.                                 src_x1, src_y1,
  162.                                 dst_x0, dst_y0,
  163.                                 dst_x1, dst_y1,
  164.                                 mirror_x, mirror_y);
  165.    brw_blorp_exec(brw, &params);
  166.  
  167.    intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
  168. }
  169.  
  170. static void
  171. do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
  172.               struct intel_renderbuffer *src_irb,
  173.               struct intel_renderbuffer *dst_irb,
  174.               GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
  175.               GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
  176.               bool mirror_x, bool mirror_y)
  177. {
  178.    /* Find source/dst miptrees */
  179.    struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
  180.    struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
  181.  
  182.    /* Do the blit */
  183.    brw_blorp_blit_miptrees(brw,
  184.                            src_mt, src_irb->mt_level, src_irb->mt_layer,
  185.                            dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
  186.                            srcX0, srcY0, srcX1, srcY1,
  187.                            dstX0, dstY0, dstX1, dstY1,
  188.                            mirror_x, mirror_y);
  189.  
  190.    intel_renderbuffer_set_needs_downsample(dst_irb);
  191. }
  192.  
  193. static bool
  194. color_formats_match(gl_format src_format, gl_format dst_format)
  195. {
  196.    gl_format linear_src_format = _mesa_get_srgb_format_linear(src_format);
  197.    gl_format linear_dst_format = _mesa_get_srgb_format_linear(dst_format);
  198.  
  199.    /* Normally, we require the formats to be equal.  However, we also support
  200.     * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
  201.     * (overriding alpha to 1.0 via blending).
  202.     */
  203.    return linear_src_format == linear_dst_format ||
  204.           (linear_src_format == MESA_FORMAT_XRGB8888 &&
  205.            linear_dst_format == MESA_FORMAT_ARGB8888) ||
  206.           (linear_src_format == MESA_FORMAT_ARGB8888 &&
  207.            linear_dst_format == MESA_FORMAT_XRGB8888);
  208. }
  209.  
  210. static bool
  211. formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb,
  212.               struct intel_renderbuffer *dst_irb)
  213. {
  214.    /* Note: don't just check gl_renderbuffer::Format, because in some cases
  215.     * multiple gl_formats resolve to the same native type in the miptree (for
  216.     * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
  217.     * between those formats.
  218.     */
  219.    gl_format src_format = find_miptree(buffer_bit, src_irb)->format;
  220.    gl_format dst_format = find_miptree(buffer_bit, dst_irb)->format;
  221.  
  222.    return color_formats_match(src_format, dst_format);
  223. }
  224.  
  225. static bool
  226. try_blorp_blit(struct brw_context *brw,
  227.                GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
  228.                GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
  229.                GLenum filter, GLbitfield buffer_bit)
  230. {
  231.    struct gl_context *ctx = &brw->ctx;
  232.  
  233.    /* Sync up the state of window system buffers.  We need to do this before
  234.     * we go looking for the buffers.
  235.     */
  236.    intel_prepare_render(brw);
  237.  
  238.    const struct gl_framebuffer *read_fb = ctx->ReadBuffer;
  239.    const struct gl_framebuffer *draw_fb = ctx->DrawBuffer;
  240.  
  241.    /* Detect if the blit needs to be mirrored */
  242.    bool mirror_x = false, mirror_y = false;
  243.    fixup_mirroring(mirror_x, srcX0, srcX1);
  244.    fixup_mirroring(mirror_x, dstX0, dstX1);
  245.    fixup_mirroring(mirror_y, srcY0, srcY1);
  246.    fixup_mirroring(mirror_y, dstY0, dstY1);
  247.  
  248.    /* Linear filtering is not yet implemented in blorp engine. So, fallback
  249.     * to other blit paths.
  250.     */
  251.    if ((srcX1 - srcX0 != dstX1 - dstX0 ||
  252.         srcY1 - srcY0 != dstY1 - dstY0) &&
  253.        filter == GL_LINEAR)
  254.       return false;
  255.  
  256.    /* If the destination rectangle needs to be clipped or scissored, do so.
  257.     */
  258.    if (!(clip_or_scissor(mirror_x, srcX0, srcX1, dstX0, dstX1,
  259.                          draw_fb->_Xmin, draw_fb->_Xmax) &&
  260.          clip_or_scissor(mirror_y, srcY0, srcY1, dstY0, dstY1,
  261.                          draw_fb->_Ymin, draw_fb->_Ymax))) {
  262.       /* Everything got clipped/scissored away, so the blit was successful. */
  263.       return true;
  264.    }
  265.  
  266.    /* If the source rectangle needs to be clipped or scissored, do so. */
  267.    if (!(clip_or_scissor(mirror_x, dstX0, dstX1, srcX0, srcX1,
  268.                          0, read_fb->Width) &&
  269.          clip_or_scissor(mirror_y, dstY0, dstY1, srcY0, srcY1,
  270.                          0, read_fb->Height))) {
  271.       /* Everything got clipped/scissored away, so the blit was successful. */
  272.       return true;
  273.    }
  274.  
  275.    /* Account for the fact that in the system framebuffer, the origin is at
  276.     * the lower left.
  277.     */
  278.    if (_mesa_is_winsys_fbo(read_fb)) {
  279.       GLint tmp = read_fb->Height - srcY0;
  280.       srcY0 = read_fb->Height - srcY1;
  281.       srcY1 = tmp;
  282.       mirror_y = !mirror_y;
  283.    }
  284.    if (_mesa_is_winsys_fbo(draw_fb)) {
  285.       GLint tmp = draw_fb->Height - dstY0;
  286.       dstY0 = draw_fb->Height - dstY1;
  287.       dstY1 = tmp;
  288.       mirror_y = !mirror_y;
  289.    }
  290.  
  291.    /* Find buffers */
  292.    struct intel_renderbuffer *src_irb;
  293.    struct intel_renderbuffer *dst_irb;
  294.    switch (buffer_bit) {
  295.    case GL_COLOR_BUFFER_BIT:
  296.       src_irb = intel_renderbuffer(read_fb->_ColorReadBuffer);
  297.       for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) {
  298.          dst_irb = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i]);
  299.          if (dst_irb && !formats_match(buffer_bit, src_irb, dst_irb))
  300.             return false;
  301.       }
  302.       for (unsigned i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; ++i) {
  303.          dst_irb = intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i]);
  304.          if (dst_irb)
  305.             do_blorp_blit(brw, buffer_bit, src_irb, dst_irb, srcX0, srcY0,
  306.                           srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
  307.                           mirror_x, mirror_y);
  308.       }
  309.       break;
  310.    case GL_DEPTH_BUFFER_BIT:
  311.       src_irb =
  312.          intel_renderbuffer(read_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
  313.       dst_irb =
  314.          intel_renderbuffer(draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer);
  315.       if (!formats_match(buffer_bit, src_irb, dst_irb))
  316.          return false;
  317.       do_blorp_blit(brw, buffer_bit, src_irb, dst_irb, srcX0, srcY0,
  318.                     srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
  319.                     mirror_x, mirror_y);
  320.       break;
  321.    case GL_STENCIL_BUFFER_BIT:
  322.       src_irb =
  323.          intel_renderbuffer(read_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
  324.       dst_irb =
  325.          intel_renderbuffer(draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer);
  326.       if (!formats_match(buffer_bit, src_irb, dst_irb))
  327.          return false;
  328.       do_blorp_blit(brw, buffer_bit, src_irb, dst_irb, srcX0, srcY0,
  329.                     srcX1, srcY1, dstX0, dstY0, dstX1, dstY1,
  330.                     mirror_x, mirror_y);
  331.       break;
  332.    default:
  333.       assert(false);
  334.    }
  335.  
  336.    return true;
  337. }
  338.  
  339. bool
  340. brw_blorp_copytexsubimage(struct brw_context *brw,
  341.                           struct gl_renderbuffer *src_rb,
  342.                           struct gl_texture_image *dst_image,
  343.                           int slice,
  344.                           int srcX0, int srcY0,
  345.                           int dstX0, int dstY0,
  346.                           int width, int height)
  347. {
  348.    struct gl_context *ctx = &brw->ctx;
  349.    struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
  350.    struct intel_texture_image *intel_image = intel_texture_image(dst_image);
  351.  
  352.    /* Sync up the state of window system buffers.  We need to do this before
  353.     * we go looking at the src renderbuffer's miptree.
  354.     */
  355.    intel_prepare_render(brw);
  356.  
  357.    struct intel_mipmap_tree *src_mt = src_irb->mt;
  358.    struct intel_mipmap_tree *dst_mt = intel_image->mt;
  359.  
  360.    /* BLORP is not supported before Gen6. */
  361.    if (brw->gen < 6)
  362.       return false;
  363.  
  364.    if (!color_formats_match(src_mt->format, dst_mt->format)) {
  365.       return false;
  366.    }
  367.  
  368.    /* Source clipping shouldn't be necessary, since copytexsubimage (in
  369.     * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
  370.     * takes care of it.
  371.     *
  372.     * Destination clipping shouldn't be necessary since the restrictions on
  373.     * glCopyTexSubImage prevent the user from specifying a destination rectangle
  374.     * that falls outside the bounds of the destination texture.
  375.     * See error_check_subtexture_dimensions().
  376.     */
  377.  
  378.    int srcY1 = srcY0 + height;
  379.    int srcX1 = srcX0 + width;
  380.    int dstX1 = dstX0 + width;
  381.    int dstY1 = dstY0 + height;
  382.  
  383.    /* Account for the fact that in the system framebuffer, the origin is at
  384.     * the lower left.
  385.     */
  386.    bool mirror_y = false;
  387.    if (_mesa_is_winsys_fbo(ctx->ReadBuffer)) {
  388.       GLint tmp = src_rb->Height - srcY0;
  389.       srcY0 = src_rb->Height - srcY1;
  390.       srcY1 = tmp;
  391.       mirror_y = true;
  392.    }
  393.  
  394.    brw_blorp_blit_miptrees(brw,
  395.                            src_mt, src_irb->mt_level, src_irb->mt_layer,
  396.                            dst_mt, dst_image->Level, dst_image->Face + slice,
  397.                            srcX0, srcY0, srcX1, srcY1,
  398.                            dstX0, dstY0, dstX1, dstY1,
  399.                            false, mirror_y);
  400.  
  401.    /* If we're copying to a packed depth stencil texture and the source
  402.     * framebuffer has separate stencil, we need to also copy the stencil data
  403.     * over.
  404.     */
  405.    src_rb = ctx->ReadBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
  406.    if (_mesa_get_format_bits(dst_image->TexFormat, GL_STENCIL_BITS) > 0 &&
  407.        src_rb != NULL) {
  408.       src_irb = intel_renderbuffer(src_rb);
  409.       src_mt = src_irb->mt;
  410.  
  411.       if (src_mt->stencil_mt)
  412.          src_mt = src_mt->stencil_mt;
  413.       if (dst_mt->stencil_mt)
  414.          dst_mt = dst_mt->stencil_mt;
  415.  
  416.       if (src_mt != dst_mt) {
  417.          brw_blorp_blit_miptrees(brw,
  418.                                  src_mt, src_irb->mt_level, src_irb->mt_layer,
  419.                                  dst_mt, dst_image->Level,
  420.                                  dst_image->Face + slice,
  421.                                  srcX0, srcY0, srcX1, srcY1,
  422.                                  dstX0, dstY0, dstX1, dstY1,
  423.                                  false, mirror_y);
  424.       }
  425.    }
  426.  
  427.    return true;
  428. }
  429.  
  430.  
  431. GLbitfield
  432. brw_blorp_framebuffer(struct brw_context *brw,
  433.                       GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
  434.                       GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
  435.                       GLbitfield mask, GLenum filter)
  436. {
  437.    /* BLORP is not supported before Gen6. */
  438.    if (brw->gen < 6)
  439.       return mask;
  440.  
  441.    static GLbitfield buffer_bits[] = {
  442.       GL_COLOR_BUFFER_BIT,
  443.       GL_DEPTH_BUFFER_BIT,
  444.       GL_STENCIL_BUFFER_BIT,
  445.    };
  446.  
  447.    for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
  448.       if ((mask & buffer_bits[i]) &&
  449.        try_blorp_blit(brw,
  450.                       srcX0, srcY0, srcX1, srcY1,
  451.                       dstX0, dstY0, dstX1, dstY1,
  452.                       filter, buffer_bits[i])) {
  453.          mask &= ~buffer_bits[i];
  454.       }
  455.    }
  456.  
  457.    return mask;
  458. }
  459.  
  460.  
  461. /**
  462.  * Enum to specify the order of arguments in a sampler message
  463.  */
  464. enum sampler_message_arg
  465. {
  466.    SAMPLER_MESSAGE_ARG_U_FLOAT,
  467.    SAMPLER_MESSAGE_ARG_V_FLOAT,
  468.    SAMPLER_MESSAGE_ARG_U_INT,
  469.    SAMPLER_MESSAGE_ARG_V_INT,
  470.    SAMPLER_MESSAGE_ARG_SI_INT,
  471.    SAMPLER_MESSAGE_ARG_MCS_INT,
  472.    SAMPLER_MESSAGE_ARG_ZERO_INT,
  473. };
  474.  
  475. /**
  476.  * Generator for WM programs used in BLORP blits.
  477.  *
  478.  * The bulk of the work done by the WM program is to wrap and unwrap the
  479.  * coordinate transformations used by the hardware to store surfaces in
  480.  * memory.  The hardware transforms a pixel location (X, Y, S) (where S is the
  481.  * sample index for a multisampled surface) to a memory offset by the
  482.  * following formulas:
  483.  *
  484.  *   offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
  485.  *   (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
  486.  *
  487.  * For a single-sampled surface, or for a multisampled surface using
  488.  * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
  489.  * function:
  490.  *
  491.  *   encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
  492.  *   decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
  493.  *   encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
  494.  *   decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
  495.  *
  496.  * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
  497.  * embeds the sample number into bit 1 of the X and Y coordinates:
  498.  *
  499.  *   encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
  500.  *     where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
  501.  *           Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
  502.  *   decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
  503.  *     where X' = (X & ~0b11) >> 1 | (X & 0b1)
  504.  *           Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
  505.  *           S = (Y & 0b10) | (X & 0b10) >> 1
  506.  *
  507.  * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
  508.  * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
  509.  * the Y coordinate:
  510.  *
  511.  *   encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
  512.  *     where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
  513.  *           Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
  514.  *   decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
  515.  *     where X' = (X & ~0b111) >> 2 | (X & 0b1)
  516.  *           Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
  517.  *           S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
  518.  *
  519.  * For X tiling, tile() combines together the low-order bits of the X and Y
  520.  * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
  521.  * bytes wide and 8 rows high:
  522.  *
  523.  *   tile(x_tiled, X, Y, S) = A
  524.  *     where A = tile_num << 12 | offset
  525.  *           tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
  526.  *           offset = (Y' & 0b111) << 9
  527.  *                    | (X & 0b111111111)
  528.  *           X' = X * cpp
  529.  *           Y' = Y + S * qpitch
  530.  *   detile(x_tiled, A) = (X, Y, S)
  531.  *     where X = X' / cpp
  532.  *           Y = Y' % qpitch
  533.  *           S = Y' / qpitch
  534.  *           Y' = (tile_num / tile_pitch) << 3
  535.  *                | (A & 0b111000000000) >> 9
  536.  *           X' = (tile_num % tile_pitch) << 9
  537.  *                | (A & 0b111111111)
  538.  *
  539.  * (In all tiling formulas, cpp is the number of bytes occupied by a single
  540.  * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
  541.  * to fill the width of the surface, and qpitch is the spacing (in rows)
  542.  * between array slices).
  543.  *
  544.  * For Y tiling, tile() combines together the low-order bits of the X and Y
  545.  * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
  546.  * bytes wide and 32 rows high:
  547.  *
  548.  *   tile(y_tiled, X, Y, S) = A
  549.  *     where A = tile_num << 12 | offset
  550.  *           tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
  551.  *           offset = (X' & 0b1110000) << 5
  552.  *                    | (Y' & 0b11111) << 4
  553.  *                    | (X' & 0b1111)
  554.  *           X' = X * cpp
  555.  *           Y' = Y + S * qpitch
  556.  *   detile(y_tiled, A) = (X, Y, S)
  557.  *     where X = X' / cpp
  558.  *           Y = Y' % qpitch
  559.  *           S = Y' / qpitch
  560.  *           Y' = (tile_num / tile_pitch) << 5
  561.  *                | (A & 0b111110000) >> 4
  562.  *           X' = (tile_num % tile_pitch) << 7
  563.  *                | (A & 0b111000000000) >> 5
  564.  *                | (A & 0b1111)
  565.  *
  566.  * For W tiling, tile() combines together the low-order bits of the X and Y
  567.  * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
  568.  * bytes wide and 64 rows high (note that W tiling is only used for stencil
  569.  * buffers, which always have cpp = 1 and S=0):
  570.  *
  571.  *   tile(w_tiled, X, Y, S) = A
  572.  *     where A = tile_num << 12 | offset
  573.  *           tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
  574.  *           offset = (X' & 0b111000) << 6
  575.  *                    | (Y' & 0b111100) << 3
  576.  *                    | (X' & 0b100) << 2
  577.  *                    | (Y' & 0b10) << 2
  578.  *                    | (X' & 0b10) << 1
  579.  *                    | (Y' & 0b1) << 1
  580.  *                    | (X' & 0b1)
  581.  *           X' = X * cpp = X
  582.  *           Y' = Y + S * qpitch
  583.  *   detile(w_tiled, A) = (X, Y, S)
  584.  *     where X = X' / cpp = X'
  585.  *           Y = Y' % qpitch = Y'
  586.  *           S = Y / qpitch = 0
  587.  *           Y' = (tile_num / tile_pitch) << 6
  588.  *                | (A & 0b111100000) >> 3
  589.  *                | (A & 0b1000) >> 2
  590.  *                | (A & 0b10) >> 1
  591.  *           X' = (tile_num % tile_pitch) << 6
  592.  *                | (A & 0b111000000000) >> 6
  593.  *                | (A & 0b10000) >> 2
  594.  *                | (A & 0b100) >> 1
  595.  *                | (A & 0b1)
  596.  *
  597.  * Finally, for a non-tiled surface, tile() simply combines together the X and
  598.  * Y coordinates in the natural way:
  599.  *
  600.  *   tile(untiled, X, Y, S) = A
  601.  *     where A = Y * pitch + X'
  602.  *           X' = X * cpp
  603.  *           Y' = Y + S * qpitch
  604.  *   detile(untiled, A) = (X, Y, S)
  605.  *     where X = X' / cpp
  606.  *           Y = Y' % qpitch
  607.  *           S = Y' / qpitch
  608.  *           X' = A % pitch
  609.  *           Y' = A / pitch
  610.  *
  611.  * (In these formulas, pitch is the number of bytes occupied by a single row
  612.  * of samples).
  613.  */
  614. class brw_blorp_blit_program
  615. {
  616. public:
  617.    brw_blorp_blit_program(struct brw_context *brw,
  618.                           const brw_blorp_blit_prog_key *key);
  619.    ~brw_blorp_blit_program();
  620.  
  621.    const GLuint *compile(struct brw_context *brw, GLuint *program_size);
  622.  
  623.    brw_blorp_prog_data prog_data;
  624.  
  625. private:
  626.    void alloc_regs();
  627.    void alloc_push_const_regs(int base_reg);
  628.    void compute_frag_coords();
  629.    void translate_tiling(bool old_tiled_w, bool new_tiled_w);
  630.    void encode_msaa(unsigned num_samples, intel_msaa_layout layout);
  631.    void decode_msaa(unsigned num_samples, intel_msaa_layout layout);
  632.    void kill_if_outside_dst_rect();
  633.    void translate_dst_to_src();
  634.    void single_to_blend();
  635.    void manual_blend_average(unsigned num_samples);
  636.    void manual_blend_bilinear(unsigned num_samples);
  637.    void sample(struct brw_reg dst);
  638.    void texel_fetch(struct brw_reg dst);
  639.    void mcs_fetch();
  640.    void texture_lookup(struct brw_reg dst, GLuint msg_type,
  641.                        const sampler_message_arg *args, int num_args);
  642.    void render_target_write();
  643.  
  644.    /**
  645.     * Base-2 logarithm of the maximum number of samples that can be blended.
  646.     */
  647.    static const unsigned LOG2_MAX_BLEND_SAMPLES = 3;
  648.  
  649.    void *mem_ctx;
  650.    struct brw_context *brw;
  651.    const brw_blorp_blit_prog_key *key;
  652.    struct brw_compile func;
  653.  
  654.    /* Thread dispatch header */
  655.    struct brw_reg R0;
  656.  
  657.    /* Pixel X/Y coordinates (always in R1). */
  658.    struct brw_reg R1;
  659.  
  660.    /* Push constants */
  661.    struct brw_reg dst_x0;
  662.    struct brw_reg dst_x1;
  663.    struct brw_reg dst_y0;
  664.    struct brw_reg dst_y1;
  665.    /* Top right coordinates of the rectangular sample grid used for
  666.     * multisample scaled blitting.
  667.     */
  668.    struct brw_reg sample_grid_x1;
  669.    struct brw_reg sample_grid_y1;
  670.    struct {
  671.       struct brw_reg multiplier;
  672.       struct brw_reg offset;
  673.    } x_transform, y_transform;
  674.  
  675.    /* Data read from texture (4 vec16's per array element) */
  676.    struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1];
  677.  
  678.    /* Auxiliary storage for the contents of the MCS surface.
  679.     *
  680.     * Since the sampler always returns 8 registers worth of data, this is 8
  681.     * registers wide, even though we only use the first 2 registers of it.
  682.     */
  683.    struct brw_reg mcs_data;
  684.  
  685.    /* X coordinates.  We have two of them so that we can perform coordinate
  686.     * transformations easily.
  687.     */
  688.    struct brw_reg x_coords[2];
  689.  
  690.    /* Y coordinates.  We have two of them so that we can perform coordinate
  691.     * transformations easily.
  692.     */
  693.    struct brw_reg y_coords[2];
  694.  
  695.    /* X, Y coordinates of the pixel from which we need to fetch the specific
  696.     *  sample. These are used for multisample scaled blitting.
  697.     */
  698.    struct brw_reg x_sample_coords;
  699.    struct brw_reg y_sample_coords;
  700.  
  701.    /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
  702.    struct brw_reg x_frac;
  703.    struct brw_reg y_frac;
  704.  
  705.    /* Which element of x_coords and y_coords is currently in use.
  706.     */
  707.    int xy_coord_index;
  708.  
  709.    /* True if, at the point in the program currently being compiled, the
  710.     * sample index is known to be zero.
  711.     */
  712.    bool s_is_zero;
  713.  
  714.    /* Register storing the sample index when s_is_zero is false. */
  715.    struct brw_reg sample_index;
  716.  
  717.    /* Temporaries */
  718.    struct brw_reg t1;
  719.    struct brw_reg t2;
  720.  
  721.    /* MRF used for sampling and render target writes */
  722.    GLuint base_mrf;
  723. };
  724.  
  725. brw_blorp_blit_program::brw_blorp_blit_program(
  726.       struct brw_context *brw,
  727.       const brw_blorp_blit_prog_key *key)
  728.    : mem_ctx(ralloc_context(NULL)),
  729.      brw(brw),
  730.      key(key)
  731. {
  732.    brw_init_compile(brw, &func, mem_ctx);
  733. }
  734.  
  735. brw_blorp_blit_program::~brw_blorp_blit_program()
  736. {
  737.    ralloc_free(mem_ctx);
  738. }
  739.  
  740. const GLuint *
  741. brw_blorp_blit_program::compile(struct brw_context *brw,
  742.                                 GLuint *program_size)
  743. {
  744.    /* Sanity checks */
  745.    if (key->dst_tiled_w && key->rt_samples > 0) {
  746.       /* If the destination image is W tiled and multisampled, then the thread
  747.        * must be dispatched once per sample, not once per pixel.  This is
  748.        * necessary because after conversion between W and Y tiling, there's no
  749.        * guarantee that all samples corresponding to a single pixel will still
  750.        * be together.
  751.        */
  752.       assert(key->persample_msaa_dispatch);
  753.    }
  754.  
  755.    if (key->blend) {
  756.       /* We are blending, which means we won't have an opportunity to
  757.        * translate the tiling and sample count for the texture surface.  So
  758.        * the surface state for the texture must be configured with the correct
  759.        * tiling and sample count.
  760.        */
  761.       assert(!key->src_tiled_w);
  762.       assert(key->tex_samples == key->src_samples);
  763.       assert(key->tex_layout == key->src_layout);
  764.       assert(key->tex_samples > 0);
  765.    }
  766.  
  767.    if (key->persample_msaa_dispatch) {
  768.       /* It only makes sense to do persample dispatch if the render target is
  769.        * configured as multisampled.
  770.        */
  771.       assert(key->rt_samples > 0);
  772.    }
  773.  
  774.    /* Make sure layout is consistent with sample count */
  775.    assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) ==
  776.           (key->tex_samples == 0));
  777.    assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) ==
  778.           (key->rt_samples == 0));
  779.    assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) ==
  780.           (key->src_samples == 0));
  781.    assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) ==
  782.           (key->dst_samples == 0));
  783.  
  784.    /* Set up prog_data */
  785.    memset(&prog_data, 0, sizeof(prog_data));
  786.    prog_data.persample_msaa_dispatch = key->persample_msaa_dispatch;
  787.  
  788.    brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
  789.  
  790.    alloc_regs();
  791.    compute_frag_coords();
  792.  
  793.    /* Render target and texture hardware don't support W tiling. */
  794.    const bool rt_tiled_w = false;
  795.    const bool tex_tiled_w = false;
  796.  
  797.    /* The address that data will be written to is determined by the
  798.     * coordinates supplied to the WM thread and the tiling and sample count of
  799.     * the render target, according to the formula:
  800.     *
  801.     * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
  802.     *
  803.     * If the actual tiling and sample count of the destination surface are not
  804.     * the same as the configuration of the render target, then these
  805.     * coordinates are wrong and we have to adjust them to compensate for the
  806.     * difference.
  807.     */
  808.    if (rt_tiled_w != key->dst_tiled_w ||
  809.        key->rt_samples != key->dst_samples ||
  810.        key->rt_layout != key->dst_layout) {
  811.       encode_msaa(key->rt_samples, key->rt_layout);
  812.       /* Now (X, Y, S) = detile(rt_tiling, offset) */
  813.       translate_tiling(rt_tiled_w, key->dst_tiled_w);
  814.       /* Now (X, Y, S) = detile(dst_tiling, offset) */
  815.       decode_msaa(key->dst_samples, key->dst_layout);
  816.    }
  817.  
  818.    /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
  819.     *
  820.     * That is: X, Y and S now contain the true coordinates and sample index of
  821.     * the data that the WM thread should output.
  822.     *
  823.     * If we need to kill pixels that are outside the destination rectangle,
  824.     * now is the time to do it.
  825.     */
  826.  
  827.    if (key->use_kill)
  828.       kill_if_outside_dst_rect();
  829.  
  830.    /* Next, apply a translation to obtain coordinates in the source image. */
  831.    translate_dst_to_src();
  832.  
  833.    /* If the source image is not multisampled, then we want to fetch sample
  834.     * number 0, because that's the only sample there is.
  835.     */
  836.    if (key->src_samples == 0)
  837.       s_is_zero = true;
  838.  
  839.    /* X, Y, and S are now the coordinates of the pixel in the source image
  840.     * that we want to texture from.  Exception: if we are blending, then S is
  841.     * irrelevant, because we are going to fetch all samples.
  842.     */
  843.    if (key->blend && !key->blit_scaled) {
  844.       if (brw->gen == 6) {
  845.          /* Gen6 hardware an automatically blend using the SAMPLE message */
  846.          single_to_blend();
  847.          sample(texture_data[0]);
  848.       } else {
  849.          /* Gen7+ hardware doesn't automaticaly blend. */
  850.          manual_blend_average(key->src_samples);
  851.       }
  852.    } else if(key->blend && key->blit_scaled) {
  853.       manual_blend_bilinear(key->src_samples);
  854.    } else {
  855.       /* We aren't blending, which means we just want to fetch a single sample
  856.        * from the source surface.  The address that we want to fetch from is
  857.        * related to the X, Y and S values according to the formula:
  858.        *
  859.        * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
  860.        *
  861.        * If the actual tiling and sample count of the source surface are not
  862.        * the same as the configuration of the texture, then we need to adjust
  863.        * the coordinates to compensate for the difference.
  864.        */
  865.       if (tex_tiled_w != key->src_tiled_w ||
  866.           key->tex_samples != key->src_samples ||
  867.           key->tex_layout != key->src_layout) {
  868.          encode_msaa(key->src_samples, key->src_layout);
  869.          /* Now (X, Y, S) = detile(src_tiling, offset) */
  870.          translate_tiling(key->src_tiled_w, tex_tiled_w);
  871.          /* Now (X, Y, S) = detile(tex_tiling, offset) */
  872.          decode_msaa(key->tex_samples, key->tex_layout);
  873.       }
  874.  
  875.       /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
  876.        *
  877.        * In other words: X, Y, and S now contain values which, when passed to
  878.        * the texturing unit, will cause data to be read from the correct
  879.        * memory location.  So we can fetch the texel now.
  880.        */
  881.       if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
  882.          mcs_fetch();
  883.       texel_fetch(texture_data[0]);
  884.    }
  885.  
  886.    /* Finally, write the fetched (or blended) value to the render target and
  887.     * terminate the thread.
  888.     */
  889.    render_target_write();
  890.  
  891.    if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
  892.       printf("Native code for BLORP blit:\n");
  893.       brw_dump_compile(&func, stdout, 0, func.next_insn_offset);
  894.       printf("\n");
  895.    }
  896.    return brw_get_program(&func, program_size);
  897. }
  898.  
  899. void
  900. brw_blorp_blit_program::alloc_push_const_regs(int base_reg)
  901. {
  902. #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
  903. #define ALLOC_REG(name) \
  904.    this->name = \
  905.       brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
  906.                    base_reg + CONST_LOC(name) / 32, \
  907.                    (CONST_LOC(name) % 32) / 4)
  908.  
  909.    ALLOC_REG(dst_x0);
  910.    ALLOC_REG(dst_x1);
  911.    ALLOC_REG(dst_y0);
  912.    ALLOC_REG(dst_y1);
  913.    ALLOC_REG(sample_grid_x1);
  914.    ALLOC_REG(sample_grid_y1);
  915.    ALLOC_REG(x_transform.multiplier);
  916.    ALLOC_REG(x_transform.offset);
  917.    ALLOC_REG(y_transform.multiplier);
  918.    ALLOC_REG(y_transform.offset);
  919. #undef CONST_LOC
  920. #undef ALLOC_REG
  921. }
  922.  
  923. void
  924. brw_blorp_blit_program::alloc_regs()
  925. {
  926.    int reg = 0;
  927.    this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW);
  928.    this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW);
  929.    prog_data.first_curbe_grf = reg;
  930.    alloc_push_const_regs(reg);
  931.    reg += BRW_BLORP_NUM_PUSH_CONST_REGS;
  932.    for (unsigned i = 0; i < ARRAY_SIZE(texture_data); ++i) {
  933.       this->texture_data[i] =
  934.          retype(vec16(brw_vec8_grf(reg, 0)), key->texture_data_type);
  935.       reg += 8;
  936.    }
  937.    this->mcs_data =
  938.       retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8;
  939.  
  940.    for (int i = 0; i < 2; ++i) {
  941.       this->x_coords[i]
  942.          = retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD);
  943.       reg += 2;
  944.       this->y_coords[i]
  945.          = retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD);
  946.       reg += 2;
  947.    }
  948.  
  949.    if (key->blit_scaled && key->blend) {
  950.       this->x_sample_coords = brw_vec8_grf(reg, 0);
  951.       reg += 2;
  952.       this->y_sample_coords = brw_vec8_grf(reg, 0);
  953.       reg += 2;
  954.       this->x_frac = brw_vec8_grf(reg, 0);
  955.       reg += 2;
  956.       this->y_frac = brw_vec8_grf(reg, 0);
  957.       reg += 2;
  958.    }
  959.  
  960.    this->xy_coord_index = 0;
  961.    this->sample_index
  962.       = retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD);
  963.    reg += 2;
  964.    this->t1 = retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD);
  965.    reg += 2;
  966.    this->t2 = retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD);
  967.    reg += 2;
  968.  
  969.    /* Make sure we didn't run out of registers */
  970.    assert(reg <= GEN7_MRF_HACK_START);
  971.  
  972.    int mrf = 2;
  973.    this->base_mrf = mrf;
  974. }
  975.  
  976. /* In the code that follows, X and Y can be used to quickly refer to the
  977.  * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
  978.  * prime") to the inactive elements.
  979.  *
  980.  * S can be used to quickly refer to sample_index.
  981.  */
  982. #define X x_coords[xy_coord_index]
  983. #define Y y_coords[xy_coord_index]
  984. #define Xp x_coords[!xy_coord_index]
  985. #define Yp y_coords[!xy_coord_index]
  986. #define S sample_index
  987.  
  988. /* Quickly swap the roles of (X, Y) and (Xp, Yp).  Saves us from having to do
  989.  * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
  990.  */
  991. #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
  992.  
  993. /**
  994.  * Emit code to compute the X and Y coordinates of the pixels being rendered
  995.  * by this WM invocation.
  996.  *
  997.  * Assuming the render target is set up for Y tiling, these (X, Y) values are
  998.  * related to the address offset where outputs will be written by the formula:
  999.  *
  1000.  *   (X, Y, S) = decode_msaa(detile(offset)).
  1001.  *
  1002.  * (See brw_blorp_blit_program).
  1003.  */
  1004. void
  1005. brw_blorp_blit_program::compute_frag_coords()
  1006. {
  1007.    /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
  1008.     * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
  1009.     * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
  1010.     * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
  1011.     *
  1012.     * Pixels within a subspan are laid out in this arrangement:
  1013.     * 0 1
  1014.     * 2 3
  1015.     *
  1016.     * So, to compute the coordinates of each pixel, we need to read every 2nd
  1017.     * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
  1018.     * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
  1019.     * In other words, the data we want to access is R1.4<2;4,0>UW.
  1020.     *
  1021.     * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
  1022.     * result, since pixels n+1 and n+3 are in the right half of the subspan.
  1023.     */
  1024.    brw_ADD(&func, vec16(retype(X, BRW_REGISTER_TYPE_UW)),
  1025.            stride(suboffset(R1, 4), 2, 4, 0), brw_imm_v(0x10101010));
  1026.  
  1027.    /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
  1028.     * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
  1029.     * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
  1030.     * R1.4<2;4,0>UW).
  1031.     *
  1032.     * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
  1033.     * pixels n+2 and n+3 are in the bottom half of the subspan.
  1034.     */
  1035.    brw_ADD(&func, vec16(retype(Y, BRW_REGISTER_TYPE_UW)),
  1036.            stride(suboffset(R1, 5), 2, 4, 0), brw_imm_v(0x11001100));
  1037.  
  1038.    /* Move the coordinates to UD registers. */
  1039.    brw_MOV(&func, vec16(Xp), retype(X, BRW_REGISTER_TYPE_UW));
  1040.    brw_MOV(&func, vec16(Yp), retype(Y, BRW_REGISTER_TYPE_UW));
  1041.    SWAP_XY_AND_XPYP();
  1042.  
  1043.    if (key->persample_msaa_dispatch) {
  1044.       switch (key->rt_samples) {
  1045.       case 4: {
  1046.          /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
  1047.           * Therefore, subspan 0 will represent sample 0, subspan 1 will
  1048.           * represent sample 1, and so on.
  1049.           *
  1050.           * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
  1051.           * 1, 2, 2, 2, 2, 3, 3, 3, 3).  The easiest way to do this is to
  1052.           * populate a temporary variable with the sequence (0, 1, 2, 3), and
  1053.           * then copy from it using vstride=1, width=4, hstride=0.
  1054.           */
  1055.          struct brw_reg t1_uw1 = retype(t1, BRW_REGISTER_TYPE_UW);
  1056.          brw_MOV(&func, vec16(t1_uw1), brw_imm_v(0x3210));
  1057.          /* Move to UD sample_index register. */
  1058.          brw_MOV(&func, S, stride(t1_uw1, 1, 4, 0));
  1059.          brw_MOV(&func, offset(S, 1), suboffset(stride(t1_uw1, 1, 4, 0), 2));
  1060.          break;
  1061.       }
  1062.       case 8: {
  1063.          /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
  1064.           * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
  1065.           * subspan 1 will represent sample 1, and so on.  We can find the
  1066.           * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
  1067.           * Index") and multiplying by two (since samples are always delivered
  1068.           * in pairs).  That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
  1069.           * 0xc0) >> 5.
  1070.           *
  1071.           * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
  1072.           * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
  1073.           * variable with the sequence (0, 1, 2, 3), and then reading from it
  1074.           * using vstride=1, width=4, hstride=0.
  1075.           */
  1076.          struct brw_reg t1_ud1 = vec1(retype(t1, BRW_REGISTER_TYPE_UD));
  1077.          struct brw_reg t2_uw1 = retype(t2, BRW_REGISTER_TYPE_UW);
  1078.          struct brw_reg r0_ud1 = vec1(retype(R0, BRW_REGISTER_TYPE_UD));
  1079.          brw_AND(&func, t1_ud1, r0_ud1, brw_imm_ud(0xc0));
  1080.          brw_SHR(&func, t1_ud1, t1_ud1, brw_imm_ud(5));
  1081.          brw_MOV(&func, vec16(t2_uw1), brw_imm_v(0x3210));
  1082.          brw_ADD(&func, vec16(S), retype(t1_ud1, BRW_REGISTER_TYPE_UW),
  1083.                  stride(t2_uw1, 1, 4, 0));
  1084.          brw_ADD(&func, offset(S, 1),
  1085.                  retype(t1_ud1, BRW_REGISTER_TYPE_UW),
  1086.                  suboffset(stride(t2_uw1, 1, 4, 0), 2));
  1087.          break;
  1088.       }
  1089.       default:
  1090.          assert(!"Unrecognized sample count in "
  1091.                 "brw_blorp_blit_program::compute_frag_coords()");
  1092.          break;
  1093.       }
  1094.       s_is_zero = false;
  1095.    } else {
  1096.       /* Either the destination surface is single-sampled, or the WM will be
  1097.        * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
  1098.        * per pixel).  In either case, it's not meaningful to compute a sample
  1099.        * value.  Just set it to 0.
  1100.        */
  1101.       s_is_zero = true;
  1102.    }
  1103. }
  1104.  
  1105. /**
  1106.  * Emit code to compensate for the difference between Y and W tiling.
  1107.  *
  1108.  * This code modifies the X and Y coordinates according to the formula:
  1109.  *
  1110.  *   (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
  1111.  *
  1112.  * (See brw_blorp_blit_program).
  1113.  *
  1114.  * It can only translate between W and Y tiling, so new_tiling and old_tiling
  1115.  * are booleans where true represents W tiling and false represents Y tiling.
  1116.  */
  1117. void
  1118. brw_blorp_blit_program::translate_tiling(bool old_tiled_w, bool new_tiled_w)
  1119. {
  1120.    if (old_tiled_w == new_tiled_w)
  1121.       return;
  1122.  
  1123.    /* In the code that follows, we can safely assume that S = 0, because W
  1124.     * tiling formats always use IMS layout.
  1125.     */
  1126.    assert(s_is_zero);
  1127.  
  1128.    brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
  1129.    if (new_tiled_w) {
  1130.       /* Given X and Y coordinates that describe an address using Y tiling,
  1131.        * translate to the X and Y coordinates that describe the same address
  1132.        * using W tiling.
  1133.        *
  1134.        * If we break down the low order bits of X and Y, using a
  1135.        * single letter to represent each low-order bit:
  1136.        *
  1137.        *   X = A << 7 | 0bBCDEFGH
  1138.        *   Y = J << 5 | 0bKLMNP                                       (1)
  1139.        *
  1140.        * Then we can apply the Y tiling formula to see the memory offset being
  1141.        * addressed:
  1142.        *
  1143.        *   offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH       (2)
  1144.        *
  1145.        * If we apply the W detiling formula to this memory location, that the
  1146.        * corresponding X' and Y' coordinates are:
  1147.        *
  1148.        *   X' = A << 6 | 0bBCDPFH                                     (3)
  1149.        *   Y' = J << 6 | 0bKLMNEG
  1150.        *
  1151.        * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
  1152.        * we need to make the following computation:
  1153.        *
  1154.        *   X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1         (4)
  1155.        *   Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
  1156.        */
  1157.       brw_AND(&func, t1, X, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
  1158.       brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
  1159.       brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
  1160.       brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
  1161.       brw_OR(&func, t1, t1, t2); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
  1162.       brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
  1163.       brw_OR(&func, Xp, t1, t2);
  1164.       brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
  1165.       brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
  1166.       brw_AND(&func, t2, X, brw_imm_uw(8)); /* X & 0b1000 */
  1167.       brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
  1168.       brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
  1169.       brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */
  1170.       brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
  1171.       brw_OR(&func, Yp, t1, t2);
  1172.       SWAP_XY_AND_XPYP();
  1173.    } else {
  1174.       /* Applying the same logic as above, but in reverse, we obtain the
  1175.        * formulas:
  1176.        *
  1177.        * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
  1178.        * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
  1179.        */
  1180.       brw_AND(&func, t1, X, brw_imm_uw(0xfffa)); /* X & ~0b101 */
  1181.       brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
  1182.       brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */
  1183.       brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
  1184.       brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
  1185.       brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
  1186.       brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
  1187.       brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
  1188.                                     | (Y & 0b1) << 1 */
  1189.       brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
  1190.       brw_OR(&func, Xp, t1, t2);
  1191.       brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
  1192.       brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
  1193.       brw_AND(&func, t2, X, brw_imm_uw(4)); /* X & 0b100 */
  1194.       brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
  1195.       brw_OR(&func, Yp, t1, t2);
  1196.       SWAP_XY_AND_XPYP();
  1197.    }
  1198.    brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
  1199. }
  1200.  
  1201. /**
  1202.  * Emit code to compensate for the difference between MSAA and non-MSAA
  1203.  * surfaces.
  1204.  *
  1205.  * This code modifies the X and Y coordinates according to the formula:
  1206.  *
  1207.  *   (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
  1208.  *
  1209.  * (See brw_blorp_blit_program).
  1210.  */
  1211. void
  1212. brw_blorp_blit_program::encode_msaa(unsigned num_samples,
  1213.                                     intel_msaa_layout layout)
  1214. {
  1215.    brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
  1216.    switch (layout) {
  1217.    case INTEL_MSAA_LAYOUT_NONE:
  1218.       /* No translation necessary, and S should already be zero. */
  1219.       assert(s_is_zero);
  1220.       break;
  1221.    case INTEL_MSAA_LAYOUT_CMS:
  1222.       /* We can't compensate for compressed layout since at this point in the
  1223.        * program we haven't read from the MCS buffer.
  1224.        */
  1225.       assert(!"Bad layout in encode_msaa");
  1226.       break;
  1227.    case INTEL_MSAA_LAYOUT_UMS:
  1228.       /* No translation necessary. */
  1229.       break;
  1230.    case INTEL_MSAA_LAYOUT_IMS:
  1231.       switch (num_samples) {
  1232.       case 4:
  1233.          /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
  1234.           *   where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
  1235.           *         Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
  1236.           */
  1237.          brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */
  1238.          if (!s_is_zero) {
  1239.             brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */
  1240.             brw_OR(&func, t1, t1, t2); /* (X & ~0b1) | (S & 0b1) */
  1241.          }
  1242.          brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1) << 1
  1243.                                                    | (S & 0b1) << 1 */
  1244.          brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
  1245.          brw_OR(&func, Xp, t1, t2);
  1246.          brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
  1247.          brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
  1248.          if (!s_is_zero) {
  1249.             brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */
  1250.             brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */
  1251.          }
  1252.          brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
  1253.          brw_OR(&func, Yp, t1, t2);
  1254.          break;
  1255.       case 8:
  1256.          /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
  1257.           *   where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
  1258.           *              | (X & 0b1)
  1259.           *         Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
  1260.           */
  1261.          brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */
  1262.          brw_SHL(&func, t1, t1, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
  1263.          if (!s_is_zero) {
  1264.             brw_AND(&func, t2, S, brw_imm_uw(4)); /* S & 0b100 */
  1265.             brw_OR(&func, t1, t1, t2); /* (X & ~0b1) << 2 | (S & 0b100) */
  1266.             brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */
  1267.             brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (S & 0b1) << 1 */
  1268.             brw_OR(&func, t1, t1, t2); /* (X & ~0b1) << 2 | (S & 0b100)
  1269.                                           | (S & 0b1) << 1 */
  1270.          }
  1271.          brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
  1272.          brw_OR(&func, Xp, t1, t2);
  1273.          brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
  1274.          brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
  1275.          if (!s_is_zero) {
  1276.             brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */
  1277.             brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */
  1278.          }
  1279.          brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
  1280.          brw_OR(&func, Yp, t1, t2);
  1281.          break;
  1282.       }
  1283.       SWAP_XY_AND_XPYP();
  1284.       s_is_zero = true;
  1285.       break;
  1286.    }
  1287.    brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
  1288. }
  1289.  
  1290. /**
  1291.  * Emit code to compensate for the difference between MSAA and non-MSAA
  1292.  * surfaces.
  1293.  *
  1294.  * This code modifies the X and Y coordinates according to the formula:
  1295.  *
  1296.  *   (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
  1297.  *
  1298.  * (See brw_blorp_blit_program).
  1299.  */
  1300. void
  1301. brw_blorp_blit_program::decode_msaa(unsigned num_samples,
  1302.                                     intel_msaa_layout layout)
  1303. {
  1304.    brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
  1305.    switch (layout) {
  1306.    case INTEL_MSAA_LAYOUT_NONE:
  1307.       /* No translation necessary, and S should already be zero. */
  1308.       assert(s_is_zero);
  1309.       break;
  1310.    case INTEL_MSAA_LAYOUT_CMS:
  1311.       /* We can't compensate for compressed layout since at this point in the
  1312.        * program we don't have access to the MCS buffer.
  1313.        */
  1314.       assert(!"Bad layout in encode_msaa");
  1315.       break;
  1316.    case INTEL_MSAA_LAYOUT_UMS:
  1317.       /* No translation necessary. */
  1318.       break;
  1319.    case INTEL_MSAA_LAYOUT_IMS:
  1320.       assert(s_is_zero);
  1321.       switch (num_samples) {
  1322.       case 4:
  1323.          /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
  1324.           *   where X' = (X & ~0b11) >> 1 | (X & 0b1)
  1325.           *         Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
  1326.           *         S = (Y & 0b10) | (X & 0b10) >> 1
  1327.           */
  1328.          brw_AND(&func, t1, X, brw_imm_uw(0xfffc)); /* X & ~0b11 */
  1329.          brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
  1330.          brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
  1331.          brw_OR(&func, Xp, t1, t2);
  1332.          brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
  1333.          brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
  1334.          brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
  1335.          brw_OR(&func, Yp, t1, t2);
  1336.          brw_AND(&func, t1, Y, brw_imm_uw(2)); /* Y & 0b10 */
  1337.          brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */
  1338.          brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
  1339.          brw_OR(&func, S, t1, t2);
  1340.          break;
  1341.       case 8:
  1342.          /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
  1343.           *   where X' = (X & ~0b111) >> 2 | (X & 0b1)
  1344.           *         Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
  1345.           *         S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
  1346.           */
  1347.          brw_AND(&func, t1, X, brw_imm_uw(0xfff8)); /* X & ~0b111 */
  1348.          brw_SHR(&func, t1, t1, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
  1349.          brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
  1350.          brw_OR(&func, Xp, t1, t2);
  1351.          brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
  1352.          brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
  1353.          brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
  1354.          brw_OR(&func, Yp, t1, t2);
  1355.          brw_AND(&func, t1, X, brw_imm_uw(4)); /* X & 0b100 */
  1356.          brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */
  1357.          brw_OR(&func, t1, t1, t2); /* (X & 0b100) | (Y & 0b10) */
  1358.          brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */
  1359.          brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
  1360.          brw_OR(&func, S, t1, t2);
  1361.          break;
  1362.       }
  1363.       s_is_zero = false;
  1364.       SWAP_XY_AND_XPYP();
  1365.       break;
  1366.    }
  1367.    brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
  1368. }
  1369.  
  1370. /**
  1371.  * Emit code that kills pixels whose X and Y coordinates are outside the
  1372.  * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
  1373.  * dst_x1, dst_y1).
  1374.  */
  1375. void
  1376. brw_blorp_blit_program::kill_if_outside_dst_rect()
  1377. {
  1378.    struct brw_reg f0 = brw_flag_reg(0, 0);
  1379.    struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
  1380.    struct brw_reg null32 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
  1381.  
  1382.    brw_CMP(&func, null32, BRW_CONDITIONAL_GE, X, dst_x0);
  1383.    brw_CMP(&func, null32, BRW_CONDITIONAL_GE, Y, dst_y0);
  1384.    brw_CMP(&func, null32, BRW_CONDITIONAL_L, X, dst_x1);
  1385.    brw_CMP(&func, null32, BRW_CONDITIONAL_L, Y, dst_y1);
  1386.  
  1387.    brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1388.    brw_push_insn_state(&func);
  1389.    brw_set_mask_control(&func, BRW_MASK_DISABLE);
  1390.    brw_AND(&func, g1, f0, g1);
  1391.    brw_pop_insn_state(&func);
  1392. }
  1393.  
  1394. /**
  1395.  * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
  1396.  * coordinates.
  1397.  */
  1398. void
  1399. brw_blorp_blit_program::translate_dst_to_src()
  1400. {
  1401.    struct brw_reg X_f = retype(X, BRW_REGISTER_TYPE_F);
  1402.    struct brw_reg Y_f = retype(Y, BRW_REGISTER_TYPE_F);
  1403.    struct brw_reg Xp_f = retype(Xp, BRW_REGISTER_TYPE_F);
  1404.    struct brw_reg Yp_f = retype(Yp, BRW_REGISTER_TYPE_F);
  1405.  
  1406.    brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
  1407.    /* Move the UD coordinates to float registers. */
  1408.    brw_MOV(&func, Xp_f, X);
  1409.    brw_MOV(&func, Yp_f, Y);
  1410.    /* Scale and offset */
  1411.    brw_MUL(&func, X_f, Xp_f, x_transform.multiplier);
  1412.    brw_MUL(&func, Y_f, Yp_f, y_transform.multiplier);
  1413.    brw_ADD(&func, X_f, X_f, x_transform.offset);
  1414.    brw_ADD(&func, Y_f, Y_f, y_transform.offset);
  1415.    if (key->blit_scaled && key->blend) {
  1416.       /* Translate coordinates to lay out the samples in a rectangular  grid
  1417.        * roughly corresponding to sample locations.
  1418.        */
  1419.       brw_MUL(&func, X_f, X_f, brw_imm_f(key->x_scale));
  1420.       brw_MUL(&func, Y_f, Y_f, brw_imm_f(key->y_scale));
  1421.      /* Adjust coordinates so that integers represent pixel centers rather
  1422.       * than pixel edges.
  1423.       */
  1424.       brw_ADD(&func, X_f, X_f, brw_imm_f(-0.5));
  1425.       brw_ADD(&func, Y_f, Y_f, brw_imm_f(-0.5));
  1426.  
  1427.       /* Clamp the X, Y texture coordinates to properly handle the sampling of
  1428.        *  texels on texture edges.
  1429.        */
  1430.       brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_L,
  1431.               X_f, brw_imm_f(0.0));
  1432.       brw_MOV(&func, X_f, brw_imm_f(0.0));
  1433.       brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1434.  
  1435.       brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_GE,
  1436.               X_f, sample_grid_x1);
  1437.       brw_MOV(&func, X_f, sample_grid_x1);
  1438.       brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1439.  
  1440.       brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_L,
  1441.               Y_f, brw_imm_f(0.0));
  1442.       brw_MOV(&func, Y_f, brw_imm_f(0.0));
  1443.       brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1444.  
  1445.       brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_GE,
  1446.               Y_f, sample_grid_y1);
  1447.       brw_MOV(&func, Y_f, sample_grid_y1);
  1448.       brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1449.  
  1450.       /* Store the fractional parts to be used as bilinear interpolation
  1451.        *  coefficients.
  1452.       */
  1453.       brw_FRC(&func, x_frac, X_f);
  1454.       brw_FRC(&func, y_frac, Y_f);
  1455.  
  1456.       /* Round the float coordinates down to nearest integer */
  1457.       brw_RNDD(&func, Xp_f, X_f);
  1458.       brw_RNDD(&func, Yp_f, Y_f);
  1459.       brw_MUL(&func, X_f, Xp_f, brw_imm_f(1 / key->x_scale));
  1460.       brw_MUL(&func, Y_f, Yp_f, brw_imm_f(1 / key->y_scale));
  1461.    } else {
  1462.       /* Round the float coordinates down to nearest integer by moving to
  1463.        * UD registers.
  1464.        */
  1465.       brw_MOV(&func, Xp, X_f);
  1466.       brw_MOV(&func, Yp, Y_f);
  1467.    }
  1468.    SWAP_XY_AND_XPYP();
  1469.    brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
  1470. }
  1471.  
  1472. /**
  1473.  * Emit code to transform the X and Y coordinates as needed for blending
  1474.  * together the different samples in an MSAA texture.
  1475.  */
  1476. void
  1477. brw_blorp_blit_program::single_to_blend()
  1478. {
  1479.    /* When looking up samples in an MSAA texture using the SAMPLE message,
  1480.     * Gen6 requires the texture coordinates to be odd integers (so that they
  1481.     * correspond to the center of a 2x2 block representing the four samples
  1482.     * that maxe up a pixel).  So we need to multiply our X and Y coordinates
  1483.     * each by 2 and then add 1.
  1484.     */
  1485.    brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
  1486.    brw_SHL(&func, t1, X, brw_imm_w(1));
  1487.    brw_SHL(&func, t2, Y, brw_imm_w(1));
  1488.    brw_ADD(&func, Xp, t1, brw_imm_w(1));
  1489.    brw_ADD(&func, Yp, t2, brw_imm_w(1));
  1490.    brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
  1491.    SWAP_XY_AND_XPYP();
  1492. }
  1493.  
  1494.  
  1495. /**
  1496.  * Count the number of trailing 1 bits in the given value.  For example:
  1497.  *
  1498.  * count_trailing_one_bits(0) == 0
  1499.  * count_trailing_one_bits(7) == 3
  1500.  * count_trailing_one_bits(11) == 2
  1501.  */
  1502. inline int count_trailing_one_bits(unsigned value)
  1503. {
  1504. #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
  1505.    return __builtin_ctz(~value);
  1506. #else
  1507.    return _mesa_bitcount(value & ~(value + 1));
  1508. #endif
  1509. }
  1510.  
  1511.  
  1512. void
  1513. brw_blorp_blit_program::manual_blend_average(unsigned num_samples)
  1514. {
  1515.    if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
  1516.       mcs_fetch();
  1517.  
  1518.    /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
  1519.     *
  1520.     *   result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
  1521.     *
  1522.     * This ensures that when all samples have the same value, no numerical
  1523.     * precision is lost, since each addition operation always adds two equal
  1524.     * values, and summing two equal floating point values does not lose
  1525.     * precision.
  1526.     *
  1527.     * We perform this computation by treating the texture_data array as a
  1528.     * stack and performing the following operations:
  1529.     *
  1530.     * - push sample 0 onto stack
  1531.     * - push sample 1 onto stack
  1532.     * - add top two stack entries
  1533.     * - push sample 2 onto stack
  1534.     * - push sample 3 onto stack
  1535.     * - add top two stack entries
  1536.     * - add top two stack entries
  1537.     * - divide top stack entry by 4
  1538.     *
  1539.     * Note that after pushing sample i onto the stack, the number of add
  1540.     * operations we do is equal to the number of trailing 1 bits in i.  This
  1541.     * works provided the total number of samples is a power of two, which it
  1542.     * always is for i965.
  1543.     *
  1544.     * For integer formats, we replace the add operations with average
  1545.     * operations and skip the final division.
  1546.     */
  1547.    typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *,
  1548.                                                   struct brw_reg,
  1549.                                                   struct brw_reg,
  1550.                                                   struct brw_reg);
  1551.    brw_op2_ptr combine_op =
  1552.       key->texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG;
  1553.    unsigned stack_depth = 0;
  1554.    for (unsigned i = 0; i < num_samples; ++i) {
  1555.       assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */
  1556.  
  1557.       /* Push sample i onto the stack */
  1558.       assert(stack_depth < ARRAY_SIZE(texture_data));
  1559.       if (i == 0) {
  1560.          s_is_zero = true;
  1561.       } else {
  1562.          s_is_zero = false;
  1563.          brw_MOV(&func, vec16(S), brw_imm_ud(i));
  1564.       }
  1565.       texel_fetch(texture_data[stack_depth++]);
  1566.  
  1567.       if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) {
  1568.          /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
  1569.           * suggests an optimization:
  1570.           *
  1571.           *     "A simple optimization with probable large return in
  1572.           *     performance is to compare the MCS value to zero (indicating
  1573.           *     all samples are on sample slice 0), and sample only from
  1574.           *     sample slice 0 using ld2dss if MCS is zero."
  1575.           *
  1576.           * Note that in the case where the MCS value is zero, sampling from
  1577.           * sample slice 0 using ld2dss and sampling from sample 0 using
  1578.           * ld2dms are equivalent (since all samples are on sample slice 0).
  1579.           * Since we have already sampled from sample 0, all we need to do is
  1580.           * skip the remaining fetches and averaging if MCS is zero.
  1581.           */
  1582.          brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ,
  1583.                  mcs_data, brw_imm_ud(0));
  1584.          brw_IF(&func, BRW_EXECUTE_16);
  1585.       }
  1586.  
  1587.       /* Do count_trailing_one_bits(i) times */
  1588.       for (int j = count_trailing_one_bits(i); j-- > 0; ) {
  1589.          assert(stack_depth >= 2);
  1590.          --stack_depth;
  1591.  
  1592.          /* TODO: should use a smaller loop bound for non_RGBA formats */
  1593.          for (int k = 0; k < 4; ++k) {
  1594.             combine_op(&func, offset(texture_data[stack_depth - 1], 2*k),
  1595.                        offset(vec8(texture_data[stack_depth - 1]), 2*k),
  1596.                        offset(vec8(texture_data[stack_depth]), 2*k));
  1597.          }
  1598.       }
  1599.    }
  1600.  
  1601.    /* We should have just 1 sample on the stack now. */
  1602.    assert(stack_depth == 1);
  1603.  
  1604.    if (key->texture_data_type == BRW_REGISTER_TYPE_F) {
  1605.       /* Scale the result down by a factor of num_samples */
  1606.       /* TODO: should use a smaller loop bound for non-RGBA formats */
  1607.       for (int j = 0; j < 4; ++j) {
  1608.          brw_MUL(&func, offset(texture_data[0], 2*j),
  1609.                  offset(vec8(texture_data[0]), 2*j),
  1610.                  brw_imm_f(1.0/num_samples));
  1611.       }
  1612.    }
  1613.  
  1614.    if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
  1615.       brw_ENDIF(&func);
  1616. }
  1617.  
  1618. void
  1619. brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples)
  1620. {
  1621.    /* We do this computation by performing the following operations:
  1622.     *
  1623.     * In case of 4x, 8x MSAA:
  1624.     * - Compute the pixel coordinates and sample numbers (a, b, c, d)
  1625.     *   which are later used for interpolation
  1626.     * - linearly interpolate samples a and b in X
  1627.     * - linearly interpolate samples c and d in X
  1628.     * - linearly interpolate the results of last two operations in Y
  1629.     *
  1630.     *   result = lrp(lrp(a + b) + lrp(c + d))
  1631.     */
  1632.    struct brw_reg Xp_f = retype(Xp, BRW_REGISTER_TYPE_F);
  1633.    struct brw_reg Yp_f = retype(Yp, BRW_REGISTER_TYPE_F);
  1634.    struct brw_reg t1_f = retype(t1, BRW_REGISTER_TYPE_F);
  1635.    struct brw_reg t2_f = retype(t2, BRW_REGISTER_TYPE_F);
  1636.  
  1637.    for (unsigned i = 0; i < 4; ++i) {
  1638.       assert(i < ARRAY_SIZE(texture_data));
  1639.       s_is_zero = false;
  1640.  
  1641.       /* Compute pixel coordinates */
  1642.       brw_ADD(&func, vec16(x_sample_coords), Xp_f,
  1643.               brw_imm_f((float)(i & 0x1) * (1.0 / key->x_scale)));
  1644.       brw_ADD(&func, vec16(y_sample_coords), Yp_f,
  1645.               brw_imm_f((float)((i >> 1) & 0x1) * (1.0 / key->y_scale)));
  1646.       brw_MOV(&func, vec16(X), x_sample_coords);
  1647.       brw_MOV(&func, vec16(Y), y_sample_coords);
  1648.  
  1649.       /* The MCS value we fetch has to match up with the pixel that we're
  1650.        * sampling from. Since we sample from different pixels in each
  1651.        * iteration of this "for" loop, the call to mcs_fetch() should be
  1652.        * here inside the loop after computing the pixel coordinates.
  1653.        */
  1654.       if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
  1655.          mcs_fetch();
  1656.  
  1657.      /* Compute sample index and map the sample index to a sample number.
  1658.       * Sample index layout shows the numbering of slots in a rectangular
  1659.       * grid of samples with in a pixel. Sample number layout shows the
  1660.       * rectangular grid of samples roughly corresponding to the real sample
  1661.       * locations with in a pixel.
  1662.       * In case of 4x MSAA, layout of sample indices matches the layout of
  1663.       * sample numbers:
  1664.       *           ---------
  1665.       *           | 0 | 1 |
  1666.       *           ---------
  1667.       *           | 2 | 3 |
  1668.       *           ---------
  1669.       *
  1670.       * In case of 8x MSAA the two layouts don't match.
  1671.       * sample index layout :  ---------    sample number layout :  ---------
  1672.       *                        | 0 | 1 |                            | 5 | 2 |
  1673.       *                        ---------                            ---------
  1674.       *                        | 2 | 3 |                            | 4 | 6 |
  1675.       *                        ---------                            ---------
  1676.       *                        | 4 | 5 |                            | 0 | 3 |
  1677.       *                        ---------                            ---------
  1678.       *                        | 6 | 7 |                            | 7 | 1 |
  1679.       *                        ---------                            ---------
  1680.       */
  1681.       brw_FRC(&func, vec16(t1_f), x_sample_coords);
  1682.       brw_FRC(&func, vec16(t2_f), y_sample_coords);
  1683.       brw_MUL(&func, vec16(t1_f), t1_f, brw_imm_f(key->x_scale));
  1684.       brw_MUL(&func, vec16(t2_f), t2_f, brw_imm_f(key->x_scale * key->y_scale));
  1685.       brw_ADD(&func, vec16(t1_f), t1_f, t2_f);
  1686.       brw_MOV(&func, vec16(S), t1_f);
  1687.  
  1688.       if (num_samples == 8) {
  1689.          /* Map the sample index to a sample number */
  1690.          brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_L,
  1691.                  S, brw_imm_d(4));
  1692.          brw_IF(&func, BRW_EXECUTE_16);
  1693.          {
  1694.             brw_MOV(&func, vec16(t2), brw_imm_d(5));
  1695.             brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ,
  1696.                     S, brw_imm_d(1));
  1697.             brw_MOV(&func, vec16(t2), brw_imm_d(2));
  1698.             brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1699.             brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ,
  1700.                     S, brw_imm_d(2));
  1701.             brw_MOV(&func, vec16(t2), brw_imm_d(4));
  1702.             brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1703.             brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ,
  1704.                     S, brw_imm_d(3));
  1705.             brw_MOV(&func, vec16(t2), brw_imm_d(6));
  1706.             brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1707.          }
  1708.          brw_ELSE(&func);
  1709.          {
  1710.             brw_MOV(&func, vec16(t2), brw_imm_d(0));
  1711.             brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ,
  1712.                     S, brw_imm_d(5));
  1713.             brw_MOV(&func, vec16(t2), brw_imm_d(3));
  1714.             brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1715.             brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ,
  1716.                     S, brw_imm_d(6));
  1717.             brw_MOV(&func, vec16(t2), brw_imm_d(7));
  1718.             brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1719.             brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ,
  1720.                     S, brw_imm_d(7));
  1721.             brw_MOV(&func, vec16(t2), brw_imm_d(1));
  1722.             brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  1723.          }
  1724.          brw_ENDIF(&func);
  1725.          brw_MOV(&func, vec16(S), t2);
  1726.       }
  1727.       texel_fetch(texture_data[i]);
  1728.    }
  1729.  
  1730. #define SAMPLE(x, y) offset(texture_data[x], y)
  1731.    brw_set_access_mode(&func, BRW_ALIGN_16);
  1732.    for (int index = 3; index > 0; ) {
  1733.       /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
  1734.        * Counter value of 8 in 'for' loop below is used to interpolate all
  1735.        * the color components.
  1736.        */
  1737.       for (int k = 0; k < 8; ++k)
  1738.          brw_LRP(&func,
  1739.                  vec8(SAMPLE(index - 1, k)),
  1740.                  offset(x_frac, k & 1),
  1741.                  SAMPLE(index, k),
  1742.                  SAMPLE(index - 1, k));
  1743.       index -= 2;
  1744.    }
  1745.    for (int k = 0; k < 8; ++k)
  1746.       brw_LRP(&func,
  1747.               vec8(SAMPLE(0, k)),
  1748.               offset(y_frac, k & 1),
  1749.               vec8(SAMPLE(2, k)),
  1750.               vec8(SAMPLE(0, k)));
  1751.    brw_set_access_mode(&func, BRW_ALIGN_1);
  1752. #undef SAMPLE
  1753. }
  1754.  
  1755. /**
  1756.  * Emit code to look up a value in the texture using the SAMPLE message (which
  1757.  * does blending of MSAA surfaces).
  1758.  */
  1759. void
  1760. brw_blorp_blit_program::sample(struct brw_reg dst)
  1761. {
  1762.    static const sampler_message_arg args[2] = {
  1763.       SAMPLER_MESSAGE_ARG_U_FLOAT,
  1764.       SAMPLER_MESSAGE_ARG_V_FLOAT
  1765.    };
  1766.  
  1767.    texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE, args,
  1768.                   ARRAY_SIZE(args));
  1769. }
  1770.  
  1771. /**
  1772.  * Emit code to look up a value in the texture using the SAMPLE_LD message
  1773.  * (which does a simple texel fetch).
  1774.  */
  1775. void
  1776. brw_blorp_blit_program::texel_fetch(struct brw_reg dst)
  1777. {
  1778.    static const sampler_message_arg gen6_args[5] = {
  1779.       SAMPLER_MESSAGE_ARG_U_INT,
  1780.       SAMPLER_MESSAGE_ARG_V_INT,
  1781.       SAMPLER_MESSAGE_ARG_ZERO_INT, /* R */
  1782.       SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
  1783.       SAMPLER_MESSAGE_ARG_SI_INT
  1784.    };
  1785.    static const sampler_message_arg gen7_ld_args[3] = {
  1786.       SAMPLER_MESSAGE_ARG_U_INT,
  1787.       SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
  1788.       SAMPLER_MESSAGE_ARG_V_INT
  1789.    };
  1790.    static const sampler_message_arg gen7_ld2dss_args[3] = {
  1791.       SAMPLER_MESSAGE_ARG_SI_INT,
  1792.       SAMPLER_MESSAGE_ARG_U_INT,
  1793.       SAMPLER_MESSAGE_ARG_V_INT
  1794.    };
  1795.    static const sampler_message_arg gen7_ld2dms_args[4] = {
  1796.       SAMPLER_MESSAGE_ARG_SI_INT,
  1797.       SAMPLER_MESSAGE_ARG_MCS_INT,
  1798.       SAMPLER_MESSAGE_ARG_U_INT,
  1799.       SAMPLER_MESSAGE_ARG_V_INT
  1800.    };
  1801.  
  1802.    switch (brw->gen) {
  1803.    case 6:
  1804.       texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen6_args,
  1805.                      s_is_zero ? 2 : 5);
  1806.       break;
  1807.    case 7:
  1808.       switch (key->tex_layout) {
  1809.       case INTEL_MSAA_LAYOUT_IMS:
  1810.          /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
  1811.           * Format):
  1812.           *
  1813.           *     If this field is MSFMT_DEPTH_STENCIL
  1814.           *     [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
  1815.           *     messages allowed are "ld2dms", "resinfo", and "sampleinfo".
  1816.           *
  1817.           * So fall through to emit the same message as we use for
  1818.           * INTEL_MSAA_LAYOUT_CMS.
  1819.           */
  1820.       case INTEL_MSAA_LAYOUT_CMS:
  1821.          texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS,
  1822.                         gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args));
  1823.          break;
  1824.       case INTEL_MSAA_LAYOUT_UMS:
  1825.          texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS,
  1826.                         gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args));
  1827.          break;
  1828.       case INTEL_MSAA_LAYOUT_NONE:
  1829.          assert(s_is_zero);
  1830.          texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen7_ld_args,
  1831.                         ARRAY_SIZE(gen7_ld_args));
  1832.          break;
  1833.       }
  1834.       break;
  1835.    default:
  1836.       assert(!"Should not get here.");
  1837.       break;
  1838.    };
  1839. }
  1840.  
  1841. void
  1842. brw_blorp_blit_program::mcs_fetch()
  1843. {
  1844.    static const sampler_message_arg gen7_ld_mcs_args[2] = {
  1845.       SAMPLER_MESSAGE_ARG_U_INT,
  1846.       SAMPLER_MESSAGE_ARG_V_INT
  1847.    };
  1848.    texture_lookup(vec16(mcs_data), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS,
  1849.                   gen7_ld_mcs_args, ARRAY_SIZE(gen7_ld_mcs_args));
  1850. }
  1851.  
  1852. void
  1853. brw_blorp_blit_program::texture_lookup(struct brw_reg dst,
  1854.                                        GLuint msg_type,
  1855.                                        const sampler_message_arg *args,
  1856.                                        int num_args)
  1857. {
  1858.    struct brw_reg mrf =
  1859.       retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_UD);
  1860.    for (int arg = 0; arg < num_args; ++arg) {
  1861.       switch (args[arg]) {
  1862.       case SAMPLER_MESSAGE_ARG_U_FLOAT:
  1863.          brw_MOV(&func, retype(mrf, BRW_REGISTER_TYPE_F), X);
  1864.          break;
  1865.       case SAMPLER_MESSAGE_ARG_V_FLOAT:
  1866.          brw_MOV(&func, retype(mrf, BRW_REGISTER_TYPE_F), Y);
  1867.          break;
  1868.       case SAMPLER_MESSAGE_ARG_U_INT:
  1869.          brw_MOV(&func, mrf, X);
  1870.          break;
  1871.       case SAMPLER_MESSAGE_ARG_V_INT:
  1872.          brw_MOV(&func, mrf, Y);
  1873.          break;
  1874.       case SAMPLER_MESSAGE_ARG_SI_INT:
  1875.          /* Note: on Gen7, this code may be reached with s_is_zero==true
  1876.           * because in Gen7's ld2dss message, the sample index is the first
  1877.           * argument.  When this happens, we need to move a 0 into the
  1878.           * appropriate message register.
  1879.           */
  1880.          if (s_is_zero)
  1881.             brw_MOV(&func, mrf, brw_imm_ud(0));
  1882.          else
  1883.             brw_MOV(&func, mrf, S);
  1884.          break;
  1885.       case SAMPLER_MESSAGE_ARG_MCS_INT:
  1886.          switch (key->tex_layout) {
  1887.          case INTEL_MSAA_LAYOUT_CMS:
  1888.             brw_MOV(&func, mrf, mcs_data);
  1889.             break;
  1890.          case INTEL_MSAA_LAYOUT_IMS:
  1891.             /* When sampling from an IMS surface, MCS data is not relevant,
  1892.              * and the hardware ignores it.  So don't bother populating it.
  1893.              */
  1894.             break;
  1895.          default:
  1896.             /* We shouldn't be trying to send MCS data with any other
  1897.              * layouts.
  1898.              */
  1899.             assert (!"Unsupported layout for MCS data");
  1900.             break;
  1901.          }
  1902.          break;
  1903.       case SAMPLER_MESSAGE_ARG_ZERO_INT:
  1904.          brw_MOV(&func, mrf, brw_imm_ud(0));
  1905.          break;
  1906.       }
  1907.       mrf.nr += 2;
  1908.    }
  1909.  
  1910.    brw_SAMPLE(&func,
  1911.               retype(dst, BRW_REGISTER_TYPE_F) /* dest */,
  1912.               base_mrf /* msg_reg_nr */,
  1913.               brw_message_reg(base_mrf) /* src0 */,
  1914.               BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  1915.               0 /* sampler */,
  1916.               msg_type,
  1917.               8 /* response_length.  TODO: should be smaller for non-RGBA formats? */,
  1918.               mrf.nr - base_mrf /* msg_length */,
  1919.               0 /* header_present */,
  1920.               BRW_SAMPLER_SIMD_MODE_SIMD16,
  1921.               BRW_SAMPLER_RETURN_FORMAT_FLOAT32);
  1922. }
  1923.  
  1924. #undef X
  1925. #undef Y
  1926. #undef U
  1927. #undef V
  1928. #undef S
  1929. #undef SWAP_XY_AND_XPYP
  1930.  
  1931. void
  1932. brw_blorp_blit_program::render_target_write()
  1933. {
  1934.    struct brw_reg mrf_rt_write =
  1935.       retype(vec16(brw_message_reg(base_mrf)), key->texture_data_type);
  1936.    int mrf_offset = 0;
  1937.  
  1938.    /* If we may have killed pixels, then we need to send R0 and R1 in a header
  1939.     * so that the render target knows which pixels we killed.
  1940.     */
  1941.    bool use_header = key->use_kill;
  1942.    if (use_header) {
  1943.       /* Copy R0/1 to MRF */
  1944.       brw_MOV(&func, retype(mrf_rt_write, BRW_REGISTER_TYPE_UD),
  1945.               retype(R0, BRW_REGISTER_TYPE_UD));
  1946.       mrf_offset += 2;
  1947.    }
  1948.  
  1949.    /* Copy texture data to MRFs */
  1950.    for (int i = 0; i < 4; ++i) {
  1951.       /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
  1952.       brw_MOV(&func, offset(mrf_rt_write, mrf_offset),
  1953.               offset(vec8(texture_data[0]), 2*i));
  1954.       mrf_offset += 2;
  1955.    }
  1956.  
  1957.    /* Now write to the render target and terminate the thread */
  1958.    brw_fb_WRITE(&func,
  1959.                 16 /* dispatch_width */,
  1960.                 base_mrf /* msg_reg_nr */,
  1961.                 mrf_rt_write /* src0 */,
  1962.                 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
  1963.                 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  1964.                 mrf_offset /* msg_length.  TODO: Should be smaller for non-RGBA formats. */,
  1965.                 0 /* response_length */,
  1966.                 true /* eot */,
  1967.                 use_header);
  1968. }
  1969.  
  1970.  
  1971. void
  1972. brw_blorp_coord_transform_params::setup(GLfloat src0, GLfloat src1,
  1973.                                         GLfloat dst0, GLfloat dst1,
  1974.                                         bool mirror)
  1975. {
  1976.    float scale = (src1 - src0) / (dst1 - dst0);
  1977.    if (!mirror) {
  1978.       /* When not mirroring a coordinate (say, X), we need:
  1979.        *   src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
  1980.        * Therefore:
  1981.        *   src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
  1982.        *
  1983.        * blorp program uses "round toward zero" to convert the
  1984.        * transformed floating point coordinates to integer coordinates,
  1985.        * whereas the behaviour we actually want is "round to nearest",
  1986.        * so 0.5 provides the necessary correction.
  1987.        */
  1988.       multiplier = scale;
  1989.       offset = src0 + (-dst0 + 0.5) * scale;
  1990.    } else {
  1991.       /* When mirroring X we need:
  1992.        *   src_x - src_x0 = dst_x1 - dst_x - 0.5
  1993.        * Therefore:
  1994.        *   src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
  1995.        */
  1996.       multiplier = -scale;
  1997.       offset = src0 + (dst1 - 0.5) * scale;
  1998.    }
  1999. }
  2000.  
  2001.  
  2002. /**
  2003.  * Determine which MSAA layout the GPU pipeline should be configured for,
  2004.  * based on the chip generation, the number of samples, and the true layout of
  2005.  * the image in memory.
  2006.  */
  2007. inline intel_msaa_layout
  2008. compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples,
  2009.                                  intel_msaa_layout true_layout)
  2010. {
  2011.    if (num_samples <= 1) {
  2012.       /* When configuring the GPU for non-MSAA, we can still accommodate IMS
  2013.        * format buffers, by transforming coordinates appropriately.
  2014.        */
  2015.       assert(true_layout == INTEL_MSAA_LAYOUT_NONE ||
  2016.              true_layout == INTEL_MSAA_LAYOUT_IMS);
  2017.       return INTEL_MSAA_LAYOUT_NONE;
  2018.    } else {
  2019.       assert(true_layout != INTEL_MSAA_LAYOUT_NONE);
  2020.    }
  2021.  
  2022.    /* Prior to Gen7, all MSAA surfaces use IMS layout. */
  2023.    if (brw->gen == 6) {
  2024.       assert(true_layout == INTEL_MSAA_LAYOUT_IMS);
  2025.    }
  2026.  
  2027.    return true_layout;
  2028. }
  2029.  
  2030.  
  2031. brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
  2032.                                              struct intel_mipmap_tree *src_mt,
  2033.                                              unsigned src_level, unsigned src_layer,
  2034.                                              struct intel_mipmap_tree *dst_mt,
  2035.                                              unsigned dst_level, unsigned dst_layer,
  2036.                                              GLfloat src_x0, GLfloat src_y0,
  2037.                                              GLfloat src_x1, GLfloat src_y1,
  2038.                                              GLfloat dst_x0, GLfloat dst_y0,
  2039.                                              GLfloat dst_x1, GLfloat dst_y1,
  2040.                                              bool mirror_x, bool mirror_y)
  2041. {
  2042.    struct gl_context *ctx = &brw->ctx;
  2043.    const struct gl_framebuffer *read_fb = ctx->ReadBuffer;
  2044.  
  2045.    src.set(brw, src_mt, src_level, src_layer);
  2046.    dst.set(brw, dst_mt, dst_level, dst_layer);
  2047.  
  2048.    src.brw_surfaceformat = dst.brw_surfaceformat;
  2049.  
  2050.    use_wm_prog = true;
  2051.    memset(&wm_prog_key, 0, sizeof(wm_prog_key));
  2052.  
  2053.    /* texture_data_type indicates the register type that should be used to
  2054.     * manipulate texture data.
  2055.     */
  2056.    switch (_mesa_get_format_datatype(src_mt->format)) {
  2057.    case GL_UNSIGNED_NORMALIZED:
  2058.    case GL_SIGNED_NORMALIZED:
  2059.    case GL_FLOAT:
  2060.       wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
  2061.       break;
  2062.    case GL_UNSIGNED_INT:
  2063.       if (src_mt->format == MESA_FORMAT_S8) {
  2064.          /* We process stencil as though it's an unsigned normalized color */
  2065.          wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
  2066.       } else {
  2067.          wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD;
  2068.       }
  2069.       break;
  2070.    case GL_INT:
  2071.       wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_D;
  2072.       break;
  2073.    default:
  2074.       assert(!"Unrecognized blorp format");
  2075.       break;
  2076.    }
  2077.  
  2078.    if (brw->gen > 6) {
  2079.       /* Gen7's rendering hardware only supports the IMS layout for depth and
  2080.        * stencil render targets.  Blorp always maps its destination surface as
  2081.        * a color render target (even if it's actually a depth or stencil
  2082.        * buffer).  So if the destination is IMS, we'll have to map it as a
  2083.        * single-sampled texture and interleave the samples ourselves.
  2084.        */
  2085.       if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS)
  2086.          dst.num_samples = 0;
  2087.    }
  2088.  
  2089.    if (dst.map_stencil_as_y_tiled && dst.num_samples > 1) {
  2090.       /* If the destination surface is a W-tiled multisampled stencil buffer
  2091.        * that we're mapping as Y tiled, then we need to arrange for the WM
  2092.        * program to run once per sample rather than once per pixel, because
  2093.        * the memory layout of related samples doesn't match between W and Y
  2094.        * tiling.
  2095.        */
  2096.       wm_prog_key.persample_msaa_dispatch = true;
  2097.    }
  2098.  
  2099.    if (src.num_samples > 0 && dst.num_samples > 1) {
  2100.       /* We are blitting from a multisample buffer to a multisample buffer, so
  2101.        * we must preserve samples within a pixel.  This means we have to
  2102.        * arrange for the WM program to run once per sample rather than once
  2103.        * per pixel.
  2104.        */
  2105.       wm_prog_key.persample_msaa_dispatch = true;
  2106.    }
  2107.  
  2108.    /* Scaled blitting or not. */
  2109.    wm_prog_key.blit_scaled =
  2110.       ((dst_x1 - dst_x0) == (src_x1 - src_x0) &&
  2111.        (dst_y1 - dst_y0) == (src_y1 - src_y0)) ? false : true;
  2112.  
  2113.    /* Scaling factors used for bilinear filtering in multisample scaled
  2114.     * blits.
  2115.     */
  2116.    wm_prog_key.x_scale = 2.0;
  2117.    wm_prog_key.y_scale = src_mt->num_samples / 2.0;
  2118.  
  2119.    /* The render path must be configured to use the same number of samples as
  2120.     * the destination buffer.
  2121.     */
  2122.    num_samples = dst.num_samples;
  2123.  
  2124.    GLenum base_format = _mesa_get_format_base_format(src_mt->format);
  2125.    if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? */
  2126.        base_format != GL_STENCIL_INDEX &&
  2127.        src_mt->num_samples > 1 && dst_mt->num_samples <= 1) {
  2128.       /* We are downsampling a color buffer, so blend. */
  2129.       wm_prog_key.blend = true;
  2130.    }
  2131.  
  2132.    /* src_samples and dst_samples are the true sample counts */
  2133.    wm_prog_key.src_samples = src_mt->num_samples;
  2134.    wm_prog_key.dst_samples = dst_mt->num_samples;
  2135.  
  2136.    /* tex_samples and rt_samples are the sample counts that are set up in
  2137.     * SURFACE_STATE.
  2138.     */
  2139.    wm_prog_key.tex_samples = src.num_samples;
  2140.    wm_prog_key.rt_samples  = dst.num_samples;
  2141.  
  2142.    /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
  2143.     * use to access the source and destination surfaces.
  2144.     */
  2145.    wm_prog_key.tex_layout =
  2146.       compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout);
  2147.    wm_prog_key.rt_layout =
  2148.       compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout);
  2149.  
  2150.    /* src_layout and dst_layout indicate the true MSAA layout used by src and
  2151.     * dst.
  2152.     */
  2153.    wm_prog_key.src_layout = src_mt->msaa_layout;
  2154.    wm_prog_key.dst_layout = dst_mt->msaa_layout;
  2155.  
  2156.    wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled;
  2157.    wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled;
  2158.    x0 = wm_push_consts.dst_x0 = dst_x0;
  2159.    y0 = wm_push_consts.dst_y0 = dst_y0;
  2160.    x1 = wm_push_consts.dst_x1 = dst_x1;
  2161.    y1 = wm_push_consts.dst_y1 = dst_y1;
  2162.    wm_push_consts.sample_grid_x1 = read_fb->Width * wm_prog_key.x_scale - 1.0;
  2163.    wm_push_consts.sample_grid_y1 = read_fb->Height * wm_prog_key.y_scale - 1.0;
  2164.  
  2165.    wm_push_consts.x_transform.setup(src_x0, src_x1, dst_x0, dst_x1, mirror_x);
  2166.    wm_push_consts.y_transform.setup(src_y0, src_y1, dst_y0, dst_y1, mirror_y);
  2167.  
  2168.    if (dst.num_samples <= 1 && dst_mt->num_samples > 1) {
  2169.       /* We must expand the rectangle we send through the rendering pipeline,
  2170.        * to account for the fact that we are mapping the destination region as
  2171.        * single-sampled when it is in fact multisampled.  We must also align
  2172.        * it to a multiple of the multisampling pattern, because the
  2173.        * differences between multisampled and single-sampled surface formats
  2174.        * will mean that pixels are scrambled within the multisampling pattern.
  2175.        * TODO: what if this makes the coordinates too large?
  2176.        *
  2177.        * Note: this only works if the destination surface uses the IMS layout.
  2178.        * If it's UMS, then we have no choice but to set up the rendering
  2179.        * pipeline as multisampled.
  2180.        */
  2181.       assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
  2182.       switch (dst_mt->num_samples) {
  2183.       case 4:
  2184.          x0 = ROUND_DOWN_TO(x0 * 2, 4);
  2185.          y0 = ROUND_DOWN_TO(y0 * 2, 4);
  2186.          x1 = ALIGN(x1 * 2, 4);
  2187.          y1 = ALIGN(y1 * 2, 4);
  2188.          break;
  2189.       case 8:
  2190.          x0 = ROUND_DOWN_TO(x0 * 4, 8);
  2191.          y0 = ROUND_DOWN_TO(y0 * 2, 4);
  2192.          x1 = ALIGN(x1 * 4, 8);
  2193.          y1 = ALIGN(y1 * 2, 4);
  2194.          break;
  2195.       default:
  2196.          assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
  2197.          break;
  2198.       }
  2199.       wm_prog_key.use_kill = true;
  2200.    }
  2201.  
  2202.    if (dst.map_stencil_as_y_tiled) {
  2203.       /* We must modify the rectangle we send through the rendering pipeline
  2204.        * (and the size and x/y offset of the destination surface), to account
  2205.        * for the fact that we are mapping it as Y-tiled when it is in fact
  2206.        * W-tiled.
  2207.        *
  2208.        * Both Y tiling and W tiling can be understood as organizations of
  2209.        * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
  2210.        * is different, but the layout of the 32-byte sub-tiles within the 4k
  2211.        * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
  2212.        * column-major order).  In Y tiling, the sub-tiles are 16 bytes wide
  2213.        * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
  2214.        *
  2215.        * Therefore, to account for the layout differences within the 32-byte
  2216.        * sub-tiles, we must expand the rectangle so the X coordinates of its
  2217.        * edges are multiples of 8 (the W sub-tile width), and its Y
  2218.        * coordinates of its edges are multiples of 4 (the W sub-tile height).
  2219.        * Then we need to scale the X and Y coordinates of the rectangle to
  2220.        * account for the differences in aspect ratio between the Y and W
  2221.        * sub-tiles.  We need to modify the layer width and height similarly.
  2222.        *
  2223.        * A correction needs to be applied when MSAA is in use: since
  2224.        * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
  2225.        * we need to align the Y coordinates to multiples of 8, so that when
  2226.        * they are divided by two they are still multiples of 4.
  2227.        *
  2228.        * Note: Since the x/y offset of the surface will be applied using the
  2229.        * SURFACE_STATE command packet, it will be invisible to the swizzling
  2230.        * code in the shader; therefore it needs to be in a multiple of the
  2231.        * 32-byte sub-tile size.  Fortunately it is, since the sub-tile is 8
  2232.        * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
  2233.        * buffer), and the miplevel alignment used for stencil buffers is 8
  2234.        * pixels horizontally and either 4 or 8 pixels vertically (see
  2235.        * intel_horizontal_texture_alignment_unit() and
  2236.        * intel_vertical_texture_alignment_unit()).
  2237.        *
  2238.        * Note: Also, since the SURFACE_STATE command packet can only apply
  2239.        * offsets that are multiples of 4 pixels horizontally and 2 pixels
  2240.        * vertically, it is important that the offsets will be multiples of
  2241.        * these sizes after they are converted into Y-tiled coordinates.
  2242.        * Fortunately they will be, since we know from above that the offsets
  2243.        * are a multiple of the 32-byte sub-tile size, and in Y-tiled
  2244.        * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
  2245.        *
  2246.        * TODO: what if this makes the coordinates (or the texture size) too
  2247.        * large?
  2248.        */
  2249.       const unsigned x_align = 8, y_align = dst.num_samples != 0 ? 8 : 4;
  2250.       x0 = ROUND_DOWN_TO(x0, x_align) * 2;
  2251.       y0 = ROUND_DOWN_TO(y0, y_align) / 2;
  2252.       x1 = ALIGN(x1, x_align) * 2;
  2253.       y1 = ALIGN(y1, y_align) / 2;
  2254.       dst.width = ALIGN(dst.width, x_align) * 2;
  2255.       dst.height = ALIGN(dst.height, y_align) / 2;
  2256.       dst.x_offset *= 2;
  2257.       dst.y_offset /= 2;
  2258.       wm_prog_key.use_kill = true;
  2259.    }
  2260.  
  2261.    if (src.map_stencil_as_y_tiled) {
  2262.       /* We must modify the size and x/y offset of the source surface to
  2263.        * account for the fact that we are mapping it as Y-tiled when it is in
  2264.        * fact W tiled.
  2265.        *
  2266.        * See the comments above concerning x/y offset alignment for the
  2267.        * destination surface.
  2268.        *
  2269.        * TODO: what if this makes the texture size too large?
  2270.        */
  2271.       const unsigned x_align = 8, y_align = src.num_samples != 0 ? 8 : 4;
  2272.       src.width = ALIGN(src.width, x_align) * 2;
  2273.       src.height = ALIGN(src.height, y_align) / 2;
  2274.       src.x_offset *= 2;
  2275.       src.y_offset /= 2;
  2276.    }
  2277. }
  2278.  
  2279. uint32_t
  2280. brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
  2281.                                    brw_blorp_prog_data **prog_data) const
  2282. {
  2283.    uint32_t prog_offset = 0;
  2284.    if (!brw_search_cache(&brw->cache, BRW_BLORP_BLIT_PROG,
  2285.                          &this->wm_prog_key, sizeof(this->wm_prog_key),
  2286.                          &prog_offset, prog_data)) {
  2287.       brw_blorp_blit_program prog(brw, &this->wm_prog_key);
  2288.       GLuint program_size;
  2289.       const GLuint *program = prog.compile(brw, &program_size);
  2290.       brw_upload_cache(&brw->cache, BRW_BLORP_BLIT_PROG,
  2291.                        &this->wm_prog_key, sizeof(this->wm_prog_key),
  2292.                        program, program_size,
  2293.                        &prog.prog_data, sizeof(prog.prog_data),
  2294.                        &prog_offset, prog_data);
  2295.    }
  2296.    return prog_offset;
  2297. }
  2298.