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  1. #ifndef NVE4_COMPUTE_XML
  2. #define NVE4_COMPUTE_XML
  3.  
  4. /* Autogenerated file, DO NOT EDIT manually!
  5.  
  6. This file was generated by the rules-ng-ng headergen tool in this git repository:
  7. http://0x04.net/cgit/index.cgi/rules-ng-ng
  8. git clone git://0x04.net/rules-ng-ng
  9.  
  10. The rules-ng-ng source files this header was generated from are:
  11. - nve4_compute.xml (  10168 bytes, from 2013-03-31 20:05:20)
  12. - copyright.xml    (   6452 bytes, from 2011-08-11 18:25:12)
  13. - nvchipsets.xml   (   3954 bytes, from 2013-03-26 01:26:43)
  14. - nv_object.xml    (  14395 bytes, from 2013-03-31 20:05:20)
  15. - nv_defs.xml      (   4437 bytes, from 2011-08-11 18:25:12)
  16. - nv50_defs.xml    (   9613 bytes, from 2013-03-28 11:02:04)
  17. - nve4_p2mf.xml    (   2373 bytes, from 2013-03-31 20:05:20)
  18.  
  19. Copyright (C) 2006-2013 by the following authors:
  20. - Artur Huillet <arthur.huillet@free.fr> (ahuillet)
  21. - Ben Skeggs (darktama, darktama_)
  22. - B. R. <koala_br@users.sourceforge.net> (koala_br)
  23. - Carlos Martin <carlosmn@users.sf.net> (carlosmn)
  24. - Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
  25. - Dawid Gajownik <gajownik@users.sf.net> (gajownik)
  26. - Dmitry Baryshkov
  27. - Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
  28. - EdB <edb_@users.sf.net> (edb_)
  29. - Erik Waling <erikwailing@users.sf.net> (erikwaling)
  30. - Francisco Jerez <currojerez@riseup.net> (curro)
  31. - imirkin <imirkin@users.sf.net> (imirkin)
  32. - jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
  33. - Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
  34. - Laurent Carlier <lordheavym@gmail.com> (lordheavy)
  35. - Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
  36. - Maarten Maathuis <madman2003@gmail.com> (stillunknown)
  37. - Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
  38. - Mark Carey <mark.carey@gmail.com> (careym)
  39. - Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
  40. - nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
  41. - Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
  42. - Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
  43. - Peter Popov <ironpeter@users.sf.net> (ironpeter)
  44. - Richard Hughes <hughsient@users.sf.net> (hughsient)
  45. - Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
  46. - Serge Martin
  47. - Simon Raffeiner
  48. - Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
  49. - Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
  50. - sturmflut <sturmflut@users.sf.net> (sturmflut)
  51. - Sylvain Munaut <tnt@246tNt.com>
  52. - Victor Stinner <victor.stinner@haypocalc.com> (haypo)
  53. - Wladmir van der Laan <laanwj@gmail.com> (miathan6)
  54. - Younes Manton <younes.m@gmail.com> (ymanton)
  55.  
  56. Permission is hereby granted, free of charge, to any person obtaining
  57. a copy of this software and associated documentation files (the
  58. "Software"), to deal in the Software without restriction, including
  59. without limitation the rights to use, copy, modify, merge, publish,
  60. distribute, sublicense, and/or sell copies of the Software, and to
  61. permit persons to whom the Software is furnished to do so, subject to
  62. the following conditions:
  63.  
  64. The above copyright notice and this permission notice (including the
  65. next paragraph) shall be included in all copies or substantial
  66. portions of the Software.
  67.  
  68. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  69. EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  70. MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  71. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  72. LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  73. OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  74. WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  75. */
  76.  
  77.  
  78.  
  79.  
  80. #define NVE4_COMPUTE_UNK0144                                    0x00000144
  81.  
  82. #define NVE4_COMPUTE_UPLOAD                                     0x00000000
  83.  
  84. #define NVE4_COMPUTE_UPLOAD_LINE_LENGTH_IN                      0x00000180
  85.  
  86. #define NVE4_COMPUTE_UPLOAD_LINE_COUNT                          0x00000184
  87.  
  88. #define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_HIGH                    0x00000188
  89.  
  90. #define NVE4_COMPUTE_UPLOAD_DST_ADDRESS_LOW                     0x0000018c
  91.  
  92. #define NVE4_COMPUTE_UPLOAD_DST_PITCH                           0x00000190
  93.  
  94. #define NVE4_COMPUTE_UPLOAD_DST_TILE_MODE                       0x00000194
  95.  
  96. #define NVE4_COMPUTE_UPLOAD_DST_WIDTH                           0x00000198
  97.  
  98. #define NVE4_COMPUTE_UPLOAD_DST_HEIGHT                          0x0000019c
  99.  
  100. #define NVE4_COMPUTE_UPLOAD_DST_DEPTH                           0x000001a0
  101.  
  102. #define NVE4_COMPUTE_UPLOAD_DST_Z                               0x000001a4
  103.  
  104. #define NVE4_COMPUTE_UPLOAD_DST_X                               0x000001a8
  105.  
  106. #define NVE4_COMPUTE_UPLOAD_DST_Y                               0x000001ac
  107.  
  108. #define NVE4_COMPUTE_UPLOAD_EXEC                                0x000001b0
  109. #define NVE4_COMPUTE_UPLOAD_EXEC_LINEAR                         0x00000001
  110. #define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__MASK                     0x0000007e
  111. #define NVE4_COMPUTE_UPLOAD_EXEC_UNK1__SHIFT                    1
  112. #define NVE4_COMPUTE_UPLOAD_EXEC_BUF_NOTIFY                     0x00000300
  113. #define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__MASK                    0x0000f000
  114. #define NVE4_COMPUTE_UPLOAD_EXEC_UNK12__SHIFT                   12
  115.  
  116. #define NVE4_COMPUTE_UPLOAD_DATA                                0x000001b4
  117.  
  118. #define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_HIGH                  0x000001dc
  119.  
  120. #define NVE4_COMPUTE_UPLOAD_QUERY_ADDRESS_LOW                   0x000001e0
  121.  
  122. #define NVE4_COMPUTE_UPLOAD_QUERY_SEQUENCE                      0x000001e4
  123.  
  124. #define NVE4_COMPUTE_UPLOAD_UNK01F0                             0x000001f0
  125.  
  126. #define NVE4_COMPUTE_UPLOAD_UNK01F4                             0x000001f4
  127.  
  128. #define NVE4_COMPUTE_UPLOAD_UNK01F8                             0x000001f8
  129.  
  130. #define NVE4_COMPUTE_UPLOAD_UNK01FC                             0x000001fc
  131.  
  132. #define NVE4_COMPUTE_SHARED_BASE                                0x00000214
  133.  
  134. #define NVE4_COMPUTE_MEM_BARRIER                                0x0000021c
  135. #define NVE4_COMPUTE_MEM_BARRIER_UNK0__MASK                     0x00000007
  136. #define NVE4_COMPUTE_MEM_BARRIER_UNK0__SHIFT                    0
  137. #define NVE4_COMPUTE_MEM_BARRIER_UNK4                           0x00000010
  138. #define NVE4_COMPUTE_MEM_BARRIER_UNK12                          0x00001000
  139.  
  140. #define NVE4_COMPUTE_UNK0240                                    0x00000240
  141.  
  142. #define NVE4_COMPUTE_UNK244_TIC_FLUSH                           0x00000244
  143.  
  144. #define NVE4_COMPUTE_UNK0248                                    0x00000248
  145. #define NVE4_COMPUTE_UNK0248_UNK0__MASK                         0x0000003f
  146. #define NVE4_COMPUTE_UNK0248_UNK0__SHIFT                        0
  147. #define NVE4_COMPUTE_UNK0248_UNK8__MASK                         0x00ffff00
  148. #define NVE4_COMPUTE_UNK0248_UNK8__SHIFT                        8
  149.  
  150. #define NVE4_COMPUTE_UNK0274                                    0x00000274
  151.  
  152. #define NVE4_COMPUTE_UNK0278                                    0x00000278
  153.  
  154. #define NVE4_COMPUTE_UNK027C                                    0x0000027c
  155.  
  156. #define NVE4_COMPUTE_UNK0280                                    0x00000280
  157.  
  158. #define NVE4_COMPUTE_UNK0284                                    0x00000284
  159.  
  160. #define NVE4_COMPUTE_UNK0288                                    0x00000288
  161.  
  162. #define NVE4_COMPUTE_UNK0290                                    0x00000290
  163.  
  164. #define NVE4_COMPUTE_UNK02B0                                    0x000002b0
  165.  
  166. #define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS                        0x000002b4
  167. #define NVE4_COMPUTE_LAUNCH_DESC_ADDRESS__SHR                   8
  168.  
  169. #define NVE4_COMPUTE_UNK02B8                                    0x000002b8
  170.  
  171. #define NVE4_COMPUTE_LAUNCH                                     0x000002bc
  172.  
  173. #define NVE4_COMPUTE_MP_TEMP_SIZE(i0)                          (0x000002e4 + 0xc*(i0))
  174. #define NVE4_COMPUTE_MP_TEMP_SIZE__ESIZE                        0x0000000c
  175. #define NVE4_COMPUTE_MP_TEMP_SIZE__LEN                          0x00000002
  176.  
  177. #define NVE4_COMPUTE_MP_TEMP_SIZE_HIGH(i0)                     (0x000002e4 + 0xc*(i0))
  178.  
  179. #define NVE4_COMPUTE_MP_TEMP_SIZE_LOW(i0)                      (0x000002e8 + 0xc*(i0))
  180.  
  181. #define NVE4_COMPUTE_MP_TEMP_SIZE_MASK(i0)                     (0x000002ec + 0xc*(i0))
  182.  
  183. #define NVE4_COMPUTE_UNK0310                                    0x00000310
  184.  
  185. #define NVE4_COMPUTE_FIRMWARE(i0)                              (0x00000500 + 0x4*(i0))
  186. #define NVE4_COMPUTE_FIRMWARE__ESIZE                            0x00000004
  187. #define NVE4_COMPUTE_FIRMWARE__LEN                              0x00000020
  188.  
  189. #define NVE4_COMPUTE_LOCAL_BASE                                 0x0000077c
  190.  
  191. #define NVE4_COMPUTE_TEMP_ADDRESS_HIGH                          0x00000790
  192.  
  193. #define NVE4_COMPUTE_TEMP_ADDRESS_LOW                           0x00000794
  194.  
  195. #define NVE4_COMPUTE_UNK0D94                                    0x00000d94
  196.  
  197. #define NVE4_COMPUTE_WATCHDOG_TIMER                             0x00000de4
  198.  
  199. #define NVE4_COMPUTE_UNK0F44(i0)                               (0x00000f44 + 0x4*(i0))
  200. #define NVE4_COMPUTE_UNK0F44__ESIZE                             0x00000004
  201. #define NVE4_COMPUTE_UNK0F44__LEN                               0x00000004
  202.  
  203. #define NVE4_COMPUTE_UNK1040(i0)                               (0x00001040 + 0x4*(i0))
  204. #define NVE4_COMPUTE_UNK1040__ESIZE                             0x00000004
  205. #define NVE4_COMPUTE_UNK1040__LEN                               0x0000000c
  206.  
  207. #define NVE4_COMPUTE_UNK1288_TIC_FLUSH                          0x00001288
  208.  
  209. #define NVE4_COMPUTE_TSC_FLUSH                                  0x00001330
  210. #define NVE4_COMPUTE_TSC_FLUSH_SPECIFIC                         0x00000001
  211. #define NVE4_COMPUTE_TSC_FLUSH_ENTRY__MASK                      0x03fffff0
  212. #define NVE4_COMPUTE_TSC_FLUSH_ENTRY__SHIFT                     4
  213.  
  214. #define NVE4_COMPUTE_TIC_FLUSH                                  0x00001334
  215. #define NVE4_COMPUTE_TIC_FLUSH_SPECIFIC                         0x00000001
  216. #define NVE4_COMPUTE_TIC_FLUSH_ENTRY__MASK                      0x03fffff0
  217. #define NVE4_COMPUTE_TIC_FLUSH_ENTRY__SHIFT                     4
  218.  
  219. #define NVE4_COMPUTE_TEX_CACHE_CTL                              0x00001338
  220. #define NVE4_COMPUTE_TEX_CACHE_CTL_UNK0                         0x00000001
  221. #define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__MASK                  0x03fffff0
  222. #define NVE4_COMPUTE_TEX_CACHE_CTL_ENTRY__SHIFT                 4
  223.  
  224. #define NVE4_COMPUTE_UNK1424_TSC_FLUSH                          0x00001424
  225.  
  226. #define NVE4_COMPUTE_COND_ADDRESS_HIGH                          0x00001550
  227.  
  228. #define NVE4_COMPUTE_COND_ADDRESS_LOW                           0x00001554
  229.  
  230. #define NVE4_COMPUTE_COND_MODE                                  0x00001558
  231. #define NVE4_COMPUTE_COND_MODE_NEVER                            0x00000000
  232. #define NVE4_COMPUTE_COND_MODE_ALWAYS                           0x00000001
  233. #define NVE4_COMPUTE_COND_MODE_RES_NON_ZERO                     0x00000002
  234. #define NVE4_COMPUTE_COND_MODE_EQUAL                            0x00000003
  235. #define NVE4_COMPUTE_COND_MODE_NOT_EQUAL                        0x00000004
  236.  
  237. #define NVE4_COMPUTE_TSC_ADDRESS_HIGH                           0x0000155c
  238.  
  239. #define NVE4_COMPUTE_TSC_ADDRESS_LOW                            0x00001560
  240.  
  241. #define NVE4_COMPUTE_TSC_LIMIT                                  0x00001564
  242.  
  243. #define NVE4_COMPUTE_TIC_ADDRESS_HIGH                           0x00001574
  244.  
  245. #define NVE4_COMPUTE_TIC_ADDRESS_LOW                            0x00001578
  246.  
  247. #define NVE4_COMPUTE_TIC_LIMIT                                  0x0000157c
  248.  
  249. #define NVE4_COMPUTE_CODE_ADDRESS_HIGH                          0x00001608
  250.  
  251. #define NVE4_COMPUTE_CODE_ADDRESS_LOW                           0x0000160c
  252.  
  253. #define NVE4_COMPUTE_UNK1690                                    0x00001690
  254.  
  255. #define NVE4_COMPUTE_FLUSH                                      0x00001698
  256. #define NVE4_COMPUTE_FLUSH_CODE                                 0x00000001
  257. #define NVE4_COMPUTE_FLUSH_GLOBAL                               0x00000010
  258. #define NVE4_COMPUTE_FLUSH_CB                                   0x00001000
  259.  
  260. #define NVE4_COMPUTE_UNK1944                                    0x00001944
  261.  
  262. #define NVE4_COMPUTE_DELAY                                      0x00001a24
  263.  
  264. #define NVE4_COMPUTE_UNK1A2C(i0)                               (0x00001a2c + 0x4*(i0))
  265. #define NVE4_COMPUTE_UNK1A2C__ESIZE                             0x00000004
  266. #define NVE4_COMPUTE_UNK1A2C__LEN                               0x00000005
  267.  
  268. #define NVE4_COMPUTE_QUERY_ADDRESS_HIGH                         0x00001b00
  269.  
  270. #define NVE4_COMPUTE_QUERY_ADDRESS_LOW                          0x00001b04
  271.  
  272. #define NVE4_COMPUTE_QUERY_SEQUENCE                             0x00001b08
  273.  
  274. #define NVE4_COMPUTE_QUERY_GET                                  0x00001b0c
  275. #define NVE4_COMPUTE_QUERY_GET_MODE__MASK                       0x00000003
  276. #define NVE4_COMPUTE_QUERY_GET_MODE__SHIFT                      0
  277. #define NVE4_COMPUTE_QUERY_GET_MODE_WRITE                       0x00000000
  278. #define NVE4_COMPUTE_QUERY_GET_MODE_WRITE_INTR_NRHOST           0x00000003
  279. #define NVE4_COMPUTE_QUERY_GET_INTR                             0x00100000
  280. #define NVE4_COMPUTE_QUERY_GET_SHORT                            0x10000000
  281.  
  282. #define NVE4_COMPUTE_TEX_CB_INDEX                               0x00002608
  283.  
  284. #define NVE4_COMPUTE_UNK260C                                    0x0000260c
  285.  
  286. #define NVE4_COMPUTE_MP_PM_SET(i0)                             (0x0000335c + 0x4*(i0))
  287. #define NVE4_COMPUTE_MP_PM_SET__ESIZE                           0x00000004
  288. #define NVE4_COMPUTE_MP_PM_SET__LEN                             0x00000008
  289.  
  290. #define NVE4_COMPUTE_MP_PM_A_SIGSEL(i0)                        (0x0000337c + 0x4*(i0))
  291. #define NVE4_COMPUTE_MP_PM_A_SIGSEL__ESIZE                      0x00000004
  292. #define NVE4_COMPUTE_MP_PM_A_SIGSEL__LEN                        0x00000004
  293. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_NONE                        0x00000000
  294. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_USER                        0x00000001
  295. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LAUNCH                      0x00000003
  296. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_EXEC                        0x00000004
  297. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_ISSUE                       0x00000005
  298. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_LDST                        0x0000001b
  299. #define NVE4_COMPUTE_MP_PM_A_SIGSEL_BRANCH                      0x0000001c
  300.  
  301. #define NVE4_COMPUTE_MP_PM_B_SIGSEL(i0)                        (0x0000338c + 0x4*(i0))
  302. #define NVE4_COMPUTE_MP_PM_B_SIGSEL__ESIZE                      0x00000004
  303. #define NVE4_COMPUTE_MP_PM_B_SIGSEL__LEN                        0x00000004
  304. #define NVE4_COMPUTE_MP_PM_B_SIGSEL_NONE                        0x00000000
  305. #define NVE4_COMPUTE_MP_PM_B_SIGSEL_WARP                        0x00000002
  306. #define NVE4_COMPUTE_MP_PM_B_SIGSEL_L1                          0x00000010
  307. #define NVE4_COMPUTE_MP_PM_B_SIGSEL_MEM                         0x00000011
  308.  
  309. #define NVE4_COMPUTE_MP_PM_SRCSEL(i0)                          (0x0000339c + 0x4*(i0))
  310. #define NVE4_COMPUTE_MP_PM_SRCSEL__ESIZE                        0x00000004
  311. #define NVE4_COMPUTE_MP_PM_SRCSEL__LEN                          0x00000008
  312. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__MASK                    0x00000003
  313. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP0__SHIFT                   0
  314. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__MASK                    0x0000001c
  315. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG0__SHIFT                   2
  316. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__MASK                    0x00000060
  317. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP1__SHIFT                   5
  318. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__MASK                    0x00000380
  319. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG1__SHIFT                   7
  320. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__MASK                    0x00000c00
  321. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP2__SHIFT                   10
  322. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__MASK                    0x00007000
  323. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG2__SHIFT                   12
  324. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__MASK                    0x00018000
  325. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP3__SHIFT                   15
  326. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__MASK                    0x000e0000
  327. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG3__SHIFT                   17
  328. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__MASK                    0x00300000
  329. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP4__SHIFT                   20
  330. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__MASK                    0x01c00000
  331. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG4__SHIFT                   22
  332. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__MASK                    0x06000000
  333. #define NVE4_COMPUTE_MP_PM_SRCSEL_GRP5__SHIFT                   25
  334. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__MASK                    0x38000000
  335. #define NVE4_COMPUTE_MP_PM_SRCSEL_SIG5__SHIFT                   27
  336.  
  337. #define NVE4_COMPUTE_MP_PM_FUNC(i0)                            (0x000033bc + 0x4*(i0))
  338. #define NVE4_COMPUTE_MP_PM_FUNC__ESIZE                          0x00000004
  339. #define NVE4_COMPUTE_MP_PM_FUNC__LEN                            0x00000008
  340. #define NVE4_COMPUTE_MP_PM_FUNC_MODE__MASK                      0x0000000f
  341. #define NVE4_COMPUTE_MP_PM_FUNC_MODE__SHIFT                     0
  342. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP                      0x00000000
  343. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_PULSE                0x00000001
  344. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_B6                         0x00000002
  345. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK3                       0x00000003
  346. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6                   0x00000004
  347. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_LOGOP_B6_PULSE             0x00000005
  348. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK6                       0x00000006
  349. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK7                       0x00000007
  350. #define NVE4_COMPUTE_MP_PM_FUNC_MODE_UNK8                       0x00000008
  351. #define NVE4_COMPUTE_MP_PM_FUNC_FUNC__MASK                      0x000ffff0
  352. #define NVE4_COMPUTE_MP_PM_FUNC_FUNC__SHIFT                     4
  353.  
  354. #define NVE4_COMPUTE_MP_PM_UNK33DC                              0x000033dc
  355.  
  356. #define NVE4_COMPUTE_LAUNCH_DESC__SIZE                          0x00000100
  357. #define NVE4_COMPUTE_LAUNCH_DESC_6                              0x00000018
  358. #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__MASK                 0x00000c00
  359. #define NVE4_COMPUTE_LAUNCH_DESC_6_NOTIFY__SHIFT                10
  360.  
  361. #define NVE4_COMPUTE_LAUNCH_DESC_PROG_START                     0x00000020
  362.  
  363. #define NVE4_COMPUTE_LAUNCH_DESC_12                             0x00000030
  364. #define NVE4_COMPUTE_LAUNCH_DESC_12_GRIDDIM_X__MASK             0x7fffffff
  365. #define NVE4_COMPUTE_LAUNCH_DESC_12_GRIDDIM_X__SHIFT            0
  366.  
  367. #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ                     0x00000034
  368. #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Y__MASK             0x0000ffff
  369. #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Y__SHIFT            0
  370. #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Z__MASK             0xffff0000
  371. #define NVE4_COMPUTE_LAUNCH_DESC_GRIDDIM_YZ_Z__SHIFT            16
  372.  
  373. #define NVE4_COMPUTE_LAUNCH_DESC_17                             0x00000044
  374. #define NVE4_COMPUTE_LAUNCH_DESC_17_SHARED_ALLOC__MASK          0x0000ffff
  375. #define NVE4_COMPUTE_LAUNCH_DESC_17_SHARED_ALLOC__SHIFT         0
  376.  
  377. #define NVE4_COMPUTE_LAUNCH_DESC_18                             0x00000048
  378. #define NVE4_COMPUTE_LAUNCH_DESC_18_BLOCKDIM_X__MASK            0xffff0000
  379. #define NVE4_COMPUTE_LAUNCH_DESC_18_BLOCKDIM_X__SHIFT           16
  380.  
  381. #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ                    0x0000004c
  382. #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Y__MASK            0x0000ffff
  383. #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Y__SHIFT           0
  384. #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Z__MASK            0xffff0000
  385. #define NVE4_COMPUTE_LAUNCH_DESC_BLOCKDIM_YZ_Z__SHIFT           16
  386.  
  387. #define NVE4_COMPUTE_LAUNCH_DESC_20                             0x00000050
  388. #define NVE4_COMPUTE_LAUNCH_DESC_20_CB_VALID__MASK              0x000000ff
  389. #define NVE4_COMPUTE_LAUNCH_DESC_20_CB_VALID__SHIFT             0
  390. #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT__MASK           0x60000000
  391. #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT__SHIFT          29
  392. #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_16K_SHARED_48K_L1       0x20000000
  393. #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_32K_SHARED_32K_L1       0x40000000
  394. #define NVE4_COMPUTE_LAUNCH_DESC_20_CACHE_SPLIT_48K_SHARED_16K_L1       0x60000000
  395.  
  396. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0(i0)               (0x00000074 + 0x8*(i0))
  397. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0__ESIZE             0x00000008
  398. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0__LEN               0x00000008
  399. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0_ADDRESS_LOW__MASK  0xffffffff
  400. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_0_ADDRESS_LOW__SHIFT 0
  401.  
  402. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1(i0)               (0x00000078 + 0x8*(i0))
  403. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1__ESIZE             0x00000008
  404. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1__LEN               0x00000008
  405. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_ADDRESS_HIGH__MASK 0x000000ff
  406. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_ADDRESS_HIGH__SHIFT        0
  407. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_SIZE__MASK         0xffff8000
  408. #define NVE4_COMPUTE_LAUNCH_DESC_CB_CONFIG_1_SIZE__SHIFT        15
  409.  
  410. #define NVE4_COMPUTE_LAUNCH_DESC_45                             0x000000b4
  411. #define NVE4_COMPUTE_LAUNCH_DESC_45_LOCAL_POS_ALLOC__MASK       0x000fffff
  412. #define NVE4_COMPUTE_LAUNCH_DESC_45_LOCAL_POS_ALLOC__SHIFT      0
  413. #define NVE4_COMPUTE_LAUNCH_DESC_45_BARRIER_ALLOC__MASK         0xf8000000
  414. #define NVE4_COMPUTE_LAUNCH_DESC_45_BARRIER_ALLOC__SHIFT        27
  415.  
  416. #define NVE4_COMPUTE_LAUNCH_DESC_46                             0x000000b8
  417. #define NVE4_COMPUTE_LAUNCH_DESC_46_LOCAL_NEG_ALLOC__MASK       0x000fffff
  418. #define NVE4_COMPUTE_LAUNCH_DESC_46_LOCAL_NEG_ALLOC__SHIFT      0
  419. #define NVE4_COMPUTE_LAUNCH_DESC_46_GPR_ALLOC__MASK             0x3f000000
  420. #define NVE4_COMPUTE_LAUNCH_DESC_46_GPR_ALLOC__SHIFT            24
  421.  
  422. #define NVE4_COMPUTE_LAUNCH_DESC_47                             0x000000bc
  423. #define NVE4_COMPUTE_LAUNCH_DESC_47_WARP_CSTACK_SIZE__MASK      0x000fffff
  424. #define NVE4_COMPUTE_LAUNCH_DESC_47_WARP_CSTACK_SIZE__SHIFT     0
  425.  
  426.  
  427. #endif /* NVE4_COMPUTE_XML */
  428.