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  1. /*
  2.  * Copyright 2011 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #include "nv50_ir_target_nvc0.h"
  24.  
  25. namespace nv50_ir {
  26.  
  27. Target *getTargetNVC0(unsigned int chipset)
  28. {
  29.    return new TargetNVC0(chipset);
  30. }
  31.  
  32. TargetNVC0::TargetNVC0(unsigned int card) : Target(false, card >= 0xe4)
  33. {
  34.    chipset = card;
  35.    initOpInfo();
  36. }
  37.  
  38. // BULTINS / LIBRARY FUNCTIONS:
  39.  
  40. // lazyness -> will just hardcode everything for the time being
  41.  
  42. #include "target_lib_nvc0.asm.h"
  43. #include "target_lib_nve4.asm.h"
  44. #include "target_lib_nvf0.asm.h"
  45.  
  46. void
  47. TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
  48. {
  49.    switch (chipset & 0xf0) {
  50.    case 0xe0:
  51.       *code = (const uint32_t *)&nve4_builtin_code[0];
  52.       *size = sizeof(nve4_builtin_code);
  53.       break;
  54.    case 0xf0:
  55.       *code = (const uint32_t *)&nvf0_builtin_code[0];
  56.       *size = sizeof(nvf0_builtin_code);
  57.       break;
  58.    default:
  59.       *code = (const uint32_t *)&nvc0_builtin_code[0];
  60.       *size = sizeof(nvc0_builtin_code);
  61.       break;
  62.    }
  63. }
  64.  
  65. uint32_t
  66. TargetNVC0::getBuiltinOffset(int builtin) const
  67. {
  68.    assert(builtin < NVC0_BUILTIN_COUNT);
  69.  
  70.    switch (chipset & 0xf0) {
  71.    case 0xe0: return nve4_builtin_offsets[builtin];
  72.    case 0xf0: return nvf0_builtin_offsets[builtin];
  73.    default:
  74.       return nvc0_builtin_offsets[builtin];
  75.    }
  76. }
  77.  
  78. struct opProperties
  79. {
  80.    operation op;
  81.    unsigned int mNeg   : 4;
  82.    unsigned int mAbs   : 4;
  83.    unsigned int mNot   : 4;
  84.    unsigned int mSat   : 4;
  85.    unsigned int fConst : 3;
  86.    unsigned int fImmd  : 4; // last bit indicates if full immediate is suppoted
  87. };
  88.  
  89. static const struct opProperties _initProps[] =
  90. {
  91.    //           neg  abs  not  sat  c[]  imm
  92.    { OP_ADD,    0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  93.    { OP_SUB,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
  94.    { OP_MUL,    0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  95.    { OP_MAX,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  96.    { OP_MIN,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  97.    { OP_MAD,    0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint
  98.    { OP_MADSP,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  99.    { OP_ABS,    0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
  100.    { OP_NEG,    0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
  101.    { OP_CVT,    0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  102.    { OP_CEIL,   0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  103.    { OP_FLOOR,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  104.    { OP_TRUNC,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  105.    { OP_AND,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
  106.    { OP_OR,     0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
  107.    { OP_XOR,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
  108.    { OP_SHL,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  109.    { OP_SHR,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  110.    { OP_SET,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  111.    { OP_SLCT,   0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
  112.    { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
  113.    { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
  114.    { OP_COS,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  115.    { OP_SIN,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  116.    { OP_EX2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  117.    { OP_LG2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  118.    { OP_RCP,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  119.    { OP_RSQ,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  120.    { OP_DFDX,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
  121.    { OP_DFDY,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
  122.    { OP_CALL,   0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
  123.    { OP_INSBF,  0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
  124.    { OP_PERMT,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  125.    { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  126.    { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  127.    { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  128.    // saturate only:
  129.    { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
  130.    { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
  131.    // nve4 ops:
  132.    { OP_SULDB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
  133.    { OP_SUSTB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
  134.    { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
  135.    { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  136.    { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  137.    { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
  138. };
  139.  
  140. void TargetNVC0::initOpInfo()
  141. {
  142.    unsigned int i, j;
  143.  
  144.    static const uint32_t commutative[(OP_LAST + 31) / 32] =
  145.    {
  146.       // ADD, MAD, MUL, AND, OR, XOR, MAX, MIN
  147.       0x0670ca00, 0x0000003f, 0x00000000, 0x00000000
  148.    };
  149.  
  150.    static const uint32_t shortForm[(OP_LAST + 31) / 32] =
  151.    {
  152.       // ADD, MAD, MUL, AND, OR, XOR, PRESIN, PREEX2, SFN, CVT, PINTERP, MOV
  153.       0x0670ca00, 0x00000000, 0x00000000, 0x00000000
  154.    };
  155.  
  156.    static const operation noDest[] =
  157.    {
  158.       OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
  159.       OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
  160.       OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
  161.       OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
  162.       OP_SUREDB, OP_BAR
  163.    };
  164.  
  165.    static const operation noPred[] =
  166.    {
  167.       OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
  168.       OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
  169.    };
  170.  
  171.    for (i = 0; i < DATA_FILE_COUNT; ++i)
  172.       nativeFileMap[i] = (DataFile)i;
  173.    nativeFileMap[FILE_ADDRESS] = FILE_GPR;
  174.  
  175.    for (i = 0; i < OP_LAST; ++i) {
  176.       opInfo[i].variants = NULL;
  177.       opInfo[i].op = (operation)i;
  178.       opInfo[i].srcTypes = 1 << (int)TYPE_F32;
  179.       opInfo[i].dstTypes = 1 << (int)TYPE_F32;
  180.       opInfo[i].immdBits = 0;
  181.       opInfo[i].srcNr = operationSrcNr[i];
  182.  
  183.       for (j = 0; j < opInfo[i].srcNr; ++j) {
  184.          opInfo[i].srcMods[j] = 0;
  185.          opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
  186.       }
  187.       opInfo[i].dstMods = 0;
  188.       opInfo[i].dstFiles = 1 << (int)FILE_GPR;
  189.  
  190.       opInfo[i].hasDest = 1;
  191.       opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
  192.       opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
  193.       opInfo[i].pseudo = (i < OP_MOV);
  194.       opInfo[i].predicate = !opInfo[i].pseudo;
  195.       opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
  196.       opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
  197.    }
  198.    for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
  199.       opInfo[noDest[i]].hasDest = 0;
  200.    for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
  201.       opInfo[noPred[i]].predicate = 0;
  202.  
  203.    for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
  204.       const struct opProperties *prop = &_initProps[i];
  205.  
  206.       for (int s = 0; s < 3; ++s) {
  207.          if (prop->mNeg & (1 << s))
  208.             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
  209.          if (prop->mAbs & (1 << s))
  210.             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
  211.          if (prop->mNot & (1 << s))
  212.             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
  213.          if (prop->fConst & (1 << s))
  214.             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
  215.          if (prop->fImmd & (1 << s))
  216.             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
  217.          if (prop->fImmd & 8)
  218.             opInfo[prop->op].immdBits = 0xffffffff;
  219.       }
  220.       if (prop->mSat & 8)
  221.          opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
  222.    }
  223. }
  224.  
  225. unsigned int
  226. TargetNVC0::getFileSize(DataFile file) const
  227. {
  228.    switch (file) {
  229.    case FILE_NULL:          return 0;
  230.    case FILE_GPR:           return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63;
  231.    case FILE_PREDICATE:     return 7;
  232.    case FILE_FLAGS:         return 1;
  233.    case FILE_ADDRESS:       return 0;
  234.    case FILE_IMMEDIATE:     return 0;
  235.    case FILE_MEMORY_CONST:  return 65536;
  236.    case FILE_SHADER_INPUT:  return 0x400;
  237.    case FILE_SHADER_OUTPUT: return 0x400;
  238.    case FILE_MEMORY_GLOBAL: return 0xffffffff;
  239.    case FILE_MEMORY_SHARED: return 16 << 10;
  240.    case FILE_MEMORY_LOCAL:  return 48 << 10;
  241.    case FILE_SYSTEM_VALUE:  return 32;
  242.    default:
  243.       assert(!"invalid file");
  244.       return 0;
  245.    }
  246. }
  247.  
  248. unsigned int
  249. TargetNVC0::getFileUnit(DataFile file) const
  250. {
  251.    if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
  252.       return 2;
  253.    return 0;
  254. }
  255.  
  256. uint32_t
  257. TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
  258. {
  259.    const int idx = sym->reg.data.sv.index;
  260.    const SVSemantic sv = sym->reg.data.sv.sv;
  261.  
  262.    const bool isInput = shaderFile == FILE_SHADER_INPUT;
  263.    const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
  264.  
  265.    switch (sv) {
  266.    case SV_POSITION:       return 0x070 + idx * 4;
  267.    case SV_INSTANCE_ID:    return 0x2f8;
  268.    case SV_VERTEX_ID:      return 0x2fc;
  269.    case SV_PRIMITIVE_ID:   return isInput ? 0x060 : 0x040;
  270.    case SV_LAYER:          return 0x064;
  271.    case SV_VIEWPORT_INDEX: return 0x068;
  272.    case SV_POINT_SIZE:     return 0x06c;
  273.    case SV_CLIP_DISTANCE:  return 0x2c0 + idx * 4;
  274.    case SV_POINT_COORD:    return 0x2e0 + idx * 4;
  275.    case SV_FACE:           return 0x3fc;
  276.    case SV_TESS_FACTOR:    return 0x000 + idx * 4;
  277.    case SV_TESS_COORD:     return 0x2f0 + idx * 4;
  278.    case SV_NTID:           return kepler ? (0x00 + idx * 4) : ~0;
  279.    case SV_NCTAID:         return kepler ? (0x0c + idx * 4) : ~0;
  280.    case SV_GRIDID:         return kepler ? 0x18 : ~0;
  281.    default:
  282.       return 0xffffffff;
  283.    }
  284. }
  285.  
  286. bool
  287. TargetNVC0::insnCanLoad(const Instruction *i, int s,
  288.                         const Instruction *ld) const
  289. {
  290.    DataFile sf = ld->src(0).getFile();
  291.  
  292.    // immediate 0 can be represented by GPR $r63/$r255
  293.    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
  294.       return (!i->isPseudo() &&
  295.               !i->asTex() &&
  296.               i->op != OP_EXPORT && i->op != OP_STORE);
  297.  
  298.    if (s >= opInfo[i->op].srcNr)
  299.       return false;
  300.    if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
  301.       return false;
  302.  
  303.    // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
  304.    if (ld->src(0).isIndirect(0))
  305.       return false;
  306.  
  307.    for (int k = 0; i->srcExists(k); ++k) {
  308.       if (i->src(k).getFile() == FILE_IMMEDIATE) {
  309.          if (k == 2 && i->op == OP_SUCLAMP) // special case
  310.             continue;
  311.          if (i->getSrc(k)->reg.data.u64 != 0)
  312.             return false;
  313.       } else
  314.       if (i->src(k).getFile() != FILE_GPR &&
  315.           i->src(k).getFile() != FILE_PREDICATE) {
  316.          return false;
  317.       }
  318.    }
  319.  
  320.    // not all instructions support full 32 bit immediates
  321.    if (sf == FILE_IMMEDIATE) {
  322.       Storage &reg = ld->getSrc(0)->asImm()->reg;
  323.  
  324.       if (opInfo[i->op].immdBits != 0xffffffff) {
  325.          if (i->sType == TYPE_F32) {
  326.             if (reg.data.u32 & 0xfff)
  327.                return false;
  328.          } else
  329.          if (i->sType == TYPE_S32 || i->sType == TYPE_U32) {
  330.             // with u32, 0xfffff counts as 0xffffffff as well
  331.             if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
  332.                return false;
  333.          }
  334.       } else
  335.       if (i->op == OP_MAD || i->op == OP_FMA) {
  336.          // requires src == dst, cannot decide before RA
  337.          // (except if we implement more constraints)
  338.          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
  339.             return false;
  340.       } else
  341.       if (i->op == OP_ADD && i->sType == TYPE_F32) {
  342.          // add f32 LIMM cannot saturate
  343.          if (i->saturate && (reg.data.u32 & 0xfff))
  344.             return false;
  345.       }
  346.    }
  347.  
  348.    return true;
  349. }
  350.  
  351. bool
  352. TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
  353. {
  354.    if (ty == TYPE_NONE)
  355.       return false;
  356.    if (file == FILE_MEMORY_CONST && getChipset() >= 0xe0) // wrong encoding ?
  357.       return typeSizeof(ty) <= 8;
  358.    if (ty == TYPE_B96)
  359.       return false;
  360.    if (getChipset() >= 0xf0) {
  361.       // XXX: find wide vfetch/export
  362.       if (ty == TYPE_B128)
  363.          return false;
  364.       if (ty == TYPE_U64)
  365.          return false;
  366.    }
  367.    return true;
  368. }
  369.  
  370. bool
  371. TargetNVC0::isOpSupported(operation op, DataType ty) const
  372. {
  373.    if ((op == OP_MAD || op == OP_FMA) && (ty != TYPE_F32))
  374.       return false;
  375.    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
  376.       return false;
  377.    if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
  378.       return false;
  379.    return true;
  380. }
  381.  
  382. bool
  383. TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
  384. {
  385.    if (!isFloatType(insn->dType)) {
  386.       switch (insn->op) {
  387.       case OP_ABS:
  388.       case OP_NEG:
  389.       case OP_CVT:
  390.       case OP_CEIL:
  391.       case OP_FLOOR:
  392.       case OP_TRUNC:
  393.       case OP_AND:
  394.       case OP_OR:
  395.       case OP_XOR:
  396.          break;
  397.       case OP_SET:
  398.          if (insn->sType != TYPE_F32)
  399.             return false;
  400.          break;
  401.       case OP_ADD:
  402.          if (mod.abs())
  403.             return false;
  404.          if (insn->src(s ? 0 : 1).mod.neg())
  405.             return false;
  406.          break;
  407.       case OP_SUB:
  408.          if (s == 0)
  409.             return insn->src(1).mod.neg() ? false : true;
  410.          break;
  411.       default:
  412.          return false;
  413.       }
  414.    }
  415.    if (s > 3)
  416.       return false;
  417.    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
  418. }
  419.  
  420. bool
  421. TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
  422. {
  423.    if (insn->getPredicate())
  424.       return false;
  425.    return opInfo[insn->op].predicate;
  426. }
  427.  
  428. bool
  429. TargetNVC0::isSatSupported(const Instruction *insn) const
  430. {
  431.    if (insn->op == OP_CVT)
  432.       return true;
  433.    if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
  434.       return false;
  435.  
  436.    if (insn->dType == TYPE_U32)
  437.       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
  438.  
  439.    // add f32 LIMM cannot saturate
  440.    if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
  441.       if (insn->getSrc(1)->asImm() &&
  442.           insn->getSrc(1)->reg.data.u32 & 0xfff)
  443.          return false;
  444.    }
  445.  
  446.    return insn->dType == TYPE_F32;
  447. }
  448.  
  449. bool
  450. TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
  451. {
  452.    if (op != OP_MUL)
  453.       return false;
  454.    f = fabsf(f);
  455.    e = static_cast<int>(log2f(f));
  456.    if (e < -3 || e > 3)
  457.       return false;
  458.    return f == exp2f(static_cast<float>(e));
  459. }
  460.  
  461. // TODO: better values
  462. // this could be more precise, e.g. depending on the issue-to-read/write delay
  463. // of the depending instruction, but it's good enough
  464. int TargetNVC0::getLatency(const Instruction *i) const
  465. {
  466.    if (chipset >= 0xe4) {
  467.       if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
  468.          return 20;
  469.       switch (i->op) {
  470.       case OP_LINTERP:
  471.       case OP_PINTERP:
  472.          return 15;
  473.       case OP_LOAD:
  474.          if (i->src(0).getFile() == FILE_MEMORY_CONST)
  475.             return 9;
  476.          // fall through
  477.       case OP_VFETCH:
  478.          return 24;
  479.       default:
  480.          if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
  481.             return 17;
  482.          if (i->op == OP_MUL && i->dType != TYPE_F32)
  483.             return 15;
  484.          return 9;
  485.       }
  486.    } else {
  487.       if (i->op == OP_LOAD) {
  488.          if (i->cache == CACHE_CV)
  489.             return 700;
  490.          return 48;
  491.       }
  492.       return 24;
  493.    }
  494.    return 32;
  495. }
  496.  
  497. // These are "inverse" throughput values, i.e. the number of cycles required
  498. // to issue a specific instruction for a full warp (32 threads).
  499. //
  500. // Assuming we have more than 1 warp in flight, a higher issue latency results
  501. // in a lower result latency since the MP will have spent more time with other
  502. // warps.
  503. // This also helps to determine the number of cycles between instructions in
  504. // a single warp.
  505. //
  506. int TargetNVC0::getThroughput(const Instruction *i) const
  507. {
  508.    // TODO: better values
  509.    if (i->dType == TYPE_F32) {
  510.       switch (i->op) {
  511.       case OP_ADD:
  512.       case OP_MUL:
  513.       case OP_MAD:
  514.       case OP_FMA:
  515.          return 1;
  516.       case OP_CVT:
  517.       case OP_CEIL:
  518.       case OP_FLOOR:
  519.       case OP_TRUNC:
  520.       case OP_SET:
  521.       case OP_SLCT:
  522.       case OP_MIN:
  523.       case OP_MAX:
  524.          return 2;
  525.       case OP_RCP:
  526.       case OP_RSQ:
  527.       case OP_LG2:
  528.       case OP_SIN:
  529.       case OP_COS:
  530.       case OP_PRESIN:
  531.       case OP_PREEX2:
  532.       default:
  533.          return 8;
  534.       }
  535.    } else
  536.    if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
  537.       switch (i->op) {
  538.       case OP_ADD:
  539.       case OP_AND:
  540.       case OP_OR:
  541.       case OP_XOR:
  542.       case OP_NOT:
  543.          return 1;
  544.       case OP_MUL:
  545.       case OP_MAD:
  546.       case OP_CVT:
  547.       case OP_SET:
  548.       case OP_SLCT:
  549.       case OP_SHL:
  550.       case OP_SHR:
  551.       case OP_NEG:
  552.       case OP_ABS:
  553.       case OP_MIN:
  554.       case OP_MAX:
  555.       default:
  556.          return 2;
  557.       }
  558.    } else
  559.    if (i->dType == TYPE_F64) {
  560.       return 2;
  561.    } else {
  562.       return 1;
  563.    }
  564. }
  565.  
  566. bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
  567. {
  568.    const OpClass clA = operationClass[a->op];
  569.    const OpClass clB = operationClass[b->op];
  570.  
  571.    if (getChipset() >= 0xe4) {
  572.       // not texturing
  573.       // not if the 2nd instruction isn't necessarily executed
  574.       if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
  575.          return false;
  576.       // anything with MOV
  577.       if (a->op == OP_MOV || b->op == OP_MOV)
  578.          return true;
  579.       if (clA == clB) {
  580.          // only F32 arith or integer additions
  581.          if (clA != OPCLASS_ARITH)
  582.             return false;
  583.          return (a->dType == TYPE_F32 || a->op == OP_ADD ||
  584.                  b->dType == TYPE_F32 || b->op == OP_ADD);
  585.       }
  586.       // nothing with TEXBAR
  587.       if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
  588.          return false;
  589.       // no loads and stores accessing the the same space
  590.       if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
  591.           (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
  592.          if (a->src(0).getFile() == b->src(0).getFile())
  593.             return false;
  594.       // no > 32-bit ops
  595.       if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
  596.           typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
  597.          return false;
  598.       return true;
  599.    } else {
  600.       return false; // info not needed (yet)
  601.    }
  602. }
  603.  
  604. } // namespace nv50_ir
  605.