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  1. /**************************************************************************
  2.  *
  3.  * Copyright 2007-2008 VMware, Inc.
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21.  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27.  
  28. /*
  29.  * \author
  30.  * Michal Krol,
  31.  * Keith Whitwell
  32.  */
  33.  
  34. #include "pipe/p_compiler.h"
  35. #include "pipe/p_context.h"
  36. #include "pipe/p_screen.h"
  37. #include "pipe/p_shader_tokens.h"
  38. #include "pipe/p_state.h"
  39. #include "tgsi/tgsi_ureg.h"
  40. #include "st_mesa_to_tgsi.h"
  41. #include "st_context.h"
  42. #include "program/prog_instruction.h"
  43. #include "program/prog_parameter.h"
  44. #include "util/u_debug.h"
  45. #include "util/u_math.h"
  46. #include "util/u_memory.h"
  47. #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  48.  
  49.  
  50. #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  51.                            (1 << PROGRAM_CONSTANT) |     \
  52.                            (1 << PROGRAM_UNIFORM))
  53.  
  54.  
  55. struct label {
  56.    unsigned branch_target;
  57.    unsigned token;
  58. };
  59.  
  60.  
  61. /**
  62.  * Intermediate state used during shader translation.
  63.  */
  64. struct st_translate {
  65.    struct ureg_program *ureg;
  66.  
  67.    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  68.    struct ureg_src *constants;
  69.    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  70.    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  71.    struct ureg_dst address[1];
  72.    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  73.    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  74.  
  75.    const GLuint *inputMapping;
  76.    const GLuint *outputMapping;
  77.  
  78.    /* For every instruction that contains a label (eg CALL), keep
  79.     * details so that we can go back afterwards and emit the correct
  80.     * tgsi instruction number for each label.
  81.     */
  82.    struct label *labels;
  83.    unsigned labels_size;
  84.    unsigned labels_count;
  85.  
  86.    /* Keep a record of the tgsi instruction number that each mesa
  87.     * instruction starts at, will be used to fix up labels after
  88.     * translation.
  89.     */
  90.    unsigned *insn;
  91.    unsigned insn_size;
  92.    unsigned insn_count;
  93.  
  94.    unsigned procType;  /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
  95.  
  96.    boolean error;
  97. };
  98.  
  99.  
  100. /**
  101.  * Make note of a branch to a label in the TGSI code.
  102.  * After we've emitted all instructions, we'll go over the list
  103.  * of labels built here and patch the TGSI code with the actual
  104.  * location of each label.
  105.  */
  106. static unsigned *get_label( struct st_translate *t,
  107.                             unsigned branch_target )
  108. {
  109.    unsigned i;
  110.  
  111.    if (t->labels_count + 1 >= t->labels_size) {
  112.       t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
  113.       t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
  114.       if (t->labels == NULL) {
  115.          static unsigned dummy;
  116.          t->error = TRUE;
  117.          return &dummy;
  118.       }
  119.    }
  120.  
  121.    i = t->labels_count++;
  122.    t->labels[i].branch_target = branch_target;
  123.    return &t->labels[i].token;
  124. }
  125.  
  126.  
  127. /**
  128.  * Called prior to emitting the TGSI code for each Mesa instruction.
  129.  * Allocate additional space for instructions if needed.
  130.  * Update the insn[] array so the next Mesa instruction points to
  131.  * the next TGSI instruction.
  132.  */
  133. static void set_insn_start( struct st_translate *t,
  134.                             unsigned start )
  135. {
  136.    if (t->insn_count + 1 >= t->insn_size) {
  137.       t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
  138.       t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
  139.       if (t->insn == NULL) {
  140.          t->error = TRUE;
  141.          return;
  142.       }
  143.    }
  144.  
  145.    t->insn[t->insn_count++] = start;
  146. }
  147.  
  148.  
  149. /**
  150.  * Map a Mesa dst register to a TGSI ureg_dst register.
  151.  */
  152. static struct ureg_dst
  153. dst_register( struct st_translate *t,
  154.               gl_register_file file,
  155.               GLuint index )
  156. {
  157.    switch( file ) {
  158.    case PROGRAM_UNDEFINED:
  159.       return ureg_dst_undef();
  160.  
  161.    case PROGRAM_TEMPORARY:
  162.       if (ureg_dst_is_undef(t->temps[index]))
  163.          t->temps[index] = ureg_DECL_temporary( t->ureg );
  164.  
  165.       return t->temps[index];
  166.  
  167.    case PROGRAM_OUTPUT:
  168.       if (t->procType == TGSI_PROCESSOR_VERTEX)
  169.          assert(index < VARYING_SLOT_MAX);
  170.       else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
  171.          assert(index < FRAG_RESULT_MAX);
  172.       else
  173.          assert(index < VARYING_SLOT_MAX);
  174.  
  175.       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
  176.  
  177.       return t->outputs[t->outputMapping[index]];
  178.  
  179.    case PROGRAM_ADDRESS:
  180.       return t->address[index];
  181.  
  182.    default:
  183.       debug_assert( 0 );
  184.       return ureg_dst_undef();
  185.    }
  186. }
  187.  
  188.  
  189. /**
  190.  * Map a Mesa src register to a TGSI ureg_src register.
  191.  */
  192. static struct ureg_src
  193. src_register( struct st_translate *t,
  194.               gl_register_file file,
  195.               GLint index )
  196. {
  197.    switch( file ) {
  198.    case PROGRAM_UNDEFINED:
  199.       return ureg_src_undef();
  200.  
  201.    case PROGRAM_TEMPORARY:
  202.       assert(index >= 0);
  203.       assert(index < ARRAY_SIZE(t->temps));
  204.       if (ureg_dst_is_undef(t->temps[index]))
  205.          t->temps[index] = ureg_DECL_temporary( t->ureg );
  206.       return ureg_src(t->temps[index]);
  207.  
  208.    case PROGRAM_UNIFORM:
  209.       assert(index >= 0);
  210.       return t->constants[index];
  211.    case PROGRAM_STATE_VAR:
  212.    case PROGRAM_CONSTANT:       /* ie, immediate */
  213.       if (index < 0)
  214.          return ureg_DECL_constant( t->ureg, 0 );
  215.       else
  216.          return t->constants[index];
  217.  
  218.    case PROGRAM_INPUT:
  219.       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
  220.       return t->inputs[t->inputMapping[index]];
  221.  
  222.    case PROGRAM_OUTPUT:
  223.       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
  224.       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
  225.  
  226.    case PROGRAM_ADDRESS:
  227.       return ureg_src(t->address[index]);
  228.  
  229.    case PROGRAM_SYSTEM_VALUE:
  230.       assert(index < ARRAY_SIZE(t->systemValues));
  231.       return t->systemValues[index];
  232.  
  233.    default:
  234.       debug_assert( 0 );
  235.       return ureg_src_undef();
  236.    }
  237. }
  238.  
  239.  
  240. /**
  241.  * Map mesa texture target to TGSI texture target.
  242.  */
  243. unsigned
  244. st_translate_texture_target( GLuint textarget,
  245.                           GLboolean shadow )
  246. {
  247.    if (shadow) {
  248.       switch( textarget ) {
  249.       case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_SHADOW1D;
  250.       case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_SHADOW2D;
  251.       case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
  252.       case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
  253.       case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
  254.       case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
  255.       case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
  256.       default: break;
  257.       }
  258.    }
  259.  
  260.    switch( textarget ) {
  261.    case TEXTURE_2D_MULTISAMPLE_INDEX: return TGSI_TEXTURE_2D_MSAA;
  262.    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY_MSAA;
  263.    case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
  264.    case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_1D;
  265.    case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_2D;
  266.    case TEXTURE_3D_INDEX:   return TGSI_TEXTURE_3D;
  267.    case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
  268.    case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
  269.    case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
  270.    case TEXTURE_1D_ARRAY_INDEX:   return TGSI_TEXTURE_1D_ARRAY;
  271.    case TEXTURE_2D_ARRAY_INDEX:   return TGSI_TEXTURE_2D_ARRAY;
  272.    case TEXTURE_EXTERNAL_INDEX:   return TGSI_TEXTURE_2D;
  273.    default:
  274.       debug_assert( 0 );
  275.       return TGSI_TEXTURE_1D;
  276.    }
  277. }
  278.  
  279.  
  280. /**
  281.  * Create a TGSI ureg_dst register from a Mesa dest register.
  282.  */
  283. static struct ureg_dst
  284. translate_dst( struct st_translate *t,
  285.                const struct prog_dst_register *DstReg,
  286.                boolean saturate,
  287.                boolean clamp_color)
  288. {
  289.    struct ureg_dst dst = dst_register( t,
  290.                                        DstReg->File,
  291.                                        DstReg->Index );
  292.  
  293.    dst = ureg_writemask( dst,
  294.                          DstReg->WriteMask );
  295.    
  296.    if (saturate)
  297.       dst = ureg_saturate( dst );
  298.    else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
  299.       /* Clamp colors for ARB_color_buffer_float. */
  300.       switch (t->procType) {
  301.       case TGSI_PROCESSOR_VERTEX:
  302.          /* This can only occur with a compatibility profile, which doesn't
  303.           * support geometry shaders. */
  304.          if (DstReg->Index == VARYING_SLOT_COL0 ||
  305.              DstReg->Index == VARYING_SLOT_COL1 ||
  306.              DstReg->Index == VARYING_SLOT_BFC0 ||
  307.              DstReg->Index == VARYING_SLOT_BFC1) {
  308.             dst = ureg_saturate(dst);
  309.          }
  310.          break;
  311.  
  312.       case TGSI_PROCESSOR_FRAGMENT:
  313.          if (DstReg->Index >= FRAG_RESULT_COLOR) {
  314.             dst = ureg_saturate(dst);
  315.          }
  316.          break;
  317.       }
  318.    }
  319.  
  320.    if (DstReg->RelAddr)
  321.       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
  322.  
  323.    return dst;
  324. }
  325.  
  326.  
  327. /**
  328.  * Create a TGSI ureg_src register from a Mesa src register.
  329.  */
  330. static struct ureg_src
  331. translate_src( struct st_translate *t,
  332.                const struct prog_src_register *SrcReg )
  333. {
  334.    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
  335.  
  336.    if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
  337.       src = src_register( t, SrcReg->File, SrcReg->Index2 );
  338.       if (SrcReg->RelAddr2)
  339.          src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
  340.                                             SrcReg->Index);
  341.       else
  342.          src = ureg_src_dimension( src, SrcReg->Index);
  343.    }
  344.  
  345.    src = ureg_swizzle( src,
  346.                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
  347.                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
  348.                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
  349.                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
  350.  
  351.    if (SrcReg->Negate == NEGATE_XYZW)
  352.       src = ureg_negate(src);
  353.  
  354.    if (SrcReg->Abs)
  355.       src = ureg_abs(src);
  356.  
  357.    if (SrcReg->RelAddr) {
  358.       src = ureg_src_indirect( src, ureg_src(t->address[0]));
  359.       if (SrcReg->File != PROGRAM_INPUT &&
  360.           SrcReg->File != PROGRAM_OUTPUT) {
  361.          /* If SrcReg->Index was negative, it was set to zero in
  362.           * src_register().  Reassign it now.  But don't do this
  363.           * for input/output regs since they get remapped while
  364.           * const buffers don't.
  365.           */
  366.          src.Index = SrcReg->Index;
  367.       }
  368.    }
  369.  
  370.    return src;
  371. }
  372.  
  373.  
  374. static struct ureg_src swizzle_4v( struct ureg_src src,
  375.                                    const unsigned *swz )
  376. {
  377.    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
  378. }
  379.  
  380.  
  381. /**
  382.  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
  383.  *
  384.  *   SWZ dst, src.x-y10
  385.  *
  386.  * becomes:
  387.  *
  388.  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
  389.  */
  390. static void emit_swz( struct st_translate *t,
  391.                       struct ureg_dst dst,
  392.                       const struct prog_src_register *SrcReg )
  393. {
  394.    struct ureg_program *ureg = t->ureg;
  395.    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
  396.  
  397.    unsigned negate_mask =  SrcReg->Negate;
  398.  
  399.    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
  400.                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
  401.                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
  402.                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
  403.  
  404.    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
  405.                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
  406.                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
  407.                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
  408.  
  409.    unsigned negative_one_mask = one_mask & negate_mask;
  410.    unsigned positive_one_mask = one_mask & ~negate_mask;
  411.    
  412.    struct ureg_src imm;
  413.    unsigned i;
  414.    unsigned mul_swizzle[4] = {0,0,0,0};
  415.    unsigned add_swizzle[4] = {0,0,0,0};
  416.    unsigned src_swizzle[4] = {0,0,0,0};
  417.    boolean need_add = FALSE;
  418.    boolean need_mul = FALSE;
  419.  
  420.    if (dst.WriteMask == 0)
  421.       return;
  422.  
  423.    /* Is this just a MOV?
  424.     */
  425.    if (zero_mask == 0 &&
  426.        one_mask == 0 &&
  427.        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
  428.    {
  429.       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
  430.       return;
  431.    }
  432.  
  433. #define IMM_ZERO    0
  434. #define IMM_ONE     1
  435. #define IMM_NEG_ONE 2
  436.  
  437.    imm = ureg_imm3f( ureg, 0, 1, -1 );
  438.  
  439.    for (i = 0; i < 4; i++) {
  440.       unsigned bit = 1 << i;
  441.  
  442.       if (dst.WriteMask & bit) {
  443.          if (positive_one_mask & bit) {
  444.             mul_swizzle[i] = IMM_ZERO;
  445.             add_swizzle[i] = IMM_ONE;
  446.             need_add = TRUE;
  447.          }
  448.          else if (negative_one_mask & bit) {
  449.             mul_swizzle[i] = IMM_ZERO;
  450.             add_swizzle[i] = IMM_NEG_ONE;
  451.             need_add = TRUE;
  452.          }
  453.          else if (zero_mask & bit) {
  454.             mul_swizzle[i] = IMM_ZERO;
  455.             add_swizzle[i] = IMM_ZERO;
  456.             need_add = TRUE;
  457.          }
  458.          else {
  459.             add_swizzle[i] = IMM_ZERO;
  460.             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
  461.             need_mul = TRUE;
  462.             if (negate_mask & bit) {
  463.                mul_swizzle[i] = IMM_NEG_ONE;
  464.             }
  465.             else {
  466.                mul_swizzle[i] = IMM_ONE;
  467.             }
  468.          }
  469.       }
  470.    }
  471.  
  472.    if (need_mul && need_add) {
  473.       ureg_MAD( ureg,
  474.                 dst,
  475.                 swizzle_4v( src, src_swizzle ),
  476.                 swizzle_4v( imm, mul_swizzle ),
  477.                 swizzle_4v( imm, add_swizzle ) );
  478.    }
  479.    else if (need_mul) {
  480.       ureg_MUL( ureg,
  481.                 dst,
  482.                 swizzle_4v( src, src_swizzle ),
  483.                 swizzle_4v( imm, mul_swizzle ) );
  484.    }
  485.    else if (need_add) {
  486.       ureg_MOV( ureg,
  487.                 dst,
  488.                 swizzle_4v( imm, add_swizzle ) );
  489.    }
  490.    else {
  491.       debug_assert(0);
  492.    }
  493.  
  494. #undef IMM_ZERO
  495. #undef IMM_ONE
  496. #undef IMM_NEG_ONE
  497. }
  498.  
  499.  
  500. /**
  501.  * Negate the value of DDY to match GL semantics where (0,0) is the
  502.  * lower-left corner of the window.
  503.  * Note that the GL_ARB_fragment_coord_conventions extension will
  504.  * effect this someday.
  505.  */
  506. static void emit_ddy( struct st_translate *t,
  507.                       struct ureg_dst dst,
  508.                       const struct prog_src_register *SrcReg )
  509. {
  510.    struct ureg_program *ureg = t->ureg;
  511.    struct ureg_src src = translate_src( t, SrcReg );
  512.    src = ureg_negate( src );
  513.    ureg_DDY( ureg, dst, src );
  514. }
  515.  
  516.  
  517.  
  518. static unsigned
  519. translate_opcode( unsigned op )
  520. {
  521.    switch( op ) {
  522.    case OPCODE_ARL:
  523.       return TGSI_OPCODE_ARL;
  524.    case OPCODE_ABS:
  525.       return TGSI_OPCODE_ABS;
  526.    case OPCODE_ADD:
  527.       return TGSI_OPCODE_ADD;
  528.    case OPCODE_BGNLOOP:
  529.       return TGSI_OPCODE_BGNLOOP;
  530.    case OPCODE_BGNSUB:
  531.       return TGSI_OPCODE_BGNSUB;
  532.    case OPCODE_BRK:
  533.       return TGSI_OPCODE_BRK;
  534.    case OPCODE_CAL:
  535.       return TGSI_OPCODE_CAL;
  536.    case OPCODE_CMP:
  537.       return TGSI_OPCODE_CMP;
  538.    case OPCODE_CONT:
  539.       return TGSI_OPCODE_CONT;
  540.    case OPCODE_COS:
  541.       return TGSI_OPCODE_COS;
  542.    case OPCODE_DDX:
  543.       return TGSI_OPCODE_DDX;
  544.    case OPCODE_DDY:
  545.       return TGSI_OPCODE_DDY;
  546.    case OPCODE_DP2:
  547.       return TGSI_OPCODE_DP2;
  548.    case OPCODE_DP3:
  549.       return TGSI_OPCODE_DP3;
  550.    case OPCODE_DP4:
  551.       return TGSI_OPCODE_DP4;
  552.    case OPCODE_DPH:
  553.       return TGSI_OPCODE_DPH;
  554.    case OPCODE_DST:
  555.       return TGSI_OPCODE_DST;
  556.    case OPCODE_ELSE:
  557.       return TGSI_OPCODE_ELSE;
  558.    case OPCODE_ENDIF:
  559.       return TGSI_OPCODE_ENDIF;
  560.    case OPCODE_ENDLOOP:
  561.       return TGSI_OPCODE_ENDLOOP;
  562.    case OPCODE_ENDSUB:
  563.       return TGSI_OPCODE_ENDSUB;
  564.    case OPCODE_EX2:
  565.       return TGSI_OPCODE_EX2;
  566.    case OPCODE_EXP:
  567.       return TGSI_OPCODE_EXP;
  568.    case OPCODE_FLR:
  569.       return TGSI_OPCODE_FLR;
  570.    case OPCODE_FRC:
  571.       return TGSI_OPCODE_FRC;
  572.    case OPCODE_IF:
  573.       return TGSI_OPCODE_IF;
  574.    case OPCODE_TRUNC:
  575.       return TGSI_OPCODE_TRUNC;
  576.    case OPCODE_KIL:
  577.       return TGSI_OPCODE_KILL_IF;
  578.    case OPCODE_KIL_NV:
  579.       /* XXX we don't support condition codes in TGSI */
  580.       return TGSI_OPCODE_KILL;
  581.    case OPCODE_LG2:
  582.       return TGSI_OPCODE_LG2;
  583.    case OPCODE_LOG:
  584.       return TGSI_OPCODE_LOG;
  585.    case OPCODE_LIT:
  586.       return TGSI_OPCODE_LIT;
  587.    case OPCODE_LRP:
  588.       return TGSI_OPCODE_LRP;
  589.    case OPCODE_MAD:
  590.       return TGSI_OPCODE_MAD;
  591.    case OPCODE_MAX:
  592.       return TGSI_OPCODE_MAX;
  593.    case OPCODE_MIN:
  594.       return TGSI_OPCODE_MIN;
  595.    case OPCODE_MOV:
  596.       return TGSI_OPCODE_MOV;
  597.    case OPCODE_MUL:
  598.       return TGSI_OPCODE_MUL;
  599.    case OPCODE_NOP:
  600.       return TGSI_OPCODE_NOP;
  601.    case OPCODE_POW:
  602.       return TGSI_OPCODE_POW;
  603.    case OPCODE_RCP:
  604.       return TGSI_OPCODE_RCP;
  605.    case OPCODE_RET:
  606.       return TGSI_OPCODE_RET;
  607.    case OPCODE_SCS:
  608.       return TGSI_OPCODE_SCS;
  609.    case OPCODE_SEQ:
  610.       return TGSI_OPCODE_SEQ;
  611.    case OPCODE_SGE:
  612.       return TGSI_OPCODE_SGE;
  613.    case OPCODE_SGT:
  614.       return TGSI_OPCODE_SGT;
  615.    case OPCODE_SIN:
  616.       return TGSI_OPCODE_SIN;
  617.    case OPCODE_SLE:
  618.       return TGSI_OPCODE_SLE;
  619.    case OPCODE_SLT:
  620.       return TGSI_OPCODE_SLT;
  621.    case OPCODE_SNE:
  622.       return TGSI_OPCODE_SNE;
  623.    case OPCODE_SSG:
  624.       return TGSI_OPCODE_SSG;
  625.    case OPCODE_SUB:
  626.       return TGSI_OPCODE_SUB;
  627.    case OPCODE_TEX:
  628.       return TGSI_OPCODE_TEX;
  629.    case OPCODE_TXB:
  630.       return TGSI_OPCODE_TXB;
  631.    case OPCODE_TXD:
  632.       return TGSI_OPCODE_TXD;
  633.    case OPCODE_TXL:
  634.       return TGSI_OPCODE_TXL;
  635.    case OPCODE_TXP:
  636.       return TGSI_OPCODE_TXP;
  637.    case OPCODE_XPD:
  638.       return TGSI_OPCODE_XPD;
  639.    case OPCODE_END:
  640.       return TGSI_OPCODE_END;
  641.    default:
  642.       debug_assert( 0 );
  643.       return TGSI_OPCODE_NOP;
  644.    }
  645. }
  646.  
  647.  
  648. static void
  649. compile_instruction(
  650.    struct gl_context *ctx,
  651.    struct st_translate *t,
  652.    const struct prog_instruction *inst,
  653.    boolean clamp_dst_color_output)
  654. {
  655.    struct ureg_program *ureg = t->ureg;
  656.    GLuint i;
  657.    struct ureg_dst dst[1] = { { 0 } };
  658.    struct ureg_src src[4];
  659.    unsigned num_dst;
  660.    unsigned num_src;
  661.  
  662.    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
  663.    num_src = _mesa_num_inst_src_regs( inst->Opcode );
  664.  
  665.    if (num_dst)
  666.       dst[0] = translate_dst( t,
  667.                               &inst->DstReg,
  668.                               inst->SaturateMode,
  669.                               clamp_dst_color_output);
  670.  
  671.    for (i = 0; i < num_src; i++)
  672.       src[i] = translate_src( t, &inst->SrcReg[i] );
  673.  
  674.    switch( inst->Opcode ) {
  675.    case OPCODE_SWZ:
  676.       emit_swz( t, dst[0], &inst->SrcReg[0] );
  677.       return;
  678.  
  679.    case OPCODE_BGNLOOP:
  680.    case OPCODE_CAL:
  681.    case OPCODE_ELSE:
  682.    case OPCODE_ENDLOOP:
  683.       debug_assert(num_dst == 0);
  684.       ureg_label_insn( ureg,
  685.                        translate_opcode( inst->Opcode ),
  686.                        src, num_src,
  687.                        get_label( t, inst->BranchTarget ));
  688.       return;
  689.  
  690.    case OPCODE_IF:
  691.       debug_assert(num_dst == 0);
  692.       ureg_label_insn( ureg,
  693.                        ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF,
  694.                        src, num_src,
  695.                        get_label( t, inst->BranchTarget ));
  696.       return;
  697.  
  698.    case OPCODE_TEX:
  699.    case OPCODE_TXB:
  700.    case OPCODE_TXD:
  701.    case OPCODE_TXL:
  702.    case OPCODE_TXP:
  703.       src[num_src++] = t->samplers[inst->TexSrcUnit];
  704.       ureg_tex_insn( ureg,
  705.                      translate_opcode( inst->Opcode ),
  706.                      dst, num_dst,
  707.                      st_translate_texture_target( inst->TexSrcTarget,
  708.                                                inst->TexShadow ),
  709.                      NULL, 0,
  710.                      src, num_src );
  711.       return;
  712.  
  713.    case OPCODE_SCS:
  714.       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
  715.       ureg_insn( ureg,
  716.                  translate_opcode( inst->Opcode ),
  717.                  dst, num_dst,
  718.                  src, num_src );
  719.       break;
  720.  
  721.    case OPCODE_XPD:
  722.       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
  723.       ureg_insn( ureg,
  724.                  translate_opcode( inst->Opcode ),
  725.                  dst, num_dst,
  726.                  src, num_src );
  727.       break;
  728.  
  729.    case OPCODE_NOISE1:
  730.    case OPCODE_NOISE2:
  731.    case OPCODE_NOISE3:
  732.    case OPCODE_NOISE4:
  733.       /* At some point, a motivated person could add a better
  734.        * implementation of noise.  Currently not even the nvidia
  735.        * binary drivers do anything more than this.  In any case, the
  736.        * place to do this is in the GL state tracker, not the poor
  737.        * driver.
  738.        */
  739.       ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
  740.       break;
  741.                  
  742.    case OPCODE_DDY:
  743.       emit_ddy( t, dst[0], &inst->SrcReg[0] );
  744.       break;
  745.  
  746.    case OPCODE_RSQ:
  747.       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
  748.       break;
  749.  
  750.    default:
  751.       ureg_insn( ureg,
  752.                  translate_opcode( inst->Opcode ),
  753.                  dst, num_dst,
  754.                  src, num_src );
  755.       break;
  756.    }
  757. }
  758.  
  759.  
  760. /**
  761.  * Emit the TGSI instructions for inverting and adjusting WPOS.
  762.  * This code is unavoidable because it also depends on whether
  763.  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
  764.  */
  765. static void
  766. emit_wpos_adjustment( struct st_translate *t,
  767.                       const struct gl_program *program,
  768.                       boolean invert,
  769.                       GLfloat adjX, GLfloat adjY[2])
  770. {
  771.    struct ureg_program *ureg = t->ureg;
  772.  
  773.    /* Fragment program uses fragment position input.
  774.     * Need to replace instances of INPUT[WPOS] with temp T
  775.     * where T = INPUT[WPOS] by y is inverted.
  776.     */
  777.    static const gl_state_index wposTransformState[STATE_LENGTH]
  778.       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
  779.    
  780.    /* XXX: note we are modifying the incoming shader here!  Need to
  781.     * do this before emitting the constant decls below, or this
  782.     * will be missed:
  783.     */
  784.    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
  785.                                                        wposTransformState);
  786.  
  787.    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
  788.    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
  789.    struct ureg_src wpos_input = t->inputs[t->inputMapping[VARYING_SLOT_POS]];
  790.  
  791.    /* First, apply the coordinate shift: */
  792.    if (adjX || adjY[0] || adjY[1]) {
  793.       if (adjY[0] != adjY[1]) {
  794.          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
  795.           * depending on whether inversion is actually going to be applied
  796.           * or not, which is determined by testing against the inversion
  797.           * state variable used below, which will be either +1 or -1.
  798.           */
  799.          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
  800.  
  801.          ureg_CMP(ureg, adj_temp,
  802.                   ureg_scalar(wpostrans, invert ? 2 : 0),
  803.                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
  804.                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
  805.          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
  806.       } else {
  807.          ureg_ADD(ureg, wpos_temp, wpos_input,
  808.                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
  809.       }
  810.       wpos_input = ureg_src(wpos_temp);
  811.    } else {
  812.       /* MOV wpos_temp, input[wpos]
  813.        */
  814.       ureg_MOV( ureg, wpos_temp, wpos_input );
  815.    }
  816.  
  817.    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
  818.     * inversion/identity, or the other way around if we're drawing to an FBO.
  819.     */
  820.    if (invert) {
  821.       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
  822.        */
  823.       ureg_MAD( ureg,
  824.                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
  825.                 wpos_input,
  826.                 ureg_scalar(wpostrans, 0),
  827.                 ureg_scalar(wpostrans, 1));
  828.    } else {
  829.       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
  830.        */
  831.       ureg_MAD( ureg,
  832.                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
  833.                 wpos_input,
  834.                 ureg_scalar(wpostrans, 2),
  835.                 ureg_scalar(wpostrans, 3));
  836.    }
  837.  
  838.    /* Use wpos_temp as position input from here on:
  839.     */
  840.    t->inputs[t->inputMapping[VARYING_SLOT_POS]] = ureg_src(wpos_temp);
  841. }
  842.  
  843.  
  844. /**
  845.  * Emit fragment position/coordinate code.
  846.  */
  847. static void
  848. emit_wpos(struct st_context *st,
  849.           struct st_translate *t,
  850.           const struct gl_program *program,
  851.           struct ureg_program *ureg)
  852. {
  853.    const struct gl_fragment_program *fp =
  854.       (const struct gl_fragment_program *) program;
  855.    struct pipe_screen *pscreen = st->pipe->screen;
  856.    GLfloat adjX = 0.0f;
  857.    GLfloat adjY[2] = { 0.0f, 0.0f };
  858.    boolean invert = FALSE;
  859.  
  860.    /* Query the pixel center conventions supported by the pipe driver and set
  861.     * adjX, adjY to help out if it cannot handle the requested one internally.
  862.     *
  863.     * The bias of the y-coordinate depends on whether y-inversion takes place
  864.     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
  865.     * drawing to an FBO (causes additional inversion), and whether the the pipe
  866.     * driver origin and the requested origin differ (the latter condition is
  867.     * stored in the 'invert' variable).
  868.     *
  869.     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
  870.     *
  871.     * center shift only:
  872.     * i -> h: +0.5
  873.     * h -> i: -0.5
  874.     *
  875.     * inversion only:
  876.     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
  877.     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
  878.     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
  879.     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
  880.     *
  881.     * inversion and center shift:
  882.     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
  883.     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
  884.     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
  885.     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
  886.     */
  887.    if (fp->OriginUpperLeft) {
  888.       /* Fragment shader wants origin in upper-left */
  889.       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
  890.          /* the driver supports upper-left origin */
  891.       }
  892.       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
  893.          /* the driver supports lower-left origin, need to invert Y */
  894.          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
  895.                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
  896.          invert = TRUE;
  897.       }
  898.       else
  899.          assert(0);
  900.    }
  901.    else {
  902.       /* Fragment shader wants origin in lower-left */
  903.       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
  904.          /* the driver supports lower-left origin */
  905.          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
  906.                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
  907.       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
  908.          /* the driver supports upper-left origin, need to invert Y */
  909.          invert = TRUE;
  910.       else
  911.          assert(0);
  912.    }
  913.    
  914.    if (fp->PixelCenterInteger) {
  915.       /* Fragment shader wants pixel center integer */
  916.       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
  917.          /* the driver supports pixel center integer */
  918.          adjY[1] = 1.0f;
  919.          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
  920.                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
  921.       }
  922.       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
  923.          /* the driver supports pixel center half integer, need to bias X,Y */
  924.          adjX = -0.5f;
  925.          adjY[0] = -0.5f;
  926.          adjY[1] = 0.5f;
  927.       }
  928.       else
  929.          assert(0);
  930.    }
  931.    else {
  932.       /* Fragment shader wants pixel center half integer */
  933.       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
  934.          /* the driver supports pixel center half integer */
  935.       }
  936.       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
  937.          /* the driver supports pixel center integer, need to bias X,Y */
  938.          adjX = adjY[0] = adjY[1] = 0.5f;
  939.          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
  940.                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
  941.       }
  942.       else
  943.          assert(0);
  944.    }
  945.  
  946.    /* we invert after adjustment so that we avoid the MOV to temporary,
  947.     * and reuse the adjustment ADD instead */
  948.    emit_wpos_adjustment(t, program, invert, adjX, adjY);
  949. }
  950.  
  951.  
  952. /**
  953.  * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
  954.  * TGSI uses +1 for front, -1 for back.
  955.  * This function converts the TGSI value to the GL value.  Simply clamping/
  956.  * saturating the value to [0,1] does the job.
  957.  */
  958. static void
  959. emit_face_var( struct st_translate *t,
  960.                const struct gl_program *program )
  961. {
  962.    struct ureg_program *ureg = t->ureg;
  963.    struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
  964.    struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
  965.  
  966.    /* MOV_SAT face_temp, input[face]
  967.     */
  968.    face_temp = ureg_saturate( face_temp );
  969.    ureg_MOV( ureg, face_temp, face_input );
  970.  
  971.    /* Use face_temp as face input from here on:
  972.     */
  973.    t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
  974. }
  975.  
  976.  
  977. static void
  978. emit_edgeflags( struct st_translate *t,
  979.                  const struct gl_program *program )
  980. {
  981.    struct ureg_program *ureg = t->ureg;
  982.    struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]];
  983.    struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
  984.  
  985.    ureg_MOV( ureg, edge_dst, edge_src );
  986. }
  987.  
  988.  
  989. /**
  990.  * Translate Mesa program to TGSI format.
  991.  * \param program  the program to translate
  992.  * \param numInputs  number of input registers used
  993.  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
  994.  *                      input indexes
  995.  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
  996.  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
  997.  *                            each input
  998.  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
  999.  * \param numOutputs  number of output registers used
  1000.  * \param outputMapping  maps Mesa fragment program outputs to TGSI
  1001.  *                       generic outputs
  1002.  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
  1003.  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
  1004.  *                             each output
  1005.  *
  1006.  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
  1007.  */
  1008. enum pipe_error
  1009. st_translate_mesa_program(
  1010.    struct gl_context *ctx,
  1011.    uint procType,
  1012.    struct ureg_program *ureg,
  1013.    const struct gl_program *program,
  1014.    GLuint numInputs,
  1015.    const GLuint inputMapping[],
  1016.    const ubyte inputSemanticName[],
  1017.    const ubyte inputSemanticIndex[],
  1018.    const GLuint interpMode[],
  1019.    GLuint numOutputs,
  1020.    const GLuint outputMapping[],
  1021.    const ubyte outputSemanticName[],
  1022.    const ubyte outputSemanticIndex[],
  1023.    boolean passthrough_edgeflags,
  1024.    boolean clamp_color)
  1025. {
  1026.    struct st_translate translate, *t;
  1027.    unsigned i;
  1028.    enum pipe_error ret = PIPE_OK;
  1029.  
  1030.    assert(numInputs <= ARRAY_SIZE(t->inputs));
  1031.    assert(numOutputs <= ARRAY_SIZE(t->outputs));
  1032.  
  1033.    t = &translate;
  1034.    memset(t, 0, sizeof *t);
  1035.  
  1036.    t->procType = procType;
  1037.    t->inputMapping = inputMapping;
  1038.    t->outputMapping = outputMapping;
  1039.    t->ureg = ureg;
  1040.  
  1041.    /*_mesa_print_program(program);*/
  1042.  
  1043.    /*
  1044.     * Declare input attributes.
  1045.     */
  1046.    if (procType == TGSI_PROCESSOR_FRAGMENT) {
  1047.       for (i = 0; i < numInputs; i++) {
  1048.          t->inputs[i] = ureg_DECL_fs_input(ureg,
  1049.                                            inputSemanticName[i],
  1050.                                            inputSemanticIndex[i],
  1051.                                            interpMode[i]);
  1052.       }
  1053.  
  1054.       if (program->InputsRead & VARYING_BIT_POS) {
  1055.          /* Must do this after setting up t->inputs, and before
  1056.           * emitting constant references, below:
  1057.           */
  1058.          emit_wpos(st_context(ctx), t, program, ureg);
  1059.       }
  1060.  
  1061.       if (program->InputsRead & VARYING_BIT_FACE) {
  1062.          emit_face_var( t, program );
  1063.       }
  1064.  
  1065.       /*
  1066.        * Declare output attributes.
  1067.        */
  1068.       for (i = 0; i < numOutputs; i++) {
  1069.          switch (outputSemanticName[i]) {
  1070.          case TGSI_SEMANTIC_POSITION:
  1071.             t->outputs[i] = ureg_DECL_output( ureg,
  1072.                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
  1073.                                               outputSemanticIndex[i] );
  1074.  
  1075.             t->outputs[i] = ureg_writemask( t->outputs[i],
  1076.                                             TGSI_WRITEMASK_Z );
  1077.             break;
  1078.          case TGSI_SEMANTIC_STENCIL:
  1079.             t->outputs[i] = ureg_DECL_output( ureg,
  1080.                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
  1081.                                               outputSemanticIndex[i] );
  1082.             t->outputs[i] = ureg_writemask( t->outputs[i],
  1083.                                             TGSI_WRITEMASK_Y );
  1084.             break;
  1085.          case TGSI_SEMANTIC_COLOR:
  1086.             t->outputs[i] = ureg_DECL_output( ureg,
  1087.                                               TGSI_SEMANTIC_COLOR,
  1088.                                               outputSemanticIndex[i] );
  1089.             break;
  1090.          default:
  1091.             debug_assert(0);
  1092.             return 0;
  1093.          }
  1094.       }
  1095.    }
  1096.    else if (procType == TGSI_PROCESSOR_GEOMETRY) {
  1097.       for (i = 0; i < numInputs; i++) {
  1098.          t->inputs[i] = ureg_DECL_gs_input(ureg,
  1099.                                            i,
  1100.                                            inputSemanticName[i],
  1101.                                            inputSemanticIndex[i]);
  1102.       }
  1103.  
  1104.       for (i = 0; i < numOutputs; i++) {
  1105.          t->outputs[i] = ureg_DECL_output( ureg,
  1106.                                            outputSemanticName[i],
  1107.                                            outputSemanticIndex[i] );
  1108.       }
  1109.    }
  1110.    else {
  1111.       assert(procType == TGSI_PROCESSOR_VERTEX);
  1112.  
  1113.       for (i = 0; i < numInputs; i++) {
  1114.          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
  1115.       }
  1116.  
  1117.       for (i = 0; i < numOutputs; i++) {
  1118.          t->outputs[i] = ureg_DECL_output( ureg,
  1119.                                            outputSemanticName[i],
  1120.                                            outputSemanticIndex[i] );
  1121.          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
  1122.             /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
  1123.             ureg_MOV(ureg,
  1124.                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
  1125.                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
  1126.             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
  1127.          }
  1128.       }
  1129.       if (passthrough_edgeflags)
  1130.          emit_edgeflags( t, program );
  1131.    }
  1132.  
  1133.    /* Declare address register.
  1134.     */
  1135.    if (program->NumAddressRegs > 0) {
  1136.       debug_assert( program->NumAddressRegs == 1 );
  1137.       t->address[0] = ureg_DECL_address( ureg );
  1138.    }
  1139.  
  1140.    /* Declare misc input registers
  1141.     */
  1142.    {
  1143.       GLbitfield sysInputs = program->SystemValuesRead;
  1144.       unsigned numSys = 0;
  1145.       for (i = 0; sysInputs; i++) {
  1146.          if (sysInputs & (1 << i)) {
  1147.             unsigned semName = _mesa_sysval_to_semantic[i];
  1148.             t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
  1149.             if (semName == TGSI_SEMANTIC_INSTANCEID ||
  1150.                 semName == TGSI_SEMANTIC_VERTEXID) {
  1151.                /* From Gallium perspective, these system values are always
  1152.                 * integer, and require native integer support.  However, if
  1153.                 * native integer is supported on the vertex stage but not the
  1154.                 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
  1155.                 * assumes these system values are floats. To resolve the
  1156.                 * inconsistency, we insert a U2F.
  1157.                 */
  1158.                struct st_context *st = st_context(ctx);
  1159.                struct pipe_screen *pscreen = st->pipe->screen;
  1160.                assert(procType == TGSI_PROCESSOR_VERTEX);
  1161.                assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
  1162.                (void) pscreen;  /* silence non-debug build warnings */
  1163.                if (!ctx->Const.NativeIntegers) {
  1164.                   struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
  1165.                   ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
  1166.                   t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
  1167.                }
  1168.             }
  1169.             numSys++;
  1170.             sysInputs &= ~(1 << i);
  1171.          }
  1172.       }
  1173.    }
  1174.  
  1175.    if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
  1176.       /* If temps are accessed with indirect addressing, declare temporaries
  1177.        * in sequential order.  Else, we declare them on demand elsewhere.
  1178.        */
  1179.       for (i = 0; i < program->NumTemporaries; i++) {
  1180.          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
  1181.          t->temps[i] = ureg_DECL_temporary( t->ureg );
  1182.       }
  1183.    }
  1184.  
  1185.    /* Emit constants and immediates.  Mesa uses a single index space
  1186.     * for these, so we put all the translated regs in t->constants.
  1187.     */
  1188.    if (program->Parameters) {
  1189.       t->constants = calloc( program->Parameters->NumParameters,
  1190.                              sizeof t->constants[0] );
  1191.       if (t->constants == NULL) {
  1192.          ret = PIPE_ERROR_OUT_OF_MEMORY;
  1193.          goto out;
  1194.       }
  1195.  
  1196.       for (i = 0; i < program->Parameters->NumParameters; i++) {
  1197.          switch (program->Parameters->Parameters[i].Type) {
  1198.          case PROGRAM_STATE_VAR:
  1199.          case PROGRAM_UNIFORM:
  1200.             t->constants[i] = ureg_DECL_constant( ureg, i );
  1201.             break;
  1202.  
  1203.             /* Emit immediates only when there's no indirect addressing of
  1204.              * the const buffer.
  1205.              * FIXME: Be smarter and recognize param arrays:
  1206.              * indirect addressing is only valid within the referenced
  1207.              * array.
  1208.              */
  1209.          case PROGRAM_CONSTANT:
  1210.             if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
  1211.                t->constants[i] = ureg_DECL_constant( ureg, i );
  1212.             else
  1213.                t->constants[i] =
  1214.                   ureg_DECL_immediate( ureg,
  1215.                                        (const float*) program->Parameters->ParameterValues[i],
  1216.                                        4 );
  1217.             break;
  1218.          default:
  1219.             break;
  1220.          }
  1221.       }
  1222.    }
  1223.  
  1224.    /* texture samplers */
  1225.    for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
  1226.       if (program->SamplersUsed & (1 << i)) {
  1227.          t->samplers[i] = ureg_DECL_sampler( ureg, i );
  1228.       }
  1229.    }
  1230.  
  1231.    /* Emit each instruction in turn:
  1232.     */
  1233.    for (i = 0; i < program->NumInstructions; i++) {
  1234.       set_insn_start( t, ureg_get_instruction_number( ureg ));
  1235.       compile_instruction( ctx, t, &program->Instructions[i], clamp_color );
  1236.    }
  1237.  
  1238.    /* Fix up all emitted labels:
  1239.     */
  1240.    for (i = 0; i < t->labels_count; i++) {
  1241.       ureg_fixup_label( ureg,
  1242.                         t->labels[i].token,
  1243.                         t->insn[t->labels[i].branch_target] );
  1244.    }
  1245.  
  1246. out:
  1247.    free(t->insn);
  1248.    free(t->labels);
  1249.    free(t->constants);
  1250.  
  1251.    if (t->error) {
  1252.       debug_printf("%s: translate error flag set\n", __func__);
  1253.    }
  1254.  
  1255.    return ret;
  1256. }
  1257.