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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Zhao Yakui <yakui.zhao@intel.com>
  26.  *    Xiang Haihao <haihao.xiang@intel.com>
  27.  *
  28.  */
  29.  
  30. #include <stdio.h>
  31. #include <stdlib.h>
  32. #include <string.h>
  33. #include <math.h>
  34. #include <assert.h>
  35.  
  36. #include "intel_batchbuffer.h"
  37. #include "i965_defines.h"
  38. #include "i965_structs.h"
  39. #include "i965_drv_video.h"
  40. #include "i965_encoder.h"
  41. #include "i965_encoder_utils.h"
  42. #include "gen6_mfc.h"
  43. #include "gen6_vme.h"
  44. #include "intel_media.h"
  45.  
  46. #define SURFACE_STATE_PADDED_SIZE               SURFACE_STATE_PADDED_SIZE_GEN8
  47. #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  48. #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  49.  
  50. #define MFC_SOFTWARE_HASWELL    1
  51.  
  52. #define B0_STEP_REV             2
  53. #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
  54.  
  55. static const uint32_t gen9_mfc_batchbuffer_avc_intra[][4] = {
  56. #include "shaders/utils/mfc_batchbuffer_avc_intra.g9b"
  57. };
  58.  
  59. static const uint32_t gen9_mfc_batchbuffer_avc_inter[][4] = {
  60. #include "shaders/utils/mfc_batchbuffer_avc_inter.g9b"
  61. };
  62.  
  63. static struct i965_kernel gen9_mfc_kernels[] = {
  64.     {
  65.         "MFC AVC INTRA BATCHBUFFER ",
  66.         MFC_BATCHBUFFER_AVC_INTRA,
  67.         gen9_mfc_batchbuffer_avc_intra,
  68.         sizeof(gen9_mfc_batchbuffer_avc_intra),
  69.         NULL
  70.     },
  71.  
  72.     {
  73.         "MFC AVC INTER BATCHBUFFER ",
  74.         MFC_BATCHBUFFER_AVC_INTER,
  75.         gen9_mfc_batchbuffer_avc_inter,
  76.         sizeof(gen9_mfc_batchbuffer_avc_inter),
  77.         NULL
  78.     },
  79. };
  80.  
  81. #define         INTER_MODE_MASK         0x03
  82. #define         INTER_8X8               0x03
  83. #define         INTER_16X8              0x01
  84. #define         INTER_8X16              0x02
  85. #define         SUBMB_SHAPE_MASK        0x00FF00
  86. #define         INTER_16X16             0x00
  87.  
  88. #define         INTER_MV8               (4 << 20)
  89. #define         INTER_MV32              (6 << 20)
  90.  
  91. static void
  92. gen9_mfc_pipe_mode_select(VADriverContextP ctx,
  93.                           int standard_select,
  94.                           struct intel_encoder_context *encoder_context)
  95. {
  96.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  97.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  98.  
  99.     assert(standard_select == MFX_FORMAT_MPEG2 ||
  100.            standard_select == MFX_FORMAT_AVC  ||
  101.            standard_select == MFX_FORMAT_VP8);
  102.  
  103.     BEGIN_BCS_BATCH(batch, 5);
  104.  
  105.     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
  106.     OUT_BCS_BATCH(batch,
  107.                   (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
  108.                   (MFD_MODE_VLD << 15) | /* VLD mode */
  109.                   (0 << 10) | /* Stream-Out Enable */
  110.                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  111.                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  112.                   (0 << 6)  | /* frame statistics stream-out enable*/
  113.                   (0 << 5)  | /* not in stitch mode */
  114.                   (1 << 4)  | /* encoding mode */
  115.                   (standard_select << 0));  /* standard select: avc or mpeg2 */
  116.     OUT_BCS_BATCH(batch,
  117.                   (0 << 7)  | /* expand NOA bus flag */
  118.                   (0 << 6)  | /* disable slice-level clock gating */
  119.                   (0 << 5)  | /* disable clock gating for NOA */
  120.                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  121.                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
  122.                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
  123.                   (0 << 1)  |
  124.                   (0 << 0));
  125.     OUT_BCS_BATCH(batch, 0);
  126.     OUT_BCS_BATCH(batch, 0);
  127.  
  128.     ADVANCE_BCS_BATCH(batch);
  129. }
  130.  
  131. static void
  132. gen9_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  133. {
  134.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  135.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  136.  
  137.     BEGIN_BCS_BATCH(batch, 6);
  138.  
  139.     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
  140.     OUT_BCS_BATCH(batch, 0);
  141.     OUT_BCS_BATCH(batch,
  142.                   ((mfc_context->surface_state.height - 1) << 18) |
  143.                   ((mfc_context->surface_state.width - 1) << 4));
  144.     OUT_BCS_BATCH(batch,
  145.                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
  146.                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
  147.                   (0 << 22) | /* surface object control state, FIXME??? */
  148.                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
  149.                   (0 << 2)  | /* must be 0 for interleave U/V */
  150.                   (1 << 1)  | /* must be tiled */
  151.                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, TILEWALK_YMAJOR */
  152.     OUT_BCS_BATCH(batch,
  153.                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
  154.                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
  155.     OUT_BCS_BATCH(batch, 0);
  156.  
  157.     ADVANCE_BCS_BATCH(batch);
  158. }
  159.  
  160. static void
  161. gen9_mfc_ind_obj_base_addr_state(VADriverContextP ctx,
  162.                                  struct intel_encoder_context *encoder_context)
  163. {
  164.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  165.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  166.     struct gen6_vme_context *vme_context = encoder_context->vme_context;
  167.     int vme_size;
  168.  
  169.     BEGIN_BCS_BATCH(batch, 26);
  170.  
  171.     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
  172.     /* the DW1-3 is for the MFX indirect bistream offset */
  173.     OUT_BCS_BATCH(batch, 0);
  174.     OUT_BCS_BATCH(batch, 0);
  175.     OUT_BCS_BATCH(batch, 0);
  176.  
  177.     vme_size = vme_context->vme_output.size_block * vme_context->vme_output.num_blocks;
  178.  
  179.     OUT_BCS_BATCH(batch, 0);
  180.     OUT_BCS_BATCH(batch, 0);
  181.  
  182.     /* the DW6-10 is for MFX Indirect MV Object Base Address */
  183.     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
  184.     OUT_BCS_BATCH(batch, 0);
  185.     OUT_BCS_BATCH(batch, 0);
  186.     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, vme_size);
  187.     OUT_BCS_BATCH(batch, 0);
  188.  
  189.     /* the DW11-15 is for MFX IT-COFF. Not used on encoder */
  190.     OUT_BCS_BATCH(batch, 0);
  191.     OUT_BCS_BATCH(batch, 0);
  192.     OUT_BCS_BATCH(batch, 0);
  193.     OUT_BCS_BATCH(batch, 0);
  194.     OUT_BCS_BATCH(batch, 0);
  195.  
  196.     /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */
  197.     OUT_BCS_BATCH(batch, 0);
  198.     OUT_BCS_BATCH(batch, 0);
  199.     OUT_BCS_BATCH(batch, 0);
  200.     OUT_BCS_BATCH(batch, 0);
  201.     OUT_BCS_BATCH(batch, 0);
  202.  
  203.     /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/
  204.     OUT_BCS_RELOC(batch,
  205.                   mfc_context->mfc_indirect_pak_bse_object.bo,
  206.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  207.                   0);
  208.     OUT_BCS_BATCH(batch, 0);
  209.     OUT_BCS_BATCH(batch, 0);
  210.  
  211.     OUT_BCS_RELOC(batch,
  212.                   mfc_context->mfc_indirect_pak_bse_object.bo,
  213.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  214.                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
  215.     OUT_BCS_BATCH(batch, 0);
  216.  
  217.     ADVANCE_BCS_BATCH(batch);
  218. }
  219.  
  220. static void
  221. gen9_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
  222.                        struct intel_encoder_context *encoder_context)
  223. {
  224.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  225.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  226.     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
  227.  
  228.     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
  229.     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
  230.  
  231.     BEGIN_BCS_BATCH(batch, 16);
  232.  
  233.     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
  234.     /*DW1. MB setting of frame */
  235.     OUT_BCS_BATCH(batch,
  236.                   ((width_in_mbs * height_in_mbs - 1) & 0xFFFF));
  237.     OUT_BCS_BATCH(batch,
  238.                   ((height_in_mbs - 1) << 16) |
  239.                   ((width_in_mbs - 1) << 0));
  240.     /* DW3 QP setting */
  241.     OUT_BCS_BATCH(batch,
  242.                   (0 << 24) |   /* Second Chroma QP Offset */
  243.                   (0 << 16) |   /* Chroma QP Offset */
  244.                   (0 << 14) |   /* Max-bit conformance Intra flag */
  245.                   (0 << 13) |   /* Max Macroblock size conformance Inter flag */
  246.                   (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) |   /*Weighted_Pred_Flag */
  247.                   (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) |  /* Weighted_BiPred_Idc */
  248.                   (0 << 8)  |   /* FIXME: Image Structure */
  249.                   (0 << 0) );   /* Current Decoed Image Frame Store ID, reserved in Encode mode */
  250.     OUT_BCS_BATCH(batch,
  251.                   (0 << 16) |   /* Mininum Frame size */
  252.                   (0 << 15) |   /* Disable reading of Macroblock Status Buffer */
  253.                   (0 << 14) |   /* Load BitStream Pointer only once, 1 slic 1 frame */
  254.                   (0 << 13) |   /* CABAC 0 word insertion test enable */
  255.                   (1 << 12) |   /* MVUnpackedEnable,compliant to DXVA */
  256.                   (1 << 10) |   /* Chroma Format IDC, 4:2:0 */
  257.                   (0 << 8)  |   /* FIXME: MbMvFormatFlag */
  258.                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
  259.                   (0 << 6)  |   /* Only valid for VLD decoding mode */
  260.                   (0 << 5)  |   /* Constrained Intra Predition Flag, from PPS */
  261.                   (0 << 4)  |   /* Direct 8x8 inference flag */
  262.                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
  263.                   (1 << 2)  |   /* Frame MB only flag */
  264.                   (0 << 1)  |   /* MBAFF mode is in active */
  265.                   (0 << 0));    /* Field picture flag */
  266.     /* DW5 Trellis quantization */
  267.     OUT_BCS_BATCH(batch, 0);    /* Mainly about MB rate control and debug, just ignoring */
  268.     OUT_BCS_BATCH(batch,        /* Inter and Intra Conformance Max size limit */
  269.                   (0xBB8 << 16) |       /* InterMbMaxSz */
  270.                   (0xEE8) );            /* IntraMbMaxSz */
  271.     OUT_BCS_BATCH(batch, 0);            /* Reserved */
  272.     /* DW8. QP delta */
  273.     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
  274.     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
  275.     /* DW10. Bit setting for MB */
  276.     OUT_BCS_BATCH(batch, 0x8C000000);
  277.     OUT_BCS_BATCH(batch, 0x00010000);
  278.     /* DW12. */
  279.     OUT_BCS_BATCH(batch, 0);
  280.     OUT_BCS_BATCH(batch, 0x02010100);
  281.     /* DW14. For short format */
  282.     OUT_BCS_BATCH(batch, 0);
  283.     OUT_BCS_BATCH(batch, 0);
  284.  
  285.     ADVANCE_BCS_BATCH(batch);
  286. }
  287.  
  288. static void
  289. gen9_mfc_qm_state(VADriverContextP ctx,
  290.                   int qm_type,
  291.                   unsigned int *qm,
  292.                   int qm_length,
  293.                   struct intel_encoder_context *encoder_context)
  294. {
  295.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  296.     unsigned int qm_buffer[16];
  297.  
  298.     assert(qm_length <= 16);
  299.     assert(sizeof(*qm) == 4);
  300.     memcpy(qm_buffer, qm, qm_length * 4);
  301.  
  302.     BEGIN_BCS_BATCH(batch, 18);
  303.     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
  304.     OUT_BCS_BATCH(batch, qm_type << 0);
  305.     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
  306.     ADVANCE_BCS_BATCH(batch);
  307. }
  308.  
  309. static void
  310. gen9_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  311. {
  312.     unsigned int qm[16] = {
  313.         0x10101010, 0x10101010, 0x10101010, 0x10101010,
  314.         0x10101010, 0x10101010, 0x10101010, 0x10101010,
  315.         0x10101010, 0x10101010, 0x10101010, 0x10101010,
  316.         0x10101010, 0x10101010, 0x10101010, 0x10101010
  317.     };
  318.  
  319.     gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
  320.     gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
  321.     gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
  322.     gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
  323. }
  324.  
  325. static void
  326. gen9_mfc_fqm_state(VADriverContextP ctx,
  327.                    int fqm_type,
  328.                    unsigned int *fqm,
  329.                    int fqm_length,
  330.                    struct intel_encoder_context *encoder_context)
  331. {
  332.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  333.     unsigned int fqm_buffer[32];
  334.  
  335.     assert(fqm_length <= 32);
  336.     assert(sizeof(*fqm) == 4);
  337.     memcpy(fqm_buffer, fqm, fqm_length * 4);
  338.  
  339.     BEGIN_BCS_BATCH(batch, 34);
  340.     OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
  341.     OUT_BCS_BATCH(batch, fqm_type << 0);
  342.     intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
  343.     ADVANCE_BCS_BATCH(batch);
  344. }
  345.  
  346. static void
  347. gen9_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  348. {
  349.     unsigned int qm[32] = {
  350.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  351.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  352.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  353.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  354.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  355.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  356.         0x10001000, 0x10001000, 0x10001000, 0x10001000,
  357.         0x10001000, 0x10001000, 0x10001000, 0x10001000
  358.     };
  359.  
  360.     gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
  361.     gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
  362.     gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
  363.     gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
  364. }
  365.  
  366. static void
  367. gen9_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
  368.                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
  369.                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
  370.                            struct intel_batchbuffer *batch)
  371. {
  372.     if (batch == NULL)
  373.         batch = encoder_context->base.batch;
  374.  
  375.     if (data_bits_in_last_dw == 0)
  376.         data_bits_in_last_dw = 32;
  377.  
  378.     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
  379.  
  380.     OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
  381.     OUT_BCS_BATCH(batch,
  382.                   (0 << 16) |   /* always start at offset 0 */
  383.                   (data_bits_in_last_dw << 8) |
  384.                   (skip_emul_byte_count << 4) |
  385.                   (!!emulation_flag << 3) |
  386.                   ((!!is_last_header) << 2) |
  387.                   ((!!is_end_of_slice) << 1) |
  388.                   (0 << 0));    /* FIXME: ??? */
  389.     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
  390.  
  391.     ADVANCE_BCS_BATCH(batch);
  392. }
  393.  
  394.  
  395. static void gen9_mfc_init(VADriverContextP ctx,
  396.                           struct encode_state *encode_state,
  397.                           struct intel_encoder_context *encoder_context)
  398. {
  399.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  400.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  401.     dri_bo *bo;
  402.     int i;
  403.     int width_in_mbs = 0;
  404.     int height_in_mbs = 0;
  405.     int slice_batchbuffer_size;
  406.  
  407.     if (encoder_context->codec == CODEC_H264 ||
  408.         encoder_context->codec == CODEC_H264_MVC) {
  409.         VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
  410.         width_in_mbs = pSequenceParameter->picture_width_in_mbs;
  411.         height_in_mbs = pSequenceParameter->picture_height_in_mbs;
  412.     } else {
  413.         VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
  414.  
  415.         assert(encoder_context->codec == CODEC_MPEG2);
  416.  
  417.         width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
  418.         height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
  419.     }
  420.  
  421.     slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 +
  422.                 (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext;
  423.  
  424.     /*Encode common setup for MFC*/
  425.     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
  426.     mfc_context->post_deblocking_output.bo = NULL;
  427.  
  428.     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
  429.     mfc_context->pre_deblocking_output.bo = NULL;
  430.  
  431.     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
  432.     mfc_context->uncompressed_picture_source.bo = NULL;
  433.  
  434.     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
  435.     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
  436.  
  437.     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
  438.         if (mfc_context->direct_mv_buffers[i].bo != NULL)
  439.             dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
  440.         mfc_context->direct_mv_buffers[i].bo = NULL;
  441.     }
  442.  
  443.     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
  444.         if (mfc_context->reference_surfaces[i].bo != NULL)
  445.             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
  446.         mfc_context->reference_surfaces[i].bo = NULL;
  447.     }
  448.  
  449.     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
  450.     bo = dri_bo_alloc(i965->intel.bufmgr,
  451.                       "Buffer",
  452.                       width_in_mbs * 64,
  453.                       64);
  454.     assert(bo);
  455.     mfc_context->intra_row_store_scratch_buffer.bo = bo;
  456.  
  457.     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
  458.     bo = dri_bo_alloc(i965->intel.bufmgr,
  459.                       "Buffer",
  460.                       width_in_mbs * height_in_mbs * 16,
  461.                       64);
  462.     assert(bo);
  463.     mfc_context->macroblock_status_buffer.bo = bo;
  464.  
  465.     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
  466.     bo = dri_bo_alloc(i965->intel.bufmgr,
  467.                       "Buffer",
  468.                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
  469.                       64);
  470.     assert(bo);
  471.     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
  472.  
  473.     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
  474.     bo = dri_bo_alloc(i965->intel.bufmgr,
  475.                       "Buffer",
  476.                       2 * width_in_mbs * 64, /* 2 * width_in_mbs * 64 */
  477.                       0x1000);
  478.     assert(bo);
  479.     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
  480.  
  481.     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
  482.     mfc_context->mfc_batchbuffer_surface.bo = NULL;
  483.  
  484.     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
  485.     mfc_context->aux_batchbuffer_surface.bo = NULL;
  486.  
  487.     if (mfc_context->aux_batchbuffer)
  488.         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
  489.  
  490.     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, slice_batchbuffer_size);
  491.     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
  492.     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
  493.     mfc_context->aux_batchbuffer_surface.pitch = 16;
  494.     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
  495.     mfc_context->aux_batchbuffer_surface.size_block = 16;
  496.  
  497.     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
  498. }
  499.  
  500. static void
  501. gen9_mfc_pipe_buf_addr_state(VADriverContextP ctx,
  502.                              struct intel_encoder_context *encoder_context)
  503. {
  504.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  505.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  506.     int i;
  507.  
  508.     BEGIN_BCS_BATCH(batch, 61);
  509.  
  510.     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
  511.  
  512.     /* the DW1-3 is for pre_deblocking */
  513.     if (mfc_context->pre_deblocking_output.bo)
  514.         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
  515.                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  516.                       0);
  517.     else
  518.         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
  519.  
  520.     OUT_BCS_BATCH(batch, 0);
  521.     OUT_BCS_BATCH(batch, 0);
  522.     /* the DW4-6 is for the post_deblocking */
  523.  
  524.     /* post output addr  */
  525.     if (mfc_context->post_deblocking_output.bo)
  526.         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
  527.                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  528.                       0);
  529.     else
  530.         OUT_BCS_BATCH(batch, 0);
  531.  
  532.     OUT_BCS_BATCH(batch, 0);
  533.     OUT_BCS_BATCH(batch, 0);
  534.  
  535.     /* the DW7-9 is for the uncompressed_picture */
  536.     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
  537.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  538.                   0); /* uncompressed data */
  539.  
  540.     OUT_BCS_BATCH(batch, 0);
  541.     OUT_BCS_BATCH(batch, 0);
  542.  
  543.     /* the DW10-12 is for the mb status */
  544.     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
  545.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  546.                   0); /* StreamOut data*/
  547.  
  548.     OUT_BCS_BATCH(batch, 0);
  549.     OUT_BCS_BATCH(batch, 0);
  550.  
  551.     /* the DW13-15 is for the intra_row_store_scratch */
  552.     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
  553.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  554.                   0);
  555.  
  556.     OUT_BCS_BATCH(batch, 0);
  557.     OUT_BCS_BATCH(batch, 0);
  558.  
  559.     /* the DW16-18 is for the deblocking filter */
  560.     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
  561.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  562.                   0);
  563.  
  564.     OUT_BCS_BATCH(batch, 0);
  565.     OUT_BCS_BATCH(batch, 0);
  566.  
  567.     /* the DW 19-50 is for Reference pictures*/
  568.     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
  569.         if ( mfc_context->reference_surfaces[i].bo != NULL) {
  570.             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
  571.                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  572.                           0);
  573.         } else {
  574.             OUT_BCS_BATCH(batch, 0);
  575.         }
  576.  
  577.         OUT_BCS_BATCH(batch, 0);
  578.     }
  579.  
  580.     OUT_BCS_BATCH(batch, 0);
  581.  
  582.     /* The DW 52-54 is for the MB status buffer */
  583.     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
  584.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  585.                   0);
  586.  
  587.     OUT_BCS_BATCH(batch, 0);
  588.     OUT_BCS_BATCH(batch, 0);
  589.  
  590.     /* the DW 55-57 is the ILDB buffer */
  591.     OUT_BCS_BATCH(batch, 0);
  592.     OUT_BCS_BATCH(batch, 0);
  593.     OUT_BCS_BATCH(batch, 0);
  594.  
  595.     /* the DW 58-60 is the second ILDB buffer */
  596.     OUT_BCS_BATCH(batch, 0);
  597.     OUT_BCS_BATCH(batch, 0);
  598.     OUT_BCS_BATCH(batch, 0);
  599.  
  600.     ADVANCE_BCS_BATCH(batch);
  601. }
  602.  
  603. static void
  604. gen9_mfc_avc_directmode_state(VADriverContextP ctx,
  605.                               struct intel_encoder_context *encoder_context)
  606. {
  607.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  608.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  609.  
  610.     int i;
  611.  
  612.     BEGIN_BCS_BATCH(batch, 71);
  613.  
  614.     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
  615.  
  616.     /* Reference frames and Current frames */
  617.     /* the DW1-32 is for the direct MV for reference */
  618.     for(i = 0; i < NUM_MFC_DMV_BUFFERS - 2; i += 2) {
  619.         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
  620.             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
  621.                           I915_GEM_DOMAIN_INSTRUCTION, 0,
  622.                           0);
  623.             OUT_BCS_BATCH(batch, 0);
  624.         } else {
  625.             OUT_BCS_BATCH(batch, 0);
  626.             OUT_BCS_BATCH(batch, 0);
  627.         }
  628.     }
  629.  
  630.     OUT_BCS_BATCH(batch, 0);
  631.  
  632.     /* the DW34-36 is the MV for the current reference */
  633.     OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo,
  634.                   I915_GEM_DOMAIN_INSTRUCTION, 0,
  635.                   0);
  636.  
  637.     OUT_BCS_BATCH(batch, 0);
  638.     OUT_BCS_BATCH(batch, 0);
  639.  
  640.     /* POL list */
  641.     for(i = 0; i < 32; i++) {
  642.         OUT_BCS_BATCH(batch, i/2);
  643.     }
  644.     OUT_BCS_BATCH(batch, 0);
  645.     OUT_BCS_BATCH(batch, 0);
  646.  
  647.     ADVANCE_BCS_BATCH(batch);
  648. }
  649.  
  650.  
  651. static void
  652. gen9_mfc_bsp_buf_base_addr_state(VADriverContextP ctx,
  653.                                  struct intel_encoder_context *encoder_context)
  654. {
  655.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  656.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  657.  
  658.     BEGIN_BCS_BATCH(batch, 10);
  659.  
  660.     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
  661.     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
  662.                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  663.                   0);
  664.     OUT_BCS_BATCH(batch, 0);
  665.     OUT_BCS_BATCH(batch, 0);
  666.  
  667.     /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */
  668.     OUT_BCS_BATCH(batch, 0);
  669.     OUT_BCS_BATCH(batch, 0);
  670.     OUT_BCS_BATCH(batch, 0);
  671.  
  672.     /* the DW7-9 is for Bitplane Read Buffer Base Address */
  673.     OUT_BCS_BATCH(batch, 0);
  674.     OUT_BCS_BATCH(batch, 0);
  675.     OUT_BCS_BATCH(batch, 0);
  676.  
  677.     ADVANCE_BCS_BATCH(batch);
  678. }
  679.  
  680.  
  681. static void gen9_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
  682.                                                       struct encode_state *encode_state,
  683.                                                       struct intel_encoder_context *encoder_context)
  684. {
  685.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  686.  
  687.     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
  688.     mfc_context->set_surface_state(ctx, encoder_context);
  689.     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
  690.     gen9_mfc_pipe_buf_addr_state(ctx, encoder_context);
  691.     gen9_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
  692.     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
  693.     mfc_context->avc_qm_state(ctx, encoder_context);
  694.     mfc_context->avc_fqm_state(ctx, encoder_context);
  695.     gen9_mfc_avc_directmode_state(ctx, encoder_context);
  696.     intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
  697. }
  698.  
  699.  
  700. static VAStatus gen9_mfc_run(VADriverContextP ctx,
  701.                              struct encode_state *encode_state,
  702.                              struct intel_encoder_context *encoder_context)
  703. {
  704.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  705.  
  706.     intel_batchbuffer_flush(batch);             //run the pipeline
  707.  
  708.     return VA_STATUS_SUCCESS;
  709. }
  710.  
  711.  
  712. static VAStatus
  713. gen9_mfc_stop(VADriverContextP ctx,
  714.               struct encode_state *encode_state,
  715.               struct intel_encoder_context *encoder_context,
  716.               int *encoded_bits_size)
  717. {
  718.     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
  719.     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
  720.     VACodedBufferSegment *coded_buffer_segment;
  721.  
  722.     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
  723.     assert(vaStatus == VA_STATUS_SUCCESS);
  724.     *encoded_bits_size = coded_buffer_segment->size * 8;
  725.     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
  726.  
  727.     return VA_STATUS_SUCCESS;
  728. }
  729.  
  730.  
  731. static void
  732. gen9_mfc_avc_slice_state(VADriverContextP ctx,
  733.                          VAEncPictureParameterBufferH264 *pic_param,
  734.                          VAEncSliceParameterBufferH264 *slice_param,
  735.                          struct encode_state *encode_state,
  736.                          struct intel_encoder_context *encoder_context,
  737.                          int rate_control_enable,
  738.                          int qp,
  739.                          struct intel_batchbuffer *batch)
  740. {
  741.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  742.     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
  743.     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
  744.     int beginmb = slice_param->macroblock_address;
  745.     int endmb = beginmb + slice_param->num_macroblocks;
  746.     int beginx = beginmb % width_in_mbs;
  747.     int beginy = beginmb / width_in_mbs;
  748.     int nextx =  endmb % width_in_mbs;
  749.     int nexty = endmb / width_in_mbs;
  750.     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
  751.     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
  752.     int maxQpN, maxQpP;
  753.     unsigned char correct[6], grow, shrink;
  754.     int i;
  755.     int weighted_pred_idc = 0;
  756.     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
  757.     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
  758.     int num_ref_l0 = 0, num_ref_l1 = 0;
  759.  
  760.     if (batch == NULL)
  761.         batch = encoder_context->base.batch;
  762.  
  763.     if (slice_type == SLICE_TYPE_I) {
  764.         luma_log2_weight_denom = 0;
  765.         chroma_log2_weight_denom = 0;
  766.     } else if (slice_type == SLICE_TYPE_P) {
  767.         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
  768.         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
  769.  
  770.         if (slice_param->num_ref_idx_active_override_flag)
  771.             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
  772.     } else if (slice_type == SLICE_TYPE_B) {
  773.         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
  774.         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
  775.         num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
  776.  
  777.         if (slice_param->num_ref_idx_active_override_flag) {
  778.             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
  779.             num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
  780.         }
  781.  
  782.         if (weighted_pred_idc == 2) {
  783.             /* 8.4.3 - Derivation process for prediction weights (8-279) */
  784.             luma_log2_weight_denom = 5;
  785.             chroma_log2_weight_denom = 5;
  786.         }
  787.     }
  788.  
  789.     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
  790.     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
  791.  
  792.     for (i = 0; i < 6; i++)
  793.         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
  794.  
  795.     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
  796.         (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
  797.     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
  798.         (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
  799.  
  800.     BEGIN_BCS_BATCH(batch, 11);;
  801.  
  802.     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
  803.     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
  804.  
  805.     OUT_BCS_BATCH(batch,
  806.                   (num_ref_l0 << 16) |
  807.                   (num_ref_l1 << 24) |
  808.                   (chroma_log2_weight_denom << 8) |
  809.                   (luma_log2_weight_denom << 0));
  810.  
  811.     OUT_BCS_BATCH(batch,
  812.                   (weighted_pred_idc << 30) |
  813.                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
  814.                   (slice_param->disable_deblocking_filter_idc << 27) |
  815.                   (slice_param->cabac_init_idc << 24) |
  816.                   (qp<<16) |                    /*Slice Quantization Parameter*/
  817.                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
  818.                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
  819.     OUT_BCS_BATCH(batch,
  820.                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
  821.                   (beginx << 16) |
  822.                   slice_param->macroblock_address );
  823.     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
  824.     OUT_BCS_BATCH(batch,
  825.                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
  826.                   (1 << 30) |           /*ResetRateControlCounter*/
  827.                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
  828.                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
  829.                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
  830.                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
  831.                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
  832.                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
  833.                   (last_slice << 19) |     /*IsLastSlice*/
  834.                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
  835.                   (1 << 17) |       /*HeaderPresentFlag*/
  836.                   (1 << 16) |       /*SliceData PresentFlag*/
  837.                   (1 << 15) |       /*TailPresentFlag*/
  838.                   (1 << 13) |       /*RBSP NAL TYPE*/
  839.                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
  840.     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
  841.     OUT_BCS_BATCH(batch,
  842.                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
  843.                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
  844.                   (shrink << 8)  |
  845.                   (grow << 0));
  846.     OUT_BCS_BATCH(batch,
  847.                   (correct[5] << 20) |
  848.                   (correct[4] << 16) |
  849.                   (correct[3] << 12) |
  850.                   (correct[2] << 8) |
  851.                   (correct[1] << 4) |
  852.                   (correct[0] << 0));
  853.     OUT_BCS_BATCH(batch, 0);
  854.  
  855.     ADVANCE_BCS_BATCH(batch);
  856. }
  857.  
  858.  
  859. #ifdef MFC_SOFTWARE_HASWELL
  860.  
  861. static int
  862. gen9_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
  863.                               int qp,unsigned int *msg,
  864.                               struct intel_encoder_context *encoder_context,
  865.                               unsigned char target_mb_size, unsigned char max_mb_size,
  866.                               struct intel_batchbuffer *batch)
  867. {
  868.     int len_in_dwords = 12;
  869.     unsigned int intra_msg;
  870. #define         INTRA_MSG_FLAG          (1 << 13)
  871. #define         INTRA_MBTYPE_MASK       (0x1F0000)
  872.     if (batch == NULL)
  873.         batch = encoder_context->base.batch;
  874.  
  875.     BEGIN_BCS_BATCH(batch, len_in_dwords);
  876.  
  877.     intra_msg = msg[0] & 0xC0FF;
  878.     intra_msg |= INTRA_MSG_FLAG;
  879.     intra_msg |= ((msg[0] & INTRA_MBTYPE_MASK) >> 8);
  880.     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
  881.     OUT_BCS_BATCH(batch, 0);
  882.     OUT_BCS_BATCH(batch, 0);
  883.     OUT_BCS_BATCH(batch,
  884.                   (0 << 24) |           /* PackedMvNum, Debug*/
  885.                   (0 << 20) |           /* No motion vector */
  886.                   (1 << 19) |           /* CbpDcY */
  887.                   (1 << 18) |           /* CbpDcU */
  888.                   (1 << 17) |           /* CbpDcV */
  889.                   intra_msg);
  890.  
  891.     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
  892.     OUT_BCS_BATCH(batch, 0x000F000F);     /* Code Block Pattern */
  893.  
  894.     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
  895.  
  896.     /*Stuff for Intra MB*/
  897.     OUT_BCS_BATCH(batch, msg[1]);       /* We using Intra16x16 no 4x4 predmode*/
  898.     OUT_BCS_BATCH(batch, msg[2]);
  899.     OUT_BCS_BATCH(batch, msg[3]&0xFF);
  900.  
  901.     /*MaxSizeInWord and TargetSzieInWord*/
  902.     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
  903.                   (target_mb_size << 16) );
  904.  
  905.     OUT_BCS_BATCH(batch, 0);
  906.  
  907.     ADVANCE_BCS_BATCH(batch);
  908.  
  909.     return len_in_dwords;
  910. }
  911.  
  912. static int
  913. gen9_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
  914.                               unsigned int *msg, unsigned int offset,
  915.                               struct intel_encoder_context *encoder_context,
  916.                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
  917.                               struct intel_batchbuffer *batch)
  918. {
  919.     struct gen6_vme_context *vme_context = encoder_context->vme_context;
  920.     int len_in_dwords = 12;
  921.     unsigned int inter_msg = 0;
  922.     if (batch == NULL)
  923.         batch = encoder_context->base.batch;
  924.     {
  925. #define MSG_MV_OFFSET   4
  926.         unsigned int *mv_ptr;
  927.         mv_ptr = msg + MSG_MV_OFFSET;
  928.         /* MV of VME output is based on 16 sub-blocks. So it is necessary
  929.          * to convert them to be compatible with the format of AVC_PAK
  930.          * command.
  931.          */
  932.         if ((msg[0] & INTER_MODE_MASK) == INTER_8X16) {
  933.             /* MV[0] and MV[2] are replicated */
  934.             mv_ptr[4] = mv_ptr[0];
  935.             mv_ptr[5] = mv_ptr[1];
  936.             mv_ptr[2] = mv_ptr[8];
  937.             mv_ptr[3] = mv_ptr[9];
  938.             mv_ptr[6] = mv_ptr[8];
  939.             mv_ptr[7] = mv_ptr[9];
  940.         } else if ((msg[0] & INTER_MODE_MASK) == INTER_16X8) {
  941.             /* MV[0] and MV[1] are replicated */
  942.             mv_ptr[2] = mv_ptr[0];
  943.             mv_ptr[3] = mv_ptr[1];
  944.             mv_ptr[4] = mv_ptr[16];
  945.             mv_ptr[5] = mv_ptr[17];
  946.             mv_ptr[6] = mv_ptr[24];
  947.             mv_ptr[7] = mv_ptr[25];
  948.         } else if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
  949.                    !(msg[1] & SUBMB_SHAPE_MASK)) {
  950.             /* Don't touch MV[0] or MV[1] */
  951.             mv_ptr[2] = mv_ptr[8];
  952.             mv_ptr[3] = mv_ptr[9];
  953.             mv_ptr[4] = mv_ptr[16];
  954.             mv_ptr[5] = mv_ptr[17];
  955.             mv_ptr[6] = mv_ptr[24];
  956.             mv_ptr[7] = mv_ptr[25];
  957.         }
  958.     }
  959.  
  960.     BEGIN_BCS_BATCH(batch, len_in_dwords);
  961.  
  962.     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
  963.  
  964.     inter_msg = 32;
  965.     /* MV quantity */
  966.     if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) {
  967.         if (msg[1] & SUBMB_SHAPE_MASK)
  968.             inter_msg = 128;
  969.     }
  970.     OUT_BCS_BATCH(batch, inter_msg);         /* 32 MV*/
  971.     OUT_BCS_BATCH(batch, offset);
  972.     inter_msg = msg[0] & (0x1F00FFFF);
  973.     inter_msg |= INTER_MV8;
  974.     inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17));
  975.     if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
  976.         (msg[1] & SUBMB_SHAPE_MASK)) {
  977.         inter_msg |= INTER_MV32;
  978.     }
  979.  
  980.     OUT_BCS_BATCH(batch, inter_msg);
  981.  
  982.     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
  983.     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
  984. #if 0
  985.     if ( slice_type == SLICE_TYPE_B) {
  986.         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
  987.     } else {
  988.         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
  989.     }
  990. #else
  991.     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
  992. #endif
  993.  
  994.     inter_msg = msg[1] >> 8;
  995.     /*Stuff for Inter MB*/
  996.     OUT_BCS_BATCH(batch, inter_msg);
  997.     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
  998.     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
  999.  
  1000.     /*MaxSizeInWord and TargetSzieInWord*/
  1001.     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
  1002.                   (target_mb_size << 16) );
  1003.  
  1004.     OUT_BCS_BATCH(batch, 0x0);
  1005.     ADVANCE_BCS_BATCH(batch);
  1006.  
  1007.     return len_in_dwords;
  1008. }
  1009.  
  1010. #define         AVC_INTRA_RDO_OFFSET    4
  1011. #define         AVC_INTER_RDO_OFFSET    10
  1012. #define         AVC_INTER_MSG_OFFSET    8
  1013. #define         AVC_INTER_MV_OFFSET             48
  1014. #define         AVC_RDO_MASK            0xFFFF
  1015.  
  1016. static void
  1017. gen9_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
  1018.                                        struct encode_state *encode_state,
  1019.                                        struct intel_encoder_context *encoder_context,
  1020.                                        int slice_index,
  1021.                                        struct intel_batchbuffer *slice_batch)
  1022. {
  1023.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1024.     struct gen6_vme_context *vme_context = encoder_context->vme_context;
  1025.     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
  1026.     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
  1027.     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
  1028.     unsigned int *msg = NULL, offset = 0;
  1029.     unsigned char *msg_ptr = NULL;
  1030.     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
  1031.     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
  1032.     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
  1033.     int i,x,y;
  1034.     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
  1035.     unsigned int rate_control_mode = encoder_context->rate_control_mode;
  1036.     unsigned int tail_data[] = { 0x0, 0x0 };
  1037.     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
  1038.     int is_intra = slice_type == SLICE_TYPE_I;
  1039.     int qp_slice;
  1040.  
  1041.     qp_slice = qp;
  1042.     if (rate_control_mode == VA_RC_CBR) {
  1043.         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
  1044.         if (encode_state->slice_header_index[slice_index] == 0) {
  1045.             pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
  1046.             qp_slice = qp;
  1047.         }
  1048.     }
  1049.  
  1050.     /* only support for 8-bit pixel bit-depth */
  1051.     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
  1052.     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
  1053.     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
  1054.     assert(qp >= 0 && qp < 52);
  1055.  
  1056.          gen9_mfc_avc_slice_state(ctx,
  1057.                                   pPicParameter,
  1058.                                   pSliceParameter,
  1059.                                   encode_state, encoder_context,
  1060.                                   (rate_control_mode == VA_RC_CBR), qp_slice, slice_batch);
  1061.  
  1062.         if ( slice_index == 0)
  1063.             intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
  1064.  
  1065.          intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
  1066.  
  1067.     dri_bo_map(vme_context->vme_output.bo , 1);
  1068.     msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual;
  1069.  
  1070.     if (is_intra) {
  1071.         msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
  1072.     } else {
  1073.         msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
  1074.     }
  1075.  
  1076.     for (i = pSliceParameter->macroblock_address;
  1077.         i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
  1078.         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
  1079.         x = i % width_in_mbs;
  1080.         y = i / width_in_mbs;
  1081.         msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
  1082.  
  1083.         if (is_intra) {
  1084.             assert(msg);
  1085.             gen9_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
  1086.         } else {
  1087.             int inter_rdo, intra_rdo;
  1088.             inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK;
  1089.             intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK;
  1090.             offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET;
  1091.             if (intra_rdo < inter_rdo) {
  1092.                 gen9_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
  1093.             } else {
  1094.                 msg += AVC_INTER_MSG_OFFSET;
  1095.                 gen9_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
  1096.             }
  1097.         }
  1098.     }
  1099.  
  1100.     dri_bo_unmap(vme_context->vme_output.bo);
  1101.  
  1102.     if ( last_slice ) {
  1103.         mfc_context->insert_object(ctx, encoder_context,
  1104.                                    tail_data, 2, 8,
  1105.                                    2, 1, 1, 0, slice_batch);
  1106.     } else {
  1107.         mfc_context->insert_object(ctx, encoder_context,
  1108.                                    tail_data, 1, 8,
  1109.                                    1, 1, 1, 0, slice_batch);
  1110.     }
  1111.  
  1112.  
  1113. }
  1114.  
  1115. static dri_bo *
  1116. gen9_mfc_avc_software_batchbuffer(VADriverContextP ctx,
  1117.                                   struct encode_state *encode_state,
  1118.                                   struct intel_encoder_context *encoder_context)
  1119. {
  1120.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1121.     struct intel_batchbuffer *batch;
  1122.     dri_bo *batch_bo;
  1123.     int i;
  1124.  
  1125.     batch = mfc_context->aux_batchbuffer;
  1126.     batch_bo = batch->buffer;
  1127.     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
  1128.         gen9_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
  1129.     }
  1130.  
  1131.     intel_batchbuffer_align(batch, 8);
  1132.  
  1133.     BEGIN_BCS_BATCH(batch, 2);
  1134.     OUT_BCS_BATCH(batch, 0);
  1135.     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
  1136.     ADVANCE_BCS_BATCH(batch);
  1137.  
  1138.     dri_bo_reference(batch_bo);
  1139.     intel_batchbuffer_free(batch);
  1140.     mfc_context->aux_batchbuffer = NULL;
  1141.  
  1142.     return batch_bo;
  1143. }
  1144.  
  1145. #else
  1146.  
  1147. static void
  1148. gen9_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
  1149.                                     struct encode_state *encode_state,
  1150.                                     struct intel_encoder_context *encoder_context)
  1151.  
  1152. {
  1153.     struct gen6_vme_context *vme_context = encoder_context->vme_context;
  1154.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1155.  
  1156.     assert(vme_context->vme_output.bo);
  1157.     mfc_context->buffer_suface_setup(ctx,
  1158.                                      &mfc_context->gpe_context,
  1159.                                      &vme_context->vme_output,
  1160.                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
  1161.                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
  1162.     assert(mfc_context->aux_batchbuffer_surface.bo);
  1163.     mfc_context->buffer_suface_setup(ctx,
  1164.                                      &mfc_context->gpe_context,
  1165.                                      &mfc_context->aux_batchbuffer_surface,
  1166.                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
  1167.                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
  1168. }
  1169.  
  1170. static void
  1171. gen9_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
  1172.                                      struct encode_state *encode_state,
  1173.                                      struct intel_encoder_context *encoder_context)
  1174.  
  1175. {
  1176.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  1177.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1178.     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
  1179.     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
  1180.     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
  1181.     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
  1182.     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
  1183.     mfc_context->mfc_batchbuffer_surface.pitch = 16;
  1184.     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
  1185.                                                            "MFC batchbuffer",
  1186.                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
  1187.                                                            0x1000);
  1188.     mfc_context->buffer_suface_setup(ctx,
  1189.                                      &mfc_context->gpe_context,
  1190.                                      &mfc_context->mfc_batchbuffer_surface,
  1191.                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
  1192.                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
  1193. }
  1194.  
  1195. static void
  1196. gen9_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
  1197.                                     struct encode_state *encode_state,
  1198.                                     struct intel_encoder_context *encoder_context)
  1199. {
  1200.     gen9_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
  1201.     gen9_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
  1202. }
  1203.  
  1204. static void
  1205. gen9_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
  1206.                                 struct encode_state *encode_state,
  1207.                                 struct intel_encoder_context *encoder_context)
  1208. {
  1209.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1210.     struct gen6_interface_descriptor_data *desc;
  1211.     int i;
  1212.     dri_bo *bo;
  1213.  
  1214.     bo = mfc_context->gpe_context.idrt.bo;
  1215.     dri_bo_map(bo, 1);
  1216.     assert(bo->virtual);
  1217.     desc = bo->virtual;
  1218.  
  1219.     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
  1220.         struct i965_kernel *kernel;
  1221.  
  1222.         kernel = &mfc_context->gpe_context.kernels[i];
  1223.         assert(sizeof(*desc) == 32);
  1224.  
  1225.         /*Setup the descritor table*/
  1226.         memset(desc, 0, sizeof(*desc));
  1227.         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
  1228.         desc->desc2.sampler_count = 0;
  1229.         desc->desc2.sampler_state_pointer = 0;
  1230.         desc->desc3.binding_table_entry_count = 2;
  1231.         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
  1232.         desc->desc4.constant_urb_entry_read_offset = 0;
  1233.         desc->desc4.constant_urb_entry_read_length = 4;
  1234.  
  1235.         /*kernel start*/
  1236.         dri_bo_emit_reloc(bo,
  1237.                           I915_GEM_DOMAIN_INSTRUCTION, 0,
  1238.                           0,
  1239.                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
  1240.                           kernel->bo);
  1241.         desc++;
  1242.     }
  1243.  
  1244.     dri_bo_unmap(bo);
  1245. }
  1246.  
  1247. static void
  1248. gen9_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
  1249.                                     struct encode_state *encode_state,
  1250.                                     struct intel_encoder_context *encoder_context)
  1251. {
  1252.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1253.  
  1254.     (void)mfc_context;
  1255. }
  1256.  
  1257. static void
  1258. gen9_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
  1259.                                          int index,
  1260.                                          int head_offset,
  1261.                                          int batchbuffer_offset,
  1262.                                          int head_size,
  1263.                                          int tail_size,
  1264.                                          int number_mb_cmds,
  1265.                                          int first_object,
  1266.                                          int last_object,
  1267.                                          int last_slice,
  1268.                                          int mb_x,
  1269.                                          int mb_y,
  1270.                                          int width_in_mbs,
  1271.                                          int qp)
  1272. {
  1273.     BEGIN_BATCH(batch, 12);
  1274.  
  1275.     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
  1276.     OUT_BATCH(batch, index);
  1277.     OUT_BATCH(batch, 0);
  1278.     OUT_BATCH(batch, 0);
  1279.     OUT_BATCH(batch, 0);
  1280.     OUT_BATCH(batch, 0);
  1281.  
  1282.     /*inline data */
  1283.     OUT_BATCH(batch, head_offset);
  1284.     OUT_BATCH(batch, batchbuffer_offset);
  1285.     OUT_BATCH(batch,
  1286.               head_size << 16 |
  1287.               tail_size);
  1288.     OUT_BATCH(batch,
  1289.               number_mb_cmds << 16 |
  1290.               first_object << 2 |
  1291.               last_object << 1 |
  1292.               last_slice);
  1293.     OUT_BATCH(batch,
  1294.               mb_y << 8 |
  1295.               mb_x);
  1296.     OUT_BATCH(batch,
  1297.               qp << 16 |
  1298.               width_in_mbs);
  1299.  
  1300.     ADVANCE_BATCH(batch);
  1301. }
  1302.  
  1303. static void
  1304. gen9_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
  1305.                                        struct intel_encoder_context *encoder_context,
  1306.                                        VAEncSliceParameterBufferH264 *slice_param,
  1307.                                        int head_offset,
  1308.                                        unsigned short head_size,
  1309.                                        unsigned short tail_size,
  1310.                                        int batchbuffer_offset,
  1311.                                        int qp,
  1312.                                        int last_slice)
  1313. {
  1314.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  1315.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1316.     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
  1317.     int total_mbs = slice_param->num_macroblocks;
  1318.     int number_mb_cmds = 128;
  1319.     int starting_mb = 0;
  1320.     int last_object = 0;
  1321.     int first_object = 1;
  1322.     int i;
  1323.     int mb_x, mb_y;
  1324.     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
  1325.  
  1326.     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
  1327.         last_object = (total_mbs - starting_mb) == number_mb_cmds;
  1328.         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
  1329.         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
  1330.         assert(mb_x <= 255 && mb_y <= 255);
  1331.  
  1332.         starting_mb += number_mb_cmds;
  1333.  
  1334.         gen9_mfc_batchbuffer_emit_object_command(batch,
  1335.                                                  index,
  1336.                                                  head_offset,
  1337.                                                  batchbuffer_offset,
  1338.                                                  head_size,
  1339.                                                  tail_size,
  1340.                                                  number_mb_cmds,
  1341.                                                  first_object,
  1342.                                                  last_object,
  1343.                                                  last_slice,
  1344.                                                  mb_x,
  1345.                                                  mb_y,
  1346.                                                  width_in_mbs,
  1347.                                                  qp);
  1348.  
  1349.         if (first_object) {
  1350.             head_offset += head_size;
  1351.             batchbuffer_offset += head_size;
  1352.         }
  1353.  
  1354.         if (last_object) {
  1355.             head_offset += tail_size;
  1356.             batchbuffer_offset += tail_size;
  1357.         }
  1358.  
  1359.         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
  1360.  
  1361.         first_object = 0;
  1362.     }
  1363.  
  1364.     if (!last_object) {
  1365.         last_object = 1;
  1366.         number_mb_cmds = total_mbs % number_mb_cmds;
  1367.         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
  1368.         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
  1369.         assert(mb_x <= 255 && mb_y <= 255);
  1370.         starting_mb += number_mb_cmds;
  1371.  
  1372.         gen9_mfc_batchbuffer_emit_object_command(batch,
  1373.                                                  index,
  1374.                                                  head_offset,
  1375.                                                  batchbuffer_offset,
  1376.                                                  head_size,
  1377.                                                  tail_size,
  1378.                                                  number_mb_cmds,
  1379.                                                  first_object,
  1380.                                                  last_object,
  1381.                                                  last_slice,
  1382.                                                  mb_x,
  1383.                                                  mb_y,
  1384.                                                  width_in_mbs,
  1385.                                                  qp);
  1386.     }
  1387. }
  1388.  
  1389. /*
  1390.  * return size in Owords (16bytes)
  1391.  */
  1392. static int
  1393. gen9_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
  1394.                                struct encode_state *encode_state,
  1395.                                struct intel_encoder_context *encoder_context,
  1396.                                int slice_index,
  1397.                                int batchbuffer_offset)
  1398. {
  1399.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1400.     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
  1401.     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
  1402.     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
  1403.     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
  1404.     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
  1405.     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
  1406.     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
  1407.     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
  1408.     unsigned int rate_control_mode = encoder_context->rate_control_mode;
  1409.     unsigned int tail_data[] = { 0x0, 0x0 };
  1410.     long head_offset;
  1411.     int old_used = intel_batchbuffer_used_size(slice_batch), used;
  1412.     unsigned short head_size, tail_size;
  1413.     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
  1414.     int qp_slice;
  1415.  
  1416.     qp_slice = qp;
  1417.     if (rate_control_mode == VA_RC_CBR) {
  1418.         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
  1419.         if (encode_state->slice_header_index[slice_index] == 0) {
  1420.             pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
  1421.             qp_slice = qp;
  1422.         }
  1423.     }
  1424.  
  1425.     /* only support for 8-bit pixel bit-depth */
  1426.     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
  1427.     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
  1428.     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
  1429.     assert(qp >= 0 && qp < 52);
  1430.  
  1431.     head_offset = old_used / 16;
  1432.     gen9_mfc_avc_slice_state(ctx,
  1433.                              pPicParameter,
  1434.                              pSliceParameter,
  1435.                              encode_state,
  1436.                              encoder_context,
  1437.                              (rate_control_mode == VA_RC_CBR),
  1438.                              qp_slice,
  1439.                              slice_batch);
  1440.  
  1441.     if (slice_index == 0)
  1442.         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
  1443.  
  1444.  
  1445.     intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
  1446.  
  1447.  
  1448.     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
  1449.     used = intel_batchbuffer_used_size(slice_batch);
  1450.     head_size = (used - old_used) / 16;
  1451.     old_used = used;
  1452.  
  1453.     /* tail */
  1454.     if (last_slice) {
  1455.         mfc_context->insert_object(ctx,
  1456.                                    encoder_context,
  1457.                                    tail_data,
  1458.                                    2,
  1459.                                    8,
  1460.                                    2,
  1461.                                    1,
  1462.                                    1,
  1463.                                    0,
  1464.                                    slice_batch);
  1465.     } else {
  1466.         mfc_context->insert_object(ctx,
  1467.                                    encoder_context,
  1468.                                    tail_data,
  1469.                                    1,
  1470.                                    8,
  1471.                                    1,
  1472.                                    1,
  1473.                                    1,
  1474.                                    0,
  1475.                                    slice_batch);
  1476.     }
  1477.  
  1478.     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
  1479.     used = intel_batchbuffer_used_size(slice_batch);
  1480.     tail_size = (used - old_used) / 16;
  1481.  
  1482.     gen9_mfc_avc_batchbuffer_slice_command(ctx,
  1483.                                            encoder_context,
  1484.                                            pSliceParameter,
  1485.                                            head_offset,
  1486.                                            head_size,
  1487.                                            tail_size,
  1488.                                            batchbuffer_offset,
  1489.                                            qp,
  1490.                                            last_slice);
  1491.  
  1492.     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
  1493. }
  1494.  
  1495. static void
  1496. gen9_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
  1497.                                   struct encode_state *encode_state,
  1498.                                   struct intel_encoder_context *encoder_context)
  1499. {
  1500.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1501.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  1502.     int i, size, offset = 0;
  1503.  
  1504.     intel_batchbuffer_start_atomic(batch, 0x4000);
  1505.     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
  1506.  
  1507.     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
  1508.         size = gen9_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
  1509.         offset += size;
  1510.     }
  1511.  
  1512.     intel_batchbuffer_end_atomic(batch);
  1513.     intel_batchbuffer_flush(batch);
  1514. }
  1515.  
  1516. static void
  1517. gen9_mfc_build_avc_batchbuffer(VADriverContextP ctx,
  1518.                                struct encode_state *encode_state,
  1519.                                struct intel_encoder_context *encoder_context)
  1520. {
  1521.     gen9_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
  1522.     gen9_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
  1523.     gen9_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
  1524.     gen9_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
  1525. }
  1526.  
  1527. static dri_bo *
  1528. gen9_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
  1529.                                   struct encode_state *encode_state,
  1530.                                   struct intel_encoder_context *encoder_context)
  1531. {
  1532.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1533.  
  1534.     gen9_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
  1535.     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
  1536.  
  1537.     return mfc_context->mfc_batchbuffer_surface.bo;
  1538. }
  1539.  
  1540. #endif
  1541.  
  1542. static void
  1543. gen9_mfc_avc_pipeline_programing(VADriverContextP ctx,
  1544.                                  struct encode_state *encode_state,
  1545.                                  struct intel_encoder_context *encoder_context)
  1546. {
  1547.     struct intel_batchbuffer *batch = encoder_context->base.batch;
  1548.     dri_bo *slice_batch_bo;
  1549.  
  1550.     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
  1551.         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
  1552.         assert(0);
  1553.         return;
  1554.     }
  1555.  
  1556. #ifdef MFC_SOFTWARE_HASWELL
  1557.     slice_batch_bo = gen9_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
  1558. #else
  1559.     slice_batch_bo = gen9_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
  1560. #endif
  1561.  
  1562.     // begin programing
  1563.     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
  1564.     intel_batchbuffer_emit_mi_flush(batch);
  1565.  
  1566.     // picture level programing
  1567.     gen9_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
  1568.  
  1569.     BEGIN_BCS_BATCH(batch, 3);
  1570.     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8) | (1 << 0));
  1571.     OUT_BCS_RELOC(batch,
  1572.                   slice_batch_bo,
  1573.                   I915_GEM_DOMAIN_COMMAND, 0,
  1574.                   0);
  1575.     OUT_BCS_BATCH(batch, 0);
  1576.     ADVANCE_BCS_BATCH(batch);
  1577.  
  1578.     // end programing
  1579.     intel_batchbuffer_end_atomic(batch);
  1580.  
  1581.     dri_bo_unreference(slice_batch_bo);
  1582. }
  1583.  
  1584.  
  1585. static VAStatus
  1586. gen9_mfc_avc_encode_picture(VADriverContextP ctx,
  1587.                             struct encode_state *encode_state,
  1588.                             struct intel_encoder_context *encoder_context)
  1589. {
  1590.     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  1591.     unsigned int rate_control_mode = encoder_context->rate_control_mode;
  1592.     int current_frame_bits_size;
  1593.     int sts;
  1594.  
  1595.     for (;;) {
  1596.         gen9_mfc_init(ctx, encode_state, encoder_context);
  1597.         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
  1598.         /*Programing bcs pipeline*/
  1599.         gen9_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
  1600.         gen9_mfc_run(ctx, encode_state, encoder_context);
  1601.         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
  1602.             gen9_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
  1603.             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
  1604.             if (sts == BRC_NO_HRD_VIOLATION) {
  1605.                 intel_mfc_hrd_context_update(encode_state, mfc_context);
  1606.                 break;
  1607.             }
  1608.             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
  1609.                 if (!mfc_context->hrd.violation_noted) {
  1610.                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
  1611.                     mfc_context->hrd.violation_noted = 1;
  1612.                 }
  1613.                 return VA_STATUS_SUCCESS;
  1614.             }
  1615.         } else {
  1616.             break;
  1617.         }
  1618.     }
  1619.  
  1620.     return VA_STATUS_SUCCESS;
  1621. }
  1622.  
  1623. static void
  1624. gen9_mfc_context_destroy(void *context)
  1625. {
  1626.     struct gen6_mfc_context *mfc_context = context;
  1627.     int i;
  1628.  
  1629.     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
  1630.     mfc_context->post_deblocking_output.bo = NULL;
  1631.  
  1632.     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
  1633.     mfc_context->pre_deblocking_output.bo = NULL;
  1634.  
  1635.     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
  1636.     mfc_context->uncompressed_picture_source.bo = NULL;
  1637.  
  1638.     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
  1639.     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
  1640.  
  1641.     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
  1642.         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
  1643.         mfc_context->direct_mv_buffers[i].bo = NULL;
  1644.     }
  1645.  
  1646.     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
  1647.     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
  1648.  
  1649.     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
  1650.     mfc_context->macroblock_status_buffer.bo = NULL;
  1651.  
  1652.     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
  1653.     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
  1654.  
  1655.     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
  1656.     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
  1657.  
  1658.  
  1659.     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
  1660.         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
  1661.         mfc_context->reference_surfaces[i].bo = NULL;
  1662.     }
  1663.  
  1664.     i965_gpe_context_destroy(&mfc_context->gpe_context);
  1665.  
  1666.     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
  1667.     mfc_context->mfc_batchbuffer_surface.bo = NULL;
  1668.  
  1669.     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
  1670.     mfc_context->aux_batchbuffer_surface.bo = NULL;
  1671.  
  1672.     if (mfc_context->aux_batchbuffer)
  1673.         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
  1674.  
  1675.     mfc_context->aux_batchbuffer = NULL;
  1676.  
  1677.     free(mfc_context);
  1678. }
  1679.  
  1680. static VAStatus gen9_mfc_pipeline(VADriverContextP ctx,
  1681.                                   VAProfile profile,
  1682.                                   struct encode_state *encode_state,
  1683.                                   struct intel_encoder_context *encoder_context)
  1684. {
  1685.     VAStatus vaStatus;
  1686.  
  1687.     switch (profile) {
  1688.     case VAProfileH264ConstrainedBaseline:
  1689.     case VAProfileH264Main:
  1690.     case VAProfileH264High:
  1691.     case VAProfileH264MultiviewHigh:
  1692.     case VAProfileH264StereoHigh:
  1693.         vaStatus = gen9_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
  1694.         break;
  1695.  
  1696.     default:
  1697.         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
  1698.         break;
  1699.     }
  1700.  
  1701.     return vaStatus;
  1702. }
  1703.  
  1704. Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  1705. {
  1706.     struct gen6_mfc_context *mfc_context = NULL;
  1707.  
  1708. #if MFC_SOFTWARE_HASWELL
  1709.     if ((encoder_context->codec == CODEC_H264) ||
  1710.         (encoder_context->codec == CODEC_H264_MVC)) {
  1711.         return gen8_mfc_context_init(ctx, encoder_context);
  1712.     }
  1713. #endif
  1714.  
  1715.     if ((encoder_context->codec == CODEC_VP8) ||
  1716.         (encoder_context->codec == CODEC_MPEG2))
  1717.         return gen8_mfc_context_init(ctx, encoder_context);
  1718.  
  1719.     mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
  1720.     assert(mfc_context);
  1721.     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
  1722.  
  1723.     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
  1724.     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
  1725.  
  1726.     mfc_context->gpe_context.curbe.length = 32 * 4;
  1727.  
  1728.     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
  1729.     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
  1730.     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
  1731.     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
  1732.     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
  1733.  
  1734.     i965_gpe_load_kernels(ctx,
  1735.                           &mfc_context->gpe_context,
  1736.                           gen9_mfc_kernels,
  1737.                           NUM_MFC_KERNEL);
  1738.  
  1739.     mfc_context->pipe_mode_select = gen9_mfc_pipe_mode_select;
  1740.     mfc_context->set_surface_state = gen9_mfc_surface_state;
  1741.     mfc_context->ind_obj_base_addr_state = gen9_mfc_ind_obj_base_addr_state;
  1742.     mfc_context->avc_img_state = gen9_mfc_avc_img_state;
  1743.     mfc_context->avc_qm_state = gen9_mfc_avc_qm_state;
  1744.     mfc_context->avc_fqm_state = gen9_mfc_avc_fqm_state;
  1745.     mfc_context->insert_object = gen9_mfc_avc_insert_object;
  1746.     mfc_context->buffer_suface_setup = gen8_gpe_buffer_suface_setup;
  1747.  
  1748.     encoder_context->mfc_context = mfc_context;
  1749.     encoder_context->mfc_context_destroy = gen9_mfc_context_destroy;
  1750.     encoder_context->mfc_pipeline = gen9_mfc_pipeline;
  1751.     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
  1752.  
  1753.     return True;
  1754. }
  1755.