WebSVN – Kolibri OS – Diff – /kernel/trunk/network/eth_drv/drivers/rtl8139.inc


$Revision: 431 $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2007. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;  RTL8139.INC                                                    ;;
;;                                                                 ;;
;;  Ethernet driver for Menuet OS                                  ;;
;;                                                                 ;;
;;  Version 0.2  11 August 2003                                    ;;
;;                                                                 ;;
;;  Driver for chips of RealTek 8139 family                        ;;
;;  References:                                                    ;;
;;    www.realtek.com.hw - data sheets                             ;;
;;    rtl8139.c - linux driver                                     ;;
;;    8139too.c - linux driver                                     ;;
;;    ethernet driver template by Mike Hibbett                     ;;
;;                                                                 ;;
;;  The copyright statement is                                     ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;  Copyright 2003 Endre Kozma,                                    ;;
;;   endre.kozma@axelero.hu                                        ;;
;;                                                                 ;;
;;  See file COPYING for details                                   ;;
;;                                                                 ;;
;;  10.01.2007 Bugfix for l8139_transmit from Paolo Franchetti     ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	ETH_ALEN	       equ 6
	ETH_HLEN	       equ (2 * ETH_ALEN + 2)
	ETH_ZLEN	       equ 60 ; 60 + 4bytes auto payload for
				      ; mininmum 64bytes frame length
 
	PCI_REG_COMMAND        equ 0x04 ; command register
	PCI_BIT_PIO	       equ 0 ; bit0: io space control
	PCI_BIT_MMIO	       equ 1 ; bit1: memory space control
	PCI_BIT_MASTER	       equ 2 ; bit2: device acts as a PCI master
 
	RTL8139_REG_MAR0       equ 0x08 ; multicast filter register 0
	RTL8139_REG_MAR4       equ 0x0c ; multicast filter register 4
	RTL8139_REG_TSD0       equ 0x10 ; transmit status of descriptor
	RTL8139_REG_TSAD0      equ 0x20 ; transmit start address of descriptor
	RTL8139_REG_RBSTART    equ 0x30 ; RxBuffer start address
	RTL8139_REG_COMMAND    equ 0x37 ; command register
	RTL8139_REG_CAPR       equ 0x38 ; current address of packet read
	RTL8139_REG_IMR        equ 0x3c ; interrupt mask register
	RTL8139_REG_ISR        equ 0x3e ; interrupt status register
	RTL8139_REG_TXCONFIG   equ 0x40 ; transmit configuration register
	RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0
	RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1
	RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2
	RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3
	RTL8139_REG_RXCONFIG   equ 0x44 ; receive configuration register 0
	RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0
	RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1
	RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2
	RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3
	RTL8139_REG_MPC        equ 0x4c ; missed packet counter
	RTL8139_REG_9346CR     equ 0x50 ; serial eeprom 93C46 command register
	RTL8139_REG_CONFIG1    equ 0x52 ; configuration register 1
	RTL8139_REG_CONFIG4    equ 0x5a ; configuration register 4
	RTL8139_REG_HLTCLK     equ 0x5b ; undocumented halt clock register
	RTL8139_REG_BMCR       equ 0x62 ; basic mode control register
	RTL8139_REG_ANAR       equ 0x66 ; auto negotiation advertisement register
 
; 5.1 packet header
	RTL8139_BIT_RUNT       equ 4 ; total packet length < 64 bytes
	RTL8139_BIT_LONG       equ 3 ; total packet length > 4k
	RTL8139_BIT_CRC        equ 2 ; crc error occured
	RTL8139_BIT_FAE        equ 1 ; frame alignment error occured
	RTL8139_BIT_ROK        equ 0 ; received packet is ok
; 5.4 command register
	RTL8139_BIT_RST        equ 4 ; reset bit
	RTL8139_BIT_RE	       equ 3 ; receiver enabled
	RTL8139_BIT_TE	       equ 2 ; transmitter enabled
	RTL8139_BIT_BUFE       equ 0 ; rx buffer is empty, no packet stored
; 5.6 interrupt status register
	RTL8139_BIT_ISR_TOK    equ 2 ; transmit ok
	RTL8139_BIT_ISR_RER    equ 1 ; receive error interrupt
	RTL8139_BIT_ISR_ROK    equ 0 ; receive ok
; 5.7 transmit configyration register
	RTL8139_BIT_TX_MXDMA   equ 8 ; Max DMA burst size per Tx DMA burst
	RTL8139_BIT_TXRR       equ 4 ; Tx Retry count 16+(TXRR*16)
; 5.8 receive configuration register
	RTL8139_BIT_RXFTH      equ 13 ; Rx fifo threshold
	RTL8139_BIT_RBLEN      equ 11 ; Ring buffer length indicator
	RTL8139_BIT_RX_MXDMA   equ 8 ; Max DMA burst size per Rx DMA burst
	RTL8139_BIT_NOWRAP     equ 7 ; transfered data wrapping
	RTL8139_BIT_9356SEL    equ 6 ; eeprom selector 9346/9356
	RTL8139_BIT_AER        equ 5 ; accept error packets
	RTL8139_BIT_AR	       equ 4 ; accept runt packets
	RTL8139_BIT_AB	       equ 3 ; accept broadcast packets
	RTL8139_BIT_AM	       equ 2 ; accept multicast packets
	RTL8139_BIT_APM        equ 1 ; accept physical match packets
	RTL8139_BIT_AAP        equ 0 ; accept all packets
; 5.9 93C46/93C56 command register
	RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1
	RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0
	RTL8139_BIT_93C46_EECS equ 3 ; chip select
	RTL8139_BIT_93C46_EESK equ 2 ; serial data clock
	RTL8139_BIT_93C46_EEDI equ 1 ; serial data input
	RTL8139_BIT_93C46_EEDO equ 0 ; serial data output
; 5.11 configuration register 1
	RTL8139_BIT_LWACT      equ 4 ; see RTL8139_REG_CONFIG1
	RTL8139_BIT_SLEEP      equ 1 ; sleep bit at older chips
	RTL8139_BIT_PWRDWN     equ 0 ; power down bit at older chips
	RTL8139_BIT_PMEn       equ 0 ; power management enabled
; 5.14 configuration register 4
	RTL8139_BIT_LWPTN      equ 2 ; see RTL8139_REG_CONFIG4
; 6.2 transmit status register
	RTL8139_BIT_ERTXTH     equ 16 ; early TX threshold
	RTL8139_BIT_TOK        equ 15 ; transmit ok
	RTL8139_BIT_OWN        equ 13 ; tx DMA operation is completed
; 6.18 basic mode control register
	RTL8139_BIT_ANE        equ 12 ; auto negotiation enable
; 6.20 auto negotiation advertisement register
	RTL8139_BIT_TXFD       equ 8 ; 100base-T full duplex
	RTL8139_BIT_TX	       equ 7 ; 100base-T
	RTL8139_BIT_10FD       equ 6 ; 10base-T full duplex
	RTL8139_BIT_10	       equ 5 ; 10base-T
	RTL8139_BIT_SELECTOR   equ 0 ; binary encoded selector CSMA/CD=00001
; RX/TX buffer size
	RTL8139_RBLEN	       equ 0 ; 0==8K 1==16k 2==32k 3==64k
	RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN)
	MAX_ETH_FRAME_SIZE     equ 1516 ; exactly 1514 wthout CRC
	RTL8139_NUM_TX_DESC    equ 4
	RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC)
	RTL8139_TXRR	       equ 8 ; total retries = 16+(TXRR*16)
	RTL8139_TX_MXDMA       equ 6 ; 0==16 1==32 2==64 3==128
				     ; 4==256 5==512 6==1024 7==2048
	RTL8139_ERTXTH	       equ 8 ; in unit of 32 bytes e.g:(8*32)=256
	RTL8139_RX_MXDMA       equ 7 ; 0==16 1==32 2==64 3==128
				     ; 4==256 5==512 6==1024 7==unlimited
	RTL8139_RXFTH	       equ 7 ; 0==16 1==32 2==64 3==128
				     ; 4==256 5==512 6==1024 7==no threshold
	RTL8139_RX_CONFIG      equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \
				    or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \
				    or (1 shl RTL8139_BIT_NOWRAP) \
				    or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \
				    or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \
				    or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \
				    or (1 shl RTL8139_BIT_AM))
	RTL8139_TX_TIMEOUT     equ 30 ; 300 milliseconds timeout
 
	EE_93C46_REG_ETH_ID    equ 7 ; MAC offset
	EE_93C46_READ_CMD      equ (6 shl 6) ; 110b + 6bit address
	EE_93C56_READ_CMD      equ (6 shl 8) ; 110b + 8bit address
	EE_93C46_CMD_LENGTH    equ 9 ; start bit + cmd + 6bit address
	EE_93C56_CMD_LENGTH    equ 11 ; start bit + cmd + 8bit ddress
 
	VER_RTL8139	       equ 1100000b
	VER_RTL8139A	       equ 1110000b
;       VER_RTL8139AG          equ 1110100b
	VER_RTL8139B	       equ 1111000b
	VER_RTL8130	       equ VER_RTL8139B
	VER_RTL8139C	       equ 1110100b
	VER_RTL8100	       equ 1111010b
	VER_RTL8100B	       equ 1110101b
	VER_RTL8139D	       equ VER_RTL8100B
	VER_RTL8139CP	       equ 1110110b
	VER_RTL8101	       equ 1110111b
 
	IDX_RTL8139	       equ 0
	IDX_RTL8139A	       equ 1
	IDX_RTL8139B	       equ 2
	IDX_RTL8139C	       equ 3
	IDX_RTL8100	       equ 4
	IDX_RTL8139D	       equ 5
	IDX_RTL8139D	       equ 6
	IDX_RTL8101	       equ 7
 
 
; These two must be 4 byte aligned ( which they are )
rtl8139_rx_buff     equ     eth_data_start
rtl8139_tx_buff     equ     rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE)
 
uglobal
	align	4
rtl8139_rx_buff_offset: dd 0
curr_tx_desc dd 0
endg
 
iglobal
hw_ver_array: db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C
	      db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101
HW_VER_ARRAY_SIZE = $-hw_ver_array
endg
 
uglobal
hw_ver_id: db 0
endg
 
;***************************************************************************
;   Function
;      rtl8139_probe
;   Description
;      Searches for an ethernet card, enables it and clears the rx buffer
;      If a card was found, it enables the ethernet -> TCPIP link
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
rtl8139_probe:
; enable the device
	mov	al, 2
	mov	ah, [pci_bus]
	mov	bh, [pci_dev]
	mov	bl, PCI_REG_COMMAND
	call	pci_read_reg
	mov	cx, ax
	or	cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO)
	and	cl, not (1 shl PCI_BIT_MMIO)
	mov	al, 2
	mov	ah, [pci_bus]
	mov	bh, [pci_dev]
	mov	bl, PCI_REG_COMMAND
	call	pci_write_reg
; get chip version
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_TXCONFIG_2
	in	ax, dx
	shr	ah, 2
	shr	ax, 6
	and	al, 01111111b
	mov	ecx, HW_VER_ARRAY_SIZE-1
.chip_ver_loop:
	cmp	al, [hw_ver_array+ecx]
	je	.chip_ver_found
	dec	ecx
	jns	.chip_ver_loop
	xor	cl, cl ; default RTL8139
.chip_ver_found:
	mov	[hw_ver_id], cl
; wake up the chip
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_HLTCLK
	mov	al, 'R' ; run the clock
	out	dx, al
; unlock config and BMCR registers
	add	edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
	out	dx, al
; enable power management
	add	edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR
	in	al, dx
	cmp	byte [hw_ver_id], IDX_RTL8139B
	jl	.old_chip
; set LWAKE pin to active high (default value).
; it is for Wake-On-LAN functionality of some motherboards.
; this signal is used to inform the motherboard to execute a wake-up process.
; only at newer chips.
	or	al, (1 shl RTL8139_BIT_PMEn)
	and	al, not (1 shl RTL8139_BIT_LWACT)
	out	dx, al
	add	edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1
	in	al, dx
	and	al, not (1 shl RTL8139_BIT_LWPTN)
	out	dx, al
	jmp	.finish_wake_up
.old_chip:
; wake up older chips
	and	al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN))
	out	dx, al
.finish_wake_up:
; lock config and BMCR registers
	xor	al, al
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_9346CR
	out	dx, al
;***************************************************************************
;   Function
;      rt8139_reset
;   Description
;      Place the chip (ie, the ethernet card) into a virgin state
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
rtl8139_reset:
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_COMMAND
	mov	al, 1 shl RTL8139_BIT_RST
	out	dx, al
	mov	cx, 1000 ; wait no longer for the reset
.wait_for_reset:
	in	al, dx
	test	al, 1 shl RTL8139_BIT_RST
	jz	.reset_completed ; RST remains 1 during reset
	dec	cx
	jns	.wait_for_reset
.reset_completed:
; get MAC (hardware address)
	mov	ecx, 2
.mac_read_loop:
	lea	eax, [EE_93C46_REG_ETH_ID+ecx]
	push	ecx
	call	rtl8139_read_eeprom
	pop	ecx
	mov	[node_addr+ecx*2], ax
	dec	ecx
	jns	.mac_read_loop
; unlock config and BMCR registers
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_9346CR
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
	out	dx, al
; initialize multicast registers (no filtering)
	mov	eax, 0xffffffff
	add	edx, RTL8139_REG_MAR0 - RTL8139_REG_9346CR
	out	dx, eax
	add	edx, RTL8139_REG_MAR4 - RTL8139_REG_MAR0
	out	dx, eax
; enable Rx/Tx
	mov	al, (1 shl RTL8139_BIT_RE) or (1 shl RTL8139_BIT_TE)
	add	edx, RTL8139_REG_COMMAND - RTL8139_REG_MAR4
	out	dx, al
; 32k Rxbuffer, unlimited dma burst, no wrapping, no rx threshold
; accept broadcast packets, accept physical match packets
	mov	ax, RTL8139_RX_CONFIG
	add	edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
	out	dx, ax
; 1024 bytes DMA burst, total retries = 16 + 8 * 16 = 144
	mov	ax, (RTL8139_TX_MXDMA shl RTL8139_BIT_TX_MXDMA) \
		    or (RTL8139_TXRR shl RTL8139_BIT_TXRR)
	add	edx, RTL8139_REG_TXCONFIG - RTL8139_REG_RXCONFIG
	out	dx, ax
; enable auto negotiation
	add	edx, RTL8139_REG_BMCR - RTL8139_REG_TXCONFIG
	in	ax, dx
	or	ax, (1 shl RTL8139_BIT_ANE)
	out	dx, ax
; set auto negotiation advertisement
	add	edx, RTL8139_REG_ANAR - RTL8139_REG_BMCR
	in	ax, dx
	or	ax, (1 shl RTL8139_BIT_SELECTOR) or (1 shl RTL8139_BIT_10) \
		    or (1 shl RTL8139_BIT_10FD) or (1 shl RTL8139_BIT_TX) \
		    or (1 shl RTL8139_BIT_TXFD)
	out	dx, ax
; lock config and BMCR registers
	xor	eax, eax
	add	edx, RTL8139_REG_9346CR - RTL8139_REG_ANAR
	out	dx, al
; init RX/TX pointers
	mov	[rtl8139_rx_buff_offset], eax
	mov	[curr_tx_desc], eax
; clear missing packet counter
	add	edx, RTL8139_REG_MPC - RTL8139_REG_9346CR
	out	dx, eax
; disable all interrupts
	add	edx, RTL8139_REG_IMR - RTL8139_REG_MPC
	out	dx, ax
; set RxBuffer address, init RX buffer offset, init TX ring
	mov	eax, rtl8139_rx_buff
	add	edx, RTL8139_REG_RBSTART - RTL8139_REG_IMR
	out	dx, eax
; Indicate that we have successfully reset the card
	mov	eax, [pci_data]
	mov	[eth_status], eax
	ret
 
;***************************************************************************
;   Function
;      rtl8139_read_eeprom
;   Description
;      reads eeprom type 93c46 and 93c56
;   Parameters
;      al - word to be read (6bit in case of 93c46 and 8bit otherwise)
;   Return value
;      ax - word read in
;   Destroyed register(s)
;      eax, cx, ebx, edx
;
;***************************************************************************
rtl8139_read_eeprom:
	movzx	ebx, al
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_RXCONFIG
	in	al, dx
	test	al, (1 shl RTL8139_BIT_9356SEL)
	jz	.type_93c46
;       and     bl, 01111111b ; don't care first bit
	or	bx, EE_93C56_READ_CMD ; it contains start bit
	mov	cx, EE_93C56_CMD_LENGTH-1 ; cmd_loop counter
	jmp	.read_eeprom
.type_93c46:
	and	bl, 00111111b
	or	bx, EE_93C46_READ_CMD ; it contains start bit
	mov	cx, EE_93C46_CMD_LENGTH-1 ; cmd_loop counter
.read_eeprom:
	add	edx, RTL8139_REG_9346CR - RTL8139_REG_RXCONFIG_0
;       mov     al, (1 shl RTL8139_BIT_93C46_EEM1)
;       out     dx, al
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) \
		    or (1 shl RTL8139_BIT_93C46_EECS) ; wake up the eeprom
	out	dx, al
.cmd_loop:
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
	bt	bx, cx
	jnc	.zero_bit
	or	al, (1 shl RTL8139_BIT_93C46_EEDI)
.zero_bit:
	out	dx, al
;       push    eax
;       in      eax, dx ; eeprom delay
;       pop     eax
	or	al, (1 shl RTL8139_BIT_93C46_EESK)
	out	dx, al
;       in      eax, dx ; eeprom delay
	dec	cx
	jns	.cmd_loop
;       in      eax, dx ; eeprom delay
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
	out	dx, al
	mov	cl, 0xf
.read_loop:
	shl	ebx, 1
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) \
		    or (1 shl RTL8139_BIT_93C46_EECS) \
		    or (1 shl RTL8139_BIT_93C46_EESK)
	out	dx, al
;       in      eax, dx ; eeprom delay
	in	al, dx
	and	al, (1 shl RTL8139_BIT_93C46_EEDO)
	jz	.dont_set
	inc	ebx
.dont_set:
	mov	al, (1 shl RTL8139_BIT_93C46_EEM1) \
		    or (1 shl RTL8139_BIT_93C46_EECS)
	out	dx, al
;       in      eax, dx ; eeprom delay
	dec	cl
	jns	.read_loop
	xor	al, al
	out	dx, al
	mov	ax, bx
	ret
 
;***************************************************************************
;   Function
;      rtl8139_transmit
;   Description
;      Transmits a packet of data via the ethernet card
;         Pointer to 48 bit destination address in edi
;         Type of packet in bx
;         Size of packet in ecx
;         Pointer to packet data in esi
;   Destroyed registers
;      eax, edx, esi, edi
;   ToDo
;      for waiting of timeout the rtl8139 internal timer
;      should be used
;
;***************************************************************************
rtl8139_transmit:
	cmp	ecx, MAX_ETH_FRAME_SIZE
	jg	.finish ; packet is too long
	push	ecx
; check descriptor
	mov	ecx, [curr_tx_desc]
	mov	edx, [io_addr]
	lea	edx, [edx+ecx*4+RTL8139_REG_TSD0]
	push	edx ebx
	in	ax, dx
	test    ax, 0x1fff ; or no size given
      jz      .send_packet
      and	ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
	cmp	ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
	jz	.send_packet
; wait for timeout
	mov	ebx, RTL8139_TX_TIMEOUT
	mov	eax, 0x5 ; delay x/100 secs
	int	0x40
	in	ax, dx
	and	ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
	cmp	ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
	jz	.send_packet
; chip hung, reset it
	call	rtl8139_reset
; reset the card
.send_packet:
; calculate tx_buffer address
	pop	ebx
	push	esi
	mov	eax, MAX_ETH_FRAME_SIZE
	mul	dword [curr_tx_desc]
	mov	esi, edi
	lea	edi, [rtl8139_tx_buff+eax]
	mov	eax, edi
	cld
; copy destination address
	movsd
	movsw
; copy source address
	mov	esi, node_addr
	movsd
	movsw
; copy packet type
	mov	[edi], bx
	add	edi, 2
; copy the packet data
	pop	esi edx ecx
	push	ecx
	shr	ecx, 2
	rep	movsd
	pop	ecx
	push	ecx
	and	ecx, 3
	rep	movsb
; set address
	add	edx, RTL8139_REG_TSAD0 - RTL8139_REG_TSD0
	out	dx, eax
; set size and early threshold
	pop	eax ; pick up the size
	add	eax, ETH_HLEN
	cmp	eax, ETH_ZLEN
	jnc	.no_pad
	mov	eax, ETH_ZLEN
.no_pad:
	or	eax, (RTL8139_ERTXTH shl RTL8139_BIT_ERTXTH)
	add	edx, RTL8139_REG_TSD0 - RTL8139_REG_TSAD0
	out	dx, eax
; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ...
	inc	dword [curr_tx_desc]
	and	dword [curr_tx_desc], 3
.finish:
	ret
 
;***************************************************************************
; Function
;    rtl8139_poll
;
; Description
;    Polls the ethernet card for a received packet
;    Received data, if any, ends up in Ether_buffer
; Destroyed register(s)
;    eax, edx, ecx
;
;***************************************************************************
rtl8139_poll:
	mov	word [eth_rx_data_len], 0
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_COMMAND
	in	al, dx
	test	al, (1 shl RTL8139_BIT_BUFE)
	jnz	.finish
; new packet received copy it from rx_buffer into Ether_buffer
	mov	eax, rtl8139_rx_buff
	add	eax, [rtl8139_rx_buff_offset]
; check if packet is ok
	test	byte [eax], (1 shl RTL8139_BIT_ROK)
	jz	.reset_rx
; packet is ok copy it into the Ether_buffer
	movzx	ecx, word [eax+2] ; packet length
	sub	ecx, 4 ; don't copy CRC
	mov	word [eth_rx_data_len], cx
	push	ecx
	shr	ecx, 2 ; first copy dword-wise
	lea	esi, [eax+4] ; don't copy the packet header
	mov	edi, Ether_buffer
	cld
	rep	movsd ; copy the dwords
	pop	ecx
	and	ecx, 3
	rep	movsb ; copy the rest bytes
; update rtl8139_rx_buff_offset
	movzx	eax, word [eax+2] ; packet length
	add	eax, [rtl8139_rx_buff_offset]
	add	eax, 4+3 ; packet header is 4 bytes long + dword alignment
	and	eax, not 3 ; dword alignment
	cmp	eax, RTL8139_RX_BUFFER_SIZE
	jl	.no_wrap
	sub	eax, RTL8139_RX_BUFFER_SIZE
.no_wrap:
	mov	[rtl8139_rx_buff_offset], eax
; update CAPR register
	sub	eax, 0x10 ; value 0x10 is a constant for CAPR
	add	edx, RTL8139_REG_CAPR - RTL8139_REG_COMMAND
	out	dx, ax
.finish:
; clear active interrupt sources
	mov	edx, [io_addr]
	add	edx, RTL8139_REG_ISR
	in	ax, dx
	out	dx, ax
	ret
.reset_rx:
	in	al, dx ; read command register
	push	eax
	and	al, not (1 shl RTL8139_BIT_RE)
	out	dx, al
	pop	eax
	out	dx, al
	add	edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
	mov	ax, RTL8139_RX_CONFIG
	out	dx, ax
	ret
 
rtl8139_cable:
	pusha
	mov	edx, [io_addr]
	add	edx, 0x58
	in	al,dx
	test	al,1 SHL 2
	jnz	.notconnected
	popa
	xor	al,al
	inc	al
	ret
       .notconnected:
	popa
	xor	al,al
	ret

Rev 425	Rev 431
1	$Revision: 425 $	1	$Revision: 431 $
2	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	2	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3	;; ;;	3	;; ;;
-		4	;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
-		5	;; Distributed under terms of the GNU General Public License ;;
-		6	;; ;;
4	;; RTL8139.INC ;;	7	;; RTL8139.INC ;;
5	;; ;;	8	;; ;;
6	;; Ethernet driver for Menuet OS ;;	9	;; Ethernet driver for Menuet OS ;;
7	;; ;;	10	;; ;;
8	;; Version 0.2 11 August 2003 ;;	11	;; Version 0.2 11 August 2003 ;;
9	;; ;;	12	;; ;;
10	;; Driver for chips of RealTek 8139 family ;;	13	;; Driver for chips of RealTek 8139 family ;;
11	;; References: ;;	14	;; References: ;;
12	;; www.realtek.com.hw - data sheets ;;	15	;; www.realtek.com.hw - data sheets ;;
13	;; rtl8139.c - linux driver ;;	16	;; rtl8139.c - linux driver ;;
14	;; 8139too.c - linux driver ;;	17	;; 8139too.c - linux driver ;;
15	;; ethernet driver template by Mike Hibbett ;;	18	;; ethernet driver template by Mike Hibbett ;;
16	;; ;;	19	;; ;;
17	;; The copyright statement is ;;	20	;; The copyright statement is ;;
18	;; ;;	21	;; ;;
19	;; GNU GENERAL PUBLIC LICENSE ;;	22	;; GNU GENERAL PUBLIC LICENSE ;;
20	;; Version 2, June 1991 ;;	23	;; Version 2, June 1991 ;;
21	;; ;;	24	;; ;;
22	;; Copyright 2003 Endre Kozma, ;;	25	;; Copyright 2003 Endre Kozma, ;;
23	;; endre.kozma@axelero.hu ;;	26	;; endre.kozma@axelero.hu ;;
24	;; ;;	27	;; ;;
25	;; See file COPYING for details ;;	28	;; See file COPYING for details ;;
26	;; ;;	29	;; ;;
27	;; 10.01.2007 Bugfix for l8139_transmit from Paolo Franchetti ;;	30	;; 10.01.2007 Bugfix for l8139_transmit from Paolo Franchetti ;;
28	;; ;;	31	;; ;;
29	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	32	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30	ETH_ALEN equ 6	33	ETH_ALEN equ 6
31	ETH_HLEN equ (2 * ETH_ALEN + 2)	34	ETH_HLEN equ (2 * ETH_ALEN + 2)
32	ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for	35	ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
33	; mininmum 64bytes frame length	36	; mininmum 64bytes frame length
34		37
35	PCI_REG_COMMAND equ 0x04 ; command register	38	PCI_REG_COMMAND equ 0x04 ; command register
36	PCI_BIT_PIO equ 0 ; bit0: io space control	39	PCI_BIT_PIO equ 0 ; bit0: io space control
37	PCI_BIT_MMIO equ 1 ; bit1: memory space control	40	PCI_BIT_MMIO equ 1 ; bit1: memory space control
38	PCI_BIT_MASTER equ 2 ; bit2: device acts as a PCI master	41	PCI_BIT_MASTER equ 2 ; bit2: device acts as a PCI master
39		42
40	RTL8139_REG_MAR0 equ 0x08 ; multicast filter register 0	43	RTL8139_REG_MAR0 equ 0x08 ; multicast filter register 0
41	RTL8139_REG_MAR4 equ 0x0c ; multicast filter register 4	44	RTL8139_REG_MAR4 equ 0x0c ; multicast filter register 4
42	RTL8139_REG_TSD0 equ 0x10 ; transmit status of descriptor	45	RTL8139_REG_TSD0 equ 0x10 ; transmit status of descriptor
43	RTL8139_REG_TSAD0 equ 0x20 ; transmit start address of descriptor	46	RTL8139_REG_TSAD0 equ 0x20 ; transmit start address of descriptor
44	RTL8139_REG_RBSTART equ 0x30 ; RxBuffer start address	47	RTL8139_REG_RBSTART equ 0x30 ; RxBuffer start address
45	RTL8139_REG_COMMAND equ 0x37 ; command register	48	RTL8139_REG_COMMAND equ 0x37 ; command register
46	RTL8139_REG_CAPR equ 0x38 ; current address of packet read	49	RTL8139_REG_CAPR equ 0x38 ; current address of packet read
47	RTL8139_REG_IMR equ 0x3c ; interrupt mask register	50	RTL8139_REG_IMR equ 0x3c ; interrupt mask register
48	RTL8139_REG_ISR equ 0x3e ; interrupt status register	51	RTL8139_REG_ISR equ 0x3e ; interrupt status register
49	RTL8139_REG_TXCONFIG equ 0x40 ; transmit configuration register	52	RTL8139_REG_TXCONFIG equ 0x40 ; transmit configuration register
50	RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0	53	RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0
51	RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1	54	RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1
52	RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2	55	RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2
53	RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3	56	RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3
54	RTL8139_REG_RXCONFIG equ 0x44 ; receive configuration register 0	57	RTL8139_REG_RXCONFIG equ 0x44 ; receive configuration register 0
55	RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0	58	RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0
56	RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1	59	RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1
57	RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2	60	RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2
58	RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3	61	RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3
59	RTL8139_REG_MPC equ 0x4c ; missed packet counter	62	RTL8139_REG_MPC equ 0x4c ; missed packet counter
60	RTL8139_REG_9346CR equ 0x50 ; serial eeprom 93C46 command register	63	RTL8139_REG_9346CR equ 0x50 ; serial eeprom 93C46 command register
61	RTL8139_REG_CONFIG1 equ 0x52 ; configuration register 1	64	RTL8139_REG_CONFIG1 equ 0x52 ; configuration register 1
62	RTL8139_REG_CONFIG4 equ 0x5a ; configuration register 4	65	RTL8139_REG_CONFIG4 equ 0x5a ; configuration register 4
63	RTL8139_REG_HLTCLK equ 0x5b ; undocumented halt clock register	66	RTL8139_REG_HLTCLK equ 0x5b ; undocumented halt clock register
64	RTL8139_REG_BMCR equ 0x62 ; basic mode control register	67	RTL8139_REG_BMCR equ 0x62 ; basic mode control register
65	RTL8139_REG_ANAR equ 0x66 ; auto negotiation advertisement register	68	RTL8139_REG_ANAR equ 0x66 ; auto negotiation advertisement register
66		69
67	; 5.1 packet header	70	; 5.1 packet header
68	RTL8139_BIT_RUNT equ 4 ; total packet length < 64 bytes	71	RTL8139_BIT_RUNT equ 4 ; total packet length < 64 bytes
69	RTL8139_BIT_LONG equ 3 ; total packet length > 4k	72	RTL8139_BIT_LONG equ 3 ; total packet length > 4k
70	RTL8139_BIT_CRC equ 2 ; crc error occured	73	RTL8139_BIT_CRC equ 2 ; crc error occured
71	RTL8139_BIT_FAE equ 1 ; frame alignment error occured	74	RTL8139_BIT_FAE equ 1 ; frame alignment error occured
72	RTL8139_BIT_ROK equ 0 ; received packet is ok	75	RTL8139_BIT_ROK equ 0 ; received packet is ok
73	; 5.4 command register	76	; 5.4 command register
74	RTL8139_BIT_RST equ 4 ; reset bit	77	RTL8139_BIT_RST equ 4 ; reset bit
75	RTL8139_BIT_RE equ 3 ; receiver enabled	78	RTL8139_BIT_RE equ 3 ; receiver enabled
76	RTL8139_BIT_TE equ 2 ; transmitter enabled	79	RTL8139_BIT_TE equ 2 ; transmitter enabled
77	RTL8139_BIT_BUFE equ 0 ; rx buffer is empty, no packet stored	80	RTL8139_BIT_BUFE equ 0 ; rx buffer is empty, no packet stored
78	; 5.6 interrupt status register	81	; 5.6 interrupt status register
79	RTL8139_BIT_ISR_TOK equ 2 ; transmit ok	82	RTL8139_BIT_ISR_TOK equ 2 ; transmit ok
80	RTL8139_BIT_ISR_RER equ 1 ; receive error interrupt	83	RTL8139_BIT_ISR_RER equ 1 ; receive error interrupt
81	RTL8139_BIT_ISR_ROK equ 0 ; receive ok	84	RTL8139_BIT_ISR_ROK equ 0 ; receive ok
82	; 5.7 transmit configyration register	85	; 5.7 transmit configyration register
83	RTL8139_BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst	86	RTL8139_BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst
84	RTL8139_BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16)	87	RTL8139_BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16)
85	; 5.8 receive configuration register	88	; 5.8 receive configuration register
86	RTL8139_BIT_RXFTH equ 13 ; Rx fifo threshold	89	RTL8139_BIT_RXFTH equ 13 ; Rx fifo threshold
87	RTL8139_BIT_RBLEN equ 11 ; Ring buffer length indicator	90	RTL8139_BIT_RBLEN equ 11 ; Ring buffer length indicator
88	RTL8139_BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst	91	RTL8139_BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst
89	RTL8139_BIT_NOWRAP equ 7 ; transfered data wrapping	92	RTL8139_BIT_NOWRAP equ 7 ; transfered data wrapping
90	RTL8139_BIT_9356SEL equ 6 ; eeprom selector 9346/9356	93	RTL8139_BIT_9356SEL equ 6 ; eeprom selector 9346/9356
91	RTL8139_BIT_AER equ 5 ; accept error packets	94	RTL8139_BIT_AER equ 5 ; accept error packets
92	RTL8139_BIT_AR equ 4 ; accept runt packets	95	RTL8139_BIT_AR equ 4 ; accept runt packets
93	RTL8139_BIT_AB equ 3 ; accept broadcast packets	96	RTL8139_BIT_AB equ 3 ; accept broadcast packets
94	RTL8139_BIT_AM equ 2 ; accept multicast packets	97	RTL8139_BIT_AM equ 2 ; accept multicast packets
95	RTL8139_BIT_APM equ 1 ; accept physical match packets	98	RTL8139_BIT_APM equ 1 ; accept physical match packets
96	RTL8139_BIT_AAP equ 0 ; accept all packets	99	RTL8139_BIT_AAP equ 0 ; accept all packets
97	; 5.9 93C46/93C56 command register	100	; 5.9 93C46/93C56 command register
98	RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1	101	RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1
99	RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0	102	RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0
100	RTL8139_BIT_93C46_EECS equ 3 ; chip select	103	RTL8139_BIT_93C46_EECS equ 3 ; chip select
101	RTL8139_BIT_93C46_EESK equ 2 ; serial data clock	104	RTL8139_BIT_93C46_EESK equ 2 ; serial data clock
102	RTL8139_BIT_93C46_EEDI equ 1 ; serial data input	105	RTL8139_BIT_93C46_EEDI equ 1 ; serial data input
103	RTL8139_BIT_93C46_EEDO equ 0 ; serial data output	106	RTL8139_BIT_93C46_EEDO equ 0 ; serial data output
104	; 5.11 configuration register 1	107	; 5.11 configuration register 1
105	RTL8139_BIT_LWACT equ 4 ; see RTL8139_REG_CONFIG1	108	RTL8139_BIT_LWACT equ 4 ; see RTL8139_REG_CONFIG1
106	RTL8139_BIT_SLEEP equ 1 ; sleep bit at older chips	109	RTL8139_BIT_SLEEP equ 1 ; sleep bit at older chips
107	RTL8139_BIT_PWRDWN equ 0 ; power down bit at older chips	110	RTL8139_BIT_PWRDWN equ 0 ; power down bit at older chips
108	RTL8139_BIT_PMEn equ 0 ; power management enabled	111	RTL8139_BIT_PMEn equ 0 ; power management enabled
109	; 5.14 configuration register 4	112	; 5.14 configuration register 4
110	RTL8139_BIT_LWPTN equ 2 ; see RTL8139_REG_CONFIG4	113	RTL8139_BIT_LWPTN equ 2 ; see RTL8139_REG_CONFIG4
111	; 6.2 transmit status register	114	; 6.2 transmit status register
112	RTL8139_BIT_ERTXTH equ 16 ; early TX threshold	115	RTL8139_BIT_ERTXTH equ 16 ; early TX threshold
113	RTL8139_BIT_TOK equ 15 ; transmit ok	116	RTL8139_BIT_TOK equ 15 ; transmit ok
114	RTL8139_BIT_OWN equ 13 ; tx DMA operation is completed	117	RTL8139_BIT_OWN equ 13 ; tx DMA operation is completed
115	; 6.18 basic mode control register	118	; 6.18 basic mode control register
116	RTL8139_BIT_ANE equ 12 ; auto negotiation enable	119	RTL8139_BIT_ANE equ 12 ; auto negotiation enable
117	; 6.20 auto negotiation advertisement register	120	; 6.20 auto negotiation advertisement register
118	RTL8139_BIT_TXFD equ 8 ; 100base-T full duplex	121	RTL8139_BIT_TXFD equ 8 ; 100base-T full duplex
119	RTL8139_BIT_TX equ 7 ; 100base-T	122	RTL8139_BIT_TX equ 7 ; 100base-T
120	RTL8139_BIT_10FD equ 6 ; 10base-T full duplex	123	RTL8139_BIT_10FD equ 6 ; 10base-T full duplex
121	RTL8139_BIT_10 equ 5 ; 10base-T	124	RTL8139_BIT_10 equ 5 ; 10base-T
122	RTL8139_BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001	125	RTL8139_BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001
123	; RX/TX buffer size	126	; RX/TX buffer size
124	RTL8139_RBLEN equ 0 ; 0==8K 1==16k 2==32k 3==64k	127	RTL8139_RBLEN equ 0 ; 0==8K 1==16k 2==32k 3==64k
125	RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN)	128	RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN)
126	MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC	129	MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC
127	RTL8139_NUM_TX_DESC equ 4	130	RTL8139_NUM_TX_DESC equ 4
128	RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC)	131	RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC)
129	RTL8139_TXRR equ 8 ; total retries = 16+(TXRR*16)	132	RTL8139_TXRR equ 8 ; total retries = 16+(TXRR*16)
130	RTL8139_TX_MXDMA equ 6 ; 0==16 1==32 2==64 3==128	133	RTL8139_TX_MXDMA equ 6 ; 0==16 1==32 2==64 3==128
131	; 4==256 5==512 6==1024 7==2048	134	; 4==256 5==512 6==1024 7==2048
132	RTL8139_ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256	135	RTL8139_ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256
133	RTL8139_RX_MXDMA equ 7 ; 0==16 1==32 2==64 3==128	136	RTL8139_RX_MXDMA equ 7 ; 0==16 1==32 2==64 3==128
134	; 4==256 5==512 6==1024 7==unlimited	137	; 4==256 5==512 6==1024 7==unlimited
135	RTL8139_RXFTH equ 7 ; 0==16 1==32 2==64 3==128	138	RTL8139_RXFTH equ 7 ; 0==16 1==32 2==64 3==128
136	; 4==256 5==512 6==1024 7==no threshold	139	; 4==256 5==512 6==1024 7==no threshold
137	RTL8139_RX_CONFIG equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \	140	RTL8139_RX_CONFIG equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \
138	or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \	141	or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \
139	or (1 shl RTL8139_BIT_NOWRAP) \	142	or (1 shl RTL8139_BIT_NOWRAP) \
140	or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \	143	or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \
141	or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \	144	or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \
142	or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \	145	or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \
143	or (1 shl RTL8139_BIT_AM))	146	or (1 shl RTL8139_BIT_AM))
144	RTL8139_TX_TIMEOUT equ 30 ; 300 milliseconds timeout	147	RTL8139_TX_TIMEOUT equ 30 ; 300 milliseconds timeout
145		148
146	EE_93C46_REG_ETH_ID equ 7 ; MAC offset	149	EE_93C46_REG_ETH_ID equ 7 ; MAC offset
147	EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address	150	EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address
148	EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address	151	EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address
149	EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address	152	EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address
150	EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress	153	EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress
151		154
152	VER_RTL8139 equ 1100000b	155	VER_RTL8139 equ 1100000b
153	VER_RTL8139A equ 1110000b	156	VER_RTL8139A equ 1110000b
154	; VER_RTL8139AG equ 1110100b	157	; VER_RTL8139AG equ 1110100b
155	VER_RTL8139B equ 1111000b	158	VER_RTL8139B equ 1111000b
156	VER_RTL8130 equ VER_RTL8139B	159	VER_RTL8130 equ VER_RTL8139B
157	VER_RTL8139C equ 1110100b	160	VER_RTL8139C equ 1110100b
158	VER_RTL8100 equ 1111010b	161	VER_RTL8100 equ 1111010b
159	VER_RTL8100B equ 1110101b	162	VER_RTL8100B equ 1110101b
160	VER_RTL8139D equ VER_RTL8100B	163	VER_RTL8139D equ VER_RTL8100B
161	VER_RTL8139CP equ 1110110b	164	VER_RTL8139CP equ 1110110b
162	VER_RTL8101 equ 1110111b	165	VER_RTL8101 equ 1110111b
163		166
164	IDX_RTL8139 equ 0	167	IDX_RTL8139 equ 0
165	IDX_RTL8139A equ 1	168	IDX_RTL8139A equ 1
166	IDX_RTL8139B equ 2	169	IDX_RTL8139B equ 2
167	IDX_RTL8139C equ 3	170	IDX_RTL8139C equ 3
168	IDX_RTL8100 equ 4	171	IDX_RTL8100 equ 4
169	IDX_RTL8139D equ 5	172	IDX_RTL8139D equ 5
170	IDX_RTL8139D equ 6	173	IDX_RTL8139D equ 6
171	IDX_RTL8101 equ 7	174	IDX_RTL8101 equ 7
172		175
173		176
174	; These two must be 4 byte aligned ( which they are )	177	; These two must be 4 byte aligned ( which they are )
175	rtl8139_rx_buff equ eth_data_start	178	rtl8139_rx_buff equ eth_data_start
176	rtl8139_tx_buff equ rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE)	179	rtl8139_tx_buff equ rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE)
177		180
178	uglobal	181	uglobal
179	align 4	182	align 4
180	rtl8139_rx_buff_offset: dd 0	183	rtl8139_rx_buff_offset: dd 0
181	curr_tx_desc dd 0	184	curr_tx_desc dd 0
182	endg	185	endg
183		186
184	iglobal	187	iglobal
185	hw_ver_array: db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C	188	hw_ver_array: db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C
186	db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101	189	db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101
187	HW_VER_ARRAY_SIZE = $-hw_ver_array	190	HW_VER_ARRAY_SIZE = $-hw_ver_array
188	endg	191	endg
189		192
190	uglobal	193	uglobal
191	hw_ver_id: db 0	194	hw_ver_id: db 0
192	endg	195	endg
193		196
194	;***************************************************************************	197	;***************************************************************************
195	; Function	198	; Function
196	; rtl8139_probe	199	; rtl8139_probe
197	; Description	200	; Description
198	; Searches for an ethernet card, enables it and clears the rx buffer	201	; Searches for an ethernet card, enables it and clears the rx buffer
199	; If a card was found, it enables the ethernet -> TCPIP link	202	; If a card was found, it enables the ethernet -> TCPIP link
200	; Destroyed registers	203	; Destroyed registers
201	; eax, ebx, ecx, edx	204	; eax, ebx, ecx, edx
202	;	205	;
203	;***************************************************************************	206	;***************************************************************************
204	rtl8139_probe:	207	rtl8139_probe:
205	; enable the device	208	; enable the device
206	mov al, 2	209	mov al, 2
207	mov ah, [pci_bus]	210	mov ah, [pci_bus]
208	mov bh, [pci_dev]	211	mov bh, [pci_dev]
209	mov bl, PCI_REG_COMMAND	212	mov bl, PCI_REG_COMMAND
210	call pci_read_reg	213	call pci_read_reg
211	mov cx, ax	214	mov cx, ax
212	or cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO)	215	or cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO)
213	and cl, not (1 shl PCI_BIT_MMIO)	216	and cl, not (1 shl PCI_BIT_MMIO)
214	mov al, 2	217	mov al, 2
215	mov ah, [pci_bus]	218	mov ah, [pci_bus]
216	mov bh, [pci_dev]	219	mov bh, [pci_dev]
217	mov bl, PCI_REG_COMMAND	220	mov bl, PCI_REG_COMMAND
218	call pci_write_reg	221	call pci_write_reg
219	; get chip version	222	; get chip version
220	mov edx, [io_addr]	223	mov edx, [io_addr]
221	add edx, RTL8139_REG_TXCONFIG_2	224	add edx, RTL8139_REG_TXCONFIG_2
222	in ax, dx	225	in ax, dx
223	shr ah, 2	226	shr ah, 2
224	shr ax, 6	227	shr ax, 6
225	and al, 01111111b	228	and al, 01111111b
226	mov ecx, HW_VER_ARRAY_SIZE-1	229	mov ecx, HW_VER_ARRAY_SIZE-1
227	.chip_ver_loop:	230	.chip_ver_loop:
228	cmp al, [hw_ver_array+ecx]	231	cmp al, [hw_ver_array+ecx]
229	je .chip_ver_found	232	je .chip_ver_found
230	dec ecx	233	dec ecx
231	jns .chip_ver_loop	234	jns .chip_ver_loop
232	xor cl, cl ; default RTL8139	235	xor cl, cl ; default RTL8139
233	.chip_ver_found:	236	.chip_ver_found:
234	mov [hw_ver_id], cl	237	mov [hw_ver_id], cl
235	; wake up the chip	238	; wake up the chip
236	mov edx, [io_addr]	239	mov edx, [io_addr]
237	add edx, RTL8139_REG_HLTCLK	240	add edx, RTL8139_REG_HLTCLK
238	mov al, 'R' ; run the clock	241	mov al, 'R' ; run the clock
239	out dx, al	242	out dx, al
240	; unlock config and BMCR registers	243	; unlock config and BMCR registers
241	add edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK	244	add edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK
242	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)	245	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
243	out dx, al	246	out dx, al
244	; enable power management	247	; enable power management
245	add edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR	248	add edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR
246	in al, dx	249	in al, dx
247	cmp byte [hw_ver_id], IDX_RTL8139B	250	cmp byte [hw_ver_id], IDX_RTL8139B
248	jl .old_chip	251	jl .old_chip
249	; set LWAKE pin to active high (default value).	252	; set LWAKE pin to active high (default value).
250	; it is for Wake-On-LAN functionality of some motherboards.	253	; it is for Wake-On-LAN functionality of some motherboards.
251	; this signal is used to inform the motherboard to execute a wake-up process.	254	; this signal is used to inform the motherboard to execute a wake-up process.
252	; only at newer chips.	255	; only at newer chips.
253	or al, (1 shl RTL8139_BIT_PMEn)	256	or al, (1 shl RTL8139_BIT_PMEn)
254	and al, not (1 shl RTL8139_BIT_LWACT)	257	and al, not (1 shl RTL8139_BIT_LWACT)
255	out dx, al	258	out dx, al
256	add edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1	259	add edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1
257	in al, dx	260	in al, dx
258	and al, not (1 shl RTL8139_BIT_LWPTN)	261	and al, not (1 shl RTL8139_BIT_LWPTN)
259	out dx, al	262	out dx, al
260	jmp .finish_wake_up	263	jmp .finish_wake_up
261	.old_chip:	264	.old_chip:
262	; wake up older chips	265	; wake up older chips
263	and al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN))	266	and al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN))
264	out dx, al	267	out dx, al
265	.finish_wake_up:	268	.finish_wake_up:
266	; lock config and BMCR registers	269	; lock config and BMCR registers
267	xor al, al	270	xor al, al
268	mov edx, [io_addr]	271	mov edx, [io_addr]
269	add edx, RTL8139_REG_9346CR	272	add edx, RTL8139_REG_9346CR
270	out dx, al	273	out dx, al
271	;***************************************************************************	274	;***************************************************************************
272	; Function	275	; Function
273	; rt8139_reset	276	; rt8139_reset
274	; Description	277	; Description
275	; Place the chip (ie, the ethernet card) into a virgin state	278	; Place the chip (ie, the ethernet card) into a virgin state
276	; Destroyed registers	279	; Destroyed registers
277	; eax, ebx, ecx, edx	280	; eax, ebx, ecx, edx
278	;	281	;
279	;***************************************************************************	282	;***************************************************************************
280	rtl8139_reset:	283	rtl8139_reset:
281	mov edx, [io_addr]	284	mov edx, [io_addr]
282	add edx, RTL8139_REG_COMMAND	285	add edx, RTL8139_REG_COMMAND
283	mov al, 1 shl RTL8139_BIT_RST	286	mov al, 1 shl RTL8139_BIT_RST
284	out dx, al	287	out dx, al
285	mov cx, 1000 ; wait no longer for the reset	288	mov cx, 1000 ; wait no longer for the reset
286	.wait_for_reset:	289	.wait_for_reset:
287	in al, dx	290	in al, dx
288	test al, 1 shl RTL8139_BIT_RST	291	test al, 1 shl RTL8139_BIT_RST
289	jz .reset_completed ; RST remains 1 during reset	292	jz .reset_completed ; RST remains 1 during reset
290	dec cx	293	dec cx
291	jns .wait_for_reset	294	jns .wait_for_reset
292	.reset_completed:	295	.reset_completed:
293	; get MAC (hardware address)	296	; get MAC (hardware address)
294	mov ecx, 2	297	mov ecx, 2
295	.mac_read_loop:	298	.mac_read_loop:
296	lea eax, [EE_93C46_REG_ETH_ID+ecx]	299	lea eax, [EE_93C46_REG_ETH_ID+ecx]
297	push ecx	300	push ecx
298	call rtl8139_read_eeprom	301	call rtl8139_read_eeprom
299	pop ecx	302	pop ecx
300	mov [node_addr+ecx*2], ax	303	mov [node_addr+ecx*2], ax
301	dec ecx	304	dec ecx
302	jns .mac_read_loop	305	jns .mac_read_loop
303	; unlock config and BMCR registers	306	; unlock config and BMCR registers
304	mov edx, [io_addr]	307	mov edx, [io_addr]
305	add edx, RTL8139_REG_9346CR	308	add edx, RTL8139_REG_9346CR
306	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)	309	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
307	out dx, al	310	out dx, al
308	; initialize multicast registers (no filtering)	311	; initialize multicast registers (no filtering)
309	mov eax, 0xffffffff	312	mov eax, 0xffffffff
310	add edx, RTL8139_REG_MAR0 - RTL8139_REG_9346CR	313	add edx, RTL8139_REG_MAR0 - RTL8139_REG_9346CR
311	out dx, eax	314	out dx, eax
312	add edx, RTL8139_REG_MAR4 - RTL8139_REG_MAR0	315	add edx, RTL8139_REG_MAR4 - RTL8139_REG_MAR0
313	out dx, eax	316	out dx, eax
314	; enable Rx/Tx	317	; enable Rx/Tx
315	mov al, (1 shl RTL8139_BIT_RE) or (1 shl RTL8139_BIT_TE)	318	mov al, (1 shl RTL8139_BIT_RE) or (1 shl RTL8139_BIT_TE)
316	add edx, RTL8139_REG_COMMAND - RTL8139_REG_MAR4	319	add edx, RTL8139_REG_COMMAND - RTL8139_REG_MAR4
317	out dx, al	320	out dx, al
318	; 32k Rxbuffer, unlimited dma burst, no wrapping, no rx threshold	321	; 32k Rxbuffer, unlimited dma burst, no wrapping, no rx threshold
319	; accept broadcast packets, accept physical match packets	322	; accept broadcast packets, accept physical match packets
320	mov ax, RTL8139_RX_CONFIG	323	mov ax, RTL8139_RX_CONFIG
321	add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND	324	add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
322	out dx, ax	325	out dx, ax
323	; 1024 bytes DMA burst, total retries = 16 + 8 * 16 = 144	326	; 1024 bytes DMA burst, total retries = 16 + 8 * 16 = 144
324	mov ax, (RTL8139_TX_MXDMA shl RTL8139_BIT_TX_MXDMA) \	327	mov ax, (RTL8139_TX_MXDMA shl RTL8139_BIT_TX_MXDMA) \
325	or (RTL8139_TXRR shl RTL8139_BIT_TXRR)	328	or (RTL8139_TXRR shl RTL8139_BIT_TXRR)
326	add edx, RTL8139_REG_TXCONFIG - RTL8139_REG_RXCONFIG	329	add edx, RTL8139_REG_TXCONFIG - RTL8139_REG_RXCONFIG
327	out dx, ax	330	out dx, ax
328	; enable auto negotiation	331	; enable auto negotiation
329	add edx, RTL8139_REG_BMCR - RTL8139_REG_TXCONFIG	332	add edx, RTL8139_REG_BMCR - RTL8139_REG_TXCONFIG
330	in ax, dx	333	in ax, dx
331	or ax, (1 shl RTL8139_BIT_ANE)	334	or ax, (1 shl RTL8139_BIT_ANE)
332	out dx, ax	335	out dx, ax
333	; set auto negotiation advertisement	336	; set auto negotiation advertisement
334	add edx, RTL8139_REG_ANAR - RTL8139_REG_BMCR	337	add edx, RTL8139_REG_ANAR - RTL8139_REG_BMCR
335	in ax, dx	338	in ax, dx
336	or ax, (1 shl RTL8139_BIT_SELECTOR) or (1 shl RTL8139_BIT_10) \	339	or ax, (1 shl RTL8139_BIT_SELECTOR) or (1 shl RTL8139_BIT_10) \
337	or (1 shl RTL8139_BIT_10FD) or (1 shl RTL8139_BIT_TX) \	340	or (1 shl RTL8139_BIT_10FD) or (1 shl RTL8139_BIT_TX) \
338	or (1 shl RTL8139_BIT_TXFD)	341	or (1 shl RTL8139_BIT_TXFD)
339	out dx, ax	342	out dx, ax
340	; lock config and BMCR registers	343	; lock config and BMCR registers
341	xor eax, eax	344	xor eax, eax
342	add edx, RTL8139_REG_9346CR - RTL8139_REG_ANAR	345	add edx, RTL8139_REG_9346CR - RTL8139_REG_ANAR
343	out dx, al	346	out dx, al
344	; init RX/TX pointers	347	; init RX/TX pointers
345	mov [rtl8139_rx_buff_offset], eax	348	mov [rtl8139_rx_buff_offset], eax
346	mov [curr_tx_desc], eax	349	mov [curr_tx_desc], eax
347	; clear missing packet counter	350	; clear missing packet counter
348	add edx, RTL8139_REG_MPC - RTL8139_REG_9346CR	351	add edx, RTL8139_REG_MPC - RTL8139_REG_9346CR
349	out dx, eax	352	out dx, eax
350	; disable all interrupts	353	; disable all interrupts
351	add edx, RTL8139_REG_IMR - RTL8139_REG_MPC	354	add edx, RTL8139_REG_IMR - RTL8139_REG_MPC
352	out dx, ax	355	out dx, ax
353	; set RxBuffer address, init RX buffer offset, init TX ring	356	; set RxBuffer address, init RX buffer offset, init TX ring
354	mov eax, rtl8139_rx_buff	357	mov eax, rtl8139_rx_buff
355	add edx, RTL8139_REG_RBSTART - RTL8139_REG_IMR	358	add edx, RTL8139_REG_RBSTART - RTL8139_REG_IMR
356	out dx, eax	359	out dx, eax
357	; Indicate that we have successfully reset the card	360	; Indicate that we have successfully reset the card
358	mov eax, [pci_data]	361	mov eax, [pci_data]
359	mov [eth_status], eax	362	mov [eth_status], eax
360	ret	363	ret
361		364
362	;***************************************************************************	365	;***************************************************************************
363	; Function	366	; Function
364	; rtl8139_read_eeprom	367	; rtl8139_read_eeprom
365	; Description	368	; Description
366	; reads eeprom type 93c46 and 93c56	369	; reads eeprom type 93c46 and 93c56
367	; Parameters	370	; Parameters
368	; al - word to be read (6bit in case of 93c46 and 8bit otherwise)	371	; al - word to be read (6bit in case of 93c46 and 8bit otherwise)
369	; Return value	372	; Return value
370	; ax - word read in	373	; ax - word read in
371	; Destroyed register(s)	374	; Destroyed register(s)
372	; eax, cx, ebx, edx	375	; eax, cx, ebx, edx
373	;	376	;
374	;***************************************************************************	377	;***************************************************************************
375	rtl8139_read_eeprom:	378	rtl8139_read_eeprom:
376	movzx ebx, al	379	movzx ebx, al
377	mov edx, [io_addr]	380	mov edx, [io_addr]
378	add edx, RTL8139_REG_RXCONFIG	381	add edx, RTL8139_REG_RXCONFIG
379	in al, dx	382	in al, dx
380	test al, (1 shl RTL8139_BIT_9356SEL)	383	test al, (1 shl RTL8139_BIT_9356SEL)
381	jz .type_93c46	384	jz .type_93c46
382	; and bl, 01111111b ; don't care first bit	385	; and bl, 01111111b ; don't care first bit
383	or bx, EE_93C56_READ_CMD ; it contains start bit	386	or bx, EE_93C56_READ_CMD ; it contains start bit
384	mov cx, EE_93C56_CMD_LENGTH-1 ; cmd_loop counter	387	mov cx, EE_93C56_CMD_LENGTH-1 ; cmd_loop counter
385	jmp .read_eeprom	388	jmp .read_eeprom
386	.type_93c46:	389	.type_93c46:
387	and bl, 00111111b	390	and bl, 00111111b
388	or bx, EE_93C46_READ_CMD ; it contains start bit	391	or bx, EE_93C46_READ_CMD ; it contains start bit
389	mov cx, EE_93C46_CMD_LENGTH-1 ; cmd_loop counter	392	mov cx, EE_93C46_CMD_LENGTH-1 ; cmd_loop counter
390	.read_eeprom:	393	.read_eeprom:
391	add edx, RTL8139_REG_9346CR - RTL8139_REG_RXCONFIG_0	394	add edx, RTL8139_REG_9346CR - RTL8139_REG_RXCONFIG_0
392	; mov al, (1 shl RTL8139_BIT_93C46_EEM1)	395	; mov al, (1 shl RTL8139_BIT_93C46_EEM1)
393	; out dx, al	396	; out dx, al
394	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \	397	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
395	or (1 shl RTL8139_BIT_93C46_EECS) ; wake up the eeprom	398	or (1 shl RTL8139_BIT_93C46_EECS) ; wake up the eeprom
396	out dx, al	399	out dx, al
397	.cmd_loop:	400	.cmd_loop:
398	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)	401	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
399	bt bx, cx	402	bt bx, cx
400	jnc .zero_bit	403	jnc .zero_bit
401	or al, (1 shl RTL8139_BIT_93C46_EEDI)	404	or al, (1 shl RTL8139_BIT_93C46_EEDI)
402	.zero_bit:	405	.zero_bit:
403	out dx, al	406	out dx, al
404	; push eax	407	; push eax
405	; in eax, dx ; eeprom delay	408	; in eax, dx ; eeprom delay
406	; pop eax	409	; pop eax
407	or al, (1 shl RTL8139_BIT_93C46_EESK)	410	or al, (1 shl RTL8139_BIT_93C46_EESK)
408	out dx, al	411	out dx, al
409	; in eax, dx ; eeprom delay	412	; in eax, dx ; eeprom delay
410	dec cx	413	dec cx
411	jns .cmd_loop	414	jns .cmd_loop
412	; in eax, dx ; eeprom delay	415	; in eax, dx ; eeprom delay
413	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)	416	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
414	out dx, al	417	out dx, al
415	mov cl, 0xf	418	mov cl, 0xf
416	.read_loop:	419	.read_loop:
417	shl ebx, 1	420	shl ebx, 1
418	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \	421	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
419	or (1 shl RTL8139_BIT_93C46_EECS) \	422	or (1 shl RTL8139_BIT_93C46_EECS) \
420	or (1 shl RTL8139_BIT_93C46_EESK)	423	or (1 shl RTL8139_BIT_93C46_EESK)
421	out dx, al	424	out dx, al
422	; in eax, dx ; eeprom delay	425	; in eax, dx ; eeprom delay
423	in al, dx	426	in al, dx
424	and al, (1 shl RTL8139_BIT_93C46_EEDO)	427	and al, (1 shl RTL8139_BIT_93C46_EEDO)
425	jz .dont_set	428	jz .dont_set
426	inc ebx	429	inc ebx
427	.dont_set:	430	.dont_set:
428	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \	431	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
429	or (1 shl RTL8139_BIT_93C46_EECS)	432	or (1 shl RTL8139_BIT_93C46_EECS)
430	out dx, al	433	out dx, al
431	; in eax, dx ; eeprom delay	434	; in eax, dx ; eeprom delay
432	dec cl	435	dec cl
433	jns .read_loop	436	jns .read_loop
434	xor al, al	437	xor al, al
435	out dx, al	438	out dx, al
436	mov ax, bx	439	mov ax, bx
437	ret	440	ret
438		441
439	;***************************************************************************	442	;***************************************************************************
440	; Function	443	; Function
441	; rtl8139_transmit	444	; rtl8139_transmit
442	; Description	445	; Description
443	; Transmits a packet of data via the ethernet card	446	; Transmits a packet of data via the ethernet card
444	; Pointer to 48 bit destination address in edi	447	; Pointer to 48 bit destination address in edi
445	; Type of packet in bx	448	; Type of packet in bx
446	; Size of packet in ecx	449	; Size of packet in ecx
447	; Pointer to packet data in esi	450	; Pointer to packet data in esi
448	; Destroyed registers	451	; Destroyed registers
449	; eax, edx, esi, edi	452	; eax, edx, esi, edi
450	; ToDo	453	; ToDo
451	; for waiting of timeout the rtl8139 internal timer	454	; for waiting of timeout the rtl8139 internal timer
452	; should be used	455	; should be used
453	;	456	;
454	;***************************************************************************	457	;***************************************************************************
455	rtl8139_transmit:	458	rtl8139_transmit:
456	cmp ecx, MAX_ETH_FRAME_SIZE	459	cmp ecx, MAX_ETH_FRAME_SIZE
457	jg .finish ; packet is too long	460	jg .finish ; packet is too long
458	push ecx	461	push ecx
459	; check descriptor	462	; check descriptor
460	mov ecx, [curr_tx_desc]	463	mov ecx, [curr_tx_desc]
461	mov edx, [io_addr]	464	mov edx, [io_addr]
462	lea edx, [edx+ecx*4+RTL8139_REG_TSD0]	465	lea edx, [edx+ecx*4+RTL8139_REG_TSD0]
463	push edx ebx	466	push edx ebx
464	in ax, dx	467	in ax, dx
465	test ax, 0x1fff ; or no size given	468	test ax, 0x1fff ; or no size given
466	jz .send_packet	469	jz .send_packet
467	and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)	470	and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
468	cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)	471	cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
469	jz .send_packet	472	jz .send_packet
470	; wait for timeout	473	; wait for timeout
471	mov ebx, RTL8139_TX_TIMEOUT	474	mov ebx, RTL8139_TX_TIMEOUT
472	mov eax, 0x5 ; delay x/100 secs	475	mov eax, 0x5 ; delay x/100 secs
473	int 0x40	476	int 0x40
474	in ax, dx	477	in ax, dx
475	and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)	478	and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
476	cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)	479	cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
477	jz .send_packet	480	jz .send_packet
478	; chip hung, reset it	481	; chip hung, reset it
479	call rtl8139_reset	482	call rtl8139_reset
480	; reset the card	483	; reset the card
481	.send_packet:	484	.send_packet:
482	; calculate tx_buffer address	485	; calculate tx_buffer address
483	pop ebx	486	pop ebx
484	push esi	487	push esi
485	mov eax, MAX_ETH_FRAME_SIZE	488	mov eax, MAX_ETH_FRAME_SIZE
486	mul dword [curr_tx_desc]	489	mul dword [curr_tx_desc]
487	mov esi, edi	490	mov esi, edi
488	lea edi, [rtl8139_tx_buff+eax]	491	lea edi, [rtl8139_tx_buff+eax]
489	mov eax, edi	492	mov eax, edi
490	cld	493	cld
491	; copy destination address	494	; copy destination address
492	movsd	495	movsd
493	movsw	496	movsw
494	; copy source address	497	; copy source address
495	mov esi, node_addr	498	mov esi, node_addr
496	movsd	499	movsd
497	movsw	500	movsw

Subversion Repositories Kolibri OS

(root)/kernel/trunk/network/eth_drv/drivers/rtl8139.inc – Rev 425 → 431