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Rev 7132 Rev 7136
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;; Copyright (C) KolibriOS team 2004-2017. All rights reserved. ;;
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;; Copyright (C) KolibriOS team 2004-2017. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;;                                                              ;;
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;;                                                              ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision: 7132 $
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$Revision: 7136 $
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dpl0    equ  10010000b      ; data read       dpl0
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dpl0    =  10010000b      ; data read       dpl0
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drw0    equ  10010010b      ; data read/write dpl0
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drw0    =  10010010b      ; data read/write dpl0
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drw3    equ  11110010b      ; data read/write dpl3
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drw3    =  11110010b      ; data read/write dpl3
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cpl0    equ  10011010b      ; code read dpl0
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cpl0    =  10011010b      ; code read dpl0
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cpl3    equ  11111010b      ; code read dpl3
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cpl3    =  11111010b      ; code read dpl3
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D32     equ  01000000b      ; 32bit segment
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D32     =  01000000b      ; 32bit segment
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G32     equ  10000000b      ; page gran
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G32     =  10000000b      ; page gran
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;;;;;;;;;;;;cpu_caps flags;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;cpu_caps flags;;;;;;;;;;;;;;;;
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CPU_386        equ 3
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CPU_386        = 3
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CPU_486        equ 4
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CPU_486        = 4
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CPU_PENTIUM    equ 5
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CPU_PENTIUM    = 5
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CPU_P6         equ 6
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CPU_P6         = 6
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CPU_PENTIUM4   equ 0x0F
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CPU_PENTIUM4   = 0x0F
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29 
CAPS_FPU       equ    00 ;on-chip x87 floating point unit
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CAPS_FPU       =    00 ;on-chip x87 floating point unit
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CAPS_VME       equ    01 ;virtual-mode enhancements
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CAPS_VME       =    01 ;virtual-mode enhancements
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CAPS_DE        equ    02 ;debugging extensions
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CAPS_DE        =    02 ;debugging extensions
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CAPS_PSE       equ    03 ;page-size extensions
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CAPS_PSE       =    03 ;page-size extensions
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CAPS_TSC       equ    04 ;time stamp counter
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CAPS_TSC       =    04 ;time stamp counter
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CAPS_MSR       equ    05 ;model-specific registers
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CAPS_MSR       =    05 ;model-specific registers
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CAPS_PAE       equ    06 ;physical-address extensions
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CAPS_PAE       =    06 ;physical-address extensions
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CAPS_MCE       equ    07 ;machine check exception
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CAPS_MCE       =    07 ;machine check exception
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CAPS_CX8       equ    08 ;CMPXCHG8B instruction
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CAPS_CX8       =    08 ;CMPXCHG8B instruction
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CAPS_APIC      equ    09 ;on-chip advanced programmable
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CAPS_APIC      =    09 ;on-chip advanced programmable
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                         ; interrupt controller
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                       ;interrupt controller
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;                     10 ;unused
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;                   10 ;unused
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CAPS_SEP       equ    11 ;SYSENTER and SYSEXIT instructions
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CAPS_SEP       =    11 ;SYSENTER and SYSEXIT instructions
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CAPS_MTRR      equ    12 ;memory-type range registers
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CAPS_MTRR      =    12 ;memory-type range registers
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CAPS_PGE       equ    13 ;page global extension
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CAPS_PGE       =    13 ;page global extension
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CAPS_MCA       equ    14 ;machine check architecture
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CAPS_MCA       =    14 ;machine check architecture
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CAPS_CMOV      equ    15 ;conditional move instructions
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CAPS_CMOV      =    15 ;conditional move instructions
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CAPS_PAT       equ    16 ;page attribute table
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CAPS_PAT       =    16 ;page attribute table
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CAPS_PSE36     equ    17 ;page-size extensions
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CAPS_PSE36     =    17 ;page-size extensions
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CAPS_PSN       equ    18 ;processor serial number
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CAPS_PSN       =    18 ;processor serial number
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CAPS_CLFLUSH   equ    19 ;CLFUSH instruction
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CAPS_CLFLUSH   =    19 ;CLFUSH instruction
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CAPS_DS        equ    21 ;debug store
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CAPS_DS        =    21 ;debug store
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CAPS_ACPI      equ    22 ;thermal monitor and software
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CAPS_ACPI      =    22 ;thermal monitor and software
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                         ;controlled clock supported
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                       ;controlled clock supported
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CAPS_MMX       equ    23 ;MMX instructions
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CAPS_MMX       =    23 ;MMX instructions
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CAPS_FXSR      equ    24 ;FXSAVE and FXRSTOR instructions
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CAPS_FXSR      =    24 ;FXSAVE and FXRSTOR instructions
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CAPS_SSE       equ    25 ;SSE instructions
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CAPS_SSE       =    25 ;SSE instructions
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CAPS_SSE2      equ    26 ;SSE2 instructions
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CAPS_SSE2      =    26 ;SSE2 instructions
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CAPS_SS        equ    27 ;self-snoop
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CAPS_SS        =    27 ;self-snoop
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CAPS_HTT       equ    28 ;hyper-threading technology
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CAPS_HTT       =    28 ;hyper-threading technology
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CAPS_TM        equ    29 ;thermal monitor supported
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CAPS_TM        =    29 ;thermal monitor supported
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CAPS_IA64      equ    30 ;IA64 capabilities
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CAPS_IA64      =    30 ;IA64 capabilities
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CAPS_PBE       equ    31 ;pending break enable
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CAPS_PBE       =    31 ;pending break enable
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;ecx
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;ecx
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CAPS_SSE3      equ    32 ;SSE3 instructions
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CAPS_SSE3      =    32 ;SSE3 instructions
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;                     33
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;                   33
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;                     34
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;                   34
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CAPS_MONITOR   equ    35 ;MONITOR/MWAIT instructions
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CAPS_MONITOR   =    35 ;MONITOR/MWAIT instructions
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CAPS_DS_CPL    equ    36 ;
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CAPS_DS_CPL    =    36 ;
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CAPS_VMX       equ    37 ;virtual mode extensions
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CAPS_VMX       =    37 ;virtual mode extensions
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;                     38 ;
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;                   38 ;
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CAPS_EST       equ    39 ;enhansed speed step
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CAPS_EST       =    39 ;enhansed speed step
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CAPS_TM2       equ    40 ;thermal monitor2 supported
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CAPS_TM2       =    40 ;thermal monitor2 supported
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;                     41
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;                   41
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CAPS_CID       equ    42 ;
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CAPS_CID       =    42 ;
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;                     43
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;                   43
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;                     44
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;                   44
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CAPS_CX16      equ    45 ;CMPXCHG16B instruction
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CAPS_CX16      =    45 ;CMPXCHG16B instruction
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CAPS_xTPR      equ    46 ;
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CAPS_xTPR      =    46 ;
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CAPS_XSAVE     equ    (32 + 26) ; XSAVE and XRSTOR instructions
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CAPS_XSAVE     =    32 + 26 ; XSAVE and XRSTOR instructions
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CAPS_OSXSAVE   equ    (32 + 27)
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CAPS_OSXSAVE   =    32 + 27
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; A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable
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; A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable
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; XSETBV/XGETBV instructions to access XCR0 and to support processor extended
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; XSETBV/XGETBV instructions to access XCR0 and to support processor extended
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; state management using XSAVE/XRSTOR.
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; state management using XSAVE/XRSTOR.
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CAPS_AVX       equ    (32 + 28) ; not AVX2
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CAPS_AVX       =    32 + 28 ; not AVX2
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;
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;
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;reserved
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;reserved
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;
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;
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;ext edx /ecx
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;ext edx /ecx
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CAPS_SYSCAL    equ    64 ;
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CAPS_SYSCAL    =    64 ;
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CAPS_XD        equ    65 ;execution disable
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CAPS_XD        =    65 ;execution disable
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CAPS_FFXSR     equ    66 ;
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CAPS_FFXSR     =    66 ;
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CAPS_RDTSCP    equ    67 ;
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CAPS_RDTSCP    =    67 ;
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CAPS_X64       equ    68 ;
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CAPS_X64       =    68 ;
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CAPS_3DNOW     equ    69 ;
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CAPS_3DNOW     =    69 ;
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CAPS_3DNOWEXT  equ    70 ;
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CAPS_3DNOWEXT  =    70 ;
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CAPS_LAHF      equ    71 ;
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CAPS_LAHF      =    71 ;
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CAPS_CMP_LEG   equ    72 ;
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CAPS_CMP_LEG   =    72 ;
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CAPS_SVM       equ    73 ;secure virual machine
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CAPS_SVM       =    73 ;secure virual machine
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CAPS_ALTMOVCR8 equ    74 ;
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CAPS_ALTMOVCR8 =    74 ;
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; CPU MSR names
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; CPU MSR names
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MSR_SYSENTER_CS         equ     0x174
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MSR_SYSENTER_CS         =     0x174
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MSR_SYSENTER_ESP        equ     0x175
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MSR_SYSENTER_ESP        =     0x175
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MSR_SYSENTER_EIP        equ     0x176
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MSR_SYSENTER_EIP        =     0x176
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MSR_CR_PAT              equ     0x277
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MSR_CR_PAT              =     0x277
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MSR_MTRR_DEF_TYPE       equ     0x2FF
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MSR_MTRR_DEF_TYPE       =     0x2FF
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MSR_AMD_EFER            equ     0xC0000080      ; Extended Feature Enable Register
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MSR_AMD_EFER            =     0xC0000080      ; Extended Feature Enable Register
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MSR_AMD_STAR            equ     0xC0000081      ; SYSCALL/SYSRET Target Address Register
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MSR_AMD_STAR            =     0xC0000081      ; SYSCALL/SYSRET Target Address Register
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CR0_PE         equ    0x00000001   ;protected mode
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CR0_PE         =    0x00000001   ;protected mode
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CR0_MP         equ    0x00000002   ;monitor fpu
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CR0_MP         =    0x00000002   ;monitor fpu
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CR0_EM         equ    0x00000004   ;fpu emulation
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CR0_EM         =    0x00000004   ;fpu emulation
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CR0_TS         equ    0x00000008   ;task switch
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CR0_TS         =    0x00000008   ;task switch
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CR0_ET         equ    0x00000010   ;extension type hardcoded to 1
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CR0_ET         =    0x00000010   ;extension type hardcoded to 1
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CR0_NE         equ    0x00000020   ;numeric error
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CR0_NE         =    0x00000020   ;numeric error
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CR0_WP         equ    0x00010000   ;write protect
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CR0_WP         =    0x00010000   ;write protect
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CR0_AM         equ    0x00040000   ;alignment check
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CR0_AM         =    0x00040000   ;alignment check
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CR0_NW         equ    0x20000000   ;not write-through
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CR0_NW         =    0x20000000   ;not write-through
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CR0_CD         equ    0x40000000   ;cache disable
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CR0_CD         =    0x40000000   ;cache disable
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CR0_PG         equ    0x80000000   ;paging
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CR0_PG         =    0x80000000   ;paging
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CR4_VME        equ    0x000001
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CR4_VME        =    0x000001
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CR4_PVI        equ    0x000002
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CR4_PVI        =    0x000002
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CR4_TSD        equ    0x000004
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CR4_TSD        =    0x000004
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CR4_DE         equ    0x000008
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CR4_DE         =    0x000008
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CR4_PSE        equ    0x000010
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CR4_PSE        =    0x000010
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CR4_PAE        equ    0x000020
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CR4_PAE        =    0x000020
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CR4_MCE        equ    0x000040
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CR4_MCE        =    0x000040
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CR4_PGE        equ    0x000080
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CR4_PGE        =    0x000080
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CR4_PCE        equ    0x000100
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CR4_PCE        =    0x000100
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CR4_OSFXSR     equ    0x000200
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CR4_OSFXSR     =    0x000200
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CR4_OSXMMEXPT  equ    0x000400
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CR4_OSXMMEXPT  =    0x000400
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CR4_OSXSAVE    equ    0x040000
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CR4_OSXSAVE    =    0x040000
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XCR0_FPU_MMX   equ    0x0001
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XCR0_FPU_MMX   =    0x0001
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XCR0_SSE       equ    0x0002
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XCR0_SSE       =    0x0002
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XCR0_AVX       equ    0x0004
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XCR0_AVX       =    0x0004
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XCR0_MPX       equ    0x0018
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XCR0_MPX       =    0x0018
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XCR0_AVX512    equ    0x00e0
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XCR0_AVX512    =    0x00e0
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MXCSR_IE       equ    0x0001
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MXCSR_IE       =    0x0001
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MXCSR_DE       equ    0x0002
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MXCSR_DE       =    0x0002
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MXCSR_ZE       equ    0x0004
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MXCSR_ZE       =    0x0004
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MXCSR_OE       equ    0x0008
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MXCSR_OE       =    0x0008
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MXCSR_UE       equ    0x0010
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MXCSR_UE       =    0x0010
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MXCSR_PE       equ    0x0020
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MXCSR_PE       =    0x0020
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MXCSR_DAZ      equ    0x0040
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MXCSR_DAZ      =    0x0040
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MXCSR_IM       equ    0x0080
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MXCSR_IM       =    0x0080
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MXCSR_DM       equ    0x0100
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MXCSR_DM       =    0x0100
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MXCSR_ZM       equ    0x0200
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MXCSR_ZM       =    0x0200
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MXCSR_OM       equ    0x0400
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MXCSR_OM       =    0x0400
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MXCSR_UM       equ    0x0800
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MXCSR_UM       =    0x0800
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MXCSR_PM       equ    0x1000
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MXCSR_PM       =    0x1000
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MXCSR_FZ       equ    0x8000
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MXCSR_FZ       =    0x8000
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MXCSR_INIT     equ (MXCSR_IM+MXCSR_DM+MXCSR_ZM+MXCSR_OM+MXCSR_UM+MXCSR_PM)
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MXCSR_INIT     = MXCSR_IM + MXCSR_DM + MXCSR_ZM + MXCSR_OM + MXCSR_UM + MXCSR_PM
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162 
EFLAGS_CF      equ    0x000001  ; carry flag
 162 
EFLAGS_CF      =    0x000001  ; carry flag
163 
EFLAGS_PF      equ    0x000004  ; parity flag
 163 
EFLAGS_PF      =    0x000004  ; parity flag
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EFLAGS_AF      equ    0x000010  ; auxiliary flag
 164 
EFLAGS_AF      =    0x000010  ; auxiliary flag
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EFLAGS_ZF      equ    0x000040  ; zero flag
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EFLAGS_ZF      =    0x000040  ; zero flag
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EFLAGS_SF      equ    0x000080  ; sign flag
 166 
EFLAGS_SF      =    0x000080  ; sign flag
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EFLAGS_TF      equ    0x000100  ; trap flag
 167 
EFLAGS_TF      =    0x000100  ; trap flag
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EFLAGS_IF      equ    0x000200  ; interrupt flag
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EFLAGS_IF      =    0x000200  ; interrupt flag
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EFLAGS_DF      equ    0x000400  ; direction flag
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EFLAGS_DF      =    0x000400  ; direction flag
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EFLAGS_OF      equ    0x000800  ; overflow flag
 170 
EFLAGS_OF      =    0x000800  ; overflow flag
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EFLAGS_IOPL    equ    0x003000  ; i/o priviledge level
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EFLAGS_IOPL    =    0x003000  ; i/o priviledge level
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EFLAGS_NT      equ    0x004000  ; nested task flag
 172 
EFLAGS_NT      =    0x004000  ; nested task flag
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EFLAGS_RF      equ    0x010000  ; resume flag
 173 
EFLAGS_RF      =    0x010000  ; resume flag
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EFLAGS_VM      equ    0x020000  ; virtual 8086 mode flag
 174 
EFLAGS_VM      =    0x020000  ; virtual 8086 mode flag
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                    rb 24
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                    rb 24
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        _io_map_0   rb 4096
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        _io_map_0   rb 4096
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        _io_map_1   rb 4096
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        _io_map_1   rb 4096
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ends
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ends
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DRIVE_DATA_SIZE     equ 16
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DRIVE_DATA_SIZE     = 16
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OS_BASE             equ 0x80000000
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OS_BASE             = 0x80000000
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 219 
 
220 
window_data         equ (OS_BASE+0x0001000)
 220 
window_data         = OS_BASE + 0x0001000
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222 
CURRENT_TASK        equ (OS_BASE+0x0003000)
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CURRENT_TASK        = OS_BASE + 0x0003000
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TASK_COUNT          equ (OS_BASE+0x0003004)
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TASK_COUNT          = OS_BASE + 0x0003004
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