WebSVN – Kolibri OS – Diff – /kernel/trunk/bus/pci/pci32.inc


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                              ;;
;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License    ;;
;;                                                              ;;
;;                                                              ;;
;;  PCI32.INC                                                   ;;
;;                                                              ;;
;;  32 bit PCI driver code                                      ;;
;;                                                              ;;
;;  Version 0.3  April 9, 2007                                  ;;
;;  Version 0.2  December 21st, 2002                            ;;
;;                                                              ;;
;;  Author: Victor Prodan, victorprodan@yahoo.com               ;;
;;          Mihailov Ilia, ghost.nsk@gmail.com                  ;;
;;    Credits:                                                  ;;
;;          Ralf Brown                                          ;;
;;          Mike Hibbett, mikeh@oceanfree.net                   ;;
;;                                                              ;;
;;  See file COPYING for details                                ;;
;;                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
$Revision: 2288 $
 
;***************************************************************************
;   Function
;      pci_api:
;
;   Description
;       entry point for system PCI calls
;***************************************************************************
;mmio_pci_addr  equ  0x400               ; set actual PCI address here to activate user-MMIO
 
iglobal
align 4
f62call:
        dd      pci_fn_0
        dd      pci_fn_1
        dd      pci_fn_2
        dd      pci_service_not_supported       ;3
        dd      pci_read_reg            ;4 byte
        dd      pci_read_reg            ;5 word
        dd      pci_read_reg            ;6 dword
        dd      pci_service_not_supported   ;7
        dd      pci_write_reg           ;8 byte
        dd      pci_write_reg           ;9 word
        dd      pci_write_reg           ;10 dword
if defined mmio_pci_addr
        dd      pci_mmio_init           ;11
        dd      pci_mmio_map            ;12
        dd      pci_mmio_unmap          ;13
end if
 
endg
 
align 4
 
pci_api:
 
;cross
        mov     eax, ebx
        mov     ebx, ecx
        mov     ecx, edx
 
        cmp     [pci_access_enabled], 1
        jne     pci_service_not_supported
 
        movzx   edx, al
 
if defined mmio_pci_addr
        cmp     al, 13
        ja      pci_service_not_supported
else
        cmp     al, 10
        ja      pci_service_not_supported
end if
 
        call    dword [f62call+edx*4]
        mov     dword [esp+32], eax
        ret
 
 
align 4
pci_api_drv:
 
        cmp     [pci_access_enabled], 1
        jne     .fail
 
        cmp     eax, 2
        ja      .fail
 
        jmp     dword [f62call+eax*4]
 
.fail:
        or      eax, -1
        ret
 
 
;; ============================================
 
pci_fn_0:
; PCI function 0: get pci version (AH.AL)
        movzx   eax, word [BOOT_VAR+0x9022]
        ret
 
pci_fn_1:
; PCI function 1: get last bus in AL
        mov     al, [BOOT_VAR+0x9021]
        ret
 
pci_fn_2:
; PCI function 2: get pci access mechanism
        mov     al, [BOOT_VAR+0x9020]
        ret
 
pci_service_not_supported:
        or      eax, -1
        mov     dword [esp+32], eax
        ret
 
;***************************************************************************
;   Function
;      pci_make_config_cmd
;
;   Description
;       creates a command dword  for use with the PCI bus
;       bus # in ah
;       device+func in bh (dddddfff)
;       register in bl
;
;      command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
;***************************************************************************
 
align 4
 
pci_make_config_cmd:
        shl     eax, 8     ; move bus to bits 16-23
        mov     ax, bx     ; combine all
        and     eax, 0xffffff
        or      eax, 0x80000000
        ret
 
;***************************************************************************
;   Function
;      pci_read_reg:
;
;   Description
;       read a register from the PCI config space into EAX/AX/AL
;       IN: ah=bus,device+func=bh,register address=bl
;           number of bytes to read (1,2,4) coded into AL, bits 0-1
;           (0 - byte, 1 - word, 2 - dword)
;***************************************************************************
 
align 4
 
pci_read_reg:
        cmp     byte [BOOT_VAR+0x9020], 2;what mechanism will we use?
        je      pci_read_reg_2
 
                ; mechanism 1
        push    esi   ; save register size into ESI
        mov     esi, eax
        and     esi, 3
 
        call    pci_make_config_cmd
        mov     ebx, eax
                ; get current state
        mov     dx, 0xcf8
        in      eax, dx
        push    eax
                ; set up addressing to config data
        mov     eax, ebx
        and     al, 0xfc; make address dword-aligned
        out     dx, eax
                ; get requested DWORD of config data
        mov     dl, 0xfc
        and     bl, 3
        or      dl, bl   ; add to port address first 2 bits of register address
 
        or      esi, esi
        jz      pci_read_byte1
        cmp     esi, 1
        jz      pci_read_word1
        cmp     esi, 2
        jz      pci_read_dword1
        jmp     pci_fin_read1
 
pci_read_byte1:
        in      al, dx
        jmp     pci_fin_read1
pci_read_word1:
        in      ax, dx
        jmp     pci_fin_read1
pci_read_dword1:
        in      eax, dx
        jmp     pci_fin_read1
pci_fin_read1:
                ; restore configuration control
        xchg    eax, [esp]
        mov     dx, 0xcf8
        out     dx, eax
 
        pop     eax
        pop     esi
        ret
pci_read_reg_2:
 
        test    bh, 128 ;mech#2 only supports 16 devices per bus
        jnz     pci_read_reg_err
 
        push    esi; save register size into ESI
        mov     esi, eax
        and     esi, 3
 
        push    eax
                ;store current state of config space
        mov     dx, 0xcf8
        in      al, dx
        mov     ah, al
        mov     dl, 0xfa
        in      al, dx
 
        xchg    eax, [esp]
                ; out 0xcfa,bus
        mov     al, ah
        out     dx, al
                ; out 0xcf8,0x80
        mov     dl, 0xf8
        mov     al, 0x80
        out     dx, al
                ; compute addr
        shr     bh, 3; func is ignored in mechanism 2
        or      bh, 0xc0
        mov     dx, bx
 
        or      esi, esi
        jz      pci_read_byte2
        cmp     esi, 1
        jz      pci_read_word2
        cmp     esi, 2
        jz      pci_read_dword2
        jmp     pci_fin_read2
 
pci_read_byte2:
        in      al, dx
        jmp     pci_fin_read2
pci_read_word2:
        in      ax, dx
        jmp     pci_fin_read2
pci_read_dword2:
        in      eax, dx
;       jmp pci_fin_read2
pci_fin_read2:
 
                ; restore configuration space
        xchg    eax, [esp]
        mov     dx, 0xcfa
        out     dx, al
        mov     dl, 0xf8
        mov     al, ah
        out     dx, al
 
        pop     eax
        pop     esi
        ret
 
pci_read_reg_err:
        xor     eax, eax
        dec     eax
        ret
 
 
;***************************************************************************
;   Function
;      pci_write_reg:
;
;   Description
;       write a register from ECX/CX/CL into the PCI config space
;       IN: ah=bus,device+func=bh,register address (dword aligned)=bl,
;           value to write in ecx
;           number of bytes to write (1,2,4) coded into AL, bits 0-1
;           (0 - byte, 1 - word, 2 - dword)
;***************************************************************************
 
align 4
 
pci_write_reg:
        cmp     byte [BOOT_VAR+0x9020], 2;what mechanism will we use?
        je      pci_write_reg_2
 
                ; mechanism 1
        push    esi   ; save register size into ESI
        mov     esi, eax
        and     esi, 3
 
        call    pci_make_config_cmd
        mov     ebx, eax
                ; get current state into ecx
        mov     dx, 0xcf8
        in      eax, dx
        push    eax
                ; set up addressing to config data
        mov     eax, ebx
        and     al, 0xfc; make address dword-aligned
        out     dx, eax
                ; write DWORD of config data
        mov     dl, 0xfc
        and     bl, 3
        or      dl, bl
        mov     eax, ecx
 
        or      esi, esi
        jz      pci_write_byte1
        cmp     esi, 1
        jz      pci_write_word1
        cmp     esi, 2
        jz      pci_write_dword1
        jmp     pci_fin_write1
 
pci_write_byte1:
        out     dx, al
        jmp     pci_fin_write1
pci_write_word1:
        out     dx, ax
        jmp     pci_fin_write1
pci_write_dword1:
        out     dx, eax
        jmp     pci_fin_write1
pci_fin_write1:
 
                ; restore configuration control
        pop     eax
        mov     dl, 0xf8
        out     dx, eax
 
        xor     eax, eax
        pop     esi
 
        ret
pci_write_reg_2:
 
        test    bh, 128 ;mech#2 only supports 16 devices per bus
        jnz     pci_write_reg_err
 
 
        push    esi; save register size into ESI
        mov     esi, eax
        and     esi, 3
 
        push    eax
                ;store current state of config space
        mov     dx, 0xcf8
        in      al, dx
        mov     ah, al
        mov     dl, 0xfa
        in      al, dx
        xchg    eax, [esp]
                ; out 0xcfa,bus
        mov     al, ah
        out     dx, al
                ; out 0xcf8,0x80
        mov     dl, 0xf8
        mov     al, 0x80
        out     dx, al
                ; compute addr
        shr     bh, 3; func is ignored in mechanism 2
        or      bh, 0xc0
        mov     dx, bx
                ; write register
        mov     eax, ecx
 
        or      esi, esi
        jz      pci_write_byte2
        cmp     esi, 1
        jz      pci_write_word2
        cmp     esi, 2
        jz      pci_write_dword2
        jmp     pci_fin_write2
 
pci_write_byte2:
        out     dx, al
        jmp     pci_fin_write2
pci_write_word2:
        out     dx, ax
        jmp     pci_fin_write2
pci_write_dword2:
        out     dx, eax
        jmp     pci_fin_write2
pci_fin_write2:
                ; restore configuration space
        pop     eax
        mov     dx, 0xcfa
        out     dx, al
        mov     dl, 0xf8
        mov     al, ah
        out     dx, al
 
        xor     eax, eax
        pop     esi
        ret
 
pci_write_reg_err:
        xor     eax, eax
        dec     eax
        ret
 
if defined mmio_pci_addr        ; must be set above
;***************************************************************************
;   Function
;      pci_mmio_init
;
;   Description
;       IN:  bx = device's PCI bus address (bbbbbbbbdddddfff)
;   Returns  eax = user heap space available (bytes)
;   Error codes
;       eax = -1 : PCI user access blocked,
;       eax = -2 : device not registered for uMMIO service
;       eax = -3 : user heap initialization failure
;***************************************************************************
pci_mmio_init:
        cmp     bx, mmio_pci_addr
        jz      @f
        mov     eax, -2
        ret
@@:
        call    init_heap  ; (if not initialized yet)
        or      eax, eax
        jz      @f
        ret
@@:
        mov     eax, -3
        ret
 
 
;***************************************************************************
;   Function
;      pci_mmio_map
;
;   Description
;       maps a block of PCI memory to user-accessible linear address
;
;       WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only!
;       The target device address should be set in kernel var mmio_pci_addr
;
;       IN:  ah = BAR#;
;       IN: ebx = block size (bytes);
;       IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
;
;   Returns eax = MMIO block's linear address in the userspace (if no error)
;
;
;   Error codes
;       eax = -1 : user access to PCI blocked,
;       eax = -2 : an invalid BAR register referred
;       eax = -3 : no i/o space on that BAR
;       eax = -4 : a port i/o BAR register referred
;       eax = -5 : dynamic userspace allocation problem
;***************************************************************************
 
pci_mmio_map:
        and     edx, 0x0ffff
        cmp     ah, 6
        jc      .bar_0_5
        jz      .bar_rom
        mov     eax, -2
        ret
.bar_rom:
        mov     ah, 8   ; bar6 = Expansion ROM base address
.bar_0_5:
        push    ecx
        add     ebx, 4095
        and     ebx, -4096
        push    ebx
        mov     bl, ah  ; bl = BAR# (0..5), however bl=8 for BAR6
        shl     bl, 1
        shl     bl, 1
        add     bl, 0x10; now bl = BAR offset in PCI config. space
        mov     ax, mmio_pci_addr
        mov     bh, al  ; bh = dddddfff
        mov     al, 2   ; al : DW to read
        call    pci_read_reg
        or      eax, eax
        jnz     @f
        mov     eax, -3 ; empty I/O space
        jmp     mmio_ret_fail
@@:
        test    eax, 1
        jz      @f
        mov     eax, -4 ; damned ports (not MMIO space)
        jmp     mmio_ret_fail
@@:
        pop     ecx     ; ecx = block size, bytes (expanded to whole page)
        mov     ebx, ecx; user_alloc destroys eax, ecx, edx, but saves ebx
        and     eax, 0xFFFFFFF0
        push    eax           ; store MMIO physical address + keep 2DWords in the stack
        stdcall user_alloc, ecx
        or      eax, eax
        jnz     mmio_map_over
        mov     eax, -5 ; problem with page allocation
 
mmio_ret_fail:
        pop     ecx
        pop     edx
        ret
 
mmio_map_over:
        mov     ecx, ebx; ecx = size (bytes, expanded to whole page)
        shr     ecx, 12 ; ecx = number of pages
        mov     ebx, eax; ebx = linear address
        pop     eax     ; eax = MMIO start
        pop     edx     ; edx = MMIO shift (pages)
        shl     edx, 12 ; edx = MMIO shift (bytes)
        add     eax, edx; eax = uMMIO physical address
        or      eax, PG_SHARED
        or      eax, PG_UW
        or      eax, PG_NOCACHE
        mov     edi, ebx
        call    commit_pages
        mov     eax, edi
        ret
 
;***************************************************************************
;   Function
;      pci_mmio_unmap_page
;
;   Description
;       unmaps the linear space previously tied to a PCI memory block
;
;       IN: ebx = linear address of space previously allocated by pci_mmio_map
;       returns eax = 1 if successfully unmapped
;
;   Error codes
;       eax = -1 if no user PCI access allowed,
;       eax =  0 if unmapping failed
;***************************************************************************
 
pci_mmio_unmap:
        stdcall user_free, ebx
        ret
 
end if
 
;-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
uglobal
align 4
; VendID (2), DevID (2), Revision = 0 (1), Class Code (3), FNum (1), Bus (1)
pci_emu_dat:
                times   30*10 db 0
endg
;-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
align 4
sys_pcibios:
        cmp     [pci_access_enabled], 1
        jne     .unsupported_func
        cmp     [pci_bios_entry], 0
        jz      .emulate_bios
 
        push    ds
        mov     ax, pci_data_sel
        mov     ds, ax
        mov     eax, ebp
        mov     ah, 0B1h
        call    pword [cs:pci_bios_entry]
        pop     ds
 
        jmp     .return
        ;-=-=-=-=-=-=-=-=
.emulate_bios:
        cmp     ebp, 1                  ; PCI_FUNCTION_ID
        jnz     .not_PCI_BIOS_PRESENT
        mov     edx, 'PCI '
        mov     al, [BOOT_VAR + 0x9020]
        mov     bx, [BOOT_VAR + 0x9022]
        mov     cl, [BOOT_VAR + 0x9021]
        xor     ah, ah
        jmp     .return_abcd
 
.not_PCI_BIOS_PRESENT:
        cmp     ebp, 2                  ; FIND_PCI_DEVICE
        jne     .not_FIND_PCI_DEVICE
        mov     ebx, pci_emu_dat
..nxt:
        cmp     [ebx], dx
        jne     ..no
        cmp     [ebx + 2], cx
        jne     ..no
        dec     si
        jns     ..no
        mov     bx, [ebx + 4]
        xor     ah, ah
        jmp     .return_ab
..no:
        cmp     word[ebx], 0
        je      ..dev_not_found
        add     ebx, 10
        jmp     ..nxt
..dev_not_found:
        mov     ah, 0x86                ; DEVICE_NOT_FOUND
        jmp     .return_a
 
.not_FIND_PCI_DEVICE:
        cmp     ebp, 3                  ; FIND_PCI_CLASS_CODE
        jne     .not_FIND_PCI_CLASS_CODE
        mov     esi, pci_emu_dat
        shl     ecx, 8
..nxt2:
        cmp     [esi], ecx
        jne     ..no2
        mov     bx, [esi]
        xor     ah, ah
        jmp     .return_ab
..no2:
        cmp     dword[esi], 0
        je      ..dev_not_found
        add     esi, 10
        jmp     ..nxt2
 
.not_FIND_PCI_CLASS_CODE:
        cmp     ebp, 8                  ; READ_CONFIG_*
        jb      .not_READ_CONFIG
        cmp     ebp, 0x0A
        ja      .not_READ_CONFIG
        mov     eax, ebp
        mov     ah, bh
        mov     edx, edi
        mov     bh, bl
        mov     bl, dl
        call    pci_read_reg
        mov     ecx, eax
        xor     ah, ah                  ; SUCCESSFUL
        jmp     .return_abc
.not_READ_CONFIG:
        cmp     ebp, 0x0B               ; WRITE_CONFIG_*
        jb      .not_WRITE_CONFIG
        cmp     ebp, 0x0D
        ja      .not_WRITE_CONFIG
        lea     eax, [ebp+1]
        mov     ah, bh
        mov     edx, edi
        mov     bh, bl
        mov     bl, dl
        call    pci_write_reg
        xor     ah, ah                  ; SUCCESSFUL
        jmp     .return_abc
.not_WRITE_CONFIG:
.unsupported_func:
        mov     ah, 0x81                ; FUNC_NOT_SUPPORTED
.return:
        mov     dword[esp + 4 ], edi
        mov     dword[esp + 8], esi
.return_abcd:
        mov     dword[esp + 24], edx
.return_abc:
        mov     dword[esp + 28], ecx
.return_ab:
        mov     dword[esp + 20], ebx
.return_a:
        mov     dword[esp + 32], eax
        ret

Rev 1949	Rev 2288
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; ;;	6	;; ;;
7	;; PCI32.INC ;;	7	;; PCI32.INC ;;
8	;; ;;	8	;; ;;
9	;; 32 bit PCI driver code ;;	9	;; 32 bit PCI driver code ;;
10	;; ;;	10	;; ;;
11	;; Version 0.3 April 9, 2007 ;;	11	;; Version 0.3 April 9, 2007 ;;
12	;; Version 0.2 December 21st, 2002 ;;	12	;; Version 0.2 December 21st, 2002 ;;
13	;; ;;	13	;; ;;
14	;; Author: Victor Prodan, victorprodan@yahoo.com ;;	14	;; Author: Victor Prodan, victorprodan@yahoo.com ;;
15	;; Mihailov Ilia, ghost.nsk@gmail.com ;;	15	;; Mihailov Ilia, ghost.nsk@gmail.com ;;
16	;; Credits: ;;	16	;; Credits: ;;
17	;; Ralf Brown ;;	17	;; Ralf Brown ;;
18	;; Mike Hibbett, mikeh@oceanfree.net ;;	18	;; Mike Hibbett, mikeh@oceanfree.net ;;
19	;; ;;	19	;; ;;
20	;; See file COPYING for details ;;	20	;; See file COPYING for details ;;
21	;; ;;	21	;; ;;
22	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	22	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
23		23
24	$Revision: 1949 $	24	$Revision: 2288 $
25		25
26	;***************************************************************************	26	;***************************************************************************
27	; Function	27	; Function
28	; pci_api:	28	; pci_api:
29	;	29	;
30	; Description	30	; Description
31	; entry point for system PCI calls	31	; entry point for system PCI calls
32	;***************************************************************************	32	;***************************************************************************
33	;mmio_pci_addr equ 0x400 ; set actual PCI address here to activate user-MMIO	33	;mmio_pci_addr equ 0x400 ; set actual PCI address here to activate user-MMIO
34		34
35	iglobal	35	iglobal
36	align 4	36	align 4
37	f62call:	37	f62call:
38	dd pci_fn_0	38	dd pci_fn_0
39	dd pci_fn_1	39	dd pci_fn_1
40	dd pci_fn_2	40	dd pci_fn_2
41	dd pci_service_not_supported ;3	41	dd pci_service_not_supported ;3
42	dd pci_read_reg ;4 byte	42	dd pci_read_reg ;4 byte
43	dd pci_read_reg ;5 word	43	dd pci_read_reg ;5 word
44	dd pci_read_reg ;6 dword	44	dd pci_read_reg ;6 dword
45	dd pci_service_not_supported ;7	45	dd pci_service_not_supported ;7
46	dd pci_write_reg ;8 byte	46	dd pci_write_reg ;8 byte
47	dd pci_write_reg ;9 word	47	dd pci_write_reg ;9 word
48	dd pci_write_reg ;10 dword	48	dd pci_write_reg ;10 dword
49	if defined mmio_pci_addr	49	if defined mmio_pci_addr
50	dd pci_mmio_init ;11	50	dd pci_mmio_init ;11
51	dd pci_mmio_map ;12	51	dd pci_mmio_map ;12
52	dd pci_mmio_unmap ;13	52	dd pci_mmio_unmap ;13
53	end if	53	end if
54		54
55	endg	55	endg
56		56
57	align 4	57	align 4
58		58
59	pci_api:	59	pci_api:
60		60
61	;cross	61	;cross
62	mov eax,ebx	62	mov eax, ebx
63	mov ebx,ecx	63	mov ebx, ecx
64	mov ecx,edx	64	mov ecx, edx
65		65
66	cmp [pci_access_enabled],1	66	cmp [pci_access_enabled], 1
67	jne pci_service_not_supported	67	jne pci_service_not_supported
68		68
69	movzx edx, al	69	movzx edx, al
70		70
71	if defined mmio_pci_addr	71	if defined mmio_pci_addr
72	cmp al, 13	72	cmp al, 13
73	ja pci_service_not_supported	73	ja pci_service_not_supported
74	else	74	else
75	cmp al, 10	75	cmp al, 10
76	ja pci_service_not_supported	76	ja pci_service_not_supported
77	end if	77	end if
78		78
79	call dword [f62call+edx*4]	79	call dword [f62call+edx*4]
80	mov dword [esp+32],eax	80	mov dword [esp+32], eax
81	ret	81	ret
82		82
83		83
84	align 4	84	align 4
85	pci_api_drv:	85	pci_api_drv:
86		86
87	cmp [pci_access_enabled],1	87	cmp [pci_access_enabled], 1
88	jne .fail	88	jne .fail
89		89
90	cmp eax, 2	90	cmp eax, 2
91	ja .fail	91	ja .fail
92		92
93	jmp dword [f62call+eax*4]	93	jmp dword [f62call+eax*4]
94		94
95	.fail:	95	.fail:
96	or eax,-1	96	or eax, -1
97	ret	97	ret
98		98
99		99
100	;; ============================================	100	;; ============================================
101		101
102	pci_fn_0:	102	pci_fn_0:
103	; PCI function 0: get pci version (AH.AL)	103	; PCI function 0: get pci version (AH.AL)
104	movzx eax,word [BOOT_VAR+0x9022]	104	movzx eax, word [BOOT_VAR+0x9022]
105	ret	105	ret
106		106
107	pci_fn_1:	107	pci_fn_1:
108	; PCI function 1: get last bus in AL	108	; PCI function 1: get last bus in AL
109	mov al,[BOOT_VAR+0x9021]	109	mov al, [BOOT_VAR+0x9021]
110	ret	110	ret
111		111
112	pci_fn_2:	112	pci_fn_2:
113	; PCI function 2: get pci access mechanism	113	; PCI function 2: get pci access mechanism
114	mov al,[BOOT_VAR+0x9020]	114	mov al, [BOOT_VAR+0x9020]
115	ret	115	ret
116		116
117	pci_service_not_supported:	117	pci_service_not_supported:
118	or eax,-1	118	or eax, -1
119	mov dword [esp+32],eax	119	mov dword [esp+32], eax
120	ret	120	ret
121		121
122	;***************************************************************************	122	;***************************************************************************
123	; Function	123	; Function
124	; pci_make_config_cmd	124	; pci_make_config_cmd
125	;	125	;
126	; Description	126	; Description
127	; creates a command dword for use with the PCI bus	127	; creates a command dword for use with the PCI bus
128	; bus # in ah	128	; bus # in ah
129	; device+func in bh (dddddfff)	129	; device+func in bh (dddddfff)
130	; register in bl	130	; register in bl
131	;	131	;
132	; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )	132	; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
133	;***************************************************************************	133	;***************************************************************************
134		134
135	align 4	135	align 4
136		136
137	pci_make_config_cmd:	137	pci_make_config_cmd:
138	shl eax,8 ; move bus to bits 16-23	138	shl eax, 8 ; move bus to bits 16-23
139	mov ax,bx ; combine all	139	mov ax, bx ; combine all
140	and eax,0xffffff	140	and eax, 0xffffff
141	or eax,0x80000000	141	or eax, 0x80000000
142	ret	142	ret
143		143
144	;***************************************************************************	144	;***************************************************************************
145	; Function	145	; Function
146	; pci_read_reg:	146	; pci_read_reg:
147	;	147	;
148	; Description	148	; Description
149	; read a register from the PCI config space into EAX/AX/AL	149	; read a register from the PCI config space into EAX/AX/AL
150	; IN: ah=bus,device+func=bh,register address=bl	150	; IN: ah=bus,device+func=bh,register address=bl
151	; number of bytes to read (1,2,4) coded into AL, bits 0-1	151	; number of bytes to read (1,2,4) coded into AL, bits 0-1
152	; (0 - byte, 1 - word, 2 - dword)	152	; (0 - byte, 1 - word, 2 - dword)
153	;***************************************************************************	153	;***************************************************************************
154		154
155	align 4	155	align 4
156		156
157	pci_read_reg:	157	pci_read_reg:
158	cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?	158	cmp byte [BOOT_VAR+0x9020], 2;what mechanism will we use?
159	je pci_read_reg_2	159	je pci_read_reg_2
160		160
161	; mechanism 1	161	; mechanism 1
162	push esi ; save register size into ESI	162	push esi ; save register size into ESI
163	mov esi,eax	163	mov esi, eax
164	and esi,3	164	and esi, 3
165		165
166	call pci_make_config_cmd	166	call pci_make_config_cmd
167	mov ebx,eax	167	mov ebx, eax
168	; get current state	168	; get current state
169	mov dx,0xcf8	169	mov dx, 0xcf8
170	in eax, dx	170	in eax, dx
171	push eax	171	push eax
172	; set up addressing to config data	172	; set up addressing to config data
173	mov eax,ebx	173	mov eax, ebx
174	and al,0xfc ; make address dword-aligned	174	and al, 0xfc; make address dword-aligned
175	out dx,eax	175	out dx, eax
176	; get requested DWORD of config data	176	; get requested DWORD of config data
177	mov dl,0xfc	177	mov dl, 0xfc
178	and bl,3	178	and bl, 3
179	or dl,bl ; add to port address first 2 bits of register address	179	or dl, bl ; add to port address first 2 bits of register address
180		180
181	or esi,esi	181	or esi, esi
182	jz pci_read_byte1	182	jz pci_read_byte1
183	cmp esi,1	183	cmp esi, 1
184	jz pci_read_word1	184	jz pci_read_word1
185	cmp esi,2	185	cmp esi, 2
186	jz pci_read_dword1	186	jz pci_read_dword1
187	jmp pci_fin_read1	187	jmp pci_fin_read1
188		188
189	pci_read_byte1:	189	pci_read_byte1:
190	in al,dx	190	in al, dx
191	jmp pci_fin_read1	191	jmp pci_fin_read1
192	pci_read_word1:	192	pci_read_word1:
193	in ax,dx	193	in ax, dx
194	jmp pci_fin_read1	194	jmp pci_fin_read1
195	pci_read_dword1:	195	pci_read_dword1:
196	in eax,dx	196	in eax, dx
197	jmp pci_fin_read1	197	jmp pci_fin_read1
198	pci_fin_read1:	198	pci_fin_read1:
199	; restore configuration control	199	; restore configuration control
200	xchg eax,[esp]	200	xchg eax, [esp]
201	mov dx,0xcf8	201	mov dx, 0xcf8
202	out dx,eax	202	out dx, eax
203		203
204	pop eax	204	pop eax
205	pop esi	205	pop esi
206	ret	206	ret
207	pci_read_reg_2:	207	pci_read_reg_2:
208		208
209	test bh,128 ;mech#2 only supports 16 devices per bus	209	test bh, 128 ;mech#2 only supports 16 devices per bus
210	jnz pci_read_reg_err	210	jnz pci_read_reg_err
211		211
212	push esi ; save register size into ESI	212	push esi; save register size into ESI
213	mov esi,eax	213	mov esi, eax
214	and esi,3	214	and esi, 3
215		215
216	push eax	216	push eax
217	;store current state of config space	217	;store current state of config space
218	mov dx,0xcf8	218	mov dx, 0xcf8
219	in al,dx	219	in al, dx
220	mov ah,al	220	mov ah, al
221	mov dl,0xfa	221	mov dl, 0xfa
222	in al,dx	222	in al, dx
223		223
224	xchg eax,[esp]	224	xchg eax, [esp]
225	; out 0xcfa,bus	225	; out 0xcfa,bus
226	mov al,ah	226	mov al, ah
227	out dx,al	227	out dx, al
228	; out 0xcf8,0x80	228	; out 0xcf8,0x80
229	mov dl,0xf8	229	mov dl, 0xf8
230	mov al,0x80	230	mov al, 0x80
231	out dx,al	231	out dx, al
232	; compute addr	232	; compute addr
233	shr bh,3 ; func is ignored in mechanism 2	233	shr bh, 3; func is ignored in mechanism 2
234	or bh,0xc0	234	or bh, 0xc0
235	mov dx,bx	235	mov dx, bx
236		236
237	or esi,esi	237	or esi, esi
238	jz pci_read_byte2	238	jz pci_read_byte2
239	cmp esi,1	239	cmp esi, 1
240	jz pci_read_word2	240	jz pci_read_word2
241	cmp esi,2	241	cmp esi, 2
242	jz pci_read_dword2	242	jz pci_read_dword2
243	jmp pci_fin_read2	243	jmp pci_fin_read2
244		244
245	pci_read_byte2:	245	pci_read_byte2:
246	in al,dx	246	in al, dx
247	jmp pci_fin_read2	247	jmp pci_fin_read2
248	pci_read_word2:	248	pci_read_word2:
249	in ax,dx	249	in ax, dx
250	jmp pci_fin_read2	250	jmp pci_fin_read2
251	pci_read_dword2:	251	pci_read_dword2:
252	in eax,dx	252	in eax, dx
253	; jmp pci_fin_read2	253	; jmp pci_fin_read2
254	pci_fin_read2:	254	pci_fin_read2:
255		255
256	; restore configuration space	256	; restore configuration space
257	xchg eax,[esp]	257	xchg eax, [esp]
258	mov dx,0xcfa	258	mov dx, 0xcfa
259	out dx,al	259	out dx, al
260	mov dl,0xf8	260	mov dl, 0xf8
261	mov al,ah	261	mov al, ah
262	out dx,al	262	out dx, al
263		263
264	pop eax	264	pop eax
265	pop esi	265	pop esi
266	ret	266	ret
267		267
268	pci_read_reg_err:	268	pci_read_reg_err:
269	xor eax,eax	269	xor eax, eax
270	dec eax	270	dec eax
271	ret	271	ret
272		272
273		273
274	;***************************************************************************	274	;***************************************************************************
275	; Function	275	; Function
276	; pci_write_reg:	276	; pci_write_reg:
277	;	277	;
278	; Description	278	; Description
279	; write a register from ECX/CX/CL into the PCI config space	279	; write a register from ECX/CX/CL into the PCI config space
280	; IN: ah=bus,device+func=bh,register address (dword aligned)=bl,	280	; IN: ah=bus,device+func=bh,register address (dword aligned)=bl,
281	; value to write in ecx	281	; value to write in ecx
282	; number of bytes to write (1,2,4) coded into AL, bits 0-1	282	; number of bytes to write (1,2,4) coded into AL, bits 0-1
283	; (0 - byte, 1 - word, 2 - dword)	283	; (0 - byte, 1 - word, 2 - dword)
284	;***************************************************************************	284	;***************************************************************************
285		285
286	align 4	286	align 4
287		287
288	pci_write_reg:	288	pci_write_reg:
289	cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?	289	cmp byte [BOOT_VAR+0x9020], 2;what mechanism will we use?
290	je pci_write_reg_2	290	je pci_write_reg_2
291		291
292	; mechanism 1	292	; mechanism 1
293	push esi ; save register size into ESI	293	push esi ; save register size into ESI
294	mov esi,eax	294	mov esi, eax
295	and esi,3	295	and esi, 3
296		296
297	call pci_make_config_cmd	297	call pci_make_config_cmd
298	mov ebx,eax	298	mov ebx, eax
299	; get current state into ecx	299	; get current state into ecx
300	mov dx,0xcf8	300	mov dx, 0xcf8
301	in eax, dx	301	in eax, dx
302	push eax	302	push eax
303	; set up addressing to config data	303	; set up addressing to config data
304	mov eax,ebx	304	mov eax, ebx
305	and al,0xfc ; make address dword-aligned	305	and al, 0xfc; make address dword-aligned
306	out dx,eax	306	out dx, eax
307	; write DWORD of config data	307	; write DWORD of config data
308	mov dl,0xfc	308	mov dl, 0xfc
309	and bl,3	309	and bl, 3
310	or dl,bl	310	or dl, bl
311	mov eax,ecx	311	mov eax, ecx
312		312
313	or esi,esi	313	or esi, esi
314	jz pci_write_byte1	314	jz pci_write_byte1
315	cmp esi,1	315	cmp esi, 1
316	jz pci_write_word1	316	jz pci_write_word1
317	cmp esi,2	317	cmp esi, 2
318	jz pci_write_dword1	318	jz pci_write_dword1
319	jmp pci_fin_write1	319	jmp pci_fin_write1
320		320
321	pci_write_byte1:	321	pci_write_byte1:
322	out dx,al	322	out dx, al
323	jmp pci_fin_write1	323	jmp pci_fin_write1
324	pci_write_word1:	324	pci_write_word1:
325	out dx,ax	325	out dx, ax
326	jmp pci_fin_write1	326	jmp pci_fin_write1
327	pci_write_dword1:	327	pci_write_dword1:
328	out dx,eax	328	out dx, eax
329	jmp pci_fin_write1	329	jmp pci_fin_write1
330	pci_fin_write1:	330	pci_fin_write1:
331		331
332	; restore configuration control	332	; restore configuration control
333	pop eax	333	pop eax
334	mov dl,0xf8	334	mov dl, 0xf8
335	out dx,eax	335	out dx, eax
336		336
337	xor eax,eax	337	xor eax, eax
338	pop esi	338	pop esi
339		339
340	ret	340	ret
341	pci_write_reg_2:	341	pci_write_reg_2:
342		342
343	test bh,128 ;mech#2 only supports 16 devices per bus	343	test bh, 128 ;mech#2 only supports 16 devices per bus
344	jnz pci_write_reg_err	344	jnz pci_write_reg_err
345		345
346		346
347	push esi ; save register size into ESI	347	push esi; save register size into ESI
348	mov esi,eax	348	mov esi, eax
349	and esi,3	349	and esi, 3
350		350
351	push eax	351	push eax
352	;store current state of config space	352	;store current state of config space
353	mov dx,0xcf8	353	mov dx, 0xcf8
354	in al,dx	354	in al, dx
355	mov ah,al	355	mov ah, al
356	mov dl,0xfa	356	mov dl, 0xfa
357	in al,dx	357	in al, dx
358	xchg eax,[esp]	358	xchg eax, [esp]
359	; out 0xcfa,bus	359	; out 0xcfa,bus
360	mov al,ah	360	mov al, ah
361	out dx,al	361	out dx, al
362	; out 0xcf8,0x80	362	; out 0xcf8,0x80
363	mov dl,0xf8	363	mov dl, 0xf8
364	mov al,0x80	364	mov al, 0x80
365	out dx,al	365	out dx, al
366	; compute addr	366	; compute addr
367	shr bh,3 ; func is ignored in mechanism 2	367	shr bh, 3; func is ignored in mechanism 2
368	or bh,0xc0	368	or bh, 0xc0
369	mov dx,bx	369	mov dx, bx
370	; write register	370	; write register
371	mov eax,ecx	371	mov eax, ecx
372		372
373	or esi,esi	373	or esi, esi
374	jz pci_write_byte2	374	jz pci_write_byte2
375	cmp esi,1	375	cmp esi, 1
376	jz pci_write_word2	376	jz pci_write_word2
377	cmp esi,2	377	cmp esi, 2
378	jz pci_write_dword2	378	jz pci_write_dword2
379	jmp pci_fin_write2	379	jmp pci_fin_write2
380		380
381	pci_write_byte2:	381	pci_write_byte2:
382	out dx,al	382	out dx, al
383	jmp pci_fin_write2	383	jmp pci_fin_write2
384	pci_write_word2:	384	pci_write_word2:
385	out dx,ax	385	out dx, ax
386	jmp pci_fin_write2	386	jmp pci_fin_write2
387	pci_write_dword2:	387	pci_write_dword2:
388	out dx,eax	388	out dx, eax
389	jmp pci_fin_write2	389	jmp pci_fin_write2
390	pci_fin_write2:	390	pci_fin_write2:
391	; restore configuration space	391	; restore configuration space
392	pop eax	392	pop eax
393	mov dx,0xcfa	393	mov dx, 0xcfa
394	out dx,al	394	out dx, al
395	mov dl,0xf8	395	mov dl, 0xf8
396	mov al,ah	396	mov al, ah
397	out dx,al	397	out dx, al
398		398
399	xor eax,eax	399	xor eax, eax
400	pop esi	400	pop esi
401	ret	401	ret
402		402
403	pci_write_reg_err:	403	pci_write_reg_err:
404	xor eax,eax	404	xor eax, eax
405	dec eax	405	dec eax
406	ret	406	ret
407		407
408	if defined mmio_pci_addr ; must be set above	408	if defined mmio_pci_addr ; must be set above
409	;***************************************************************************	409	;***************************************************************************
410	; Function	410	; Function
411	; pci_mmio_init	411	; pci_mmio_init
412	;	412	;
413	; Description	413	; Description
414	; IN: bx = device's PCI bus address (bbbbbbbbdddddfff)	414	; IN: bx = device's PCI bus address (bbbbbbbbdddddfff)
415	; Returns eax = user heap space available (bytes)	415	; Returns eax = user heap space available (bytes)
416	; Error codes	416	; Error codes
417	; eax = -1 : PCI user access blocked,	417	; eax = -1 : PCI user access blocked,
418	; eax = -2 : device not registered for uMMIO service	418	; eax = -2 : device not registered for uMMIO service
419	; eax = -3 : user heap initialization failure	419	; eax = -3 : user heap initialization failure
420	;***************************************************************************	420	;***************************************************************************
421	pci_mmio_init:	421	pci_mmio_init:
422	cmp bx, mmio_pci_addr	422	cmp bx, mmio_pci_addr
423	jz @f	423	jz @f
424	mov eax,-2	424	mov eax, -2
425	ret	425	ret
426	@@:	426	@@:
427	call init_heap ; (if not initialized yet)	427	call init_heap ; (if not initialized yet)
428	or eax,eax	428	or eax, eax
429	jz @f	429	jz @f
430	ret	430	ret
431	@@:	431	@@:
432	mov eax,-3	432	mov eax, -3
433	ret	433	ret
434		434
435		435
436	;***************************************************************************	436	;***************************************************************************
437	; Function	437	; Function
438	; pci_mmio_map	438	; pci_mmio_map
439	;	439	;
440	; Description	440	; Description
441	; maps a block of PCI memory to user-accessible linear address	441	; maps a block of PCI memory to user-accessible linear address
442	;	442	;
443	; WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only!	443	; WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only!
444	; The target device address should be set in kernel var mmio_pci_addr	444	; The target device address should be set in kernel var mmio_pci_addr
445	;	445	;
446	; IN: ah = BAR#;	446	; IN: ah = BAR#;
447	; IN: ebx = block size (bytes);	447	; IN: ebx = block size (bytes);
448	; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);	448	; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
449	;	449	;
450	; Returns eax = MMIO block's linear address in the userspace (if no error)	450	; Returns eax = MMIO block's linear address in the userspace (if no error)
451	;	451	;
452	;	452	;
453	; Error codes	453	; Error codes
454	; eax = -1 : user access to PCI blocked,	454	; eax = -1 : user access to PCI blocked,
455	; eax = -2 : an invalid BAR register referred	455	; eax = -2 : an invalid BAR register referred
456	; eax = -3 : no i/o space on that BAR	456	; eax = -3 : no i/o space on that BAR
457	; eax = -4 : a port i/o BAR register referred	457	; eax = -4 : a port i/o BAR register referred
458	; eax = -5 : dynamic userspace allocation problem	458	; eax = -5 : dynamic userspace allocation problem
459	;***************************************************************************	459	;***************************************************************************
460		460
461	pci_mmio_map:	461	pci_mmio_map:
462	and edx,0x0ffff	462	and edx, 0x0ffff
463	cmp ah,6	463	cmp ah, 6
464	jc .bar_0_5	464	jc .bar_0_5
465	jz .bar_rom	465	jz .bar_rom
466	mov eax,-2	466	mov eax, -2
467	ret	467	ret
468	.bar_rom:	468	.bar_rom:
469	mov ah, 8 ; bar6 = Expansion ROM base address	469	mov ah, 8 ; bar6 = Expansion ROM base address
470	.bar_0_5:	470	.bar_0_5:
471	push ecx	471	push ecx
472	add ebx, 4095	472	add ebx, 4095
473	and ebx,-4096	473	and ebx, -4096
474	push ebx	474	push ebx
475	mov bl, ah ; bl = BAR# (0..5), however bl=8 for BAR6	475	mov bl, ah ; bl = BAR# (0..5), however bl=8 for BAR6
476	shl bl, 1	476	shl bl, 1
477	shl bl, 1	477	shl bl, 1
478	add bl, 0x10 ; now bl = BAR offset in PCI config. space	478	add bl, 0x10; now bl = BAR offset in PCI config. space
479	mov ax, mmio_pci_addr	479	mov ax, mmio_pci_addr
480	mov bh, al ; bh = dddddfff	480	mov bh, al ; bh = dddddfff
481	mov al, 2 ; al : DW to read	481	mov al, 2 ; al : DW to read
482	call pci_read_reg	482	call pci_read_reg
483	or eax, eax	483	or eax, eax
484	jnz @f	484	jnz @f
485	mov eax,-3 ; empty I/O space	485	mov eax, -3 ; empty I/O space
486	jmp mmio_ret_fail	486	jmp mmio_ret_fail
487	@@:	487	@@:
488	test eax, 1	488	test eax, 1
489	jz @f	489	jz @f
490	mov eax,-4 ; damned ports (not MMIO space)	490	mov eax, -4 ; damned ports (not MMIO space)
491	jmp mmio_ret_fail	491	jmp mmio_ret_fail
492	@@:	492	@@:
493	pop ecx ; ecx = block size, bytes (expanded to whole page)	493	pop ecx ; ecx = block size, bytes (expanded to whole page)
494	mov ebx, ecx ; user_alloc destroys eax, ecx, edx, but saves ebx	494	mov ebx, ecx; user_alloc destroys eax, ecx, edx, but saves ebx
495	and eax, 0xFFFFFFF0	495	and eax, 0xFFFFFFF0
496	push eax ; store MMIO physical address + keep 2DWords in the stack	496	push eax ; store MMIO physical address + keep 2DWords in the stack
497	stdcall user_alloc, ecx	497	stdcall user_alloc, ecx
498	or eax, eax	498	or eax, eax
499	jnz mmio_map_over	499	jnz mmio_map_over
500	mov eax,-5 ; problem with page allocation	500	mov eax, -5 ; problem with page allocation

Subversion Repositories Kolibri OS

(root)/kernel/trunk/bus/pci/pci32.inc – Rev 1949 → 2288