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1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
2 | ;; ;; |
3 | ;; Copyright (C) KolibriOS team 2010-2011. All rights reserved. ;; |
3 | ;; Copyright (C) KolibriOS team 2010-2015. All rights reserved. ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
5 | ;; ;; |
5 | ;; ;; |
6 | ;; ;; |
6 | ;; ;; |
7 | ;; PCIe.INC ;; |
7 | ;; PCIe.INC ;; |
8 | ;; ;; |
8 | ;; ;; |
9 | ;; Extended PCI express services ;; |
9 | ;; Extended PCI express services ;; |
10 | ;; ;; |
10 | ;; ;; |
11 | ;; art_zh |
11 | ;; art_zh |
12 | ;; ;; |
12 | ;; ;; |
13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
14 | 14 | ||
15 | $Revision: 1463 $ |
15 | $Revision: 1463 $ |
16 | 16 | ||
17 | ;*************************************************************************** |
17 | ;*************************************************************************** |
18 | ; Function |
18 | ; Function |
19 | ; pci_ext_config: |
19 | ; pci_ext_config: |
20 | ; |
20 | ; |
21 | ; Description |
21 | ; Description |
22 | ; PCIe extended (memory-mapped) config space detection |
22 | ; PCIe extended (memory-mapped) config space detection |
23 | ; |
23 | ; |
24 | ; WARNINGs: |
24 | ; WARNINGs: |
25 | ; 1) Very Experimental! |
25 | ; 1) Very Experimental! |
26 | ; 2) direct HT-detection (no ACPI or BIOS service used) |
26 | ; 2) direct HT-detection (no ACPI or BIOS service used) |
27 | ; 3) Only AMD/HT processors currently supported |
27 | ; 3) Only AMD/HT processors currently supported |
28 | ; |
28 | ; |
29 | ;*************************************************************************** |
29 | ;*************************************************************************** |
30 | 30 | ||
31 | PCIe_CONFIG_SPACE equ 0xF0000000 ; to be moved to const.inc |
31 | PCIe_CONFIG_SPACE equ 0xF0000000 ; to be moved to const.inc |
32 | mmio_pcie_cfg_addr dd 0x0 ; intel pcie space may be defined here |
32 | mmio_pcie_cfg_addr dd 0x0 ; intel pcie space may be defined here |
33 | mmio_pcie_cfg_lim dd 0x0 ; upper pcie space address |
33 | mmio_pcie_cfg_lim dd 0x0 ; upper pcie space address |
34 | 34 | ||
35 | 35 | ||
36 | align 4 |
36 | align 4 |
37 | 37 | ||
38 | pci_ext_config: |
38 | pci_ext_config: |
39 | 39 | ||
40 | mov ebx, [mmio_pcie_cfg_addr] |
40 | mov ebx, [mmio_pcie_cfg_addr] |
41 | or ebx, ebx |
41 | or ebx, ebx |
42 | jz @f |
42 | jz @f |
43 | or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
43 | or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
44 | jnz .pcie_failed |
44 | jnz .pcie_failed |
45 | add ebx, 0x0FFFFC |
45 | add ebx, 0x0FFFFC |
46 | cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
46 | cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
47 | ja .pcie_failed |
47 | ja .pcie_failed |
48 | jmp .pcie_cfg_mapped |
48 | jmp .pcie_cfg_mapped |
49 | @@: |
49 | @@: |
50 | mov ebx, [cpu_vendor] |
50 | mov ebx, [cpu_vendor] |
51 | cmp ebx, dword [AMD_str] |
51 | cmp ebx, dword [AMD_str] |
52 | jne .pcie_failed |
52 | jne .pcie_failed |
53 | mov bx, 0xC184 ; dev = 24, fn = 01, reg = 84h |
53 | mov bx, 0xC184 ; dev = 24, fn = 01, reg = 84h |
54 | 54 | ||
55 | .check_HT_mmio: |
55 | .check_HT_mmio: |
56 | mov cx, bx |
56 | mov cx, bx |
57 | mov ax, 0x0002 ; bus = 0, 1dword to read |
57 | mov ax, 0x0002 ; bus = 0, 1dword to read |
58 | call pci_read_reg |
58 | call pci_read_reg |
59 | mov bx, cx |
59 | mov bx, cx |
60 | sub bl, 4 |
60 | sub bl, 4 |
61 | and al, 0x80 ; check the NP bit |
61 | and al, 0x80 ; check the NP bit |
62 | jz .no_pcie_cfg |
62 | jz .no_pcie_cfg |
63 | shl eax, 8 ; bus:[27..20], dev:[19:15] |
63 | shl eax, 8 ; bus:[27..20], dev:[19:15] |
64 | or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
64 | or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
65 | mov [mmio_pcie_cfg_lim], eax |
65 | mov [mmio_pcie_cfg_lim], eax |
66 | mov cl, bl |
66 | mov cl, bl |
67 | mov ax, 0x0002 ; bus = 0, 1dword to read |
67 | mov ax, 0x0002 ; bus = 0, 1dword to read |
68 | call pci_read_reg |
68 | call pci_read_reg |
69 | mov bx, cx |
69 | mov bx, cx |
70 | test al, 0x03 ; MMIO Base RW enabled? |
70 | test al, 0x03 ; MMIO Base RW enabled? |
71 | jz .no_pcie_cfg |
71 | jz .no_pcie_cfg |
72 | test al, 0x0C ; MMIO Base locked? |
72 | test al, 0x0C ; MMIO Base locked? |
73 | jnz .no_pcie_cfg |
73 | jnz .no_pcie_cfg |
74 | xor al, al |
74 | xor al, al |
75 | shl eax, 8 |
75 | shl eax, 8 |
76 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
76 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
77 | jnz .no_pcie_cfg |
77 | jnz .no_pcie_cfg |
78 | mov [mmio_pcie_cfg_addr], eax |
78 | mov [mmio_pcie_cfg_addr], eax |
79 | add eax, 0x000FFFFC |
79 | add eax, 0x000FFFFC |
80 | sub eax, [mmio_pcie_cfg_lim]; MMIO must cover at least one bus |
80 | sub eax, [mmio_pcie_cfg_lim]; MMIO must cover at least one bus |
81 | ja .no_pcie_cfg |
81 | ja .no_pcie_cfg |
82 | 82 | ||
83 | ; -- it looks like a true PCIe config space; |
83 | ; -- it looks like a true PCIe config space; |
84 | mov eax, [mmio_pcie_cfg_addr] ; physical address |
84 | mov eax, [mmio_pcie_cfg_addr] ; physical address |
85 | or eax, (PG_SHARED + PG_LARGE + PG_USER) |
85 | or eax, (PG_SHARED + PG_LARGE + PG_USER) |
86 | mov ebx, PCIe_CONFIG_SPACE ; linear address |
86 | mov ebx, PCIe_CONFIG_SPACE ; linear address |
87 | mov ecx, ebx |
87 | mov ecx, ebx |
88 | shr ebx, 20 |
88 | shr ebx, 20 |
89 | add ebx, sys_pgdir ; PgDir entry @ |
89 | add ebx, sys_pgdir ; PgDir entry @ |
90 | @@: |
90 | @@: |
91 | mov dword[ebx], eax ; map 4 buses |
91 | mov dword[ebx], eax ; map 4 buses |
92 | invlpg [ecx] |
92 | invlpg [ecx] |
93 | cmp bl, 4 |
93 | cmp bl, 4 |
94 | jz .pcie_cfg_mapped ; fix it later |
94 | jz .pcie_cfg_mapped ; fix it later |
95 | add bl, 4 ; next PgDir entry |
95 | add bl, 4 ; next PgDir entry |
96 | add eax, 0x400000 ; eax += 4M |
96 | add eax, 0x400000 ; eax += 4M |
97 | add ecx, 0x400000 |
97 | add ecx, 0x400000 |
98 | jmp @b |
98 | jmp @b |
99 | 99 | ||
100 | .pcie_cfg_mapped: |
100 | .pcie_cfg_mapped: |
101 | 101 | ||
102 | ; -- glad to have the extended PCIe config field found |
102 | ; -- glad to have the extended PCIe config field found |
103 | ; mov esi, boot_pcie_ok |
103 | ; mov esi, boot_pcie_ok |
104 | ; call boot_log |
104 | ; call boot_log |
105 | ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
105 | ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
106 | 106 | ||
107 | .no_pcie_cfg: |
107 | .no_pcie_cfg: |
108 | 108 | ||
109 | xor eax, eax |
109 | xor eax, eax |
110 | mov [mmio_pcie_cfg_addr], eax |
110 | mov [mmio_pcie_cfg_addr], eax |
111 | mov [mmio_pcie_cfg_lim], eax |
111 | mov [mmio_pcie_cfg_lim], eax |
112 | add bl, 12 |
112 | add bl, 12 |
113 | cmp bl, 0xC0 ; MMIO regs lay below this offset |
113 | cmp bl, 0xC0 ; MMIO regs lay below this offset |
114 | jb .check_HT_mmio |
114 | jb .check_HT_mmio |
115 | .pcie_failed: |
115 | .pcie_failed: |
116 | ; mov esi, boot_pcie_fail |
116 | ; mov esi, boot_pcie_fail |
117 | ; call boot_log |
117 | ; call boot_log |
118 | ret ; <<<<<<<<< FAILURE >>>>>>>>>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<><<<<<<<<<><<<<<<<<<<> |
118 | ret ; <<<<<<<<< FAILURE >>>>>>>>>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<>><><<><<<><<<<><<<<<><<<<<<><<<<<<<><<<<<<<<><<<<<<<<<><<<<<<<<<<> |