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Rev 2544 Rev 2852
Line 16... Line 16...
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;;                                                                 ;;
 16 
;;                                                                 ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 17 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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 18 
 
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19 
format MS COFF
 19 
format MS COFF
20 
 
 20 
 
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21 
        API_VERSION             equ 0x01000100
 21 
        API_VERSION             =    0x01000100
Line 22... Line 22...
22 
        DRIVER_VERSION          equ 5
 22 
        DRIVER_VERSION          =    5
23 
 
 23 
 
24 
        MAX_DEVICES             equ 16
 24 
        MAX_DEVICES             =    16
Line 25... Line 25...
25 
 
 25 
 
26 
        DEBUG                   equ 1
 26 
        DEBUG                   =    1
27 
        __DEBUG__               equ 1
 27 
        __DEBUG__               =    1
28 
        __DEBUG_LEVEL__         equ 1
 28 
        __DEBUG_LEVEL__         =    1
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59 
end virtual
 59 
end virtual
Line 60... Line 60...
60 
 
 60 
 
61 
;-------------------------------------------
 61 
;-------------------------------------------
62 
; configuration registers
 62 
; configuration registers
63 
;-------------------------------------------
 63 
;-------------------------------------------
Line 64... Line 64...
64 
CFCS    equ     4       ; configuration and status register
 64 
CFCS    =        4       ; configuration and status register
65 
 
 65 
 
66 
CSR0    equ     0x00     ; Bus mode
 66 
CSR0    =        0x00     ; Bus mode
67 
CSR1    equ     0x08     ; Transmit Poll Command
 67 
CSR1    =        0x08     ; Transmit Poll Command
68 
CSR2    equ     0x10     ; Receive Poll Command
 68 
CSR2    =        0x10     ; Receive Poll Command
69 
CSR3    equ     0x18     ; Receive list base address
 69 
CSR3    =        0x18     ; Receive list base address
70 
CSR4    equ     0x20     ; Transmit list base address
 70 
CSR4    =        0x20     ; Transmit list base address
71 
CSR5    equ     0x28     ; Status
 71 
CSR5    =        0x28     ; Status
72 
CSR6    equ     0x30     ; Operation mode
 72 
CSR6    =        0x30     ; Operation mode
73 
CSR7    equ     0x38     ; Interrupt enable
 73 
CSR7    =        0x38     ; Interrupt enable
74 
CSR8    equ     0x40     ; Missed frames and overflow counter
 74 
CSR8    =        0x40     ; Missed frames and overflow counter
75 
CSR9    equ     0x48     ; Boot ROM, serial ROM, and MII management
 75 
CSR9    =        0x48     ; Boot ROM, serial ROM, and MII management
76 
CSR10   equ     0x50     ; Boot ROM programming address
 76 
CSR10   =        0x50     ; Boot ROM programming address
77 
CSR11   equ     0x58     ; General-purpose timer
 77 
CSR11   =        0x58     ; General-purpose timer
78 
CSR12   equ     0x60     ; General-purpose port
 78 
CSR12   =        0x60     ; General-purpose port
79 
CSR13   equ     0x68
 79 
CSR13   =        0x68
Line 80... Line 80...
80 
CSR14   equ     0x70
 80 
CSR14   =        0x70
81 
CSR15   equ     0x78     ; Watchdog timer
 81 
CSR15   =        0x78     ; Watchdog timer
Line 82... Line 82...
82 
 
 82 
 
83 
;--------bits/commands of CSR0-------------------
 83 
;--------bits/commands of CSR0-------------------
84 
CSR0_RESET              equ     1b
 84 
CSR0_RESET              =        1b
85 
 
 85 
 
86 
CSR0_WIE                equ     1 SHL 24        ; Write and Invalidate Enable
 86 
CSR0_WIE                =        1 SHL 24        ; Write and Invalidate Enable
87 
CSR0_RLE                equ     1 SHL 23        ; PCI Read Line Enable
 87 
CSR0_RLE                =        1 SHL 23        ; PCI Read Line Enable
88 
CSR0_RML                equ     1 SHL 21        ; PCI Read Multiple
 88 
CSR0_RML                =        1 SHL 21        ; PCI Read Multiple
89 
 
 89 
 
Line 90... Line 90...
90 
CSR0_CACHEALIGN_NONE    equ     00b SHL 14
 90 
CSR0_CACHEALIGN_NONE    =        00b SHL 14
91 
CSR0_CACHEALIGN_32      equ     01b SHL 14
 91 
CSR0_CACHEALIGN_32      =        01b SHL 14
Line 92... Line 92...
92 
CSR0_CACHEALIGN_64      equ     10b SHL 14
 92 
CSR0_CACHEALIGN_64      =        10b SHL 14
93 
CSR0_CACHEALIGN_128     equ     11b SHL 14
 93 
CSR0_CACHEALIGN_128     =        11b SHL 14
94 
 
 94 
 
95 
; using values from linux driver.. :P
 95 
; using values from linux driver.. :P
96 
CSR0_DEFAULT            equ     CSR0_WIE+CSR0_RLE+CSR0_RML+CSR0_CACHEALIGN_NONE ;32
 96 
CSR0_DEFAULT            =        CSR0_WIE+CSR0_RLE+CSR0_RML+CSR0_CACHEALIGN_NONE ;32
97 
 
 97 
 
98 
;------- CSR5 -STATUS- bits --------------------------------
 98 
;------- CSR5 -STATUS- bits --------------------------------
99 
CSR5_TI                 equ     1 SHL 0         ; Transmit interupt - frame transmition completed
 99 
CSR5_TI                 =        1 SHL 0         ; Transmit interupt - frame transmition completed
100 
CSR5_TPS                equ     1 SHL 1         ; Transmit process stopped
 100 
CSR5_TPS                =        1 SHL 1         ; Transmit process stopped
101 
CSR5_TU                 equ     1 SHL 2         ; Transmit Buffer unavailable
 101 
CSR5_TU                 =        1 SHL 2         ; Transmit Buffer unavailable
102 
CSR5_TJT                equ     1 SHL 3         ; Transmit Jabber Timeout (transmitter had been excessively active)
 102 
CSR5_TJT                =        1 SHL 3         ; Transmit Jabber Timeout (transmitter had been excessively active)
103 
CSR5_UNF                equ     1 SHL 5         ; Transmit underflow - FIFO underflow
 103 
CSR5_UNF                =        1 SHL 5         ; Transmit underflow - FIFO underflow
104 
CSR5_RI                 equ     1 SHL 6         ; Receive Interrupt
 104 
CSR5_RI                 =        1 SHL 6         ; Receive Interrupt
105 
CSR5_RU                 equ     1 SHL 7         ; Receive Buffer unavailable
 105 
CSR5_RU                 =        1 SHL 7         ; Receive Buffer unavailable
106 
CSR5_RPS                equ     1 SHL 8         ; Receive Process stopped
 106 
CSR5_RPS                =        1 SHL 8         ; Receive Process stopped
107 
CSR5_RWT                equ     1 SHL 9         ; Receive Watchdow Timeout
 107 
CSR5_RWT                =        1 SHL 9         ; Receive Watchdow Timeout
108 
CSR5_ETI                equ     1 SHL 10        ; Early transmit Interrupt
 108 
CSR5_ETI                =        1 SHL 10        ; Early transmit Interrupt
109 
CSR5_GTE                equ     1 SHL 11        ; General Purpose Timer Expired
 109 
CSR5_GTE                =        1 SHL 11        ; General Purpose Timer Expired
110 
CSR5_FBE                equ     1 SHL 13        ; Fatal bus error
 110 
CSR5_FBE                =        1 SHL 13        ; Fatal bus error
111 
CSR5_ERI                equ     1 SHL 14        ; Early receive Interrupt
 111 
CSR5_ERI                =        1 SHL 14        ; Early receive Interrupt
112 
CSR5_AIS                equ     1 SHL 15        ; Abnormal interrupt summary
 112 
CSR5_AIS                =        1 SHL 15        ; Abnormal interrupt summary
113 
CSR5_NIS                equ     1 SHL 16        ; normal interrupt summary
 113 
CSR5_NIS                =        1 SHL 16        ; normal interrupt summary
Line 114... Line 114...
114 
CSR5_RS_SH              equ     1 SHL 17        ; Receive process state  -shift
 114 
CSR5_RS_SH              =        1 SHL 17        ; Receive process state  -shift
115 
CSR5_RS_MASK            equ     111b            ;                        -mask
 115 
CSR5_RS_MASK            =        111b            ;                        -mask
116 
CSR5_TS_SH              equ     1 SHL 20        ; Transmit process state -shift
 116 
CSR5_TS_SH              =        1 SHL 20        ; Transmit process state -shift
117 
CSR5_TS_MASK            equ     111b            ;                        -mask
 117 
CSR5_TS_MASK            =        111b            ;                        -mask
118 
CSR5_EB_SH              equ     1 SHL 23        ; Error bits             -shift
 118 
CSR5_EB_SH              =        1 SHL 23        ; Error bits             -shift
119 
CSR5_EB_MASK            equ     111b            ; Error bits             -mask
 119 
CSR5_EB_MASK            =        111b            ; Error bits             -mask
120 
 
 120 
 
121 
;CSR5 TS values
 121 
;CSR5 TS values
Line 122... Line 122...
122 
CSR5_TS_STOPPED                equ     000b
 122 
CSR5_TS_STOPPED                =        000b
123 
CSR5_TS_RUNNING_FETCHING_DESC  equ     001b
 123 
CSR5_TS_RUNNING_FETCHING_DESC  =        001b
124 
CSR5_TS_RUNNING_WAITING_TX     equ     010b
 124 
CSR5_TS_RUNNING_WAITING_TX     =        010b
125 
CSR5_TS_RUNNING_READING_BUFF   equ     011b
 125 
CSR5_TS_RUNNING_READING_BUFF   =        011b
126 
CSR5_TS_RUNNING_SETUP_PCKT     equ     101b
 126 
CSR5_TS_RUNNING_SETUP_PCKT     =        101b
127 
CSR5_TS_SUSPENDED              equ     110b
 127 
CSR5_TS_SUSPENDED              =        110b
128 
CSR5_TS_RUNNING_CLOSING_DESC   equ     111b
 128 
CSR5_TS_RUNNING_CLOSING_DESC   =        111b
129 
 
 129 
 
130 
;------- CSR6 -OPERATION MODE- bits --------------------------------
 130 
;------- CSR6 -OPERATION MODE- bits --------------------------------
131 
CSR6_HP                 equ     1 SHL 0         ; Hash/Perfect Receive Filtering mode
 131 
CSR6_HP                 =        1 SHL 0         ; Hash/Perfect Receive Filtering mode
132 
CSR6_SR                 equ     1 SHL 1         ; Start/Stop receive
 132 
CSR6_SR                 =        1 SHL 1         ; Start/Stop receive
133 
CSR6_HO                 equ     1 SHL 2         ; Hash only Filtering mode
 133 
CSR6_HO                 =        1 SHL 2         ; Hash only Filtering mode
134 
CSR6_PB                 equ     1 SHL 3         ; Pass bad frames
 134 
CSR6_PB                 =        1 SHL 3         ; Pass bad frames
135 
CSR6_IF                 equ     1 SHL 4         ; Inverse filtering
 135 
CSR6_IF                 =        1 SHL 4         ; Inverse filtering
136 
CSR6_SB                 equ     1 SHL 5         ; Start/Stop backoff counter
 136 
CSR6_SB                 =        1 SHL 5         ; Start/Stop backoff counter
137 
CSR6_PR                 equ     1 SHL 6         ; Promiscuos mode -default after reset
 137 
CSR6_PR                 =        1 SHL 6         ; Promiscuos mode -default after reset
138 
CSR6_PM                 equ     1 SHL 7         ; Pass all multicast
 138 
CSR6_PM                 =        1 SHL 7         ; Pass all multicast
139 
CSR6_F                  equ     1 SHL 9         ; Full Duplex mode
 139 
CSR6_F                  =        1 SHL 9         ; Full Duplex mode
140 
CSR6_OM_SH              equ     1 SHL 10        ; Operating Mode -shift
 140 
CSR6_OM_SH              =        1 SHL 10        ; Operating Mode -shift
141 
CSR6_OM_MASK            equ     11b             ;                -mask
 141 
CSR6_OM_MASK            =        11b             ;                -mask
142 
CSR6_FC                 equ     1 SHL 12        ; Force Collision Mode
 142 
CSR6_FC                 =        1 SHL 12        ; Force Collision Mode
143 
CSR6_ST                 equ     1 SHL 13        ; Start/Stop Transmission Command
 143 
CSR6_ST                 =        1 SHL 13        ; Start/Stop Transmission Command
144 
CSR6_TR_SH              equ     1 SHL 14        ; Threshold Control      -shift
 144 
CSR6_TR_SH              =        1 SHL 14        ; Threshold Control      -shift
145 
CSR6_TR_MASK            equ     11b             ;                        -mask
 145 
CSR6_TR_MASK            =        11b             ;                        -mask
146 
CSR6_CA                 equ     1 SHL 17        ; Capture Effect Enable
 146 
CSR6_CA                 =        1 SHL 17        ; Capture Effect Enable
147 
CSR6_PS                 equ     1 SHL 18        ; Port select SRL / MII/SYM
 147 
CSR6_PS                 =        1 SHL 18        ; Port select SRL / MII/SYM
Line 148... Line 148...
148 
CSR6_HBD                equ     1 SHL 19        ; Heartbeat Disable
 148 
CSR6_HBD                =        1 SHL 19        ; Heartbeat Disable
149 
CSR6_SF                 equ     1 SHL 21        ; Store and Forward -transmit full packet only
 149 
CSR6_SF                 =        1 SHL 21        ; Store and Forward -transmit full packet only
150 
CSR6_TTM                equ     1 SHL 22        ; Transmit Threshold Mode -
 150 
CSR6_TTM                =        1 SHL 22        ; Transmit Threshold Mode -
151 
CSR6_PCS                equ     1 SHL 23        ; PCS active and MII/SYM port operates in symbol mode
 151 
CSR6_PCS                =        1 SHL 23        ; PCS active and MII/SYM port operates in symbol mode
152 
CSR6_SCR                equ     1 SHL 24        ; Scrambler Mode
 152 
CSR6_SCR                =        1 SHL 24        ; Scrambler Mode
153 
CSR6_MBO                equ     1 SHL 25        ; Must Be One
 153 
CSR6_MBO                =        1 SHL 25        ; Must Be One
154 
CSR6_RA                 equ     1 SHL 30        ; Receive All
 154 
CSR6_RA                 =        1 SHL 30        ; Receive All
155 
CSR6_SC                 equ     1 SHL 31        ; Special Capture Effect Enable
 155 
CSR6_SC                 =        1 SHL 31        ; Special Capture Effect Enable
156 
 
 156 
 
157 
 
 157 
 
158 
;------- CSR7 -INTERRUPT ENABLE- bits --------------------------------
 158 
;------- CSR7 -INTERRUPT ENABLE- bits --------------------------------
159 
CSR7_TI                 equ     1 SHL 0         ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )
 159 
CSR7_TI                 =        1 SHL 0         ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )
160 
CSR7_TS                 equ     1 SHL 1         ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )
 160 
CSR7_TS                 =        1 SHL 1         ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )
161 
CSR7_TU                 equ     1 SHL 2         ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )
 161 
CSR7_TU                 =        1 SHL 2         ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )
162 
CSR7_TJ                 equ     1 SHL 3         ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )
 162 
CSR7_TJ                 =        1 SHL 3         ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )
163 
CSR7_UN                 equ     1 SHL 5         ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )
 163 
CSR7_UN                 =        1 SHL 5         ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )
164 
CSR7_RI                 equ     1 SHL 6         ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )
 164 
CSR7_RI                 =        1 SHL 6         ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )
165 
CSR7_RU                 equ     1 SHL 7         ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )
 165 
CSR7_RU                 =        1 SHL 7         ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )
Line 166... Line 166...
166 
CSR7_RS                 equ     1 SHL 8         ; Receive stopped enable (set with CSR7<15> & CSR5<8> )
 166 
CSR7_RS                 =        1 SHL 8         ; Receive stopped enable (set with CSR7<15> & CSR5<8> )
167 
CSR7_RW                 equ     1 SHL 9         ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )
 167 
CSR7_RW                 =        1 SHL 9         ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )
168 
CSR7_ETE                equ     1 SHL 10        ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )
 168 
CSR7_ETE                =        1 SHL 10        ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )
Line 187... Line 187...
187 
virtual at 0
 187 
virtual at 0
188 
        DES DES
 188 
        DES DES
189 
end virtual
 189 
end virtual
Line 190... Line 190...
190 
 
 190 
 
191 
;common to Rx and Tx
 191 
;common to Rx and Tx
Line 192... Line 192...
192 
DES0_OWN        equ     1 SHL 31        ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors
 192 
DES0_OWN        =        1 SHL 31        ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors
193 
 
 193 
 
194 
;receive
 194 
;receive
195 
RDES0_ZER       equ     1 SHL 0         ; must be 0 if legal length :D
 195 
RDES0_ZER       =        1 SHL 0         ; must be 0 if legal length :D
196 
RDES0_CE        equ     1 SHL 1         ; CRC error, valid only on last desc (RDES0<8>=1)
 196 
RDES0_CE        =        1 SHL 1         ; CRC error, valid only on last desc (RDES0<8>=1)
197 
RDES0_DB        equ     1 SHL 2         ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)
 197 
RDES0_DB        =        1 SHL 2         ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)
198 
RDES0_RE        equ     1 SHL 3         ; Report on MII error.. i dont realy know what this means :P
 198 
RDES0_RE        =        1 SHL 3         ; Report on MII error.. i dont realy know what this means :P
199 
RDES0_RW        equ     1 SHL 4         ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)
 199 
RDES0_RW        =        1 SHL 4         ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)
200 
RDES0_FT        equ     1 SHL 5         ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)
 200 
RDES0_FT        =        1 SHL 5         ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)
201 
RDES0_CS        equ     1 SHL 6         ; Collision seen, valid only on last desc (RDES0<8>=1)
 201 
RDES0_CS        =        1 SHL 6         ; Collision seen, valid only on last desc (RDES0<8>=1)
202 
RDES0_TL        equ     1 SHL 7         ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)
 202 
RDES0_TL        =        1 SHL 7         ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)
203 
RDES0_LS        equ     1 SHL 8         ; Last descriptor of current frame
 203 
RDES0_LS        =        1 SHL 8         ; Last descriptor of current frame
204 
RDES0_FS        equ     1 SHL 9         ; First descriptor of current frame
 204 
RDES0_FS        =        1 SHL 9         ; First descriptor of current frame
205 
RDES0_MF        equ     1 SHL 10        ; Multicast frame, valid only on last desc (RDES0<8>=1)
 205 
RDES0_MF        =        1 SHL 10        ; Multicast frame, valid only on last desc (RDES0<8>=1)
206 
RDES0_RF        equ     1 SHL 11        ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow
 206 
RDES0_RF        =        1 SHL 11        ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow
207 
RDES0_DT_SERIAL equ     00b SHL 12      ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)
 207 
RDES0_DT_SERIAL =        00b SHL 12      ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)
208 
RDES0_DT_INTERNAL equ   01b SHL 12      ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)
 208 
RDES0_DT_INTERNAL =      01b SHL 12      ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)
209 
RDES0_DT_EXTERNAL equ   11b SHL 12      ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)
 209 
RDES0_DT_EXTERNAL =      11b SHL 12      ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)
210 
RDES0_DE        equ     1 SHL 14        ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)
 210 
RDES0_DE        =        1 SHL 14        ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)
211 
RDES0_ES        equ     1 SHL 15        ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)
 211 
RDES0_ES        =        1 SHL 15        ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)
212 
RDES0_FL_SH     equ     16              ; Field length shift, valid only on last desc (RDES0<8>=1)
 212 
RDES0_FL_SH     =        16              ; Field length shift, valid only on last desc (RDES0<8>=1)
213 
RDES0_FL_MASK   equ     11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)
 213 
RDES0_FL_MASK   =        11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)
214 
RDES0_FF        equ     1 SHL 30        ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)
 214 
RDES0_FF        =        1 SHL 30        ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)
215 
 
 215 
 
216 
RDES1_RBS1_MASK equ     11111111111b    ; firsd buffer size MASK
 216 
RDES1_RBS1_MASK =        11111111111b    ; firsd buffer size MASK
217 
RDES1_RBS2_SH   equ     1 SHL 11        ; second buffer size SHIFT
 217 
RDES1_RBS2_SH   =        1 SHL 11        ; second buffer size SHIFT
218 
RDES1_RBS2_MASK equ     11111111111b    ; second buffer size MASK
 218 
RDES1_RBS2_MASK =        11111111111b    ; second buffer size MASK
Line 219... Line 219...
219 
RDES1_RCH       equ     1 SHL 24        ; Second address chained - second address (buffer) is next desc address
 219 
RDES1_RCH       =        1 SHL 24        ; Second address chained - second address (buffer) is next desc address
220 
RDES1_RER       equ     1 SHL 25        ; Receive End of Ring - final descriptor, NIC must return to first desc
 220 
RDES1_RER       =        1 SHL 25        ; Receive End of Ring - final descriptor, NIC must return to first desc
221 
 
 221 
 
222 
;transmition
 222 
;transmition
223 
TDES0_DE        equ     1 SHL 0         ; Deffered
 223 
TDES0_DE        =        1 SHL 0         ; Deffered
224 
TDES0_UF        equ     1 SHL 1         ; Underflow error
 224 
TDES0_UF        =        1 SHL 1         ; Underflow error
225 
TDES0_LF        equ     1 SHL 2         ; Link fail report (only if CSR6<23>=1)
 225 
TDES0_LF        =        1 SHL 2         ; Link fail report (only if CSR6<23>=1)
226 
TDES0_CC_SH     equ     3               ; Collision Count shift - no of collision before transmition
 226 
TDES0_CC_SH     =        3               ; Collision Count shift - no of collision before transmition
227 
TDES0_CC_MASK   equ     1111b           ; Collision Count mask
 227 
TDES0_CC_MASK   =        1111b           ; Collision Count mask
228 
TDES0_HF        equ     1 SHL 7         ; Heartbeat fail
 228 
TDES0_HF        =        1 SHL 7         ; Heartbeat fail
229 
TDES0_EC        equ     1 SHL 8         ; Excessive Collisions - >16 collisions
 229 
TDES0_EC        =        1 SHL 8         ; Excessive Collisions - >16 collisions
230 
TDES0_LC        equ     1 SHL 9         ; Late collision
 230 
TDES0_LC        =        1 SHL 9         ; Late collision
231 
TDES0_NC        equ     1 SHL 10        ; No carrier
 231 
TDES0_NC        =        1 SHL 10        ; No carrier
232 
TDES0_LO        equ     1 SHL 11        ; Loss of carrier
 232 
TDES0_LO        =        1 SHL 11        ; Loss of carrier
233 
TDES0_TO        equ     1 SHL 14        ; Transmit Jabber Timeout
 233 
TDES0_TO        =        1 SHL 14        ; Transmit Jabber Timeout
234 
TDES0_ES        equ     1 SHL 15        ; Error summary TDES0<1+8+9+10+11+14>=1
 234 
TDES0_ES        =        1 SHL 15        ; Error summary TDES0<1+8+9+10+11+14>=1
235 
 
 235 
 
236 
TDES1_TBS1_MASK equ     11111111111b    ; Buffer 1 size mask
 236 
TDES1_TBS1_MASK =        11111111111b    ; Buffer 1 size mask
237 
TDES1_TBS2_SH   equ     11              ; Buffer 2 size shift
 237 
TDES1_TBS2_SH   =        11              ; Buffer 2 size shift
238 
TDES1_TBS2_MASK equ     11111111111b    ; Buffer 2 size mask
 238 
TDES1_TBS2_MASK =        11111111111b    ; Buffer 2 size mask
239 
TDES1_FT0       equ     1 SHL 22        ; Filtering type 0
 239 
TDES1_FT0       =        1 SHL 22        ; Filtering type 0
240 
TDES1_DPD       equ     1 SHL 23        ; Disabled padding for packets <64bytes, no padding
 240 
TDES1_DPD       =        1 SHL 23        ; Disabled padding for packets <64bytes, no padding
241 
TDES1_TCH       equ     1 SHL 24        ; Second address chained - second buffer pointer is to next desc
 241 
TDES1_TCH       =        1 SHL 24        ; Second address chained - second buffer pointer is to next desc
242 
TDES1_TER       equ     1 SHL 25        ; Transmit end of ring - final descriptor
 242 
TDES1_TER       =        1 SHL 25        ; Transmit end of ring - final descriptor
243 
TDES1_AC        equ     1 SHL 26        ; Add CRC disable -pretty obvious
 243 
TDES1_AC        =        1 SHL 26        ; Add CRC disable -pretty obvious
244 
TDES1_SET       equ     1 SHL 27        ; Setup packet
 244 
TDES1_SET       =        1 SHL 27        ; Setup packet
245 
TDES1_FT1       equ     1 SHL 28        ; Filtering type 1
 245 
TDES1_FT1       =        1 SHL 28        ; Filtering type 1
246 
TDES1_FS        equ     1 SHL 29        ; First segment - buffer is first segment of frame
 246 
TDES1_FS        =        1 SHL 29        ; First segment - buffer is first segment of frame
247 
TDES1_LS        equ     1 SHL 30        ; Last segment
 247 
TDES1_LS        =        1 SHL 30        ; Last segment
248 
TDES1_IC        equ     1 SHL 31        ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1
 248 
TDES1_IC        =        1 SHL 31        ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1
249 
 
 249 
 
250 
MAX_ETH_FRAME_SIZE      equ     1514
 250 
MAX_ETH_FRAME_SIZE      =        1514
251 
 
 251 
 
252 
RX_DES_COUNT            equ     4              ; no of RX descriptors, must be power of 2
 252 
RX_DES_COUNT            =        4              ; no of RX descriptors, must be power of 2
Line 253... Line 253...
253 
RX_BUFF_SIZE            equ     2048            ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK
 253 
RX_BUFF_SIZE            =        2048            ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK
254 
TX_DES_COUNT            equ     4              ; no of TX descriptors, must be power of 2
 254 
TX_DES_COUNT            =        4              ; no of TX descriptors, must be power of 2
Line 255... Line 255...
255 
TX_BUFF_SIZE            equ     2048            ; size of buffer for each descriptor, used for memory allocation only
 255 
TX_BUFF_SIZE            =        2048            ; size of buffer for each descriptor, used for memory allocation only
256 
 
 256 
 
257 
RX_MEM_TOTAL_SIZE       equ     RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)
 257 
RX_MEM_TOTAL_SIZE       =        RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)
258 
TX_MEM_TOTAL_SIZE       equ     TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)
 258 
TX_MEM_TOTAL_SIZE       =        TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)
259 
 
 259 
 
260 
;=============================================================================
 260 
;=============================================================================
261 
; serial ROM operations
 261 
; serial ROM operations
262 
;=============================================================================
 262 
;=============================================================================
263 
CSR9_SR                 equ     1 SHL 11        ; SROM Select
 263 
CSR9_SR                 =        1 SHL 11        ; SROM Select
Line 264... Line 264...
264 
CSR9_RD                 equ     1 SHL 14        ; ROM Read Operation
 264 
CSR9_RD                 =        1 SHL 14        ; ROM Read Operation
265 
CSR9_SROM_DO            equ     1 SHL 3         ; Data Out for SROM
 265 
CSR9_SROM_DO            =        1 SHL 3         ; Data Out for SROM
266 
CSR9_SROM_DI            equ     1 SHL 2         ; Data In to SROM
 266 
CSR9_SROM_DI            =        1 SHL 2         ; Data In to SROM
267 
CSR9_SROM_CK            equ     1 SHL 1         ; clock for SROM
 267 
CSR9_SROM_CK            =        1 SHL 1         ; clock for SROM
Line 1485... Line 1485...
1485 
 
 1485 
 
1486 
; Read and write the MII registers using software-generated serial
 1486 
; Read and write the MII registers using software-generated serial
1487 
; MDIO protocol.  It is just different enough from the EEPROM protocol
 1487 
; MDIO protocol.  It is just different enough from the EEPROM protocol
Line 1488... Line 1488...
1488 
; to not share code.  The maxium data clock rate is 2.5 Mhz.
 1488 
; to not share code.  The maxium data clock rate is 2.5 Mhz.
1489 
 
 1489 
 
1490 
MDIO_SHIFT_CLK          equ     0x10000
 1490 
MDIO_SHIFT_CLK          =        0x10000
1491 
MDIO_DATA_WRITE0        equ     0x00000
 1491 
MDIO_DATA_WRITE0        =        0x00000
1492 
MDIO_DATA_WRITE1        equ     0x20000
 1492 
MDIO_DATA_WRITE1        =        0x20000
1493 
MDIO_ENB                equ     0x00000         ; Ignore the 0x02000 databook setting.
 1493 
MDIO_ENB                =        0x00000         ; Ignore the 0x02000 databook setting.
Line 1494... Line 1494...
1494 
MDIO_ENB_IN             equ     0x40000
 1494 
MDIO_ENB_IN             =        0x40000
1495 
MDIO_DATA_READ          equ     0x80000
 1495 
MDIO_DATA_READ          =        0x80000
1496 
 
 1496 
 
1497 
; MII transceiver control section.
 1497 
; MII transceiver control section.