WebSVN – Kolibri OS – Diff – /kernel/branches/net/drivers/RTL8169.asm


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2010. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;  RTL8169 driver for KolibriOS                                   ;;
;;                                                                 ;;
;;  Copyright 2007 mike.dld,                                       ;;
;;   mike.dld@gmail.com                                            ;;
;;                                                                 ;;
;;  Version 0.1  11 February 2007                                  ;;
;;  Version 0.2  3 August 2010 - port to net branch by hidnplayr   ;;
;;                                                                 ;;
;;  References:                                                    ;;
;;    r8169.c - linux driver (etherboot project)                   ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
format MS COFF
 
	API_VERSION		equ 0x01000100
	DRIVER_VERSION		equ 5
 
	MAX_DEVICES		equ 16
 
	DEBUG			equ 1
	__DEBUG__		equ 1
	__DEBUG_LEVEL__ 	equ 1
 
	NUM_TX_DESC		equ 4
	NUM_RX_DESC		equ 4
 
include 'proc32.inc'
include 'imports.inc'
include 'fdo.inc'
include 'netdrv.inc'
 
public START
public service_proc
public version
 
 
	REG_MAC0	       equ 0x0 ; Ethernet hardware address
	REG_MAR0	       equ 0x8 ; Multicast filter
	REG_TxDescStartAddr    equ 0x20
	REG_TxHDescStartAddr   equ 0x28
	REG_FLASH	       equ 0x30
	REG_ERSR	       equ 0x36
	REG_ChipCmd	       equ 0x37
	REG_TxPoll	       equ 0x38
	REG_IntrMask	       equ 0x3C
	REG_IntrStatus	       equ 0x3E
	REG_TxConfig	       equ 0x40
	REG_RxConfig	       equ 0x44
	REG_RxMissed	       equ 0x4C
	REG_Cfg9346	       equ 0x50
	REG_Config0	       equ 0x51
	REG_Config1	       equ 0x52
	REG_Config2	       equ 0x53
	REG_Config3	       equ 0x54
	REG_Config4	       equ 0x55
	REG_Config5	       equ 0x56
	REG_MultiIntr	       equ 0x5C
	REG_PHYAR	       equ 0x60
	REG_TBICSR	       equ 0x64
	REG_TBI_ANAR	       equ 0x68
	REG_TBI_LPAR	       equ 0x6A
	REG_PHYstatus	       equ 0x6C
	REG_RxMaxSize	       equ 0xDA
	REG_CPlusCmd	       equ 0xE0
	REG_RxDescStartAddr    equ 0xE4
	REG_ETThReg	       equ 0xEC
	REG_FuncEvent	       equ 0xF0
	REG_FuncEventMask      equ 0xF4
	REG_FuncPresetState    equ 0xF8
	REG_FuncForceEvent     equ 0xFC
 
	; InterruptStatusBits
	ISB_SYSErr	       equ 0x8000
	ISB_PCSTimeout	       equ 0x4000
	ISB_SWInt	       equ 0x0100
	ISB_TxDescUnavail      equ 0x80
	ISB_RxFIFOOver	       equ 0x40
	ISB_LinkChg	       equ 0x20
	ISB_RxOverflow	       equ 0x10
	ISB_TxErr	       equ 0x08
	ISB_TxOK	       equ 0x04
	ISB_RxErr	       equ 0x02
	ISB_RxOK	       equ 0x01
 
	; RxStatusDesc
	SD_RxRES	       equ 0x00200000
	SD_RxCRC	       equ 0x00080000
	SD_RxRUNT	       equ 0x00100000
	SD_RxRWT	       equ 0x00400000
 
	; ChipCmdBits
	CMD_Reset	       equ 0x10
	CMD_RxEnb	       equ 0x08
	CMD_TxEnb	       equ 0x04
	CMD_RxBufEmpty	       equ 0x01
 
	; Cfg9346Bits
	CFG_9346_Lock	       equ 0x00
	CFG_9346_Unlock        equ 0xC0
 
	; rx_mode_bits
	RXM_AcceptErr	       equ 0x20
	RXM_AcceptRunt	       equ 0x10
	RXM_AcceptBroadcast    equ 0x08
	RXM_AcceptMulticast    equ 0x04
	RXM_AcceptMyPhys       equ 0x02
	RXM_AcceptAllPhys      equ 0x01
 
	; RxConfigBits
	RXC_FIFOShift	       equ 13
	RXC_DMAShift	       equ 8
 
	; TxConfigBits
	TXC_InterFrameGapShift equ 24
	TXC_DMAShift	       equ 8	; DMA burst value (0-7) is shift this many bits
 
	; PHYstatus
	PHYS_TBI_Enable        equ 0x80
	PHYS_TxFlowCtrl        equ 0x40
	PHYS_RxFlowCtrl        equ 0x20
	PHYS_1000bpsF	       equ 0x10
	PHYS_100bps	       equ 0x08
	PHYS_10bps	       equ 0x04
	PHYS_LinkStatus        equ 0x02
	PHYS_FullDup	       equ 0x01
 
	; GIGABIT_PHY_registers
	PHY_CTRL_REG	       equ 0
	PHY_STAT_REG	       equ 1
	PHY_AUTO_NEGO_REG      equ 4
	PHY_1000_CTRL_REG      equ 9
 
	; GIGABIT_PHY_REG_BIT
	PHY_Restart_Auto_Nego  equ 0x0200
	PHY_Enable_Auto_Nego   equ 0x1000
 
	; PHY_STAT_REG = 1;
	PHY_Auto_Neco_Comp     equ 0x0020
 
	; PHY_AUTO_NEGO_REG = 4;
	PHY_Cap_10_Half        equ 0x0020
	PHY_Cap_10_Full        equ 0x0040
	PHY_Cap_100_Half       equ 0x0080
	PHY_Cap_100_Full       equ 0x0100
 
	; PHY_1000_CTRL_REG = 9;
	PHY_Cap_1000_Full      equ 0x0200
	PHY_Cap_1000_Half      equ 0x0100
 
	PHY_Cap_PAUSE	       equ 0x0400
	PHY_Cap_ASYM_PAUSE     equ 0x0800
 
	PHY_Cap_Null	       equ 0x0
 
	; _MediaType
	MT_10_Half	       equ 0x01
	MT_10_Full	       equ 0x02
	MT_100_Half	       equ 0x04
	MT_100_Full	       equ 0x08
	MT_1000_Full	       equ 0x10
 
	; _TBICSRBit
	TBI_LinkOK	       equ 0x02000000
 
	; _DescStatusBit
	DSB_OWNbit	       equ 0x80000000
	DSB_EORbit	       equ 0x40000000
	DSB_FSbit	       equ 0x20000000
	DSB_LSbit	       equ 0x10000000
 
	RX_BUF_SIZE		equ 1536    ; Rx Buffer size
 
 
ETH_ALEN	       equ 6
ETH_HLEN	       equ (2 * ETH_ALEN + 2)
ETH_ZLEN	       equ 60 ; 60 + 4bytes auto payload for
				      ; mininmum 64bytes frame length
 
; MAC address length
MAC_ADDR_LEN	    equ 6
 
; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
MAX_ETH_FRAME_SIZE  equ 1536
 
TX_FIFO_THRESH	    equ 256	; In bytes
 
RX_FIFO_THRESH	    equ 7	; 7 means NO threshold, Rx buffer level before first PCI xfer
RX_DMA_BURST	    equ 7	; Maximum PCI burst, '6' is 1024
TX_DMA_BURST	    equ 7	; Maximum PCI burst, '6' is 1024
ETTh		    equ 0x3F	; 0x3F means NO threshold
 
EarlyTxThld	    equ 0x3F	; 0x3F means NO early transmit
RxPacketMaxSize     equ 0x0800	; Maximum size supported is 16K-1
InterFrameGap	    equ 0x03	; 3 means InterFrameGap = the shortest one
 
HZ		    equ 1000
 
RTL_MIN_IO_SIZE     equ 0x80
TX_TIMEOUT	    equ (6*HZ)
 
TIMER_EXPIRE_TIME equ 100
 
ETH_HDR_LEN	    equ 14
DEFAULT_MTU	    equ 1500
DEFAULT_RX_BUF_LEN  equ 1536
 
 
;#ifdef JUMBO_FRAME_SUPPORT
;#define MAX_JUMBO_FRAME_MTU    ( 10000 )
;#define MAX_RX_SKBDATA_SIZE    ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
;#else
MAX_RX_SKBDATA_SIZE equ 1600
;#endif                         //end #ifdef JUMBO_FRAME_SUPPORT
 
MCFG_METHOD_01	     equ 0x01
MCFG_METHOD_02	     equ 0x02
MCFG_METHOD_03	     equ 0x03
MCFG_METHOD_04	     equ 0x04
MCFG_METHOD_05	     equ 0x05
MCFG_METHOD_11	     equ 0x0b
MCFG_METHOD_12	     equ 0x0c
MCFG_METHOD_13	     equ 0x0d
MCFG_METHOD_14	     equ 0x0e
MCFG_METHOD_15	     equ 0x0f
 
PCFG_METHOD_1	    equ 0x01	; PHY Reg 0x03 bit0-3 == 0x0000
PCFG_METHOD_2	    equ 0x02	; PHY Reg 0x03 bit0-3 == 0x0001
PCFG_METHOD_3	    equ 0x03	; PHY Reg 0x03 bit0-3 == 0x0002
 
virtual at 0
  tx_desc:
  .status    dd ?
  .vlan_tag  dd ?
  .buf_addr  dq ?
  .size = $
  rb	(NUM_TX_DESC-1)*tx_desc.size
  .buf_soft_addr	dd ?
end virtual
 
virtual at 0
  rx_desc:
  .status    dd ?
  .vlan_tag  dd ?
  .buf_addr  dq ?
  .size = $
  rb	(NUM_RX_DESC-1)*rx_desc.size
  .buf_soft_addr	dd ?
end virtual
 
virtual at ebx
 
	device:
 
	ETH_DEVICE
 
	.io_addr	dd ?
	.pci_bus	db ?
	.pci_dev	db ?
	.irq_line	db ?
 
	tpc:
	.mmio_addr	dd ? ; memory map physical address
	.chipset	dd ?
	.pcfg		dd ?
	.mcfg		dd ?
	.cur_rx 	dd ? ; Index into the Rx descriptor buffer of next Rx pkt
	.cur_tx 	dd ? ; Index into the Tx descriptor buffer of next Rx pkt
	.TxDescArrays	dd ? ; Index of Tx Descriptor buffer
	.RxDescArrays	dd ? ; Index of Rx Descriptor buffer
	.TxDescArray	dd ? ; Index of 256-alignment Tx Descriptor buffer
	.RxDescArray	dd ? ; Index of 256-alignment Rx Descriptor buffer
 
	rb 256-(($ - device) and 255)		   ;        align 256
	tx_ring rb NUM_TX_DESC * tx_desc.size * 2
 
	rb 256-(($ - device) and 255)		   ;        align 256
	rx_ring rb NUM_RX_DESC * rx_desc.size * 2
 
	device_size = $ - device
 
end virtual
 
intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
 
 
macro	udelay msec {
 
	push	esi
	mov	esi, msec
	call	Sleep
	pop	esi
 
}
 
macro	WRITE_GMII_REG	RegAddr, value {
 
	set_io	REG_PHYAR
	if	value eq ax
	and	eax, 0x0000ffff
	or	eax, 0x80000000 + (RegAddr shl 16)
	else
	mov	eax, 0x80000000 + (RegAddr shl 16) + value
	end if
	out	dx, eax
 
	call	PHY_WAIT
}
 
macro	READ_GMII_REG  RegAddr {
 
local	.error, .done
 
	set_io	REG_PHYAR
	mov	eax, RegAddr shl 16
	out	dx, eax
 
	call	PHY_WAIT
	jz	.error
 
	in	eax, dx
	and	eax, 0xFFFF
	jmp	.done
 
  .error:
	or	eax, -1
  .done:
}
 
align 4
PHY_WAIT:	; io addr must already be set to REG_PHYAR
 
	udelay	1	 ;;;1000
 
	push	ecx
	mov	ecx, 2000
	; Check if the RTL8169 has completed writing/reading to the specified MII register
    @@:
	in	eax, dx
	test	eax, 0x80000000
	jz	.exit
	udelay	1	 ;;;100
	loop	@b
  .exit:
	pop	ecx
	ret
 
 
 
section '.flat' code readable align 16
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc START             ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc START stdcall, state:dword
 
	cmp [state], 1
	jne .exit
 
  .entry:
 
	DEBUGF	2,"Loading rtl8169 driver\n"
	stdcall RegService, my_service, service_proc
	ret
 
  .fail:
  .exit:
	xor eax, eax
	ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc SERVICE_PROC      ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc service_proc stdcall, ioctl:dword
 
	mov	edx, [ioctl]
	mov	eax, [IOCTL.io_code]
 
;------------------------------------------------------
 
	cmp	eax, 0 ;SRV_GETVERSION
	jne	@F
 
	cmp	[IOCTL.out_size], 4
	jl	.fail
	mov	eax, [IOCTL.output]
	mov	[eax], dword API_VERSION
 
	xor	eax, eax
	ret
 
;------------------------------------------------------
  @@:
	cmp	eax, 1 ;SRV_HOOK
	jne	.fail
 
	cmp	[IOCTL.inp_size], 3			; Data input must be at least 3 bytes
	jl	.fail
 
	mov	eax, [IOCTL.input]
	cmp	byte [eax], 1				; 1 means device number and bus number (pci) are given
	jne	.fail					; other types arent supported for this card yet
 
; check if the device is already listed
 
	mov	esi, device_list
	mov	ecx, [devices]
	test	ecx, ecx
	jz	.firstdevice
 
;        mov     eax, [IOCTL.input]                     ; get the pci bus and device numbers
	mov	ax , [eax+1]				;
  .nextdevice:
	mov	ebx, [esi]
	cmp	ax , word [device.pci_bus]		; compare with pci and device num in device list (notice the usage of word instead of byte)
	je	.find_devicenum 			; Device is already loaded, let's find it's device number
	add	esi, 4
	loop	.nextdevice
 
 
; This device doesnt have its own eth_device structure yet, lets create one
  .firstdevice:
	cmp	[devices], MAX_DEVICES			; First check if the driver can handle one more card
	jge	.fail
 
	allocate_and_clear ebx, device_size, .fail	; Allocate memory to put the device structure in
 
; Fill in the direct call addresses into the struct
 
	mov	[device.reset], reset
	mov	[device.transmit], transmit
	mov	[device.get_MAC], read_mac
	mov	[device.set_MAC], write_mac
	mov	[device.unload], unload
	mov	[device.name], my_service
 
; save the pci bus and device numbers
 
	mov	eax, [IOCTL.input]
	mov	cl , [eax+1]
	mov	[device.pci_bus], cl
	mov	cl , [eax+2]
	mov	[device.pci_dev], cl
 
; Now, it's time to find the base io addres of the PCI device
 
	find_io [device.pci_bus], [device.pci_dev], [device.io_addr]
	mov	eax, [device.io_addr]
	mov	[tpc.mmio_addr], eax
 
; We've found the io address, find IRQ now
 
	find_irq [device.pci_bus], [device.pci_dev], [device.irq_line]
 
	DEBUGF	2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
 
; Ok, the eth_device structure is ready, let's probe the device
; Because initialization fires IRQ, IRQ handler must be aware of this device
	mov	eax, [devices]						; Add the device structure to our device list
	mov	[device_list+4*eax], ebx				; (IRQ handler uses this list to find device)
	inc	[devices]						;
 
	call	probe							; this function will output in eax
	test	eax, eax
	jnz	.err2							; If an error occured, exit
 
 
	mov	[device.type], NET_TYPE_ETH
	call	NetRegDev
 
	cmp	eax, -1
	je	.destroy
 
	ret
 
; If the device was already loaded, find the device number and return it in eax
 
  .find_devicenum:
	DEBUGF	2,"Trying to find device number of already registered device\n"
	mov	ebx, eax
	call	NetPtrToNum						; This kernel procedure converts a pointer to device struct in ebx
									; into a device number in edi
	mov	eax, edi						; Application wants it in eax instead
	DEBUGF	2,"Kernel says: %u\n", eax
	ret
 
; If an error occured, remove all allocated data and exit (returning -1 in eax)
 
  .destroy:
	; todo: reset device into virgin state
 
  .err2:
	dec	[devices]
  .err:
	DEBUGF	2,"removing device structure\n"
	stdcall KernelFree, ebx
 
 
  .fail:
	or	eax, -1
	ret
 
;------------------------------------------------------
endp
 
 
align 4
unload:
 
	ret
 
 
align 4
init_board:
 
	DEBUGF	1,"init_board\n"
 
	make_bus_master [device.pci_bus], [device.pci_dev]
 
	; Soft reset the chip
	set_io	0
	set_io	REG_ChipCmd
	mov	al, CMD_Reset
	out	dx, al
 
	; Check that the chip has finished the reset
	mov	ecx, 1000
	set_io	REG_ChipCmd
    @@: in	al, dx
	test	al, CMD_Reset
	jz	@f
	udelay	10
	loop	@b
    @@:
	; identify config method
	set_io	REG_TxConfig
	in	eax, dx
	and	eax, 0x7c800000
	DEBUGF	1,"init_board: TxConfig & 0x7c800000 = 0x%x\n", eax
	mov	esi, mac_info-8
    @@: add	esi, 8
	mov	ecx, eax
	and	ecx, [esi]
	cmp	ecx, [esi]
	jne	@b
	mov	eax, [esi+4]
	mov	[tpc.mcfg], eax
 
	mov	[tpc.pcfg], PCFG_METHOD_3
	READ_GMII_REG 3
	and	al, 0x0f
	or	al, al
	jnz	@f
	mov	[tpc.pcfg], PCFG_METHOD_1
	jmp	.pconf
    @@: dec	al
	jnz	.pconf
	mov	[tpc.pcfg], PCFG_METHOD_2
  .pconf:
 
	; identify chip attached to board
	mov	ecx, 10
	mov	eax, [tpc.mcfg]
    @@: dec	ecx
	js	@f
	cmp	eax, [rtl_chip_info+ecx*8]
	jne	@b
	mov	[tpc.chipset], ecx
	jmp	.match
    @@:
	; if unknown chip, assume array element #0, original RTL-8169 in this case
	DEBUGF	1,"init_board: PCI device: unknown chip version, assuming RTL-8169\n"
	set_io	REG_TxConfig
	in	eax, dx
	DEBUGF	1,"init_board: PCI device: TxConfig = 0x%x\n", eax
 
	mov	[tpc.chipset],	0
 
	xor	eax, eax
	inc	eax
	ret
 
  .match:
	xor	eax,eax
	ret
 
 
 
;***************************************************************************
;   Function
;      probe
;   Description
;      Searches for an ethernet card, enables it and clears the rx buffer
;      If a card was found, it enables the ethernet -> TCPIP link
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
align 4
probe:
 
	DEBUGF	1,"probe\n"
 
	call	init_board
 
	call	read_mac
 
	call	PHY_config
 
;       DEBUGF  1,"K :   Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
	set_io	0
	set_io	0x82
	mov	al, 0x01
	out	dx, al
	cmp	[tpc.mcfg], MCFG_METHOD_03
	jae	@f
;       DEBUGF  1,"K :   Set PCI Latency=0x40\n"
;       stdcall pci_write_config_byte,PCI_LATENCY_TIMER,0x40
   @@:
	cmp	[tpc.mcfg], MCFG_METHOD_02
	jne	@f
;       DEBUGF  1,"K :   Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
	set_io	0x82
	mov	al, 0x01
	out	dx, al
;       DEBUGF  1,"K :   Set PHY Reg 0x0bh = 0x00h\n"
	WRITE_GMII_REG 0x0b, 0x0000	 ; w 0x0b 15 0 0
    @@:
	; if TBI is not enabled
	set_io	0
	set_io	REG_PHYstatus
	in	al, dx
	test	al, PHYS_TBI_Enable
	jz	.tbi_dis
	READ_GMII_REG PHY_AUTO_NEGO_REG
 
	; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
	and	eax, 0x0C1F
	or	eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
	WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
 
	; enable 1000 Full Mode
	WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
 
	; Enable auto-negotiation and restart auto-nigotiation
	WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
 
	udelay	100
	mov	ecx, 10000
	; wait for auto-negotiation process
    @@: dec	ecx
	jz	@f
	set_io	0
	READ_GMII_REG PHY_STAT_REG
	udelay	100
	test	eax, PHY_Auto_Neco_Comp
	jz	@b
	set_io	REG_PHYstatus
	in	al, dx
	jmp	@f
  .tbi_dis:
	udelay	100
    @@:
 
 
;***************************************************************************
;   Function
;      rt8169_reset
;   Description
;      Place the chip (ie, the ethernet card) into a virgin state
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
align 4
reset:
 
	DEBUGF	1,"reset\n"
 
	lea	eax, [tx_ring]
	mov	[tpc.TxDescArrays], eax
	mov	[tpc.TxDescArray], eax
 
	lea	eax, [rx_ring]
	mov	[tpc.RxDescArrays], eax
	mov	[tpc.RxDescArray], eax
 
	call	init_ring
	call	hw_start
 
; clear packet/byte counters
 
	xor	eax, eax
	lea	edi, [device.bytes_tx]
	mov	ecx, 6
	rep	stosd
 
	mov	[device.mtu], 1500
 
	xor	eax, eax
	ret
 
 
 
 
 
align 4
PHY_config:
 
	DEBUGF	1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n",[tpc.mcfg],[tpc.pcfg]
 
	cmp	[tpc.mcfg], MCFG_METHOD_04
	jne	.not_4
	set_io	0
;       WRITE_GMII_REG 0x1F, 0x0001
;       WRITE_GMII_REG 0x1b, 0x841e
;       WRITE_GMII_REG 0x0e, 0x7bfb
;       WRITE_GMII_REG 0x09, 0x273a
	WRITE_GMII_REG 0x1F, 0x0002
	WRITE_GMII_REG 0x01, 0x90D0
	WRITE_GMII_REG 0x1F, 0x0000
	jmp	.exit
  .not_4:
	cmp	[tpc.mcfg], MCFG_METHOD_02
	je	@f
	cmp	[tpc.mcfg], MCFG_METHOD_03
	jne	.not_2_or_3
    @@:
	set_io	0
	WRITE_GMII_REG 0x1F, 0x0001
	WRITE_GMII_REG 0x15, 0x1000
	WRITE_GMII_REG 0x18, 0x65C7
	WRITE_GMII_REG 0x04, 0x0000
	WRITE_GMII_REG 0x03, 0x00A1
	WRITE_GMII_REG 0x02, 0x0008
	WRITE_GMII_REG 0x01, 0x1020
	WRITE_GMII_REG 0x00, 0x1000
	WRITE_GMII_REG 0x04, 0x0800
	WRITE_GMII_REG 0x04, 0x0000
	WRITE_GMII_REG 0x04, 0x7000
	WRITE_GMII_REG 0x03, 0xFF41
	WRITE_GMII_REG 0x02, 0xDE60
	WRITE_GMII_REG 0x01, 0x0140
	WRITE_GMII_REG 0x00, 0x0077
	WRITE_GMII_REG 0x04, 0x7800
	WRITE_GMII_REG 0x04, 0x7000
	WRITE_GMII_REG 0x04, 0xA000
	WRITE_GMII_REG 0x03, 0xDF01
	WRITE_GMII_REG 0x02, 0xDF20
	WRITE_GMII_REG 0x01, 0xFF95
	WRITE_GMII_REG 0x00, 0xFA00
	WRITE_GMII_REG 0x04, 0xA800
	WRITE_GMII_REG 0x04, 0xA000
	WRITE_GMII_REG 0x04, 0xB000
	WRITE_GMII_REG 0x03, 0xFF41
	WRITE_GMII_REG 0x02, 0xDE20
	WRITE_GMII_REG 0x01, 0x0140
	WRITE_GMII_REG 0x00, 0x00BB
	WRITE_GMII_REG 0x04, 0xB800
	WRITE_GMII_REG 0x04, 0xB000
	WRITE_GMII_REG 0x04, 0xF000
	WRITE_GMII_REG 0x03, 0xDF01
	WRITE_GMII_REG 0x02, 0xDF20
	WRITE_GMII_REG 0x01, 0xFF95
	WRITE_GMII_REG 0x00, 0xBF00
	WRITE_GMII_REG 0x04, 0xF800
	WRITE_GMII_REG 0x04, 0xF000
	WRITE_GMII_REG 0x04, 0x0000
	WRITE_GMII_REG 0x1F, 0x0000
	WRITE_GMII_REG 0x0B, 0x0000
	jmp	.exit
  .not_2_or_3:
	DEBUGF	1,"tpc.mcfg=%d, discard hw PHY config\n", [tpc.mcfg]
  .exit:
	ret
 
 
 
align 4
set_rx_mode:
 
	DEBUGF	1,"set_rx_mode\n"
 
	; IFF_ALLMULTI
	; Too many to filter perfectly -- accept all multicasts
	set_io	0
	set_io	REG_RxConfig
	in	eax, dx
	mov	ecx, [tpc.chipset]
	and	eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
	or	eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
	out	dx, eax
 
	; Multicast hash filter
	set_io	REG_MAR0 + 0
	or	eax, -1
	out	dx, eax
	set_io	REG_MAR0 + 4
	out	dx, eax
 
	ret
 
 
align 4
init_ring:
 
	DEBUGF	1,"init_ring\n"
 
	xor	eax, eax
	mov	[tpc.cur_rx], eax
	mov	[tpc.cur_tx], eax
 
	lea	edi, [tx_ring]
	mov	ecx, (NUM_TX_DESC * tx_desc.size) / 4
	rep	stosd
 
	lea	edi, [rx_ring]
	mov	ecx, (NUM_RX_DESC * rx_desc.size) / 4
	rep	stosd
 
	mov	edi, [tpc.RxDescArray]
	mov	ecx, NUM_RX_DESC
  .loop:
	push	ecx
	stdcall KernelAlloc, RX_BUF_SIZE
	mov	[edi + rx_desc.buf_soft_addr], eax
	call	GetPgAddr
	mov	dword [edi + rx_desc.buf_addr], eax
	mov	[edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
	add	edi, rx_desc.size
	pop	ecx
	loop	.loop
	or	[edi - rx_desc.size + rx_desc.status], DSB_EORbit
 
	ret
 
 
align 4
hw_start:
 
	DEBUGF	1,"hw_start\n"
 
; attach int handler
	movzx	eax, [device.irq_line]
	DEBUGF	1,"Attaching int handler to irq %x\n", eax:1
	stdcall AttachIntHandler, eax, int_handler, dword 0
 
	; Soft reset the chip
	set_io	0
	set_io	REG_ChipCmd
	mov	al, CMD_Reset
	out	dx, al
 
	; Check that the chip has finished the reset
	mov	ecx, 1000
	set_io	REG_ChipCmd
    @@: in	al, dx
	test	al, CMD_Reset
	jz	@f
	udelay	10
	loop	@b
    @@:
 
	set_io	REG_Cfg9346
	mov	al, CFG_9346_Unlock
	out	dx, al
 
	set_io	REG_ChipCmd
	mov	al, CMD_TxEnb or CMD_RxEnb
	out	dx, al
 
	set_io	REG_ETThReg
	mov	al, ETTh
	out	dx, al
 
	; For gigabit rtl8169
	set_io	REG_RxMaxSize
	mov	ax, RxPacketMaxSize
	out	dx, ax
 
	; Set Rx Config register
	set_io	REG_RxConfig
	in	ax, dx
	mov	ecx, [tpc.chipset]
	and	eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
	or	eax, rx_config
	out	dx, eax
 
	; Set DMA burst size and Interframe Gap Time
	set_io	REG_TxConfig
	mov	eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
	out	dx, eax
 
	set_io	REG_CPlusCmd
	in	ax, dx
	out	dx, ax
 
	in	ax, dx
	or	ax, 1 shl 3
	cmp	[tpc.mcfg], MCFG_METHOD_02
	jne	@f
	cmp	[tpc.mcfg], MCFG_METHOD_03
	jne	@f
	or	ax,1 shl 14
	DEBUGF	1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
	jmp	.set
    @@:
	DEBUGF	1," Set MAC Reg C+CR Offset 0xE0: bit-3\n"
  .set:
	set_io	REG_CPlusCmd
	out	dx, ax
 
	set_io	0xE2
;        mov     ax, 0x1517
;        out     dx, ax
;        mov     ax, 0x152a
;        out     dx, ax
;        mov     ax, 0x282a
;        out     dx, ax
	xor	ax, ax
	out	dx, ax
 
	xor	eax, eax
	mov	[tpc.cur_rx], eax
	lea	eax, [tx_ring]
	GetRealAddr
	set_io	REG_TxDescStartAddr
	out	dx, eax
 
	lea	eax, [rx_ring]
	GetRealAddr
	set_io	REG_RxDescStartAddr
	out	dx, eax
 
	set_io	REG_Cfg9346
	mov	al, CFG_9346_Lock
	out	dx, al
 
	udelay	10
 
	xor	eax, eax
	set_io	REG_RxMissed
	out	dx, eax
 
	call	set_rx_mode
 
	set_io	0
	; no early-rx interrupts
	set_io	REG_MultiIntr
	in	ax, dx
	and	ax, 0xF000
	out	dx, ax
 
	; set interrupt mask
	set_io	REG_IntrMask
	mov	ax, intr_mask
	out	dx, ax
 
	xor	eax, eax
	ret
 
 
align 4
read_mac:
 
	set_io	0
	set_io	REG_MAC0
	xor	ecx, ecx
	lea	edi, [device.mac]
	mov	ecx, MAC_ADDR_LEN
 
	; Get MAC address. FIXME: read EEPROM
    @@: in	al, dx
	stosb
	inc	edx
	loop	@r
 
	DEBUGF	1,"MAC = %x-%x-%x-%x-%x-%x\n",[device.mac+0]:2,[device.mac+1]:2,[device.mac+2]:2,[device.mac+3]:2,[device.mac+4]:2,[device.mac+5]:2
 
	ret
 
align 4
write_mac:
 
	ret	6
 
 
 
 
 
;***************************************************************************
;   Function
;      transmit
;   Description
;      Transmits a packet of data via the ethernet card
;
;   Destroyed registers
;      eax, edx, esi, edi
;
;***************************************************************************
align 4
transmit:
 
	DEBUGF	1,"Transmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8]
	mov	eax, [esp+4]
	DEBUGF	1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
	[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
	[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
	[eax+13]:2,[eax+12]:2
 
	cmp	dword [esp+8], MAX_ETH_FRAME_SIZE
	ja	.fail
 
;----------------------------------
; Find currentTX descriptor address
 
	mov	eax, tx_desc.size
	mul	[tpc.cur_tx]
	lea	esi, [eax + tx_ring]
 
;---------------------------
; Program the packet pointer
 
	mov	eax, [esp + 4]
	mov	[esi + tx_desc.buf_soft_addr], eax
	GetRealAddr
	mov	dword [esi + tx_desc.buf_addr], eax
 
;------------------------
; Program the packet size
 
	mov	eax, [esp + 8]
    @@: or	eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
	cmp	[tpc.cur_tx], NUM_TX_DESC - 1
	jne	@f
	or	eax, DSB_EORbit
    @@: mov	[esi + tx_desc.status], eax
 
;-----------------------------------------
; Set the polling bit (start transmission)
 
	set_io	0
	set_io	REG_TxPoll
	mov	al, 0x40     ; set polling bit
	out	dx, al
 
;-----------------------
; Update TX descriptor
 
	inc	[tpc.cur_tx]
	and	[tpc.cur_tx], NUM_TX_DESC - 1
 
;-------------
; Update stats
 
	inc	[device.packets_tx]
	mov	eax, [esp+8]
	add	dword [device.bytes_tx], eax
	adc	dword [device.bytes_tx + 4], 0
 
	ret	8
 
  .fail:
	DEBUGF	1,"transmit failed\n"
	or	eax, -1
	stdcall KernelFree, [esp+4]
	ret	8
 
 
;;;DSB_OWNbit
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Interrupt handler ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
int_handler:
 
	DEBUGF	1,"IRQ %x ",eax:2
 
; find pointer of device wich made IRQ occur
 
	mov	ecx, [devices]
	test	ecx, ecx
	jz	.fail
	mov	esi, device_list
  .nextdevice:
	mov	ebx, dword [esi]
 
	set_io	0
	set_io	REG_IntrStatus
	in	ax, dx
 
	test	ax, ax
	jnz	.got_it
 
  .continue:
	add	esi, 4
	dec	ecx
	jnz	.nextdevice
 
	ret						; If no device was found, abort (The irq was probably for a device, not registered to this driver)
 
  .got_it:
	DEBUGF	1,"IntrStatus = 0x%x\n",ax
 
	cmp	ax, 0xFFFF	; if so, hardware is no longer present
	je	.fail
 
;--------
; Receive
 
	test	ax, ISB_RxOK
	jz	.no_rx
 
	push	ax
 
  .check_more:
	mov	eax, rx_desc.size
	mul	[tpc.cur_rx]
	lea	esi, [eax + rx_ring]
 
	DEBUGF	1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
 
	mov	eax, [esi + rx_desc.status]
	test	eax, DSB_OWNbit ;;;
	jnz	.rx_return
 
	DEBUGF	1,"tpc.cur_rx = %u\n", [tpc.cur_rx]
 
	test	eax, SD_RxRES
	jnz	.rx_return	;;;;; RX error!
 
	push	.check_more
	and	eax, 0x00001FFF
	add	eax, -4 			; we dont need CRC
	push	eax
	DEBUGF	1,"data length = %u\n", ax
 
;-------------
; Update stats
 
	add	dword [device.bytes_rx], eax
	adc	dword [device.bytes_rx + 4], 0
	inc	dword [device.packets_rx]
 
	push	[esi + rx_desc.buf_soft_addr]
 
;----------------------
; Allocate a new buffer
 
	stdcall KernelAlloc, RX_BUF_SIZE
	mov	[esi + rx_desc.buf_soft_addr], eax
	GetRealAddr
	mov	dword [esi + rx_desc.buf_addr], eax
 
;---------------
; re set OWN bit
 
	mov	eax, DSB_OWNbit or RX_BUF_SIZE
	cmp	[tpc.cur_rx], NUM_RX_DESC - 1
	jne	@f
	or	eax, DSB_EORbit
    @@: mov	[esi + rx_desc.status], eax
 
;--------------
; Update rx ptr
 
	inc	[tpc.cur_rx]
	and	[tpc.cur_rx], NUM_RX_DESC - 1
 
	jmp	EthReceiver
  .rx_return:
 
	pop	ax
  .no_rx:
 
;---------
; Transmit
 
	test	ax, ISB_TxOK
	jz	.no_tx
	push	ax
 
	DEBUGF	1,"TX ok!\n"
 
	mov	ecx, NUM_TX_DESC
	lea	esi, [tx_ring]
  .txloop:
	cmp	[esi+tx_desc.buf_soft_addr], 0
	jz	.maybenext
 
	test	[esi+tx_desc.status], DSB_OWNbit
	jnz	.maybenext
 
	push	ecx
	stdcall KernelFree, [esi+tx_desc.buf_soft_addr]
	pop	ecx
	and	[esi+tx_desc.buf_soft_addr], 0
 
  .maybenext:
	add	esi, tx_desc.size
	dec	ecx
	jnz	.txloop
 
	pop	ax
  .no_tx:
 
;-------
; Finish
 
	set_io	0
	set_io	REG_IntrStatus
	out	dx, ax			; ACK all interrupts
 
  .fail:
	ret
 
 
 
 
 
 
 
 
 
; End of code
align 4 					; Place all initialised data here
 
devices       dd 0
version       dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF)
my_service    db 'RTL8169',0			; max 16 chars include zero
 
include_debug_strings				; All data wich FDO uses will be included here
 
rtl_chip_info dd \
  MCFG_METHOD_01, 0xff7e1880, \ ; RTL8169
  MCFG_METHOD_02, 0xff7e1880, \ ; RTL8169s/8110s
  MCFG_METHOD_03, 0xff7e1880, \ ; RTL8169s/8110s
  MCFG_METHOD_04, 0xff7e1880, \ ; RTL8169sb/8110sb
  MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc
  MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b   // PCI-E
  MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b   // PCI-E
  MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e         // PCI-E 8139
  MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e         // PCI-E 8139
  MCFG_METHOD_15, 0xff7e1880	; RTL8100e         // PCI-E 8139
 
mac_info dd \
  0x38800000, MCFG_METHOD_15, \
  0x38000000, MCFG_METHOD_12, \
  0x34000000, MCFG_METHOD_13, \
  0x30800000, MCFG_METHOD_14, \
  0x30000000, MCFG_METHOD_11, \
  0x18000000, MCFG_METHOD_05, \
  0x10000000, MCFG_METHOD_04, \
  0x04000000, MCFG_METHOD_03, \
  0x00800000, MCFG_METHOD_02, \
  0x00000000, MCFG_METHOD_01	; catch-all
 
name_01 	db "RTL8169", 0
name_02_03	db "RTL8169s/8110s", 0
name_04 	db "RTL8169sb/8110sb", 0
name_05 	db "RTL8169sc/8110sc", 0
name_11_12	db "RTL8168b/8111b", 0	; PCI-E
name_13 	db "RTL8101e", 0	; PCI-E 8139
name_14_15	db "RTL8100e", 0	; PCI-E 8139
 
 
section '.data' data readable writable align 16 ; place all uninitialized data place here
 
device_list rd MAX_DEVICES		       ; This list contains all pointers to device structures the driver is handling

Rev 1558	Rev 1559
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2010. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2010. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; RTL8169 driver for KolibriOS ;;	6	;; RTL8169 driver for KolibriOS ;;
7	;; ;;	7	;; ;;
8	;; Copyright 2007 mike.dld, ;;	8	;; Copyright 2007 mike.dld, ;;
9	;; mike.dld@gmail.com ;;	9	;; mike.dld@gmail.com ;;
10	;; ;;	10	;; ;;
11	;; Version 0.1 11 February 2007 ;;	11	;; Version 0.1 11 February 2007 ;;
12	;; Version 0.2 3 August 2010 - port to net branch by hidnplayr ;;	12	;; Version 0.2 3 August 2010 - port to net branch by hidnplayr ;;
13	;; ;;	13	;; ;;
14	;; References: ;;	14	;; References: ;;
15	;; r8169.c - linux driver (etherboot project) ;;	15	;; r8169.c - linux driver (etherboot project) ;;
16	;; ;;	16	;; ;;
17	;; GNU GENERAL PUBLIC LICENSE ;;	17	;; GNU GENERAL PUBLIC LICENSE ;;
18	;; Version 2, June 1991 ;;	18	;; Version 2, June 1991 ;;
19	;; ;;	19	;; ;;
20	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	20	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
21		21
22	format MS COFF	22	format MS COFF
23		23
24	API_VERSION equ 0x01000100	24	API_VERSION equ 0x01000100
25	DRIVER_VERSION equ 5	25	DRIVER_VERSION equ 5
26		26
27	MAX_DEVICES equ 16	27	MAX_DEVICES equ 16
28		28
29	DEBUG equ 1	29	DEBUG equ 1
30	__DEBUG__ equ 1	30	__DEBUG__ equ 1
31	__DEBUG_LEVEL__ equ 1	31	__DEBUG_LEVEL__ equ 1
32		32
33	NUM_TX_DESC equ 4	33	NUM_TX_DESC equ 4
34	NUM_RX_DESC equ 4	34	NUM_RX_DESC equ 4
35		35
36	include 'proc32.inc'	36	include 'proc32.inc'
37	include 'imports.inc'	37	include 'imports.inc'
38	include 'fdo.inc'	38	include 'fdo.inc'
39	include 'netdrv.inc'	39	include 'netdrv.inc'
40		40
41	public START	41	public START
42	public service_proc	42	public service_proc
43	public version	43	public version
44		44
45		45
46	REG_MAC0 equ 0x0 ; Ethernet hardware address	46	REG_MAC0 equ 0x0 ; Ethernet hardware address
47	REG_MAR0 equ 0x8 ; Multicast filter	47	REG_MAR0 equ 0x8 ; Multicast filter
48	REG_TxDescStartAddr equ 0x20	48	REG_TxDescStartAddr equ 0x20
49	REG_TxHDescStartAddr equ 0x28	49	REG_TxHDescStartAddr equ 0x28
50	REG_FLASH equ 0x30	50	REG_FLASH equ 0x30
51	REG_ERSR equ 0x36	51	REG_ERSR equ 0x36
52	REG_ChipCmd equ 0x37	52	REG_ChipCmd equ 0x37
53	REG_TxPoll equ 0x38	53	REG_TxPoll equ 0x38
54	REG_IntrMask equ 0x3C	54	REG_IntrMask equ 0x3C
55	REG_IntrStatus equ 0x3E	55	REG_IntrStatus equ 0x3E
56	REG_TxConfig equ 0x40	56	REG_TxConfig equ 0x40
57	REG_RxConfig equ 0x44	57	REG_RxConfig equ 0x44
58	REG_RxMissed equ 0x4C	58	REG_RxMissed equ 0x4C
59	REG_Cfg9346 equ 0x50	59	REG_Cfg9346 equ 0x50
60	REG_Config0 equ 0x51	60	REG_Config0 equ 0x51
61	REG_Config1 equ 0x52	61	REG_Config1 equ 0x52
62	REG_Config2 equ 0x53	62	REG_Config2 equ 0x53
63	REG_Config3 equ 0x54	63	REG_Config3 equ 0x54
64	REG_Config4 equ 0x55	64	REG_Config4 equ 0x55
65	REG_Config5 equ 0x56	65	REG_Config5 equ 0x56
66	REG_MultiIntr equ 0x5C	66	REG_MultiIntr equ 0x5C
67	REG_PHYAR equ 0x60	67	REG_PHYAR equ 0x60
68	REG_TBICSR equ 0x64	68	REG_TBICSR equ 0x64
69	REG_TBI_ANAR equ 0x68	69	REG_TBI_ANAR equ 0x68
70	REG_TBI_LPAR equ 0x6A	70	REG_TBI_LPAR equ 0x6A
71	REG_PHYstatus equ 0x6C	71	REG_PHYstatus equ 0x6C
72	REG_RxMaxSize equ 0xDA	72	REG_RxMaxSize equ 0xDA
73	REG_CPlusCmd equ 0xE0	73	REG_CPlusCmd equ 0xE0
74	REG_RxDescStartAddr equ 0xE4	74	REG_RxDescStartAddr equ 0xE4
75	REG_ETThReg equ 0xEC	75	REG_ETThReg equ 0xEC
76	REG_FuncEvent equ 0xF0	76	REG_FuncEvent equ 0xF0
77	REG_FuncEventMask equ 0xF4	77	REG_FuncEventMask equ 0xF4
78	REG_FuncPresetState equ 0xF8	78	REG_FuncPresetState equ 0xF8
79	REG_FuncForceEvent equ 0xFC	79	REG_FuncForceEvent equ 0xFC
80		80
81	; InterruptStatusBits	81	; InterruptStatusBits
82	ISB_SYSErr equ 0x8000	82	ISB_SYSErr equ 0x8000
83	ISB_PCSTimeout equ 0x4000	83	ISB_PCSTimeout equ 0x4000
84	ISB_SWInt equ 0x0100	84	ISB_SWInt equ 0x0100
85	ISB_TxDescUnavail equ 0x80	85	ISB_TxDescUnavail equ 0x80
86	ISB_RxFIFOOver equ 0x40	86	ISB_RxFIFOOver equ 0x40
87	ISB_LinkChg equ 0x20	87	ISB_LinkChg equ 0x20
88	ISB_RxOverflow equ 0x10	88	ISB_RxOverflow equ 0x10
89	ISB_TxErr equ 0x08	89	ISB_TxErr equ 0x08
90	ISB_TxOK equ 0x04	90	ISB_TxOK equ 0x04
91	ISB_RxErr equ 0x02	91	ISB_RxErr equ 0x02
92	ISB_RxOK equ 0x01	92	ISB_RxOK equ 0x01
93		93
94	; RxStatusDesc	94	; RxStatusDesc
95	SD_RxRES equ 0x00200000	95	SD_RxRES equ 0x00200000
96	SD_RxCRC equ 0x00080000	96	SD_RxCRC equ 0x00080000
97	SD_RxRUNT equ 0x00100000	97	SD_RxRUNT equ 0x00100000
98	SD_RxRWT equ 0x00400000	98	SD_RxRWT equ 0x00400000
99		99
100	; ChipCmdBits	100	; ChipCmdBits
101	CMD_Reset equ 0x10	101	CMD_Reset equ 0x10
102	CMD_RxEnb equ 0x08	102	CMD_RxEnb equ 0x08
103	CMD_TxEnb equ 0x04	103	CMD_TxEnb equ 0x04
104	CMD_RxBufEmpty equ 0x01	104	CMD_RxBufEmpty equ 0x01
105		105
106	; Cfg9346Bits	106	; Cfg9346Bits
107	CFG_9346_Lock equ 0x00	107	CFG_9346_Lock equ 0x00
108	CFG_9346_Unlock equ 0xC0	108	CFG_9346_Unlock equ 0xC0
109		109
110	; rx_mode_bits	110	; rx_mode_bits
111	RXM_AcceptErr equ 0x20	111	RXM_AcceptErr equ 0x20
112	RXM_AcceptRunt equ 0x10	112	RXM_AcceptRunt equ 0x10
113	RXM_AcceptBroadcast equ 0x08	113	RXM_AcceptBroadcast equ 0x08
114	RXM_AcceptMulticast equ 0x04	114	RXM_AcceptMulticast equ 0x04
115	RXM_AcceptMyPhys equ 0x02	115	RXM_AcceptMyPhys equ 0x02
116	RXM_AcceptAllPhys equ 0x01	116	RXM_AcceptAllPhys equ 0x01
117		117
118	; RxConfigBits	118	; RxConfigBits
119	RXC_FIFOShift equ 13	119	RXC_FIFOShift equ 13
120	RXC_DMAShift equ 8	120	RXC_DMAShift equ 8
121		121
122	; TxConfigBits	122	; TxConfigBits
123	TXC_InterFrameGapShift equ 24	123	TXC_InterFrameGapShift equ 24
124	TXC_DMAShift equ 8 ; DMA burst value (0-7) is shift this many bits	124	TXC_DMAShift equ 8 ; DMA burst value (0-7) is shift this many bits
125		125
126	; PHYstatus	126	; PHYstatus
127	PHYS_TBI_Enable equ 0x80	127	PHYS_TBI_Enable equ 0x80
128	PHYS_TxFlowCtrl equ 0x40	128	PHYS_TxFlowCtrl equ 0x40
129	PHYS_RxFlowCtrl equ 0x20	129	PHYS_RxFlowCtrl equ 0x20
130	PHYS_1000bpsF equ 0x10	130	PHYS_1000bpsF equ 0x10
131	PHYS_100bps equ 0x08	131	PHYS_100bps equ 0x08
132	PHYS_10bps equ 0x04	132	PHYS_10bps equ 0x04
133	PHYS_LinkStatus equ 0x02	133	PHYS_LinkStatus equ 0x02
134	PHYS_FullDup equ 0x01	134	PHYS_FullDup equ 0x01
135		135
136	; GIGABIT_PHY_registers	136	; GIGABIT_PHY_registers
137	PHY_CTRL_REG equ 0	137	PHY_CTRL_REG equ 0
138	PHY_STAT_REG equ 1	138	PHY_STAT_REG equ 1
139	PHY_AUTO_NEGO_REG equ 4	139	PHY_AUTO_NEGO_REG equ 4
140	PHY_1000_CTRL_REG equ 9	140	PHY_1000_CTRL_REG equ 9
141		141
142	; GIGABIT_PHY_REG_BIT	142	; GIGABIT_PHY_REG_BIT
143	PHY_Restart_Auto_Nego equ 0x0200	143	PHY_Restart_Auto_Nego equ 0x0200
144	PHY_Enable_Auto_Nego equ 0x1000	144	PHY_Enable_Auto_Nego equ 0x1000
145		145
146	; PHY_STAT_REG = 1;	146	; PHY_STAT_REG = 1;
147	PHY_Auto_Neco_Comp equ 0x0020	147	PHY_Auto_Neco_Comp equ 0x0020
148		148
149	; PHY_AUTO_NEGO_REG = 4;	149	; PHY_AUTO_NEGO_REG = 4;
150	PHY_Cap_10_Half equ 0x0020	150	PHY_Cap_10_Half equ 0x0020
151	PHY_Cap_10_Full equ 0x0040	151	PHY_Cap_10_Full equ 0x0040
152	PHY_Cap_100_Half equ 0x0080	152	PHY_Cap_100_Half equ 0x0080
153	PHY_Cap_100_Full equ 0x0100	153	PHY_Cap_100_Full equ 0x0100
154		154
155	; PHY_1000_CTRL_REG = 9;	155	; PHY_1000_CTRL_REG = 9;
156	PHY_Cap_1000_Full equ 0x0200	156	PHY_Cap_1000_Full equ 0x0200
157	PHY_Cap_1000_Half equ 0x0100	157	PHY_Cap_1000_Half equ 0x0100
158		158
159	PHY_Cap_PAUSE equ 0x0400	159	PHY_Cap_PAUSE equ 0x0400
160	PHY_Cap_ASYM_PAUSE equ 0x0800	160	PHY_Cap_ASYM_PAUSE equ 0x0800
161		161
162	PHY_Cap_Null equ 0x0	162	PHY_Cap_Null equ 0x0
163		163
164	; _MediaType	164	; _MediaType
165	MT_10_Half equ 0x01	165	MT_10_Half equ 0x01
166	MT_10_Full equ 0x02	166	MT_10_Full equ 0x02
167	MT_100_Half equ 0x04	167	MT_100_Half equ 0x04
168	MT_100_Full equ 0x08	168	MT_100_Full equ 0x08
169	MT_1000_Full equ 0x10	169	MT_1000_Full equ 0x10
170		170
171	; _TBICSRBit	171	; _TBICSRBit
172	TBI_LinkOK equ 0x02000000	172	TBI_LinkOK equ 0x02000000
173		173
174	; _DescStatusBit	174	; _DescStatusBit
175	DSB_OWNbit equ 0x80000000	175	DSB_OWNbit equ 0x80000000
176	DSB_EORbit equ 0x40000000	176	DSB_EORbit equ 0x40000000
177	DSB_FSbit equ 0x20000000	177	DSB_FSbit equ 0x20000000
178	DSB_LSbit equ 0x10000000	178	DSB_LSbit equ 0x10000000
179		179
180	RX_BUF_SIZE equ 1536 ; Rx Buffer size	180	RX_BUF_SIZE equ 1536 ; Rx Buffer size
181		181
182		182
183	ETH_ALEN equ 6	183	ETH_ALEN equ 6
184	ETH_HLEN equ (2 * ETH_ALEN + 2)	184	ETH_HLEN equ (2 * ETH_ALEN + 2)
185	ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for	185	ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
186	; mininmum 64bytes frame length	186	; mininmum 64bytes frame length
187		187
188	; MAC address length	188	; MAC address length
189	MAC_ADDR_LEN equ 6	189	MAC_ADDR_LEN equ 6
190		190
191	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)	191	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
192	MAX_ETH_FRAME_SIZE equ 1536	192	MAX_ETH_FRAME_SIZE equ 1536
193		193
194	TX_FIFO_THRESH equ 256 ; In bytes	194	TX_FIFO_THRESH equ 256 ; In bytes
195		195
196	RX_FIFO_THRESH equ 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer	196	RX_FIFO_THRESH equ 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
197	RX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024	197	RX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024
198	TX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024	198	TX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024
199	ETTh equ 0x3F ; 0x3F means NO threshold	199	ETTh equ 0x3F ; 0x3F means NO threshold
200		200
201	EarlyTxThld equ 0x3F ; 0x3F means NO early transmit	201	EarlyTxThld equ 0x3F ; 0x3F means NO early transmit
202	RxPacketMaxSize equ 0x0800 ; Maximum size supported is 16K-1	202	RxPacketMaxSize equ 0x0800 ; Maximum size supported is 16K-1
203	InterFrameGap equ 0x03 ; 3 means InterFrameGap = the shortest one	203	InterFrameGap equ 0x03 ; 3 means InterFrameGap = the shortest one
204		204
205	HZ equ 1000	205	HZ equ 1000
206		206
207	RTL_MIN_IO_SIZE equ 0x80	207	RTL_MIN_IO_SIZE equ 0x80
208	TX_TIMEOUT equ (6*HZ)	208	TX_TIMEOUT equ (6*HZ)
209		209
210	TIMER_EXPIRE_TIME equ 100	210	TIMER_EXPIRE_TIME equ 100
211		211
212	ETH_HDR_LEN equ 14	212	ETH_HDR_LEN equ 14
213	DEFAULT_MTU equ 1500	213	DEFAULT_MTU equ 1500
214	DEFAULT_RX_BUF_LEN equ 1536	214	DEFAULT_RX_BUF_LEN equ 1536
215		215
216		216
217	;#ifdef JUMBO_FRAME_SUPPORT	217	;#ifdef JUMBO_FRAME_SUPPORT
218	;#define MAX_JUMBO_FRAME_MTU ( 10000 )	218	;#define MAX_JUMBO_FRAME_MTU ( 10000 )
219	;#define MAX_RX_SKBDATA_SIZE ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )	219	;#define MAX_RX_SKBDATA_SIZE ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
220	;#else	220	;#else
221	MAX_RX_SKBDATA_SIZE equ 1600	221	MAX_RX_SKBDATA_SIZE equ 1600
222	;#endif //end #ifdef JUMBO_FRAME_SUPPORT	222	;#endif //end #ifdef JUMBO_FRAME_SUPPORT
223		223
224	MCFG_METHOD_01 equ 0x01	224	MCFG_METHOD_01 equ 0x01
225	MCFG_METHOD_02 equ 0x02	225	MCFG_METHOD_02 equ 0x02
226	MCFG_METHOD_03 equ 0x03	226	MCFG_METHOD_03 equ 0x03
227	MCFG_METHOD_04 equ 0x04	227	MCFG_METHOD_04 equ 0x04
228	MCFG_METHOD_05 equ 0x05	228	MCFG_METHOD_05 equ 0x05
229	MCFG_METHOD_11 equ 0x0b	229	MCFG_METHOD_11 equ 0x0b
230	MCFG_METHOD_12 equ 0x0c	230	MCFG_METHOD_12 equ 0x0c
231	MCFG_METHOD_13 equ 0x0d	231	MCFG_METHOD_13 equ 0x0d
232	MCFG_METHOD_14 equ 0x0e	232	MCFG_METHOD_14 equ 0x0e
233	MCFG_METHOD_15 equ 0x0f	233	MCFG_METHOD_15 equ 0x0f
234		234
235	PCFG_METHOD_1 equ 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000	235	PCFG_METHOD_1 equ 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
236	PCFG_METHOD_2 equ 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001	236	PCFG_METHOD_2 equ 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
237	PCFG_METHOD_3 equ 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002	237	PCFG_METHOD_3 equ 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
238		238
239	virtual at 0	239	virtual at 0
240	tx_desc:	240	tx_desc:
241	.status dd ?	241	.status dd ?
242	.vlan_tag dd ?	242	.vlan_tag dd ?
243	.buf_addr dq ?	243	.buf_addr dq ?
244	.size = $	244	.size = $
245	rb (NUM_TX_DESC-1)*tx_desc.size	245	rb (NUM_TX_DESC-1)*tx_desc.size
246	.buf_soft_addr dd ?	246	.buf_soft_addr dd ?
247	end virtual	247	end virtual
248		248
249	virtual at 0	249	virtual at 0
250	rx_desc:	250	rx_desc:
251	.status dd ?	251	.status dd ?
252	.vlan_tag dd ?	252	.vlan_tag dd ?
253	.buf_addr dq ?	253	.buf_addr dq ?
254	.size = $	254	.size = $
255	rb (NUM_RX_DESC-1)*rx_desc.size	255	rb (NUM_RX_DESC-1)*rx_desc.size
256	.buf_soft_addr dd ?	256	.buf_soft_addr dd ?
257	end virtual	257	end virtual
258		258
259	virtual at ebx	259	virtual at ebx
260		260
261	device:	261	device:
262		262
263	ETH_DEVICE	263	ETH_DEVICE
264		264
265	.io_addr dd ?	265	.io_addr dd ?
266	.pci_bus db ?	266	.pci_bus db ?
267	.pci_dev db ?	267	.pci_dev db ?
268	.irq_line db ?	268	.irq_line db ?
269		269
270	tpc:	270	tpc:
271	.mmio_addr dd ? ; memory map physical address	271	.mmio_addr dd ? ; memory map physical address
272	.chipset dd ?	272	.chipset dd ?
273	.pcfg dd ?	273	.pcfg dd ?
274	.mcfg dd ?	274	.mcfg dd ?
275	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt	275	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
276	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt	276	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
277	.TxDescArrays dd ? ; Index of Tx Descriptor buffer	277	.TxDescArrays dd ? ; Index of Tx Descriptor buffer
278	.RxDescArrays dd ? ; Index of Rx Descriptor buffer	278	.RxDescArrays dd ? ; Index of Rx Descriptor buffer
279	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer	279	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer
280	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer	280	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer
281		281
282	rb 256-(($ - device) and 255) ; align 256	282	rb 256-(($ - device) and 255) ; align 256
283	tx_ring rb NUM_TX_DESC * tx_desc.size * 2	283	tx_ring rb NUM_TX_DESC * tx_desc.size * 2
284		284
285	rb 256-(($ - device) and 255) ; align 256	285	rb 256-(($ - device) and 255) ; align 256
286	rx_ring rb NUM_RX_DESC * rx_desc.size * 2	286	rx_ring rb NUM_RX_DESC * rx_desc.size * 2
287		287
288	device_size = $ - device	288	device_size = $ - device
289		289
290	end virtual	290	end virtual
291		291
292	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK	292	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
293	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E	293	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
294		294
295		295
296	macro udelay msec {	296	macro udelay msec {
297		297
298	push esi	298	push esi
299	mov esi, msec	299	mov esi, msec
300	call Sleep	300	call Sleep
301	pop esi	301	pop esi
302		302
303	}	303	}
304		304
305	macro WRITE_GMII_REG RegAddr, value {	305	macro WRITE_GMII_REG RegAddr, value {
306		306
307	set_io REG_PHYAR	307	set_io REG_PHYAR
308	if value eq ax	308	if value eq ax
309	and eax, 0x0000ffff	309	and eax, 0x0000ffff
310	or eax, 0x80000000 + (RegAddr shl 16)	310	or eax, 0x80000000 + (RegAddr shl 16)
311	else	311	else
312	mov eax, 0x80000000 + (RegAddr shl 16) + value	312	mov eax, 0x80000000 + (RegAddr shl 16) + value
313	end if	313	end if
314	out dx, eax	314	out dx, eax
315		315
316	call PHY_WAIT	316	call PHY_WAIT
317	}	317	}
318		318
319	macro READ_GMII_REG RegAddr {	319	macro READ_GMII_REG RegAddr {
320		320
321	local .error, .done	321	local .error, .done
322		322
323	set_io REG_PHYAR	323	set_io REG_PHYAR
324	mov eax, RegAddr shl 16	324	mov eax, RegAddr shl 16
325	out dx, eax	325	out dx, eax
326		326
327	call PHY_WAIT	327	call PHY_WAIT
328	jz .error	328	jz .error
329		329
330	in eax, dx	330	in eax, dx
331	and eax, 0xFFFF	331	and eax, 0xFFFF
332	jmp .done	332	jmp .done
333		333
334	.error:	334	.error:
335	or eax, -1	335	or eax, -1
336	.done:	336	.done:
337	}	337	}
338		338
339	align 4	339	align 4
340	PHY_WAIT: ; io addr must already be set to REG_PHYAR	340	PHY_WAIT: ; io addr must already be set to REG_PHYAR
341		341
342	udelay 1 ;;;1000	342	udelay 1 ;;;1000
343		343
344	push ecx	344	push ecx
345	mov ecx, 2000	345	mov ecx, 2000
346	; Check if the RTL8169 has completed writing/reading to the specified MII register	346	; Check if the RTL8169 has completed writing/reading to the specified MII register
347	@@:	347	@@:
348	in eax, dx	348	in eax, dx
349	test eax, 0x80000000	349	test eax, 0x80000000
350	jz .exit	350	jz .exit
351	udelay 1 ;;;100	351	udelay 1 ;;;100
352	loop @b	352	loop @b
353	.exit:	353	.exit:
354	pop ecx	354	pop ecx
355	ret	355	ret
356		356
357		357
358		358
359	section '.flat' code readable align 16	359	section '.flat' code readable align 16
360		360
361	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	361	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
362	;; ;;	362	;; ;;
363	;; proc START ;;	363	;; proc START ;;
364	;; ;;	364	;; ;;
365	;; (standard driver proc) ;;	365	;; (standard driver proc) ;;
366	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	366	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
367		367
368	align 4	368	align 4
369	proc START stdcall, state:dword	369	proc START stdcall, state:dword
370		370
371	cmp [state], 1	371	cmp [state], 1
372	jne .exit	372	jne .exit
373		373
374	.entry:	374	.entry:
375		375
376	DEBUGF 2,"Loading rtl8169 driver\n"	376	DEBUGF 2,"Loading rtl8169 driver\n"
377	stdcall RegService, my_service, service_proc	377	stdcall RegService, my_service, service_proc
378	ret	378	ret
379		379
380	.fail:	380	.fail:
381	.exit:	381	.exit:
382	xor eax, eax	382	xor eax, eax
383	ret	383	ret
384		384
385	endp	385	endp
386		386
387		387
388	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	388	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
389	;; ;;	389	;; ;;
390	;; proc SERVICE_PROC ;;	390	;; proc SERVICE_PROC ;;
391	;; ;;	391	;; ;;
392	;; (standard driver proc) ;;	392	;; (standard driver proc) ;;
393	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	393	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
394		394
395	align 4	395	align 4
396	proc service_proc stdcall, ioctl:dword	396	proc service_proc stdcall, ioctl:dword
397		397
398	mov edx, [ioctl]	398	mov edx, [ioctl]
399	mov eax, [IOCTL.io_code]	399	mov eax, [IOCTL.io_code]
400		400
401	;------------------------------------------------------	401	;------------------------------------------------------
402		402
403	cmp eax, 0 ;SRV_GETVERSION	403	cmp eax, 0 ;SRV_GETVERSION
404	jne @F	404	jne @F
405		405
406	cmp [IOCTL.out_size], 4	406	cmp [IOCTL.out_size], 4
407	jl .fail	407	jl .fail
408	mov eax, [IOCTL.output]	408	mov eax, [IOCTL.output]
409	mov [eax], dword API_VERSION	409	mov [eax], dword API_VERSION
410		410
411	xor eax, eax	411	xor eax, eax
412	ret	412	ret
413		413
414	;------------------------------------------------------	414	;------------------------------------------------------
415	@@:	415	@@:
416	cmp eax, 1 ;SRV_HOOK	416	cmp eax, 1 ;SRV_HOOK
417	jne .fail	417	jne .fail
418		418
419	cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes	419	cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
420	jl .fail	420	jl .fail
421		421
422	mov eax, [IOCTL.input]	422	mov eax, [IOCTL.input]
423	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given	423	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
424	jne .fail ; other types arent supported for this card yet	424	jne .fail ; other types arent supported for this card yet
425		425
426	; check if the device is already listed	426	; check if the device is already listed
427		427
428	mov esi, device_list	428	mov esi, device_list
429	mov ecx, [devices]	429	mov ecx, [devices]
430	test ecx, ecx	430	test ecx, ecx
431	jz .firstdevice	431	jz .firstdevice
432		432
433	; mov eax, [IOCTL.input] ; get the pci bus and device numbers	433	; mov eax, [IOCTL.input] ; get the pci bus and device numbers
434	mov ax , [eax+1] ;	434	mov ax , [eax+1] ;
435	.nextdevice:	435	.nextdevice:
436	mov ebx, [esi]	436	mov ebx, [esi]
437	cmp ax , word [device.pci_bus] ; compare with pci and device num in device list (notice the usage of word instead of byte)	437	cmp ax , word [device.pci_bus] ; compare with pci and device num in device list (notice the usage of word instead of byte)
438	je .find_devicenum ; Device is already loaded, let's find it's device number	438	je .find_devicenum ; Device is already loaded, let's find it's device number
439	add esi, 4	439	add esi, 4
440	loop .nextdevice	440	loop .nextdevice
441		441
442		442
443	; This device doesnt have its own eth_device structure yet, lets create one	443	; This device doesnt have its own eth_device structure yet, lets create one
444	.firstdevice:	444	.firstdevice:
445	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card	445	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
446	jge .fail	446	jge .fail
447		447
448	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in	448	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in
449		449
450	; Fill in the direct call addresses into the struct	450	; Fill in the direct call addresses into the struct
451		451
452	mov [device.reset], reset	452	mov [device.reset], reset
453	mov [device.transmit], transmit	453	mov [device.transmit], transmit
454	mov [device.get_MAC], read_mac	454	mov [device.get_MAC], read_mac
455	mov [device.set_MAC], write_mac	455	mov [device.set_MAC], write_mac
456	mov [device.unload], unload	456	mov [device.unload], unload
457	mov [device.name], my_service	457	mov [device.name], my_service
458		458
459	; save the pci bus and device numbers	459	; save the pci bus and device numbers
460		460
461	mov eax, [IOCTL.input]	461	mov eax, [IOCTL.input]
462	mov cl , [eax+1]	462	mov cl , [eax+1]
463	mov [device.pci_bus], cl	463	mov [device.pci_bus], cl
464	mov cl , [eax+2]	464	mov cl , [eax+2]
465	mov [device.pci_dev], cl	465	mov [device.pci_dev], cl
466		466
467	; Now, it's time to find the base io addres of the PCI device	467	; Now, it's time to find the base io addres of the PCI device
468		468
469	find_io [device.pci_bus], [device.pci_dev], [device.io_addr]	469	find_io [device.pci_bus], [device.pci_dev], [device.io_addr]
470	mov eax, [device.io_addr]	470	mov eax, [device.io_addr]
471	mov [tpc.mmio_addr], eax	471	mov [tpc.mmio_addr], eax
472		472
473	; We've found the io address, find IRQ now	473	; We've found the io address, find IRQ now
474		474
475	find_irq [device.pci_bus], [device.pci_dev], [device.irq_line]	475	find_irq [device.pci_bus], [device.pci_dev], [device.irq_line]
476		476
477	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\	477	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
478	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8	478	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
479		479
480	; Ok, the eth_device structure is ready, let's probe the device	480	; Ok, the eth_device structure is ready, let's probe the device
481	; Because initialization fires IRQ, IRQ handler must be aware of this device	481	; Because initialization fires IRQ, IRQ handler must be aware of this device
482	mov eax, [devices] ; Add the device structure to our device list	482	mov eax, [devices] ; Add the device structure to our device list
483	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)	483	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)
484	inc [devices] ;	484	inc [devices] ;
485		485
486	call probe ; this function will output in eax	486	call probe ; this function will output in eax
487	test eax, eax	487	test eax, eax
488	jnz .err2 ; If an error occured, exit	488	jnz .err2 ; If an error occured, exit
489		489
490		490
491	mov [device.type], NET_TYPE_ETH	491	mov [device.type], NET_TYPE_ETH
492	call NetRegDev	492	call NetRegDev
493		493
494	cmp eax, -1	494	cmp eax, -1
495	je .destroy	495	je .destroy
496		496
497	ret	497	ret
498		498
499	; If the device was already loaded, find the device number and return it in eax	499	; If the device was already loaded, find the device number and return it in eax
500		500

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(root)/kernel/branches/net/drivers/RTL8169.asm @ 1823 – Rev 1558 → 1559