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Rev 9069 | Rev 9072 | ||
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Line 60... | Line 60... | ||
60 | ccc_pts dd ? ; 0x18, Command completion coalescing ports |
60 | ccc_pts dd ? ; 0x18, Command completion coalescing ports |
61 | em_loc dd ? ; 0x1C, Enclosure management location |
61 | em_loc dd ? ; 0x1C, Enclosure management location |
62 | em_ctl dd ? ; 0x20, Enclosure management control |
62 | em_ctl dd ? ; 0x20, Enclosure management control |
63 | cap2 dd ? ; 0x24, Host capabilities extended |
63 | cap2 dd ? ; 0x24, Host capabilities extended |
64 | bohc dd ? ; 0x28, BIOS/OS handoff control and status |
64 | bohc dd ? ; 0x28, BIOS/OS handoff control and status |
65 | reserved rb (0xA0-0x2C) ; 0x2C - 0x9F, Reserved |
65 | reserved rb (0xA0-HBA_MEM.reserved) ; 0x2C - 0x9F, Reserved |
66 | vendor rb (0x100-0xA0) ; 0xA0 - 0xFF, Vendor specific |
66 | vendor rb (0x100-HBA_MEM.vendor) ; 0xA0 - 0xFF, Vendor specific |
67 | ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS |
67 | ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS |
68 | ends |
68 | ends |
Line 69... | Line 69... | ||
69 | 69 | ||
70 | ; Port Control registers |
70 | ; Port Control registers |
Line 100... | Line 100... | ||
100 | 100 | ||
101 | prdtl dw ? ; Physical region descriptor table length in entries |
101 | prdtl dw ? ; Physical region descriptor table length in entries |
102 | prdbc dd ? ; Physical region descriptor byte count transferred |
102 | prdbc dd ? ; Physical region descriptor byte count transferred |
103 | ctba dd ? ; Command table descriptor base address |
103 | ctba dd ? ; Command table descriptor base address |
104 | ctbau dd ? ; Command table descriptor base address upper 32 bits |
104 | ctbau dd ? ; Command table descriptor base address upper 32 bits |
105 | rsv1 rd 4 ; Reserved |
105 | rd 4 ; Reserved |
Line 106... | Line 106... | ||
106 | ends |
106 | ends |
107 | 107 | ||
108 | struct HBA_PRDT_ENTRY |
108 | struct HBA_PRDT_ENTRY |
109 | dba dd ? ; Data base address |
109 | dba dd ? ; Data base address |
110 | dbau dd ? ; Data base address upper 32 bits |
110 | dbau dd ? ; Data base address upper 32 bits |
111 | rsv0 dd ? ; Reserved |
111 | dd ? ; Reserved |
112 | _flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion, |
112 | _flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion, |
Line 113... | Line 113... | ||
113 | ; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max |
113 | ; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max |
114 | ends |
114 | ends |
115 | 115 | ||
116 | struct HBA_CMD_TBL |
116 | struct HBA_CMD_TBL |
117 | cfis rb 64 ; 0x00, Command FIS |
117 | cfis rb 64 ; 0x00, Command FIS |
118 | acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes |
118 | acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes |
119 | rsv rb 48 ; 0x50, Reserved |
119 | rb 48 ; 0x50, Reserved |
Line 120... | Line 120... | ||
120 | prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535 |
120 | prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535 |
Line 151... | Line 151... | ||
151 | countl db ? ; Count register, 7:0 |
151 | countl db ? ; Count register, 7:0 |
152 | counth db ? ; Count register, 15:8 |
152 | counth db ? ; Count register, 15:8 |
153 | icc db ? ; Isochronous command completion |
153 | icc db ? ; Isochronous command completion |
154 | control db ? ; Control register |
154 | control db ? ; Control register |
Line 155... | Line 155... | ||
155 | 155 | ||
156 | rsv1 rb 4 ; Reserved |
156 | rb 4 ; Reserved |
Line 157... | Line 157... | ||
157 | ends |
157 | ends |
158 | 158 | ||
159 | ; Register FIS – Device to Host |
159 | ; Register FIS – Device to Host |
Line 172... | Line 172... | ||
172 | device db ? ; Device register |
172 | device db ? ; Device register |
Line 173... | Line 173... | ||
173 | 173 | ||
174 | lba3 db ? ; LBA register, 31:24 |
174 | lba3 db ? ; LBA register, 31:24 |
175 | lba4 db ? ; LBA register, 39:32 |
175 | lba4 db ? ; LBA register, 39:32 |
176 | lba5 db ? ; LBA register, 47:40 |
176 | lba5 db ? ; LBA register, 47:40 |
Line 177... | Line 177... | ||
177 | rsv2 db ? ; Reserved |
177 | db ? ; Reserved |
178 | 178 | ||
179 | countl db ? ; Count register, 7:0 |
179 | countl db ? ; Count register, 7:0 |
Line 180... | Line 180... | ||
180 | counth db ? ; Count register, 15:8 |
180 | counth db ? ; Count register, 15:8 |
181 | rsv3 rb 2 ; Reserved |
181 | rb 2 ; Reserved |
Line 182... | Line 182... | ||
182 | 182 | ||
183 | rsv4 rb 4 ; Reserved |
183 | rb 4 ; Reserved |
184 | ends |
184 | ends |
185 | 185 | ||
186 | ; Data FIS – Bidirectional |
186 | ; Data FIS – Bidirectional |
187 | struct FIS_DATA |
187 | struct FIS_DATA |
188 | fis_type db ? ; FIS_TYPE_DATA |
188 | fis_type db ? ; FIS_TYPE_DATA |
189 | _flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier |
189 | _flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier |
Line 190... | Line 190... | ||
190 | rsv1 rb 2 ; Reserved |
190 | rb 2 ; Reserved |
Line 208... | Line 208... | ||
208 | device db ? ; Device register |
208 | device db ? ; Device register |
Line 209... | Line 209... | ||
209 | 209 | ||
210 | lba3 db ? ; LBA register, 31:24 |
210 | lba3 db ? ; LBA register, 31:24 |
211 | lba4 db ? ; LBA register, 39:32 |
211 | lba4 db ? ; LBA register, 39:32 |
212 | lba5 db ? ; LBA register, 47:40 |
212 | lba5 db ? ; LBA register, 47:40 |
Line 213... | Line 213... | ||
213 | rsv2 db ? ; Reserved |
213 | db ? ; Reserved |
214 | 214 | ||
215 | countl db ? ; Count register, 7:0 |
215 | countl db ? ; Count register, 7:0 |
216 | counth db ? ; Count register, 15:8 |
216 | counth db ? ; Count register, 15:8 |
Line 217... | Line 217... | ||
217 | rsv3 db ? ; Reserved |
217 | db ? ; Reserved |
218 | e_status db ? ; New value of status register |
218 | e_status db ? ; New value of status register |
219 | 219 | ||
Line 220... | Line 220... | ||
220 | tc dw ? ; Transfer count |
220 | tc dw ? ; Transfer count |
221 | rsv4 rb 2 ; Reserved |
221 | rb 2 ; Reserved |
222 | ends |
222 | ends |
223 | 223 | ||
224 | ; DMA Setup – Device to Host |
224 | ; DMA Setup – Device to Host |
225 | struct FIS_DMA_SETUP |
225 | struct FIS_DMA_SETUP |
Line 226... | Line 226... | ||
226 | fis_type db ? ; FIS_TYPE_DMA_SETUP |
226 | fis_type db ? ; FIS_TYPE_DMA_SETUP |
227 | _flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed, |
227 | _flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed, |
228 | ; I - Interrupt bit, D - Data transfer direction, 1 - device to host, |
228 | ; I - Interrupt bit, D - Data transfer direction, 1 - device to host, |
229 | ; R - Reserved, P - Port multiplier |
229 | ; R - Reserved, P - Port multiplier |
230 | 230 | ||
Line -... | Line 231... | ||
- | 231 | rb 2 ; Reserved |
|
- | 232 | DMAbufferID dq ? ; DMA Buffer Identifier. |
|
231 | rsved rb 2 ; Reserved |
233 | ; Used to Identify DMA buffer in host memory. |
232 | DMAbufferID dq ? ; DMA Buffer Identifier. |
234 | ; SATA Spec says host specific and not in Spec. |
233 | ; Used to Identify DMA buffer in host memory. |
235 | ; Trying AHCI spec might work. |
Line 234... | Line 236... | ||
234 | ; SATA Spec says host specific and not in Spec. |
236 | |
235 | ; Trying AHCI spec might work. |
237 | dd ? ; Reserved |
236 | 238 | DMAbufOffset dd ? ; Byte offset into buffer. First 2 bits must be 0 |
|
Line 250... | Line 252... | ||
250 | protocol dd ? ; Protocol |
252 | protocol dd ? ; Protocol |
251 | ends |
253 | ends |
Line 252... | Line 254... | ||
252 | 254 | ||
253 | struct HBA_FIS |
255 | struct HBA_FIS |
254 | dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS |
256 | dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS |
Line 255... | Line 257... | ||
255 | pad0 rb 4 ; |
257 | rb 4 ; padding |
256 | 258 | ||
Line 257... | Line 259... | ||
257 | psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS |
259 | psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS |
258 | pad1 rb 12 ; |
260 | rb 12 ; padding |
Line 259... | Line 261... | ||
259 | 261 | ||
Line 260... | Line 262... | ||
260 | rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS |
262 | rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS |
Line 261... | Line 263... | ||
261 | pad2 rb 4 ; |
263 | rb 4 ; padding |
262 | 264 | ||
Line 263... | Line 265... | ||
263 | sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS |
265 | sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS |
264 | 266 | ||
265 | ufis rb 64 ; 0x60 |
267 | ufis rb 64 ; 0x60 |