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10 | ;; ;; |
10 | ;; ;; |
11 | ;; art_zh |
11 | ;; art_zh |
12 | ;; ;; |
12 | ;; ;; |
13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
Line 14... | Line 14... | ||
14 | 14 | ||
Line 15... | Line 15... | ||
15 | $Revision: 1463 $ |
15 | $Revision: 1554 $ |
16 | 16 | ||
17 | ;*************************************************************************** |
17 | ;*************************************************************************** |
18 | ; Function |
18 | ; Function |
Line 29... | Line 29... | ||
29 | ;*************************************************************************** |
29 | ;*************************************************************************** |
Line 30... | Line 30... | ||
30 | 30 | ||
31 | align 4 |
31 | align 4 |
32 | mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here |
32 | mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here |
33 | mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address |
33 | mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address |
34 | mmio_pcie_cfg_pdes dw 0 ; number of PDEs to map the space |
34 | mmio_pcie_cfg_pdes dw 1 ; number of PDEs to map the space |
Line 35... | Line 35... | ||
35 | PCIe_bus_range dw 0 ; the Bus range: power-of-2 Megabytes |
35 | PCIe_bus_range dw 2 ; the Bus range: power-of-2 Megabytes |
36 | 36 | ||
37 | 37 | ||
- | 38 | align 4 |
|
38 | align 4 |
39 | pci_ext_config: |
39 | pci_ext_config: |
40 | mov eax, [mmio_pcie_cfg_addr] |
40 | mov ebx, [mmio_pcie_cfg_addr] |
41 | mov ebx, eax |
41 | or ebx,ebx |
42 | or ebx, ebx |
42 | jz @f |
43 | jz @f |
43 | or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
44 | or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
44 | jnz .pcie_failed |
45 | jnz .pcie_failed |
45 | add ebx, 0x0FFFFC |
46 | add ebx, 0x0FFFFC |
46 | cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
47 | cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
47 | ja .pcie_failed |
48 | ja .pcie_failed |
48 | jmp .pcie_cfg_mapped |
49 | ret ; return the address forced |
49 | @@: |
50 | @@: |
50 | mov ebx, [cpu_vendor] |
51 | mov ebx, [cpu_vendor] |
Line 73... | Line 74... | ||
73 | jnz .no_pcie_cfg |
74 | jnz .no_pcie_cfg |
74 | xor al, al |
75 | xor al, al |
75 | shl eax, 8 |
76 | shl eax, 8 |
76 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
77 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
77 | jnz .no_pcie_cfg |
78 | jnz .no_pcie_cfg |
78 | mov [mmio_pcie_cfg_addr], eax |
- | |
79 | ; add eax, 0x000FFFFC |
- | |
80 | ; sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus |
- | |
81 | ; ja .no_pcie_cfg |
- | |
Line 82... | Line 79... | ||
82 | 79 | ||
Line 83... | Line -... | ||
83 | ; -- it looks like a true PCIe config space; |
- | |
84 | - | ||
85 | .pcie_cfg_mapped: |
- | |
86 | - | ||
87 | mov esi, boot_pcie_ok |
80 | ; -- it looks like a true PCIe config space; |
Line 88... | Line 81... | ||
88 | call boot_log |
81 | |
89 | ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
- | |
90 | 82 | ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
|
91 | .no_pcie_cfg: |
83 | |
92 | 84 | .no_pcie_cfg: |
|
93 | xor eax, eax |
85 | xor eax, eax |
94 | mov [mmio_pcie_cfg_addr], eax |
86 | mov [mmio_pcie_cfg_addr], eax |
95 | mov [mmio_pcie_cfg_lim], eax |
87 | mov [mmio_pcie_cfg_lim], eax |
- | 88 | add bl, 12 |
|
96 | add bl, 12 |
89 | cmp bl, 0xC0 ; MMIO regs lay below this offset |
97 | cmp bl, 0xC0 ; MMIO regs lay below this offset |
90 | jb .check_HT_mmio |
98 | jb .check_HT_mmio |
91 | |
99 | .pcie_failed: |
92 | .pcie_failed: |