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;;                                                              ;;
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;;                                                              ;;
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;;  	            art_zh                  ;;
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;;                  art_zh                  ;;
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;;                                                              ;;
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;;                                                              ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision: 1463 $
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$Revision: 1554 $
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;***************************************************************************
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;***************************************************************************
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;   Function
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;   Function
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;***************************************************************************
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;***************************************************************************
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align 4
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align 4
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mmio_pcie_cfg_addr	dd  	0x00000000	; pcie space may be defined here
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mmio_pcie_cfg_addr	dd	0x00000000	; pcie space may be defined here
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mmio_pcie_cfg_lim	dd	0x000FFFFF	; upper pcie space address
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mmio_pcie_cfg_lim	dd	0x000FFFFF	; upper pcie space address
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mmio_pcie_cfg_pdes	dw	0		; number of PDEs to map the space
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mmio_pcie_cfg_pdes	dw	1		; number of PDEs to map the space
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PCIe_bus_range		dw	0		; the Bus range: power-of-2 Megabytes
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PCIe_bus_range		dw	2		; the Bus range: power-of-2 Megabytes
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- 
 
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align 4
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align 4
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pci_ext_config:
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pci_ext_config:
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	mov	eax, [mmio_pcie_cfg_addr]
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	mov	ebx, [mmio_pcie_cfg_addr]
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	mov	ebx, eax
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	or	ebx,ebx
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	or	ebx, ebx
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	jz	@f
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	jz	@f
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	or	ebx, 0x7FFFFFFF		; required by PCI-SIG standards
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	or	ebx, 0x7FFFFFFF 	; required by PCI-SIG standards
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	jnz	.pcie_failed
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	jnz	.pcie_failed
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	add	ebx, 0x0FFFFC
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	add	ebx, 0x0FFFFC
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	cmp	ebx, [mmio_pcie_cfg_lim]; is the space limit correct?
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	cmp	ebx, [mmio_pcie_cfg_lim]; is the space limit correct?
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	ja	.pcie_failed
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	ja	.pcie_failed
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	jmp	.pcie_cfg_mapped
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	ret				; return the address forced
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@@:
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@@:
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	mov	ebx, [cpu_vendor]
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	mov	ebx, [cpu_vendor]
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	jnz	.no_pcie_cfg
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	jnz	.no_pcie_cfg
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	xor	al, al
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	xor	al, al
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	shl	eax, 8
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	shl	eax, 8
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	test	eax, 0x000F0000		; MMIO Base must be bus0-aligned
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	test	eax, 0x000F0000 	; MMIO Base must be bus0-aligned
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	jnz	.no_pcie_cfg
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	jnz	.no_pcie_cfg
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	mov	[mmio_pcie_cfg_addr], eax
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;	add	eax, 0x000FFFFC
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;	sub	eax,[mmio_pcie_cfg_lim]	; MMIO must cover at least one bus
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;	ja	.no_pcie_cfg
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;	-- it looks like a true PCIe config space;
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.pcie_cfg_mapped:
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- 
 
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	mov	esi, boot_pcie_ok
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;       -- it looks like a true PCIe config space;
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	call	boot_log
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	ret	; <<<<<<<<<<< OK >>>>>>>>>>>
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	ret	; <<<<<<<<<<< OK >>>>>>>>>>>
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.no_pcie_cfg:
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.no_pcie_cfg:
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	xor	eax, eax
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	xor	eax, eax
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	mov	[mmio_pcie_cfg_addr], eax
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	mov	[mmio_pcie_cfg_addr], eax
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	mov	[mmio_pcie_cfg_lim],  eax
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	mov	[mmio_pcie_cfg_lim],  eax
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	add	bl, 12
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	add	bl, 12
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	cmp	bl, 0xC0		; MMIO regs lay below this offset
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	cmp	bl, 0xC0		; MMIO regs lay below this offset
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	jb	.check_HT_mmio
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	jb	.check_HT_mmio
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.pcie_failed:
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.pcie_failed: