WebSVN – Kolibri OS – Diff – /kernel/branches/Kolibri-A/trunk/bus/HT.inc


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;;                                                              ;;
;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
;; Distributed under terms of the GNU General Public License    ;;
;;                                                              ;;
;;  HT.inc                                                      ;;                                                    ;;
;;                                                              ;;
;;  AMD HyperTransport bus control                              ;;
;;                                                              ;;
;;                  art_zh                ;;
;;                                                              ;;
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$Revision: 1554 $
 
NB_MISC_INDEX	equ	0xF0000060	; NB Misc indirect access
NB_MISC_DATA	equ	0xF0000064
PCIEIND_INDEX	equ	0xF00000E0	; PCIe Core indirect config space access
HTIU_NB_INDEX	equ	0xF0000094	; HyperTransport indirect config space access
 
;=============================================================================
;
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
;
;=============================================================================
 
org $-OS_BASE	; physical addresses needed at initial stage
 
align 4
 
;------------------------------------------
;       params:   al = nbconfig register#
;       returns: eax = register content
;
rs7xx_nbconfig_read_pci:
	and	eax, 0x0FC		 ; leave register# only
	or	eax, 0x80000000 	 ; bdf = 0:0.0
	mov	dx,  0x0CF8		 ; write to index reg
	out	dx, eax
	add	dl, 4
	in	eax, dx
	ret
align 4
 
rs7xx_nbconfig_flush_pci:
	mov	eax, 0x0B0		; a scratch reg
	mov	dx,  0xCF8
	out	dx,  eax
	ret
 
align 4
 
;------------------------------------------
;       params:   al = nbconfig register#
;                ebx = register content
;
rs7xx_nbconfig_write_pci:
	and	eax, 0x0FC		 ; leave register# only
	or	eax, 0x80000000 	 ; bdf = 0:0.0
	mov	dx,  0x0CF8		 ; write to index reg
	out	dx, eax
	add	dl, 4
	mov	eax, ebx
	out	dx, eax
	ret
 
;***************************************************************************
;   Function
;      rs7xx_unlock_bar3:     unlocks the BAR3 register of nbconfig that
;                             makes pcie config address space visible
;   -----------------------
;   in: nothing      out: nothing      destroys:   eax ebx edx
;
;***************************************************************************
align 4
rs7xx_unlock_bar3:
	mov	eax, NB_MISC_INDEX
	mov	ebx, 0x080			; NBMISCIND:0x0; write-enable
	call	rs7xx_nbconfig_write_pci	; set index
	mov	eax, NB_MISC_DATA
	call	rs7xx_nbconfig_read_pci 	; read data
	mov	ebx, eax
	and	ebx, 0xFFFFFFF7 		; clear bit3
	mov	eax, NB_MISC_DATA
	call	rs7xx_nbconfig_write_pci	; write it back
	mov	eax, NB_MISC_INDEX
	xor	ebx, ebx			; reg#0; write-locked
	call	rs7xx_nbconfig_write_pci	; set index
	ret
 
 
 
;***************************************************************************
;   Function
;      fusion_pcie_init:
;
;   Description
;       PCIe extended  config space detection and mapping
;
;***************************************************************************
 
align 4
 
 
 
; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
align 4
fusion_pcie_init:
	mov	ecx, 0xC0010058
	rdmsr
	or	edx, edx
	jnz	$				; PCIe is in the upper memory. Stop.
	xchg	dl, al
	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; store the physical address
	mov	ecx, edx
	and	dl, 1
	jz	$				; bit[0] = 1 means no PCIe mapping allowed. Stop.
	shr	cl, 2				; ecx = log2(number of buses)
	mov	word[PCIe_bus_range-OS_BASE], cx
	sub	cl, 2
	jae	@f
	xor	cl, cl
@@:
	shl	edx, cl 			; edx = number of 4M pages to map
	mov	word[mmio_pcie_cfg_pdes-OS_BASE], dx
	shl	edx, 22
	dec	edx
	add	edx, eax			; the upper configspace limit
	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
 
; ---- large pages mapping  ----
; (eax = phys. address of PCIe conf.space)
;
.map_pcie_pages:
	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
	mov	ecx, PCIe_CONFIG_SPACE			; linear address
	mov	ebx, ecx
	shr	ebx, 20
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
	jb	@f
	mov	dl, 0x33
	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
@@:
	xor	dx,  dx 			; PDEs counter
.write_pde:
	mov	dword[ebx], eax 		; map 4 buses
	add	bx,  4				; new PDE
	add	eax, 0x400000			; +4M phys.
	add	ecx, 0x400000			; +4M lin.
	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
	jae	.pcie_cfg_mapped
	inc	dl
	jmp	.write_pde
 
.pcie_cfg_mapped:
 
create_mmio_pte:
	mov	ecx, mmio_pte				; physical address
	or	ecx, (PG_NOCACHE + PG_SHARED + PG_SW)
	mov	ebx, FUSION_MMIO			; linear address
	shr	ebx, 20
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
	mov	dword[ebx], ecx 			; Fusion MMIO tables
 
; ---- short page mapping  ----
.map_apic_mmio:
	mov	ecx, 0x01B	; APIC BAR
	rdmsr
	and	eax, 0xFFFFF000 			; physical address
	or	eax, (PG_NOCACHE + PG_SHARED + PG_SW)
	mov	dword[mmio_pte + 0], eax
 
	ret	; <<< OK >>>
 
; ================================================================================
 
org OS_BASE+$	; back to the linear address space
 
;--------------------------------------------------------------
align 4
rs780_read_misc:
;  in: eax(al) - reg#           out: eax = NBMISCIND data
	push	edx
	mov	edx, NB_MISC_INDEX
	and	eax, 0x07F
	mov	[edx], eax
	add	dl, 4
	mov	eax, [edx]
	pop	edx
	ret
 
;-------------------------------------------
align 4
rs780_write_misc:
;  in: eax(al) - reg#     ebx = NBMISCIND data
	push	edx
	mov	edx, NB_MISC_INDEX
	and	eax, 0x07F
	or	eax, 0x080		; set WE
	mov	[edx], eax
	add	dl, 4
	mov	[edx], ebx
	sub	dl, 4
	xor	eax,   eax
	mov	[edx], eax		; safety last
	pop	edx
	ret
 
;-------------------------------------------------------------
align 4
rs780_read_pcieind:
;  in: ah = bridge#, al = reg#           out: eax = PCIEIND data
	push	edx
	xor	edx, edx
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
	shl	edx, 15 		; device#
	add	edx, PCIEIND_INDEX	; full bdf-address
	and	eax, 0x30FF
	or	al,  al
	jnz	@f
	shl	eax, 4			; set bits 17..16 for a Core bridge
@@:
	mov	[edx], eax
	add	dl,  4
	mov	eax, [edx]
	pop	edx
	ret
 
;-------------------------------------------
align 4
rs780_write_pcieind:
;  in: ah = bridge#, al = reg#,  ebx = PCIEIND data
	push	edx
	xor	edx, edx
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
	shl	edx, 15 		; device#
	add	edx, PCIEIND_INDEX	; full bdf-address
	and	eax, 0x30FF
	or	al,  al
	jnz	@f
	shl	eax, 4			; set bits 17..16 for a Core bridge
@@:
	mov	[edx], eax
	add	dl,  4
	mov	[edx], ebx
	sub	dl,  4
	xor	eax,   eax
	mov	[edx], eax		; safety last
	pop	edx
	ret
 
;------------------------------------------------
align 4
rs780_read_htiu:
; in:  al = reg#  |  out: eax = HTIU data
;------------------------------------------------
	push	edx
	mov	edx,  HTIU_NB_INDEX
	and	eax, 0x07F
	mov	[edx], eax
	add	dl,  4
	mov	eax, [edx]
	pop	edx
	ret
;------------------------------------------------
align 4
rs780_write_htiu:
; in:  al = reg#; ebx = data
;------------------------------------------------
	push	edx
	mov	edx,  HTIU_NB_INDEX
	and	eax, 0x07F
	or	eax, 0x100
	mov	[edx], eax
	add	dl,  4
	mov	[edx], ebx
	sub	dl,  4
	xor	eax,   eax
	mov	[edx], eax
	pop	edx
	ret
 
;------------------------------------------------
align 4
sys_rdmsr:
;  in: [esp+8] = MSR#
; out: [esp+8] = MSR[63:32]
;        [eax] = MSR[31: 0]
;------------------------------------------------
	push	ecx edx
	mov	ecx, [esp+16]
	rdmsr
	mov	[esp+16], edx
	pop	edx ecx
	ret
 
apic_timer_reset:
	xor	eax, eax
	mov	[apic_data+0], eax
	mov	ebx, LAPIC_BAR+ 0x320
	mov	eax, [ebx]
	and	eax, 0xFFFEFF00
	or	eax, 0x0000003F       ; int vector + norestart
	mov	[ebx], eax
	mov	dword[apic_data + 8], 100000000
	ret
 
 
apic_timer_int:
	push	eax
	inc	dword [apic_data + 0]
	mov	eax,  [apic_data + 8]
	mov	dword [LAPIC_BAR + 0x380], eax	      ; load APICTIC
	mov	dword [LAPIC_BAR + 0x0B0], 0	    ; end of interrupt
;        mov     dword [LAPIC_BAR + 0x420], 0x3F     ; end of interrupt
	pop	eax
	iretd

Rev 3526	Rev 3531
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;;	3	;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; HT.inc ;; ;;	6	;; HT.inc ;; ;;
7	;; ;;	7	;; ;;
8	;; AMD HyperTransport bus control ;;	8	;; AMD HyperTransport bus control ;;
9	;; ;;	9	;; ;;
10	;; art_zh ;;	10	;; art_zh ;;
11	;; ;;	11	;; ;;
12	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	12	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13		13
14	$Revision: 1554 $	14	$Revision: 1554 $
15		15
16	NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access	16	NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access
17	NB_MISC_DATA equ 0xF0000064	17	NB_MISC_DATA equ 0xF0000064
18	PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access	18	PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access
19	HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access	19	HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access
20		20
21	;=============================================================================	21	;=============================================================================
22	;	22	;
23	; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets	23	; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
24	;	24	;
25	;=============================================================================	25	;=============================================================================
26		26
27	org $-OS_BASE ; physical addresses needed at initial stage	27	org $-OS_BASE ; physical addresses needed at initial stage
28		28
29	align 4	29	align 4
30		30
31	;------------------------------------------	31	;------------------------------------------
32	; params: al = nbconfig register#	32	; params: al = nbconfig register#
33	; returns: eax = register content	33	; returns: eax = register content
34	;	34	;
35	rs7xx_nbconfig_read_pci:	35	rs7xx_nbconfig_read_pci:
36	and eax, 0x0FC ; leave register# only	36	and eax, 0x0FC ; leave register# only
37	or eax, 0x80000000 ; bdf = 0:0.0	37	or eax, 0x80000000 ; bdf = 0:0.0
38	mov dx, 0x0CF8 ; write to index reg	38	mov dx, 0x0CF8 ; write to index reg
39	out dx, eax	39	out dx, eax
40	add dl, 4	40	add dl, 4
41	in eax, dx	41	in eax, dx
42	ret	42	ret
43	align 4	43	align 4
44		44
45	rs7xx_nbconfig_flush_pci:	45	rs7xx_nbconfig_flush_pci:
46	mov eax, 0x0B0 ; a scratch reg	46	mov eax, 0x0B0 ; a scratch reg
47	mov dx, 0xCF8	47	mov dx, 0xCF8
48	out dx, eax	48	out dx, eax
49	ret	49	ret
50		50
51	align 4	51	align 4
52		52
53	;------------------------------------------	53	;------------------------------------------
54	; params: al = nbconfig register#	54	; params: al = nbconfig register#
55	; ebx = register content	55	; ebx = register content
56	;	56	;
57	rs7xx_nbconfig_write_pci:	57	rs7xx_nbconfig_write_pci:
58	and eax, 0x0FC ; leave register# only	58	and eax, 0x0FC ; leave register# only
59	or eax, 0x80000000 ; bdf = 0:0.0	59	or eax, 0x80000000 ; bdf = 0:0.0
60	mov dx, 0x0CF8 ; write to index reg	60	mov dx, 0x0CF8 ; write to index reg
61	out dx, eax	61	out dx, eax
62	add dl, 4	62	add dl, 4
63	mov eax, ebx	63	mov eax, ebx
64	out dx, eax	64	out dx, eax
65	ret	65	ret
66		66
67	;***************************************************************************	67	;***************************************************************************
68	; Function	68	; Function
69	; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that	69	; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that
70	; makes pcie config address space visible	70	; makes pcie config address space visible
71	; -----------------------	71	; -----------------------
72	; in: nothing out: nothing destroys: eax ebx edx	72	; in: nothing out: nothing destroys: eax ebx edx
73	;	73	;
74	;***************************************************************************	74	;***************************************************************************
75	align 4	75	align 4
76	rs7xx_unlock_bar3:	76	rs7xx_unlock_bar3:
77	mov eax, NB_MISC_INDEX	77	mov eax, NB_MISC_INDEX
78	mov ebx, 0x080 ; NBMISCIND:0x0; write-enable	78	mov ebx, 0x080 ; NBMISCIND:0x0; write-enable
79	call rs7xx_nbconfig_write_pci ; set index	79	call rs7xx_nbconfig_write_pci ; set index
80	mov eax, NB_MISC_DATA	80	mov eax, NB_MISC_DATA
81	call rs7xx_nbconfig_read_pci ; read data	81	call rs7xx_nbconfig_read_pci ; read data
82	mov ebx, eax	82	mov ebx, eax
83	and ebx, 0xFFFFFFF7 ; clear bit3	83	and ebx, 0xFFFFFFF7 ; clear bit3
84	mov eax, NB_MISC_DATA	84	mov eax, NB_MISC_DATA
85	call rs7xx_nbconfig_write_pci ; write it back	85	call rs7xx_nbconfig_write_pci ; write it back
86	mov eax, NB_MISC_INDEX	86	mov eax, NB_MISC_INDEX
87	xor ebx, ebx ; reg#0; write-locked	87	xor ebx, ebx ; reg#0; write-locked
88	call rs7xx_nbconfig_write_pci ; set index	88	call rs7xx_nbconfig_write_pci ; set index
89	ret	89	ret
90		90
91		91
92		92
93	;***************************************************************************	93	;***************************************************************************
94	; Function	94	; Function
95	; fusion_pcie_init:	95	; fusion_pcie_init:
96	;	96	;
97	; Description	97	; Description
98	; PCIe extended config space detection and mapping	98	; PCIe extended config space detection and mapping
99	;	99	;
100	;***************************************************************************	100	;***************************************************************************
101		101
102	align 4	102	align 4
103		103
104		104
105		105
106	; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----	106	; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
107	align 4	107	align 4
108	fusion_pcie_init:	108	fusion_pcie_init:
109	mov ecx, 0xC0010058	109	mov ecx, 0xC0010058
110	rdmsr	110	rdmsr
111	or edx, edx	111	or edx, edx
112	jnz $ ; PCIe is in the upper memory. Stop.	112	jnz $ ; PCIe is in the upper memory. Stop.
113	xchg dl, al	113	xchg dl, al
114	mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address	114	mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address
115	mov ecx, edx	115	mov ecx, edx
116	and dl, 1	116	and dl, 1
117	jz $ ; bit[0] = 1 means no PCIe mapping allowed. Stop.	117	jz $ ; bit[0] = 1 means no PCIe mapping allowed. Stop.
118	shr cl, 2 ; ecx = log2(number of buses)	118	shr cl, 2 ; ecx = log2(number of buses)
119	mov word[PCIe_bus_range-OS_BASE], cx	119	mov word[PCIe_bus_range-OS_BASE], cx
120	sub cl, 2	120	sub cl, 2
121	jae @f	121	jae @f
122	xor cl, cl	122	xor cl, cl
123	@@:	123	@@:
124	shl edx, cl ; edx = number of 4M pages to map	124	shl edx, cl ; edx = number of 4M pages to map
125	mov word[mmio_pcie_cfg_pdes-OS_BASE], dx	125	mov word[mmio_pcie_cfg_pdes-OS_BASE], dx
126	shl edx, 22	126	shl edx, 22
127	dec edx	127	dec edx
128	add edx, eax ; the upper configspace limit	128	add edx, eax ; the upper configspace limit
129	mov dword[mmio_pcie_cfg_lim-OS_BASE], edx	129	mov dword[mmio_pcie_cfg_lim-OS_BASE], edx
130		130
131	; ---- large pages mapping ----	131	; ---- large pages mapping ----
132	; (eax = phys. address of PCIe conf.space)	132	; (eax = phys. address of PCIe conf.space)
133	;	133	;
134	.map_pcie_pages:	134	.map_pcie_pages:
135	or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!	135	or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!
136	mov ecx, PCIe_CONFIG_SPACE ; linear address	136	mov ecx, PCIe_CONFIG_SPACE ; linear address
137	mov ebx, ecx	137	mov ebx, ecx
138	shr ebx, 20	138	shr ebx, 20
139	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @	139	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
140	mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space	140	mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space
141	cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M	141	cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
142	jb @f	142	jb @f
143	mov dl, 0x33	143	mov dl, 0x33
144	mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl	144	mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl
145	@@:	145	@@:
146	xor dx, dx ; PDEs counter	146	xor dx, dx ; PDEs counter
147	.write_pde:	147	.write_pde:
148	mov dword[ebx], eax ; map 4 buses	148	mov dword[ebx], eax ; map 4 buses
149	add bx, 4 ; new PDE	149	add bx, 4 ; new PDE
150	add eax, 0x400000 ; +4M phys.	150	add eax, 0x400000 ; +4M phys.
151	add ecx, 0x400000 ; +4M lin.	151	add ecx, 0x400000 ; +4M lin.
152	cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	152	cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
153	jae .pcie_cfg_mapped	153	jae .pcie_cfg_mapped
154	inc dl	154	inc dl
155	jmp .write_pde	155	jmp .write_pde
156		156
157	.pcie_cfg_mapped:	157	.pcie_cfg_mapped:
158		158
159	create_mmio_pte:	159	create_mmio_pte:
160	mov ecx, mmio_pte ; physical address	160	mov ecx, mmio_pte ; physical address
161	or ecx, (PG_NOCACHE + PG_SHARED)	161	or ecx, (PG_NOCACHE + PG_SHARED + PG_SW)
162	mov ebx, FUSION_MMIO ; linear address	162	mov ebx, FUSION_MMIO ; linear address
163	shr ebx, 20	163	shr ebx, 20
164	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @	164	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
165	mov dword[ebx], ecx ; Fusion MMIO tables	165	mov dword[ebx], ecx ; Fusion MMIO tables
166		166
167	; ---- short page mapping ----	167	; ---- short page mapping ----
168	.map_apic_mmio:	168	.map_apic_mmio:
169	mov ecx, 0x01B ; APIC BAR	169	mov ecx, 0x01B ; APIC BAR
170	rdmsr	170	rdmsr
171	and eax, 0xFFFFF000 ; physical address	171	and eax, 0xFFFFF000 ; physical address
172	or eax, (PG_NOCACHE + PG_SHARED)	172	or eax, (PG_NOCACHE + PG_SHARED + PG_SW)
173	mov dword[mmio_pte + 0], eax	173	mov dword[mmio_pte + 0], eax
174		174
175	ret ; <<< OK >>>	175	ret ; <<< OK >>>
176		176
177	; ================================================================================	177	; ================================================================================
178		178
179	org OS_BASE+$ ; back to the linear address space	179	org OS_BASE+$ ; back to the linear address space
180		180
181	;--------------------------------------------------------------	181	;--------------------------------------------------------------
182	align 4	182	align 4
183	rs780_read_misc:	183	rs780_read_misc:
184	; in: eax(al) - reg# out: eax = NBMISCIND data	184	; in: eax(al) - reg# out: eax = NBMISCIND data
185	push edx	185	push edx
186	mov edx, NB_MISC_INDEX	186	mov edx, NB_MISC_INDEX
187	and eax, 0x07F	187	and eax, 0x07F
188	mov [edx], eax	188	mov [edx], eax
189	add dl, 4	189	add dl, 4
190	mov eax, [edx]	190	mov eax, [edx]
191	pop edx	191	pop edx
192	ret	192	ret
193		193
194	;-------------------------------------------	194	;-------------------------------------------
195	align 4	195	align 4
196	rs780_write_misc:	196	rs780_write_misc:
197	; in: eax(al) - reg# ebx = NBMISCIND data	197	; in: eax(al) - reg# ebx = NBMISCIND data
198	push edx	198	push edx
199	mov edx, NB_MISC_INDEX	199	mov edx, NB_MISC_INDEX
200	and eax, 0x07F	200	and eax, 0x07F
201	or eax, 0x080 ; set WE	201	or eax, 0x080 ; set WE
202	mov [edx], eax	202	mov [edx], eax
203	add dl, 4	203	add dl, 4
204	mov [edx], ebx	204	mov [edx], ebx
205	sub dl, 4	205	sub dl, 4
206	xor eax, eax	206	xor eax, eax
207	mov [edx], eax ; safety last	207	mov [edx], eax ; safety last
208	pop edx	208	pop edx
209	ret	209	ret
210		210
211	;-------------------------------------------------------------	211	;-------------------------------------------------------------
212	align 4	212	align 4
213	rs780_read_pcieind:	213	rs780_read_pcieind:
214	; in: ah = bridge#, al = reg# out: eax = PCIEIND data	214	; in: ah = bridge#, al = reg# out: eax = PCIEIND data
215	push edx	215	push edx
216	xor edx, edx	216	xor edx, edx
217	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB	217	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB
218	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge	218	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge
219	shl edx, 15 ; device#	219	shl edx, 15 ; device#
220	add edx, PCIEIND_INDEX ; full bdf-address	220	add edx, PCIEIND_INDEX ; full bdf-address
221	and eax, 0x30FF	221	and eax, 0x30FF
222	or al, al	222	or al, al
223	jnz @f	223	jnz @f
224	shl eax, 4 ; set bits 17..16 for a Core bridge	224	shl eax, 4 ; set bits 17..16 for a Core bridge
225	@@:	225	@@:
226	mov [edx], eax	226	mov [edx], eax
227	add dl, 4	227	add dl, 4
228	mov eax, [edx]	228	mov eax, [edx]
229	pop edx	229	pop edx
230	ret	230	ret
231		231
232	;-------------------------------------------	232	;-------------------------------------------
233	align 4	233	align 4
234	rs780_write_pcieind:	234	rs780_write_pcieind:
235	; in: ah = bridge#, al = reg#, ebx = PCIEIND data	235	; in: ah = bridge#, al = reg#, ebx = PCIEIND data
236	push edx	236	push edx
237	xor edx, edx	237	xor edx, edx
238	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB	238	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB
239	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge	239	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge
240	shl edx, 15 ; device#	240	shl edx, 15 ; device#
241	add edx, PCIEIND_INDEX ; full bdf-address	241	add edx, PCIEIND_INDEX ; full bdf-address
242	and eax, 0x30FF	242	and eax, 0x30FF
243	or al, al	243	or al, al
244	jnz @f	244	jnz @f
245	shl eax, 4 ; set bits 17..16 for a Core bridge	245	shl eax, 4 ; set bits 17..16 for a Core bridge
246	@@:	246	@@:
247	mov [edx], eax	247	mov [edx], eax
248	add dl, 4	248	add dl, 4
249	mov [edx], ebx	249	mov [edx], ebx
250	sub dl, 4	250	sub dl, 4
251	xor eax, eax	251	xor eax, eax
252	mov [edx], eax ; safety last	252	mov [edx], eax ; safety last
253	pop edx	253	pop edx
254	ret	254	ret
255		255
256	;------------------------------------------------	256	;------------------------------------------------
257	align 4	257	align 4
258	rs780_read_htiu:	258	rs780_read_htiu:
259	; in: al = reg# \| out: eax = HTIU data	259	; in: al = reg# \| out: eax = HTIU data
260	;------------------------------------------------	260	;------------------------------------------------
261	push edx	261	push edx
262	mov edx, HTIU_NB_INDEX	262	mov edx, HTIU_NB_INDEX
263	and eax, 0x07F	263	and eax, 0x07F
264	mov [edx], eax	264	mov [edx], eax
265	add dl, 4	265	add dl, 4
266	mov eax, [edx]	266	mov eax, [edx]
267	pop edx	267	pop edx
268	ret	268	ret
269	;------------------------------------------------	269	;------------------------------------------------
270	align 4	270	align 4
271	rs780_write_htiu:	271	rs780_write_htiu:
272	; in: al = reg#; ebx = data	272	; in: al = reg#; ebx = data
273	;------------------------------------------------	273	;------------------------------------------------
274	push edx	274	push edx
275	mov edx, HTIU_NB_INDEX	275	mov edx, HTIU_NB_INDEX
276	and eax, 0x07F	276	and eax, 0x07F
277	or eax, 0x100	277	or eax, 0x100
278	mov [edx], eax	278	mov [edx], eax
279	add dl, 4	279	add dl, 4
280	mov [edx], ebx	280	mov [edx], ebx
281	sub dl, 4	281	sub dl, 4
282	xor eax, eax	282	xor eax, eax
283	mov [edx], eax	283	mov [edx], eax
284	pop edx	284	pop edx
285	ret	285	ret
286		286
287	;------------------------------------------------	287	;------------------------------------------------
288	align 4	288	align 4
289	sys_rdmsr:	289	sys_rdmsr:
290	; in: [esp+8] = MSR#	290	; in: [esp+8] = MSR#
291	; out: [esp+8] = MSR[63:32]	291	; out: [esp+8] = MSR[63:32]
292	; [eax] = MSR[31: 0]	292	; [eax] = MSR[31: 0]
293	;------------------------------------------------	293	;------------------------------------------------
294	push ecx edx	294	push ecx edx
295	mov ecx, [esp+16]	295	mov ecx, [esp+16]
296	rdmsr	296	rdmsr
297	mov [esp+16], edx	297	mov [esp+16], edx
298	pop edx ecx	298	pop edx ecx
299	ret	299	ret
-		300
-		301	apic_timer_reset:
-		302	xor eax, eax
-		303	mov [apic_data+0], eax
-		304	mov ebx, LAPIC_BAR+ 0x320
-		305	mov eax, [ebx]
-		306	and eax, 0xFFFEFF00
-		307	or eax, 0x0000003F ; int vector + norestart
-		308	mov [ebx], eax
-		309	mov dword[apic_data + 8], 100000000
-		310	ret
-		311
-		312
-		313	apic_timer_int:
-		314	push eax
-		315	inc dword [apic_data + 0]
-		316	mov eax, [apic_data + 8]
-		317	mov dword [LAPIC_BAR + 0x380], eax ; load APICTIC
-		318	mov dword [LAPIC_BAR + 0x0B0], 0 ; end of interrupt
-		319	; mov dword [LAPIC_BAR + 0x420], 0x3F ; end of interrupt
-		320	pop eax
-		321	iretd

Subversion Repositories Kolibri OS

(root)/kernel/branches/Kolibri-A/trunk/bus/HT.inc – Rev 3526 → 3531