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Rev 3519 Rev 3526
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;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
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;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;; Distributed under terms of the GNU General Public License    ;;
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;;                                                              ;;
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;;                                                              ;;
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;;  HT.inc                                                      ;;                                                    ;;
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;;  HT.inc                                                      ;;                                                    ;;
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;;                                                              ;;
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;;                                                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;  AMD HyperTransport bus control                              ;;
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;;                                                              ;;
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;;                                                              ;;
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;;                  art_zh                ;;
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;;                  art_zh                ;;
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 13 
 
14 
$Revision: 1554 $
 14 
$Revision: 1554 $
15 
 
 15 
 
16 
NB_MISC_INDEX	equ	0xF0000060	; NB Misc indirect access
 16 
NB_MISC_INDEX	equ	0xF0000060	; NB Misc indirect access
17 
NB_MISC_DATA	equ	0xF0000064
 17 
NB_MISC_DATA	equ	0xF0000064
18 
PCIEIND_INDEX	equ	0xF00000E0	; PCIe Core indirect config space access
 18 
PCIEIND_INDEX	equ	0xF00000E0	; PCIe Core indirect config space access
19 
HTIU_NB_INDEX	equ	0xF0000094	; HyperTransport indirect config space access
 19 
HTIU_NB_INDEX	equ	0xF0000094	; HyperTransport indirect config space access
20 
 
 20 
 
21 
;=============================================================================
 21 
;=============================================================================
22 
;
 22 
;
23 
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
 23 
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
24 
;
 24 
;
25 
;=============================================================================
 25 
;=============================================================================
26 
 
 26 
 
27 
org $-OS_BASE	; physical addresses needed at initial stage
 27 
org $-OS_BASE	; physical addresses needed at initial stage
28 
 
 28 
 
29 
align 4
 29 
align 4
30 
 
 30 
 
31 
;------------------------------------------
 31 
;------------------------------------------
32 
;       params:   al = nbconfig register#
 32 
;       params:   al = nbconfig register#
33 
;       returns: eax = register content
 33 
;       returns: eax = register content
34 
;
 34 
;
35 
rs7xx_nbconfig_read_pci:
 35 
rs7xx_nbconfig_read_pci:
36 
	and	eax, 0x0FC		 ; leave register# only
 36 
	and	eax, 0x0FC		 ; leave register# only
37 
	or	eax, 0x80000000 	 ; bdf = 0:0.0
 37 
	or	eax, 0x80000000 	 ; bdf = 0:0.0
38 
	mov	dx,  0x0CF8		 ; write to index reg
 38 
	mov	dx,  0x0CF8		 ; write to index reg
39 
	out	dx, eax
 39 
	out	dx, eax
40 
	add	dl, 4
 40 
	add	dl, 4
41 
	in	eax, dx
 41 
	in	eax, dx
42 
	ret
 42 
	ret
43 
align 4
 43 
align 4
44 
 
 44 
 
45 
rs7xx_nbconfig_flush_pci:
 45 
rs7xx_nbconfig_flush_pci:
46 
	mov	eax, 0x0B0		; a scratch reg
 46 
	mov	eax, 0x0B0		; a scratch reg
47 
	mov	dx,  0xCF8
 47 
	mov	dx,  0xCF8
48 
	out	dx,  eax
 48 
	out	dx,  eax
49 
	ret
 49 
	ret
50 
 
 50 
 
51 
align 4
 51 
align 4
52 
 
 52 
 
53 
;------------------------------------------
 53 
;------------------------------------------
54 
;       params:   al = nbconfig register#
 54 
;       params:   al = nbconfig register#
55 
;                ebx = register content
 55 
;                ebx = register content
56 
;
 56 
;
57 
rs7xx_nbconfig_write_pci:
 57 
rs7xx_nbconfig_write_pci:
58 
	and	eax, 0x0FC		 ; leave register# only
 58 
	and	eax, 0x0FC		 ; leave register# only
59 
	or	eax, 0x80000000 	 ; bdf = 0:0.0
 59 
	or	eax, 0x80000000 	 ; bdf = 0:0.0
60 
	mov	dx,  0x0CF8		 ; write to index reg
 60 
	mov	dx,  0x0CF8		 ; write to index reg
61 
	out	dx, eax
 61 
	out	dx, eax
62 
	add	dl, 4
 62 
	add	dl, 4
63 
	mov	eax, ebx
 63 
	mov	eax, ebx
64 
	out	dx, eax
 64 
	out	dx, eax
65 
	ret
 65 
	ret
66 
 
 66 
 
67 
;***************************************************************************
 67 
;***************************************************************************
68 
;   Function
 68 
;   Function
69 
;      rs7xx_unlock_bar3:     unlocks the BAR3 register of nbconfig that
 69 
;      rs7xx_unlock_bar3:     unlocks the BAR3 register of nbconfig that
70 
;                             makes pcie config address space visible
 70 
;                             makes pcie config address space visible
71 
;   -----------------------
 71 
;   -----------------------
72 
;   in: nothing      out: nothing      destroys:   eax ebx edx
 72 
;   in: nothing      out: nothing      destroys:   eax ebx edx
73 
;
 73 
;
74 
;***************************************************************************
 74 
;***************************************************************************
75 
align 4
 75 
align 4
76 
rs7xx_unlock_bar3:
 76 
rs7xx_unlock_bar3:
77 
	mov	eax, NB_MISC_INDEX
 77 
	mov	eax, NB_MISC_INDEX
78 
	mov	ebx, 0x080			; NBMISCIND:0x0; write-enable
 78 
	mov	ebx, 0x080			; NBMISCIND:0x0; write-enable
79 
	call	rs7xx_nbconfig_write_pci	; set index
 79 
	call	rs7xx_nbconfig_write_pci	; set index
80 
	mov	eax, NB_MISC_DATA
 80 
	mov	eax, NB_MISC_DATA
81 
	call	rs7xx_nbconfig_read_pci 	; read data
 81 
	call	rs7xx_nbconfig_read_pci 	; read data
82 
	mov	ebx, eax
 82 
	mov	ebx, eax
83 
	and	ebx, 0xFFFFFFF7 		; clear bit3
 83 
	and	ebx, 0xFFFFFFF7 		; clear bit3
84 
	mov	eax, NB_MISC_DATA
 84 
	mov	eax, NB_MISC_DATA
85 
	call	rs7xx_nbconfig_write_pci	; write it back
 85 
	call	rs7xx_nbconfig_write_pci	; write it back
86 
	mov	eax, NB_MISC_INDEX
 86 
	mov	eax, NB_MISC_INDEX
87 
	xor	ebx, ebx			; reg#0; write-locked
 87 
	xor	ebx, ebx			; reg#0; write-locked
88 
	call	rs7xx_nbconfig_write_pci	; set index
 88 
	call	rs7xx_nbconfig_write_pci	; set index
89 
	ret
 89 
	ret
90 
 
 90 
 
91 
 
 91 
 
92 
 
 92 
 
93 
;***************************************************************************
 93 
;***************************************************************************
94 
;   Function
 94 
;   Function
95 
;      rs7xx_pcie_init:
 95 
;      fusion_pcie_init:
96 
;
 96 
;
97 
;   Description
 97 
;   Description
98 
;       PCIe extended (memory-mapped) config space detection
 98 
;       PCIe extended  config space detection and mapping
99 
;
 99 
;
100 
;***************************************************************************
 100 
;***************************************************************************
101 
 
 101 
 
102 
align 4
 102 
align 4
103 
 
 - 
 
104 
rs7xx_pcie_init:
 - 
 
105 
	call	rs7xx_unlock_bar3
 - 
 
106 
	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
 - 
 
107 
	call	rs7xx_nbconfig_read_pci
 - 
 
108 
	mov	ebx, eax
 - 
 
109 
;       call    rs7xx_nbconfig_flush_pci
 - 
 
110 
	test	ebx, 0x20000000 		; BAR3 locked?
 - 
 
111 
	jz	$
 - 
 
112 
	mov	al, 0x84			; NB_PCI_ARB
 - 
 
113 
	call	rs7xx_nbconfig_read_pci
 - 
 
114 
	shr	eax,16
 - 
 
115 
	and	ax, 7				; the Bus range lays here:
 - 
 
116 
	jnz	@f
 - 
 
117 
	mov	ax, 8					; 1=2Mb,  2=4MB,  3=8MB,  4=16MB
 - 
 
118 
@@:
 - 
 
119 
	mov	word[PCIe_bus_range-OS_BASE], ax	; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
 - 
 
120 
	mov	cl, al
 - 
 
121 
	call	rs7xx_nbconfig_flush_pci
 - 
 
122 
	dec	cl				; <4M ?
 - 
 
123 
	jz	@f
 - 
 
124 
	dec	cl				; one PDE needed anyway
 - 
 
125 
@@:
 - 
 
126 
	mov	ebx, 1
 - 
 
127 
	shl	ebx, cl
 - 
 
128 
	mov	word[mmio_pcie_cfg_pdes-OS_BASE], bx	; 1..64 PDE(s) needed,
 - 
 
129 
	shl	ebx, 22
 - 
 
130 
	mov	dword[mmio_pcie_cfg_lim-OS_BASE], ebx	; or 4..256Mb space to map
 - 
 
131 
	dec	dword[mmio_pcie_cfg_lim-OS_BASE]
 - 
 
132 
 
 - 
 
133 
	mov	al, 0x1C			; NB_BAR3_PCIEXP_MMCFG
 - 
 
134 
	call	rs7xx_nbconfig_read_pci
 - 
 
135 
	mov	ebx, eax
 - 
 
136 
	call	rs7xx_nbconfig_flush_pci
 - 
 
137 
	mov	eax, ebx
 - 
 
138 
	and	eax, 0xFFE00000 		; valid bits [31..21]
 - 
 
139 
	jz	$				; invalid map!
 - 
 
140 
.addr_found:
 - 
 
141 
	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
 - 
 
142 
	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
 - 
 
143 
 
 - 
 
144 
; ---- common mapping procedure ----
 - 
 
145 
; (eax = phys. address of PCIe conf.space)
 - 
 
146 
;
 - 
 
147 
map_pcie_pages:
 - 
 
148 
	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
 - 
 
149 
	mov	ecx, PCIe_CONFIG_SPACE			; linear address
 - 
 
150 
	mov	ebx, ecx
 - 
 
151 
	shr	ebx, 20
 - 
 
152 
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
 - 
 
153 
	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
 - 
 
154 
	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
 - 
 
155 
	jb	@f
 - 
 
156 
	mov	dl, 0x33
 - 
 
157 
	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
 - 
 
158 
@@:
 - 
 
159 
	xor	dx,  dx 			; PDEs counter
 - 
 
160 
.write_pde:
 - 
 
161 
	mov	dword[ebx], eax 		; map 4 buses
 - 
 
162 
	add	bx,  4				; new PDE
 - 
 
163 
	add	eax, 0x400000			; +4M phys.
 - 
 
164 
	add	ecx, 0x400000			; +4M lin.
 - 
 
165 
	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
 - 
 
166 
	jae	pcie_cfg_mapped
 - 
 
167 
	inc	dl
 103 
 
168 
	jmp	.write_pde
 104 
 
169 
 
 105 
 
170 
; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
 106 
; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
171 
align 4
 107 
align 4
172 
fusion_pcie_init:
 108 
fusion_pcie_init:
173 
	mov	ecx, 0xC0010058
 109 
	mov	ecx, 0xC0010058
174 
	rdmsr
 110 
	rdmsr
175 
	or	edx, edx
 111 
	or	edx, edx
176 
	jnz	$				; PCIe is in the upper memory. Stop.
 112 
	jnz	$				; PCIe is in the upper memory. Stop.
177 
	xchg	dl, al
 113 
	xchg	dl, al
178 
	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; store the physical address
 114 
	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; store the physical address
179 
	mov	ecx, edx
 115 
	mov	ecx, edx
180 
	and	dl, 1
 116 
	and	dl, 1
181 
	jz	$				; bit[0] = 1 means no PCIe mapping allowed. Stop.
 117 
	jz	$				; bit[0] = 1 means no PCIe mapping allowed. Stop.
182 
	shr	cl, 2				; ecx = log2(number of buses)
 118 
	shr	cl, 2				; ecx = log2(number of buses)
183 
	mov	word[PCIe_bus_range-OS_BASE], cx
 119 
	mov	word[PCIe_bus_range-OS_BASE], cx
184 
	sub	cl, 2
 120 
	sub	cl, 2
185 
	jae	@f
 121 
	jae	@f
186 
	xor	cl, cl
 122 
	xor	cl, cl
187 
@@:
 123 
@@:
188 
	shl	edx, cl 			; edx = number of 4M pages to map
 124 
	shl	edx, cl 			; edx = number of 4M pages to map
189 
	mov	word[mmio_pcie_cfg_pdes-OS_BASE], dx
 125 
	mov	word[mmio_pcie_cfg_pdes-OS_BASE], dx
190 
	shl	edx, 22
 126 
	shl	edx, 22
191 
	dec	edx
 127 
	dec	edx
192 
	add	edx, eax			; the upper configspace limit
 128 
	add	edx, eax			; the upper configspace limit
193 
	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
 129 
	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
- 
 
 130 
 
- 
 
 131 
; ---- large pages mapping  ----
- 
 
 132 
; (eax = phys. address of PCIe conf.space)
- 
 
 133 
;
- 
 
 134 
.map_pcie_pages:
- 
 
 135 
	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
- 
 
 136 
	mov	ecx, PCIe_CONFIG_SPACE			; linear address
- 
 
 137 
	mov	ebx, ecx
- 
 
 138 
	shr	ebx, 20
- 
 
 139 
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
- 
 
 140 
	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
- 
 
 141 
	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
- 
 
 142 
	jb	@f
- 
 
 143 
	mov	dl, 0x33
- 
 
 144 
	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
- 
 
 145 
@@:
- 
 
 146 
	xor	dx,  dx 			; PDEs counter
- 
 
 147 
.write_pde:
- 
 
 148 
	mov	dword[ebx], eax 		; map 4 buses
- 
 
 149 
	add	bx,  4				; new PDE
- 
 
 150 
	add	eax, 0x400000			; +4M phys.
- 
 
 151 
	add	ecx, 0x400000			; +4M lin.
194 
 
 152 
	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
- 
 
 153 
	jae	.pcie_cfg_mapped
- 
 
 154 
	inc	dl
195 
pcie_cfg_mapped:
 155 
	jmp	.write_pde
- 
 
 156 
 
196 
 
 157 
.pcie_cfg_mapped:
197 
create_mmio_pte:
 158 
 
198 
 
 159 
create_mmio_pte:
199 
	mov	ecx, mmio_pte                           ; physical address
 160 
	mov	ecx, mmio_pte                           ; physical address
200 
	or	ecx, (PG_NOCACHE + PG_SHARED)
161 
	or	ecx, (PG_NOCACHE + PG_SHARED)
201 
	mov	ebx, FUSION_MMIO			; linear address
 162 
	mov	ebx, FUSION_MMIO			; linear address
202 
	shr	ebx, 20
 163 
	shr	ebx, 20
203 
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
 164 
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
204 
        mov     dword[ebx], ecx                         ; Fusion MMIO tables
 165 
        mov     dword[ebx], ecx                         ; Fusion MMIO tables
- 
 
 166 
 
205 
 
 167 
; ---- short page mapping  ----
206 
map_apic_mmio:
 168 
.map_apic_mmio:
207 
        mov     ecx, 0x01B      ; APIC BAR
 169 
        mov     ecx, 0x01B      ; APIC BAR
208 
        rdmsr
 170 
        rdmsr
209 
        and     eax, 0xFFFFF000                         ; physical address
 171 
        and     eax, 0xFFFFF000                         ; physical address
210 
	or	eax, (PG_NOCACHE + PG_SHARED + PG_UW)   ;  UW is unsafe!
 172 
	or	eax, (PG_NOCACHE + PG_SHARED)
211 
        mov     dword[mmio_pte + 0], eax
 173 
        mov     dword[mmio_pte + 0], eax
212 
 
 174 
 
213 
	ret	; <<< OK >>>
 175 
	ret	; <<< OK >>>
214 
 
 176 
 
215 
; ================================================================================
 177 
; ================================================================================
216 
 
 178 
 
217 
org OS_BASE+$	; back to the linear address space
 179 
org OS_BASE+$	; back to the linear address space
218 
 
 180 
 
219 
;--------------------------------------------------------------
 181 
;--------------------------------------------------------------
220 
align 4
 182 
align 4
221 
rs780_read_misc:
 183 
rs780_read_misc:
222 
;  in: eax(al) - reg#           out: eax = NBMISCIND data
 184 
;  in: eax(al) - reg#           out: eax = NBMISCIND data
223 
	push	edx
 185 
	push	edx
224 
	mov	edx, NB_MISC_INDEX
 186 
	mov	edx, NB_MISC_INDEX
225 
	and	eax, 0x07F
 187 
	and	eax, 0x07F
226 
	mov	[edx], eax
 188 
	mov	[edx], eax
227 
	add	dl, 4
 189 
	add	dl, 4
228 
	mov	eax, [edx]
 190 
	mov	eax, [edx]
229 
	pop	edx
 191 
	pop	edx
230 
	ret
 192 
	ret
231 
 
 193 
 
232 
;-------------------------------------------
 194 
;-------------------------------------------
233 
align 4
 195 
align 4
234 
rs780_write_misc:
 196 
rs780_write_misc:
235 
;  in: eax(al) - reg#     ebx = NBMISCIND data
 197 
;  in: eax(al) - reg#     ebx = NBMISCIND data
236 
	push	edx
 198 
	push	edx
237 
	mov	edx, NB_MISC_INDEX
 199 
	mov	edx, NB_MISC_INDEX
238 
	and	eax, 0x07F
 200 
	and	eax, 0x07F
239 
	or	eax, 0x080		; set WE
 201 
	or	eax, 0x080		; set WE
240 
	mov	[edx], eax
 202 
	mov	[edx], eax
241 
	add	dl, 4
 203 
	add	dl, 4
242 
	mov	[edx], ebx
 204 
	mov	[edx], ebx
243 
	sub	dl, 4
 205 
	sub	dl, 4
244 
	xor	eax,   eax
 206 
	xor	eax,   eax
245 
	mov	[edx], eax		; safety last
 207 
	mov	[edx], eax		; safety last
246 
	pop	edx
 208 
	pop	edx
247 
	ret
 209 
	ret
248 
 
 210 
 
249 
;-------------------------------------------------------------
 211 
;-------------------------------------------------------------
250 
align 4
 212 
align 4
251 
rs780_read_pcieind:
 213 
rs780_read_pcieind:
252 
;  in: ah = bridge#, al = reg#           out: eax = PCIEIND data
 214 
;  in: ah = bridge#, al = reg#           out: eax = PCIEIND data
253 
	push	edx
 215 
	push	edx
254 
	xor	edx, edx
 216 
	xor	edx, edx
255 
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
 217 
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
256 
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
 218 
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
257 
	shl	edx, 15 		; device#
 219 
	shl	edx, 15 		; device#
258 
	add	edx, PCIEIND_INDEX	; full bdf-address
 220 
	add	edx, PCIEIND_INDEX	; full bdf-address
259 
	and	eax, 0x30FF
 221 
	and	eax, 0x30FF
260 
	or	al,  al
 222 
	or	al,  al
261 
	jnz	@f
 223 
	jnz	@f
262 
	shl	eax, 4			; set bits 17..16 for a Core bridge
 224 
	shl	eax, 4			; set bits 17..16 for a Core bridge
263 
@@:
 225 
@@:
264 
	mov	[edx], eax
 226 
	mov	[edx], eax
265 
	add	dl,  4
 227 
	add	dl,  4
266 
	mov	eax, [edx]
 228 
	mov	eax, [edx]
267 
	pop	edx
 229 
	pop	edx
268 
	ret
 230 
	ret
269 
 
 231 
 
270 
;-------------------------------------------
 232 
;-------------------------------------------
271 
align 4
 233 
align 4
272 
rs780_write_pcieind:
 234 
rs780_write_pcieind:
273 
;  in: ah = bridge#, al = reg#,  ebx = PCIEIND data
 235 
;  in: ah = bridge#, al = reg#,  ebx = PCIEIND data
274 
	push	edx
 236 
	push	edx
275 
	xor	edx, edx
 237 
	xor	edx, edx
276 
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
 238 
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
277 
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
 239 
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
278 
	shl	edx, 15 		; device#
 240 
	shl	edx, 15 		; device#
279 
	add	edx, PCIEIND_INDEX	; full bdf-address
 241 
	add	edx, PCIEIND_INDEX	; full bdf-address
280 
	and	eax, 0x30FF
 242 
	and	eax, 0x30FF
281 
	or	al,  al
 243 
	or	al,  al
282 
	jnz	@f
 244 
	jnz	@f
283 
	shl	eax, 4			; set bits 17..16 for a Core bridge
 245 
	shl	eax, 4			; set bits 17..16 for a Core bridge
284 
@@:
 246 
@@:
285 
	mov	[edx], eax
 247 
	mov	[edx], eax
286 
	add	dl,  4
 248 
	add	dl,  4
287 
	mov	[edx], ebx
 249 
	mov	[edx], ebx
288 
	sub	dl,  4
 250 
	sub	dl,  4
289 
	xor	eax,   eax
 251 
	xor	eax,   eax
290 
	mov	[edx], eax		; safety last
 252 
	mov	[edx], eax		; safety last
291 
	pop	edx
 253 
	pop	edx
292 
	ret
 254 
	ret
293 
 
 255 
 
294 
;------------------------------------------------
 256 
;------------------------------------------------
295 
align 4
 257 
align 4
296 
rs780_read_htiu:
 258 
rs780_read_htiu:
297 
; in:  al = reg#  |  out: eax = HTIU data
 259 
; in:  al = reg#  |  out: eax = HTIU data
298 
;------------------------------------------------
 260 
;------------------------------------------------
299 
	push	edx
 261 
	push	edx
300 
	mov	edx,  HTIU_NB_INDEX
 262 
	mov	edx,  HTIU_NB_INDEX
301 
	and	eax, 0x07F
 263 
	and	eax, 0x07F
302 
	mov	[edx], eax
 264 
	mov	[edx], eax
303 
	add	dl,  4
 265 
	add	dl,  4
304 
	mov	eax, [edx]
 266 
	mov	eax, [edx]
305 
	pop	edx
 267 
	pop	edx
306 
	ret
 268 
	ret
307 
;------------------------------------------------
 269 
;------------------------------------------------
308 
align 4
 270 
align 4
309 
rs780_write_htiu:
 271 
rs780_write_htiu:
310 
; in:  al = reg#; ebx = data
 272 
; in:  al = reg#; ebx = data
311 
;------------------------------------------------
 273 
;------------------------------------------------
312 
	push	edx
 274 
	push	edx
313 
	mov	edx,  HTIU_NB_INDEX
 275 
	mov	edx,  HTIU_NB_INDEX
314 
	and	eax, 0x07F
 276 
	and	eax, 0x07F
315 
	or	eax, 0x100
 277 
	or	eax, 0x100
316 
	mov	[edx], eax
 278 
	mov	[edx], eax
317 
	add	dl,  4
 279 
	add	dl,  4
318 
	mov	[edx], ebx
 280 
	mov	[edx], ebx
319 
	sub	dl,  4
 281 
	sub	dl,  4
320 
	xor	eax,   eax
 282 
	xor	eax,   eax
321 
	mov	[edx], eax
 283 
	mov	[edx], eax
322 
	pop	edx
 284 
	pop	edx
323 
	ret
 285 
	ret
324 
 
 286 
 
325 
;------------------------------------------------
 287 
;------------------------------------------------
326 
align 4
 288 
align 4
327 
sys_rdmsr:
 289 
sys_rdmsr:
328 
;  in: [esp+8] = MSR#
 290 
;  in: [esp+8] = MSR#
329 
; out: [esp+8] = MSR[63:32]
 291 
; out: [esp+8] = MSR[63:32]
330 
;        [eax] = MSR[31: 0]
 292 
;        [eax] = MSR[31: 0]
331 
;------------------------------------------------
 293 
;------------------------------------------------
332 
	push	ecx edx
 294 
	push	ecx edx
333 
	mov	ecx, [esp+16]
 295 
	mov	ecx, [esp+16]
334 
	rdmsr
 296 
	rdmsr
335 
	mov	[esp+16], edx
 297 
	mov	[esp+16], edx
336 
	pop	edx ecx
 298 
	pop	edx ecx
337 
	ret
 299 
	ret