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;***************************************************************************
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;***************************************************************************
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;   Function
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;   Function
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;      rs7xx_pcie_init:
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;      fusion_pcie_init:
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;
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;
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;   Description
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;   Description
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;       PCIe extended (memory-mapped) config space detection
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;       PCIe extended  config space detection and mapping
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;
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;***************************************************************************
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align 4
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rs7xx_pcie_init:
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	call	rs7xx_unlock_bar3
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	mov	al, 0x7C		       ; NB_IOC_CFG_CNTL
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	call	rs7xx_nbconfig_read_pci
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	mov	ebx, eax
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;       call    rs7xx_nbconfig_flush_pci
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	test	ebx, 0x20000000 		; BAR3 locked?
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	jz	$
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	mov	al, 0x84			; NB_PCI_ARB
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	call	rs7xx_nbconfig_read_pci
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	shr	eax,16
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	and	ax, 7				; the Bus range lays here:
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	jnz	@f
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	mov	ax, 8					; 1=2Mb,  2=4MB,  3=8MB,  4=16MB
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@@:
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	mov	word[PCIe_bus_range-OS_BASE], ax	; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
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	mov	cl, al
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	call	rs7xx_nbconfig_flush_pci
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	dec	cl				; <4M ?
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	jz	@f
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	dec	cl				; one PDE needed anyway
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@@:
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	mov	ebx, 1
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	shl	ebx, cl
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	mov	word[mmio_pcie_cfg_pdes-OS_BASE], bx	; 1..64 PDE(s) needed,
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	shl	ebx, 22
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], ebx	; or 4..256Mb space to map
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	dec	dword[mmio_pcie_cfg_lim-OS_BASE]
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	mov	al, 0x1C			; NB_BAR3_PCIEXP_MMCFG
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	call	rs7xx_nbconfig_read_pci
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	mov	ebx, eax
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	call	rs7xx_nbconfig_flush_pci
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	mov	eax, ebx
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	and	eax, 0xFFE00000 		; valid bits [31..21]
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	jz	$				; invalid map!
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.addr_found:
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	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
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	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
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; ---- common mapping procedure ----
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; (eax = phys. address of PCIe conf.space)
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;
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map_pcie_pages:
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ebx, ecx
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
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	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
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	jb	@f
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	mov	dl, 0x33
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	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
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@@:
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	xor	dx,  dx 			; PDEs counter
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.write_pde:
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	mov	dword[ebx], eax 		; map 4 buses
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	add	bx,  4				; new PDE
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	add	eax, 0x400000			; +4M phys.
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;
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	add	ecx, 0x400000			; +4M lin.
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;***************************************************************************
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	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
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	jae	pcie_cfg_mapped
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align 4
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	shl	edx, 22
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	shl	edx, 22
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	dec	edx
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	dec	edx
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	add	edx, eax			; the upper configspace limit
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	add	edx, eax			; the upper configspace limit
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
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; ---- large pages mapping  ----
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; (eax = phys. address of PCIe conf.space)
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;
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.map_pcie_pages:
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ebx, ecx
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
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	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
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	jb	@f
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	mov	dl, 0x33
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	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
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@@:
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	xor	dx,  dx 			; PDEs counter
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.write_pde:
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	mov	dword[ebx], eax 		; map 4 buses
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	add	bx,  4				; new PDE
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	add	eax, 0x400000			; +4M phys.
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	add	ecx, 0x400000			; +4M lin.
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	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
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	jae	.pcie_cfg_mapped
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	inc	dl
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pcie_cfg_mapped:
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	jmp	.write_pde
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.pcie_cfg_mapped:
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create_mmio_pte:
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create_mmio_pte:
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	mov	ecx, mmio_pte                           ; physical address
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	mov	ecx, mmio_pte                           ; physical address
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	or	ecx, (PG_NOCACHE + PG_SHARED)
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	or	ecx, (PG_NOCACHE + PG_SHARED)
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	mov	ebx, FUSION_MMIO			; linear address
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	mov	ebx, FUSION_MMIO			; linear address
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	shr	ebx, 20
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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        mov     dword[ebx], ecx                         ; Fusion MMIO tables
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        mov     dword[ebx], ecx                         ; Fusion MMIO tables
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; ---- short page mapping  ----
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map_apic_mmio:
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.map_apic_mmio:
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        mov     ecx, 0x01B      ; APIC BAR
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        mov     ecx, 0x01B      ; APIC BAR
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        rdmsr
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        rdmsr
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        and     eax, 0xFFFFF000                         ; physical address
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        and     eax, 0xFFFFF000                         ; physical address